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You searched for subject:(Very Large Scale Integration). Showing records 1 – 30 of 23173 total matches.

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Anna University

1. Hemalatha A. Certain investigations on efficient Low power multipliers for Fir filter implementation;.

Degree: Certain investigations on efficient Low power multipliers for Fir filter implementation, 2015, Anna University

Digital Signal Processing DSP is an area of Science and newlineEngineering that has developed rapidly over the recent years This rapid newlinedevelopment is the result… (more)

Subjects/Keywords: Digital Signal Processing; Large Scale Integration; Very Large Scale Integration

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APA (6th Edition):

A, H. (2015). Certain investigations on efficient Low power multipliers for Fir filter implementation;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/44188

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

A, Hemalatha. “Certain investigations on efficient Low power multipliers for Fir filter implementation;.” 2015. Thesis, Anna University. Accessed September 18, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/44188.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

A, Hemalatha. “Certain investigations on efficient Low power multipliers for Fir filter implementation;.” 2015. Web. 18 Sep 2020.

Vancouver:

A H. Certain investigations on efficient Low power multipliers for Fir filter implementation;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Sep 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/44188.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

A H. Certain investigations on efficient Low power multipliers for Fir filter implementation;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/44188

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

2. Ruggeri, Thomas L. TIMR : Time Interleaved Multi Rail.

Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University

 This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic… (more)

Subjects/Keywords: VLSI; Integrated circuits  – Very large scale integration

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APA (6th Edition):

Ruggeri, T. L. (2012). TIMR : Time Interleaved Multi Rail. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29070

Chicago Manual of Style (16th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Masters Thesis, Oregon State University. Accessed September 18, 2020. http://hdl.handle.net/1957/29070.

MLA Handbook (7th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Web. 18 Sep 2020.

Vancouver:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/1957/29070.

Council of Science Editors:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29070


Anna University

3. Anita J P. Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults;.

Degree: Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults, 2015, Anna University

newlineVery Large Scale Integration VLSI technology is a major newlinemilestone in the development of solid state electronics The advancement in newlineVLSI technology has allowed the… (more)

Subjects/Keywords: Liu and Veneris; Very Large Scale Integration

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APA (6th Edition):

P, A. J. (2015). Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33709

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

P, Anita J. “Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults;.” 2015. Thesis, Anna University. Accessed September 18, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/33709.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

P, Anita J. “Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults;.” 2015. Web. 18 Sep 2020.

Vancouver:

P AJ. Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Sep 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33709.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P AJ. Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33709

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

4. Venumbaka, Sri Ramya. Ultrafast nanoelectromechanical switches for VLSI power management.

Degree: MS, Electrical & Computer Engineering, 2010, University of Utah

 Power consumption is a major concern in the present chip design industry. Complementary Metal Oxide Semiconductor (CMOS) technology scaling has led to an exponential increase… (more)

Subjects/Keywords: Ultrafast; Nanoelectromechanical switches; VLSI; Very large scale integration; CMOS; NEMS

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APA (6th Edition):

Venumbaka, S. R. (2010). Ultrafast nanoelectromechanical switches for VLSI power management. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/549/rec/2813

Chicago Manual of Style (16th Edition):

Venumbaka, Sri Ramya. “Ultrafast nanoelectromechanical switches for VLSI power management.” 2010. Masters Thesis, University of Utah. Accessed September 18, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/549/rec/2813.

MLA Handbook (7th Edition):

Venumbaka, Sri Ramya. “Ultrafast nanoelectromechanical switches for VLSI power management.” 2010. Web. 18 Sep 2020.

Vancouver:

Venumbaka SR. Ultrafast nanoelectromechanical switches for VLSI power management. [Internet] [Masters thesis]. University of Utah; 2010. [cited 2020 Sep 18]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/549/rec/2813.

Council of Science Editors:

Venumbaka SR. Ultrafast nanoelectromechanical switches for VLSI power management. [Masters Thesis]. University of Utah; 2010. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/549/rec/2813


Columbia University

5. Kim, Hyungsik. Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI).

Degree: 2018, Columbia University

 Two dimensional (2D) materials have been explosively researched since the discovery of graphene but the applications of 2D materials have been extremely constrained because of… (more)

Subjects/Keywords: Electrical engineering; Graphene; Integrated circuits – Very large scale integration; Materials

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APA (6th Edition):

Kim, H. (2018). Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI). (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8Z33GMR

Chicago Manual of Style (16th Edition):

Kim, Hyungsik. “Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI).” 2018. Doctoral Dissertation, Columbia University. Accessed September 18, 2020. https://doi.org/10.7916/D8Z33GMR.

MLA Handbook (7th Edition):

Kim, Hyungsik. “Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI).” 2018. Web. 18 Sep 2020.

Vancouver:

Kim H. Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI). [Internet] [Doctoral dissertation]. Columbia University; 2018. [cited 2020 Sep 18]. Available from: https://doi.org/10.7916/D8Z33GMR.

Council of Science Editors:

Kim H. Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI). [Doctoral Dissertation]. Columbia University; 2018. Available from: https://doi.org/10.7916/D8Z33GMR


Iowa State University

6. Gong, Xinyu. An offset auto-calibration technique with cost-effective implementation for comparator and operational amplifier.

Degree: 2019, Iowa State University

 Comparators are one of the most fundamental building blocks in all electronic systems involving analog and digital information. A comparator’s performance, or the accuracy of… (more)

Subjects/Keywords: Analog; Very Large Scale Integration; Electrical and Electronics

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APA (6th Edition):

Gong, X. (2019). An offset auto-calibration technique with cost-effective implementation for comparator and operational amplifier. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/17453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gong, Xinyu. “An offset auto-calibration technique with cost-effective implementation for comparator and operational amplifier.” 2019. Thesis, Iowa State University. Accessed September 18, 2020. https://lib.dr.iastate.edu/etd/17453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gong, Xinyu. “An offset auto-calibration technique with cost-effective implementation for comparator and operational amplifier.” 2019. Web. 18 Sep 2020.

Vancouver:

Gong X. An offset auto-calibration technique with cost-effective implementation for comparator and operational amplifier. [Internet] [Thesis]. Iowa State University; 2019. [cited 2020 Sep 18]. Available from: https://lib.dr.iastate.edu/etd/17453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gong X. An offset auto-calibration technique with cost-effective implementation for comparator and operational amplifier. [Thesis]. Iowa State University; 2019. Available from: https://lib.dr.iastate.edu/etd/17453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Massey University

7. Alam, Sadia. Modelling, analysis and design of bioelectronic circuits in VLSI.

Degree: PhD, Electronics and Computer Engineering, 2015, Massey University

 Biological phenomena at the molecular level are being imitated by electronic circuits. The immense effectiveness and versatility of bioelectronic circuits have yielded multiple benefits to… (more)

Subjects/Keywords: Integrated circuits; Very large scale integration; Design and construction; Bioelectronics

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APA (6th Edition):

Alam, S. (2015). Modelling, analysis and design of bioelectronic circuits in VLSI. (Doctoral Dissertation). Massey University. Retrieved from http://hdl.handle.net/10179/7731

Chicago Manual of Style (16th Edition):

Alam, Sadia. “Modelling, analysis and design of bioelectronic circuits in VLSI.” 2015. Doctoral Dissertation, Massey University. Accessed September 18, 2020. http://hdl.handle.net/10179/7731.

MLA Handbook (7th Edition):

Alam, Sadia. “Modelling, analysis and design of bioelectronic circuits in VLSI.” 2015. Web. 18 Sep 2020.

Vancouver:

Alam S. Modelling, analysis and design of bioelectronic circuits in VLSI. [Internet] [Doctoral dissertation]. Massey University; 2015. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/10179/7731.

Council of Science Editors:

Alam S. Modelling, analysis and design of bioelectronic circuits in VLSI. [Doctoral Dissertation]. Massey University; 2015. Available from: http://hdl.handle.net/10179/7731


Massey University

8. Khurram, Muhammad. VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 .

Degree: 2011, Massey University

 The wide operating bandwidth of the ultra-wideband (UWB) signal leads to new circuit design challenges and methodologies. Similar to any other RF system, the most… (more)

Subjects/Keywords: Integrated circuits; Very large scale integration; Computer-aided design; VLSI; CMOS

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APA (6th Edition):

Khurram, M. (2011). VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 . (Thesis). Massey University. Retrieved from http://hdl.handle.net/10179/3701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khurram, Muhammad. “VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 .” 2011. Thesis, Massey University. Accessed September 18, 2020. http://hdl.handle.net/10179/3701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khurram, Muhammad. “VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 .” 2011. Web. 18 Sep 2020.

Vancouver:

Khurram M. VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 . [Internet] [Thesis]. Massey University; 2011. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/10179/3701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khurram M. VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 . [Thesis]. Massey University; 2011. Available from: http://hdl.handle.net/10179/3701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

9. Lim, Daniel. VLSI design methodologies and computer tools.

Degree: MS, Electrical and Computer Engineering, 1985, Oregon State University

 The rapid development of semiconductor technology and the increasing complexity of VLSI chips have prompted both the industry and the academic community alike to take… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration

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APA (6th Edition):

Lim, D. (1985). VLSI design methodologies and computer tools. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/40378

Chicago Manual of Style (16th Edition):

Lim, Daniel. “VLSI design methodologies and computer tools.” 1985. Masters Thesis, Oregon State University. Accessed September 18, 2020. http://hdl.handle.net/1957/40378.

MLA Handbook (7th Edition):

Lim, Daniel. “VLSI design methodologies and computer tools.” 1985. Web. 18 Sep 2020.

Vancouver:

Lim D. VLSI design methodologies and computer tools. [Internet] [Masters thesis]. Oregon State University; 1985. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/1957/40378.

Council of Science Editors:

Lim D. VLSI design methodologies and computer tools. [Masters Thesis]. Oregon State University; 1985. Available from: http://hdl.handle.net/1957/40378


Drexel University

10. Filippini, Leo. Charge Recovery Circuits.

Degree: 2019, Drexel University

Modern VLSI systems are under strict power and performance constraints, and the trade-offs between these two aspects drive industry and academic research alike. Static CMOS… (more)

Subjects/Keywords: Electrical engineering; Integrated circuits – Very large scale integration; Metal oxide semiconductors, Complementary

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APA (6th Edition):

Filippini, L. (2019). Charge Recovery Circuits. (Thesis). Drexel University. Retrieved from https://idea.library.drexel.edu/islandora/object/idea%3A9440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Filippini, Leo. “Charge Recovery Circuits.” 2019. Thesis, Drexel University. Accessed September 18, 2020. https://idea.library.drexel.edu/islandora/object/idea%3A9440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Filippini, Leo. “Charge Recovery Circuits.” 2019. Web. 18 Sep 2020.

Vancouver:

Filippini L. Charge Recovery Circuits. [Internet] [Thesis]. Drexel University; 2019. [cited 2020 Sep 18]. Available from: https://idea.library.drexel.edu/islandora/object/idea%3A9440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Filippini L. Charge Recovery Circuits. [Thesis]. Drexel University; 2019. Available from: https://idea.library.drexel.edu/islandora/object/idea%3A9440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

11. Santhi, M. Image compression using inter color Correlation; -.

Degree: Information and Communication Engineering, 2014, Anna University

Every day a huge amount of digital information is stored newlineprocessed and transmitted on internet Most of the on line information is still newlineor video… (more)

Subjects/Keywords: Digital communication system; Digital data storage capacity; Information and Communication engineering; Very large scale integration

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APA (6th Edition):

Santhi, M. (2014). Image compression using inter color Correlation; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/25417

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Santhi, M. “Image compression using inter color Correlation; -.” 2014. Thesis, Anna University. Accessed September 18, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/25417.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Santhi, M. “Image compression using inter color Correlation; -.” 2014. Web. 18 Sep 2020.

Vancouver:

Santhi M. Image compression using inter color Correlation; -. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Sep 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/25417.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santhi M. Image compression using inter color Correlation; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/25417

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

12. Nirmala Devi, M. VLSI realization of artificial neural Networks using digital and mixed Signal hardware; -.

Degree: Information and Communication Engineering, 2014, Anna University

A Biological Neural Network BNN forms the Central Nervous newlineSystem which has highly interconnected neurons to co ordinate all the newlinefunctions like reading and thinking… (more)

Subjects/Keywords: Artificial Neural Networks; Biological Neural Network; Central Nervous System; Very Large Scale Integration

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APA (6th Edition):

Nirmala Devi, M. (2014). VLSI realization of artificial neural Networks using digital and mixed Signal hardware; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/26986

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nirmala Devi, M. “VLSI realization of artificial neural Networks using digital and mixed Signal hardware; -.” 2014. Thesis, Anna University. Accessed September 18, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/26986.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nirmala Devi, M. “VLSI realization of artificial neural Networks using digital and mixed Signal hardware; -.” 2014. Web. 18 Sep 2020.

Vancouver:

Nirmala Devi M. VLSI realization of artificial neural Networks using digital and mixed Signal hardware; -. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Sep 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26986.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nirmala Devi M. VLSI realization of artificial neural Networks using digital and mixed Signal hardware; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26986

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Gracia nirmala rani D. Analysis and optimization of Floorplanning algorithms for VLSI physical design;.

Degree: Analysis and optimization of Floorplanning algorithms for VLSI physical design, 2015, Anna University

Rapid advances in semiconductor technologies have led to a newlinedramatic increase in the complexity of Very Large Scale Integration VLSI newlinecircuits With fabrication technology entering… (more)

Subjects/Keywords: Computer Aided Design; Integrated Circuits; Non Deterministic Polynomial time; Very Large Scale Integration

Page 1

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APA (6th Edition):

D, G. n. r. (2015). Analysis and optimization of Floorplanning algorithms for VLSI physical design;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/38605

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

D, Gracia nirmala rani. “Analysis and optimization of Floorplanning algorithms for VLSI physical design;.” 2015. Thesis, Anna University. Accessed September 18, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/38605.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

D, Gracia nirmala rani. “Analysis and optimization of Floorplanning algorithms for VLSI physical design;.” 2015. Web. 18 Sep 2020.

Vancouver:

D Gnr. Analysis and optimization of Floorplanning algorithms for VLSI physical design;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Sep 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/38605.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

D Gnr. Analysis and optimization of Floorplanning algorithms for VLSI physical design;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/38605

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

14. Zheng, Yue-Peng. Mapping of recursive algorithms onto multi-rate arrays.

Degree: PhD, Electrical and Computer Engineering, 1994, Oregon State University

 In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed and developed. Using multi-coordinate systems (MCS), a unified theory for mapping algorithms from… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration

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APA (6th Edition):

Zheng, Y. (1994). Mapping of recursive algorithms onto multi-rate arrays. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/34997

Chicago Manual of Style (16th Edition):

Zheng, Yue-Peng. “Mapping of recursive algorithms onto multi-rate arrays.” 1994. Doctoral Dissertation, Oregon State University. Accessed September 18, 2020. http://hdl.handle.net/1957/34997.

MLA Handbook (7th Edition):

Zheng, Yue-Peng. “Mapping of recursive algorithms onto multi-rate arrays.” 1994. Web. 18 Sep 2020.

Vancouver:

Zheng Y. Mapping of recursive algorithms onto multi-rate arrays. [Internet] [Doctoral dissertation]. Oregon State University; 1994. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/1957/34997.

Council of Science Editors:

Zheng Y. Mapping of recursive algorithms onto multi-rate arrays. [Doctoral Dissertation]. Oregon State University; 1994. Available from: http://hdl.handle.net/1957/34997


Oregon State University

15. Chow, Andrew Siv-Anne. Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs.

Degree: MS, Electrical and Computer Engineering, 1990, Oregon State University

 The new CMOS folded source-coupled logic (FSCL) technique intended for mixed-mode integrated circuits has been designed. It has advantages over conventional CMOS circuit in terms… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration

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APA (6th Edition):

Chow, A. S. (1990). Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/40960

Chicago Manual of Style (16th Edition):

Chow, Andrew Siv-Anne. “Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs.” 1990. Masters Thesis, Oregon State University. Accessed September 18, 2020. http://hdl.handle.net/1957/40960.

MLA Handbook (7th Edition):

Chow, Andrew Siv-Anne. “Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs.” 1990. Web. 18 Sep 2020.

Vancouver:

Chow AS. Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs. [Internet] [Masters thesis]. Oregon State University; 1990. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/1957/40960.

Council of Science Editors:

Chow AS. Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs. [Masters Thesis]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/40960


Oregon State University

16. Li, Qingwei. Efficient VLSI architectures for MIMO and cryptography systems.

Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University

 Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher… (more)

Subjects/Keywords: VLSI; Integrated circuits  – Very large scale integration  – Design and construction  – Mathematical models

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APA (6th Edition):

Li, Q. (2008). Efficient VLSI architectures for MIMO and cryptography systems. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/7521

Chicago Manual of Style (16th Edition):

Li, Qingwei. “Efficient VLSI architectures for MIMO and cryptography systems.” 2008. Doctoral Dissertation, Oregon State University. Accessed September 18, 2020. http://hdl.handle.net/1957/7521.

MLA Handbook (7th Edition):

Li, Qingwei. “Efficient VLSI architectures for MIMO and cryptography systems.” 2008. Web. 18 Sep 2020.

Vancouver:

Li Q. Efficient VLSI architectures for MIMO and cryptography systems. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/1957/7521.

Council of Science Editors:

Li Q. Efficient VLSI architectures for MIMO and cryptography systems. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/7521


Columbia University

17. Li, Jiangyi. Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications.

Degree: 2018, Columbia University

 Heading towards the era of Internet-of-things (IoT) means both opportunity and challenge for the circuit-design community. In a system where billions of devices are equipped… (more)

Subjects/Keywords: Electrical engineering; Internet of things; Electronic circuit design; Integrated circuits – Very large scale integration

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APA (6th Edition):

Li, J. (2018). Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8BG45XN

Chicago Manual of Style (16th Edition):

Li, Jiangyi. “Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications.” 2018. Doctoral Dissertation, Columbia University. Accessed September 18, 2020. https://doi.org/10.7916/D8BG45XN.

MLA Handbook (7th Edition):

Li, Jiangyi. “Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications.” 2018. Web. 18 Sep 2020.

Vancouver:

Li J. Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications. [Internet] [Doctoral dissertation]. Columbia University; 2018. [cited 2020 Sep 18]. Available from: https://doi.org/10.7916/D8BG45XN.

Council of Science Editors:

Li J. Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications. [Doctoral Dissertation]. Columbia University; 2018. Available from: https://doi.org/10.7916/D8BG45XN


Hong Kong University of Science and Technology

18. Mousavi, Mahsa ECE. VLSI architecture for list successive-cancellation decoding of polar codes.

Degree: 2017, Hong Kong University of Science and Technology

 List successive cancellation decoder (LSCD) architectures have been recently proposed for the decoding of polar codes to achieve high decoding performance. However the existing architectures… (more)

Subjects/Keywords: Coding theory ; Decoders (Electronics) ; Error-correcting codes (Information theory) ; Integrated circuits ; Very large scale integration

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APA (6th Edition):

Mousavi, M. E. (2017). VLSI architecture for list successive-cancellation decoding of polar codes. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-91064 ; https://doi.org/10.14711/thesis-991012554966003412 ; http://repository.ust.hk/ir/bitstream/1783.1-91064/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mousavi, Mahsa ECE. “VLSI architecture for list successive-cancellation decoding of polar codes.” 2017. Thesis, Hong Kong University of Science and Technology. Accessed September 18, 2020. http://repository.ust.hk/ir/Record/1783.1-91064 ; https://doi.org/10.14711/thesis-991012554966003412 ; http://repository.ust.hk/ir/bitstream/1783.1-91064/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mousavi, Mahsa ECE. “VLSI architecture for list successive-cancellation decoding of polar codes.” 2017. Web. 18 Sep 2020.

Vancouver:

Mousavi ME. VLSI architecture for list successive-cancellation decoding of polar codes. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2017. [cited 2020 Sep 18]. Available from: http://repository.ust.hk/ir/Record/1783.1-91064 ; https://doi.org/10.14711/thesis-991012554966003412 ; http://repository.ust.hk/ir/bitstream/1783.1-91064/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mousavi ME. VLSI architecture for list successive-cancellation decoding of polar codes. [Thesis]. Hong Kong University of Science and Technology; 2017. Available from: http://repository.ust.hk/ir/Record/1783.1-91064 ; https://doi.org/10.14711/thesis-991012554966003412 ; http://repository.ust.hk/ir/bitstream/1783.1-91064/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Florida Atlantic University

19. Gottipati, Chenchu B. Graph labeling and non-separating trees.

Degree: 2014, Florida Atlantic University

Summary: This dissertation studies two independent problems, one is about graph labeling and the other problem is related to connectivity condition in a simple graph.… (more)

Subjects/Keywords: Computational complexity; Computer graphics; Graph theory; Integrated circuits  – Very large scale integration; Mathematical optimization

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APA (6th Edition):

Gottipati, C. B. (2014). Graph labeling and non-separating trees. (Thesis). Florida Atlantic University. Retrieved from http://purl.flvc.org/fau/fd/FA00004289 ; (URL) http://purl.flvc.org/fau/fd/FA00004289

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gottipati, Chenchu B. “Graph labeling and non-separating trees.” 2014. Thesis, Florida Atlantic University. Accessed September 18, 2020. http://purl.flvc.org/fau/fd/FA00004289 ; (URL) http://purl.flvc.org/fau/fd/FA00004289.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gottipati, Chenchu B. “Graph labeling and non-separating trees.” 2014. Web. 18 Sep 2020.

Vancouver:

Gottipati CB. Graph labeling and non-separating trees. [Internet] [Thesis]. Florida Atlantic University; 2014. [cited 2020 Sep 18]. Available from: http://purl.flvc.org/fau/fd/FA00004289 ; (URL) http://purl.flvc.org/fau/fd/FA00004289.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gottipati CB. Graph labeling and non-separating trees. [Thesis]. Florida Atlantic University; 2014. Available from: http://purl.flvc.org/fau/fd/FA00004289 ; (URL) http://purl.flvc.org/fau/fd/FA00004289

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

20. Jafar, Mutaz, 1960-. THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING .

Degree: 1986, University of Arizona

Subjects/Keywords: Integrated circuits  – Very large scale integration.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jafar, Mutaz, 1. (1986). THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/276959

Chicago Manual of Style (16th Edition):

Jafar, Mutaz, 1960-. “THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING .” 1986. Masters Thesis, University of Arizona. Accessed September 18, 2020. http://hdl.handle.net/10150/276959.

MLA Handbook (7th Edition):

Jafar, Mutaz, 1960-. “THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING .” 1986. Web. 18 Sep 2020.

Vancouver:

Jafar, Mutaz 1. THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING . [Internet] [Masters thesis]. University of Arizona; 1986. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/10150/276959.

Council of Science Editors:

Jafar, Mutaz 1. THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING . [Masters Thesis]. University of Arizona; 1986. Available from: http://hdl.handle.net/10150/276959


University of Arizona

21. Voranantakul, Suwan, 1962-. CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES .

Degree: 1986, University of Arizona

Subjects/Keywords: Integrated circuits  – Very large scale integration.

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APA (6th Edition):

Voranantakul, Suwan, 1. (1986). CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/277037

Chicago Manual of Style (16th Edition):

Voranantakul, Suwan, 1962-. “CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES .” 1986. Masters Thesis, University of Arizona. Accessed September 18, 2020. http://hdl.handle.net/10150/277037.

MLA Handbook (7th Edition):

Voranantakul, Suwan, 1962-. “CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES .” 1986. Web. 18 Sep 2020.

Vancouver:

Voranantakul, Suwan 1. CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES . [Internet] [Masters thesis]. University of Arizona; 1986. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/10150/277037.

Council of Science Editors:

Voranantakul, Suwan 1. CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES . [Masters Thesis]. University of Arizona; 1986. Available from: http://hdl.handle.net/10150/277037


University of South Florida

22. Gurram, Venkata Lakshmi Bhargavi. Gate Level Probabilistic Simulation Based Hardware Trojan Susceptibility Analysis of Combinational Circuits.

Degree: 2018, University of South Florida

 Today multi-million gate integrated circuits are being commonly used in many critical (eg., health care) and sensitive (eg., military) applications. Therefore, they are susceptible to… (more)

Subjects/Keywords: Hardware Security; Logic Simulation; Trojan Trigger; Very-Large-Scale-Integration; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gurram, V. L. B. (2018). Gate Level Probabilistic Simulation Based Hardware Trojan Susceptibility Analysis of Combinational Circuits. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/8117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gurram, Venkata Lakshmi Bhargavi. “Gate Level Probabilistic Simulation Based Hardware Trojan Susceptibility Analysis of Combinational Circuits.” 2018. Thesis, University of South Florida. Accessed September 18, 2020. https://scholarcommons.usf.edu/etd/8117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gurram, Venkata Lakshmi Bhargavi. “Gate Level Probabilistic Simulation Based Hardware Trojan Susceptibility Analysis of Combinational Circuits.” 2018. Web. 18 Sep 2020.

Vancouver:

Gurram VLB. Gate Level Probabilistic Simulation Based Hardware Trojan Susceptibility Analysis of Combinational Circuits. [Internet] [Thesis]. University of South Florida; 2018. [cited 2020 Sep 18]. Available from: https://scholarcommons.usf.edu/etd/8117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gurram VLB. Gate Level Probabilistic Simulation Based Hardware Trojan Susceptibility Analysis of Combinational Circuits. [Thesis]. University of South Florida; 2018. Available from: https://scholarcommons.usf.edu/etd/8117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

23. Mitra, Sanjay Nirendra. VLSI implementation of a high speed systolic finite field constant multiplier.

Degree: MS, College of Engineering, 1991, Montana State University

Subjects/Keywords: Integrated circuits Very large scale integration.

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APA (6th Edition):

Mitra, S. N. (1991). VLSI implementation of a high speed systolic finite field constant multiplier. (Masters Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/7141

Chicago Manual of Style (16th Edition):

Mitra, Sanjay Nirendra. “VLSI implementation of a high speed systolic finite field constant multiplier.” 1991. Masters Thesis, Montana State University. Accessed September 18, 2020. https://scholarworks.montana.edu/xmlui/handle/1/7141.

MLA Handbook (7th Edition):

Mitra, Sanjay Nirendra. “VLSI implementation of a high speed systolic finite field constant multiplier.” 1991. Web. 18 Sep 2020.

Vancouver:

Mitra SN. VLSI implementation of a high speed systolic finite field constant multiplier. [Internet] [Masters thesis]. Montana State University; 1991. [cited 2020 Sep 18]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/7141.

Council of Science Editors:

Mitra SN. VLSI implementation of a high speed systolic finite field constant multiplier. [Masters Thesis]. Montana State University; 1991. Available from: https://scholarworks.montana.edu/xmlui/handle/1/7141


Indian Institute of Science

24. Rex, A. Physics Based Analytical Thermal Conductivity Model For Metallic Single Walled Carbon Nanotube.

Degree: MSc Engg, Faculty of Engineering, 2013, Indian Institute of Science

 Single-Walled Carbon Nanotube (SWCNT) based Very Large Scale Integrated circuit (VLSI) interconnect is one of the emerging technologies, and has the potential to overcome the… (more)

Subjects/Keywords: Single Walled Carbon Nanotube (SWCNT); Very Large Scale Integration; Metallic Single Walled Carbon Nanotube - Thermal Conductivity Model; Single Walled Carbon Nanotube Interconnect; Very Large Scale Integrated Circuit (VLSI); Nanotechnology

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APA (6th Edition):

Rex, A. (2013). Physics Based Analytical Thermal Conductivity Model For Metallic Single Walled Carbon Nanotube. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2096

Chicago Manual of Style (16th Edition):

Rex, A. “Physics Based Analytical Thermal Conductivity Model For Metallic Single Walled Carbon Nanotube.” 2013. Masters Thesis, Indian Institute of Science. Accessed September 18, 2020. http://etd.iisc.ac.in/handle/2005/2096.

MLA Handbook (7th Edition):

Rex, A. “Physics Based Analytical Thermal Conductivity Model For Metallic Single Walled Carbon Nanotube.” 2013. Web. 18 Sep 2020.

Vancouver:

Rex A. Physics Based Analytical Thermal Conductivity Model For Metallic Single Walled Carbon Nanotube. [Internet] [Masters thesis]. Indian Institute of Science; 2013. [cited 2020 Sep 18]. Available from: http://etd.iisc.ac.in/handle/2005/2096.

Council of Science Editors:

Rex A. Physics Based Analytical Thermal Conductivity Model For Metallic Single Walled Carbon Nanotube. [Masters Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ac.in/handle/2005/2096


University of Arizona

25. Matsumori, Barry Alan. QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS.

Degree: 1985, University of Arizona

Subjects/Keywords: Integrated circuits  – Very large scale integration  – Reliability.; Integrated circuits  – Large scale integration  – Reliability.

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APA (6th Edition):

Matsumori, B. A. (1985). QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/275313

Chicago Manual of Style (16th Edition):

Matsumori, Barry Alan. “QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. ” 1985. Masters Thesis, University of Arizona. Accessed September 18, 2020. http://hdl.handle.net/10150/275313.

MLA Handbook (7th Edition):

Matsumori, Barry Alan. “QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. ” 1985. Web. 18 Sep 2020.

Vancouver:

Matsumori BA. QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. [Internet] [Masters thesis]. University of Arizona; 1985. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/10150/275313.

Council of Science Editors:

Matsumori BA. QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. [Masters Thesis]. University of Arizona; 1985. Available from: http://hdl.handle.net/10150/275313


Ryerson University

26. Javaheri, Mohammad R.S. Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors.

Degree: 2010, Ryerson University

 Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration  – Testing; Integrated circuits  – Fault tolerance; Fault-tolerant computing; Field programmable gate arrays

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APA (6th Edition):

Javaheri, M. R. S. (2010). Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1855

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Javaheri, Mohammad R S. “Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors.” 2010. Thesis, Ryerson University. Accessed September 18, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A1855.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Javaheri, Mohammad R S. “Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors.” 2010. Web. 18 Sep 2020.

Vancouver:

Javaheri MRS. Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors. [Internet] [Thesis]. Ryerson University; 2010. [cited 2020 Sep 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1855.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Javaheri MRS. Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1855

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Hong Kong

27. Chu, Chung-kwan. Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling.

Degree: 2007, University of Hong Kong

Subjects/Keywords: Algorithms.; Integrated circuits - Very large scale integration - Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chu, C. (2007). Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling. (Thesis). University of Hong Kong. Retrieved from http://hdl.handle.net/10722/51480

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chu, Chung-kwan. “Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling.” 2007. Thesis, University of Hong Kong. Accessed September 18, 2020. http://hdl.handle.net/10722/51480.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chu, Chung-kwan. “Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling.” 2007. Web. 18 Sep 2020.

Vancouver:

Chu C. Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling. [Internet] [Thesis]. University of Hong Kong; 2007. [cited 2020 Sep 18]. Available from: http://hdl.handle.net/10722/51480.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chu C. Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling. [Thesis]. University of Hong Kong; 2007. Available from: http://hdl.handle.net/10722/51480

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

28. Mathana J M. Design of reconfigurable architecture for high performance turbo decoder;.

Degree: Reconfigurable architecture for High performance turbo decoder, 2014, Anna University

In digital communication error correction codes are the essential components to ensure robust digital applications Turbo code is one of the most attractive near Shannon… (more)

Subjects/Keywords: Digital communication error correction codes; High performance turbo decoder; Information and communication engineering; Very Large Scale Integration design

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APA (6th Edition):

M, M. J. (2014). Design of reconfigurable architecture for high performance turbo decoder;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/23594

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

M, Mathana J. “Design of reconfigurable architecture for high performance turbo decoder;.” 2014. Thesis, Anna University. Accessed September 18, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/23594.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

M, Mathana J. “Design of reconfigurable architecture for high performance turbo decoder;.” 2014. Web. 18 Sep 2020.

Vancouver:

M MJ. Design of reconfigurable architecture for high performance turbo decoder;. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Sep 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23594.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M MJ. Design of reconfigurable architecture for high performance turbo decoder;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23594

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Alberta

29. McKay, Ian A. CMOS square-wave oscillators.

Degree: MS, Department of Electrical Engineering, 1986, University of Alberta

Subjects/Keywords: Oscillators, Electric.; Integrated circuits – Very large scale integration.

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APA (6th Edition):

McKay, I. A. (1986). CMOS square-wave oscillators. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/9p290c51w

Chicago Manual of Style (16th Edition):

McKay, Ian A. “CMOS square-wave oscillators.” 1986. Masters Thesis, University of Alberta. Accessed September 18, 2020. https://era.library.ualberta.ca/files/9p290c51w.

MLA Handbook (7th Edition):

McKay, Ian A. “CMOS square-wave oscillators.” 1986. Web. 18 Sep 2020.

Vancouver:

McKay IA. CMOS square-wave oscillators. [Internet] [Masters thesis]. University of Alberta; 1986. [cited 2020 Sep 18]. Available from: https://era.library.ualberta.ca/files/9p290c51w.

Council of Science Editors:

McKay IA. CMOS square-wave oscillators. [Masters Thesis]. University of Alberta; 1986. Available from: https://era.library.ualberta.ca/files/9p290c51w


Portland State University

30. Park, Hoon. Formal Modeling and Verification of Delay-Insensitive Circuits.

Degree: PhD, Electrical and Computer Engineering, 2015, Portland State University

  Einstein's relativity theory tells us that the notion of simultaneity can only be approximated for events distributed over space. As a result, the use… (more)

Subjects/Keywords: Asynchronous circuits  – Design and construction; Integrated circuits  – Very large scale integration  – Design and construction; Digital Circuits; Electrical and Computer Engineering

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APA (6th Edition):

Park, H. (2015). Formal Modeling and Verification of Delay-Insensitive Circuits. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/2639

Chicago Manual of Style (16th Edition):

Park, Hoon. “Formal Modeling and Verification of Delay-Insensitive Circuits.” 2015. Doctoral Dissertation, Portland State University. Accessed September 18, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/2639.

MLA Handbook (7th Edition):

Park, Hoon. “Formal Modeling and Verification of Delay-Insensitive Circuits.” 2015. Web. 18 Sep 2020.

Vancouver:

Park H. Formal Modeling and Verification of Delay-Insensitive Circuits. [Internet] [Doctoral dissertation]. Portland State University; 2015. [cited 2020 Sep 18]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2639.

Council of Science Editors:

Park H. Formal Modeling and Verification of Delay-Insensitive Circuits. [Doctoral Dissertation]. Portland State University; 2015. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2639

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