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You searched for subject:(Verilog Computer hardware description language ). Showing records 1 – 30 of 128511 total matches.

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Florida Atlantic University

1. Cividanes, Ernesto. Smart low power obstacle avoidance device.

Degree: M.S.C.S., 2010, Florida Atlantic University

Summary: Several technologies are being made available for the blind and the visually impaired with the use of infrared and sonar sensors, Radio Frequency Identification,… (more)

Subjects/Keywords: Verilog (Computer hardware description language); VHDL (Computer hardware description language); Rapid prototyping; Logic design; Intelligent control systems; Brain-computer interfaces

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APA (6th Edition):

Cividanes, E. (2010). Smart low power obstacle avoidance device. (Masters Thesis). Florida Atlantic University. Retrieved from http://purl.flvc.org/FAU/2954841

Chicago Manual of Style (16th Edition):

Cividanes, Ernesto. “Smart low power obstacle avoidance device.” 2010. Masters Thesis, Florida Atlantic University. Accessed June 24, 2019. http://purl.flvc.org/FAU/2954841.

MLA Handbook (7th Edition):

Cividanes, Ernesto. “Smart low power obstacle avoidance device.” 2010. Web. 24 Jun 2019.

Vancouver:

Cividanes E. Smart low power obstacle avoidance device. [Internet] [Masters thesis]. Florida Atlantic University; 2010. [cited 2019 Jun 24]. Available from: http://purl.flvc.org/FAU/2954841.

Council of Science Editors:

Cividanes E. Smart low power obstacle avoidance device. [Masters Thesis]. Florida Atlantic University; 2010. Available from: http://purl.flvc.org/FAU/2954841


NSYSU

2. Wu, Cheng-tao. Software Implementation of a Configurable Design of Control Units of Pipeline Processors.

Degree: Master, Electrical Engineering, 2014, NSYSU

 CPU(Central Processing Unit) is one of the important parts in an electric computer. Controller definitely plays an important role in the CPU. Different processor architectures… (more)

Subjects/Keywords: Verilog; computer aided design; architecture description language; controller; pipeline processor

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APA (6th Edition):

Wu, C. (2014). Software Implementation of a Configurable Design of Control Units of Pipeline Processors. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Cheng-tao. “Software Implementation of a Configurable Design of Control Units of Pipeline Processors.” 2014. Thesis, NSYSU. Accessed June 24, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Cheng-tao. “Software Implementation of a Configurable Design of Control Units of Pipeline Processors.” 2014. Web. 24 Jun 2019.

Vancouver:

Wu C. Software Implementation of a Configurable Design of Control Units of Pipeline Processors. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jun 24]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. Software Implementation of a Configurable Design of Control Units of Pipeline Processors. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

3. Arshi, Taymoor. Bagit : a very high level language for application programming.

Degree: PhD, Computer Science, 1982, Oregon State University

 Very High Level Languages (VHLL) provide higher level abstractions and more powerful primitives than high level languages (HLL). A programmer uses these abstractions to solve… (more)

Subjects/Keywords: VHDL (Computer hardware description language)

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APA (6th Edition):

Arshi, T. (1982). Bagit : a very high level language for application programming. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/41788

Chicago Manual of Style (16th Edition):

Arshi, Taymoor. “Bagit : a very high level language for application programming.” 1982. Doctoral Dissertation, Oregon State University. Accessed June 24, 2019. http://hdl.handle.net/1957/41788.

MLA Handbook (7th Edition):

Arshi, Taymoor. “Bagit : a very high level language for application programming.” 1982. Web. 24 Jun 2019.

Vancouver:

Arshi T. Bagit : a very high level language for application programming. [Internet] [Doctoral dissertation]. Oregon State University; 1982. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/1957/41788.

Council of Science Editors:

Arshi T. Bagit : a very high level language for application programming. [Doctoral Dissertation]. Oregon State University; 1982. Available from: http://hdl.handle.net/1957/41788


University of Kentucky

4. Crutchfield, David Allen. VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS.

Degree: 2009, University of Kentucky

 Verification and debug of integrated circuits for embedded applications has grown in importance as the complexity in function has increased dramatically over time. Various modeling… (more)

Subjects/Keywords: C Modeling; Hardware Description Language; Verification; Debug; Testbench Portability; Electrical and Computer Engineering

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APA (6th Edition):

Crutchfield, D. A. (2009). VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/gradschool_theses/631

Chicago Manual of Style (16th Edition):

Crutchfield, David Allen. “VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS.” 2009. Masters Thesis, University of Kentucky. Accessed June 24, 2019. http://uknowledge.uky.edu/gradschool_theses/631.

MLA Handbook (7th Edition):

Crutchfield, David Allen. “VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS.” 2009. Web. 24 Jun 2019.

Vancouver:

Crutchfield DA. VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS. [Internet] [Masters thesis]. University of Kentucky; 2009. [cited 2019 Jun 24]. Available from: http://uknowledge.uky.edu/gradschool_theses/631.

Council of Science Editors:

Crutchfield DA. VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS. [Masters Thesis]. University of Kentucky; 2009. Available from: http://uknowledge.uky.edu/gradschool_theses/631


Michigan State University

5. Lee, Jin-Hyung. VHDL modeling techniques and design verification.

Degree: MS, Department of Computer Science, 1990, Michigan State University

Subjects/Keywords: VHDL (Computer hardware description language); Computers – Circuits; Computer hardware description languages

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APA (6th Edition):

Lee, J. (1990). VHDL modeling techniques and design verification. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:20736

Chicago Manual of Style (16th Edition):

Lee, Jin-Hyung. “VHDL modeling techniques and design verification.” 1990. Masters Thesis, Michigan State University. Accessed June 24, 2019. http://etd.lib.msu.edu/islandora/object/etd:20736.

MLA Handbook (7th Edition):

Lee, Jin-Hyung. “VHDL modeling techniques and design verification.” 1990. Web. 24 Jun 2019.

Vancouver:

Lee J. VHDL modeling techniques and design verification. [Internet] [Masters thesis]. Michigan State University; 1990. [cited 2019 Jun 24]. Available from: http://etd.lib.msu.edu/islandora/object/etd:20736.

Council of Science Editors:

Lee J. VHDL modeling techniques and design verification. [Masters Thesis]. Michigan State University; 1990. Available from: http://etd.lib.msu.edu/islandora/object/etd:20736


University of Missouri – Columbia

6. Zhu, Nan. PCI bus connects MizzouRISC to PC.

Degree: 2011, University of Missouri – Columbia

 This paper covers the design of a PCI transmission controller to make a 32-bit microprocessor MizzouRISC be a co-processor for a PC. The co-processor communicates… (more)

Subjects/Keywords: PCI bus (Computer bus); VHDL (Computer hardware description language); Field programmable gate arrays; Reduced instruction set computers; Image processing  – Computer programs

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APA (6th Edition):

Zhu, N. (2011). PCI bus connects MizzouRISC to PC. (Thesis). University of Missouri – Columbia. Retrieved from http://hdl.handle.net/10355/11526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhu, Nan. “PCI bus connects MizzouRISC to PC.” 2011. Thesis, University of Missouri – Columbia. Accessed June 24, 2019. http://hdl.handle.net/10355/11526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhu, Nan. “PCI bus connects MizzouRISC to PC.” 2011. Web. 24 Jun 2019.

Vancouver:

Zhu N. PCI bus connects MizzouRISC to PC. [Internet] [Thesis]. University of Missouri – Columbia; 2011. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/10355/11526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhu N. PCI bus connects MizzouRISC to PC. [Thesis]. University of Missouri – Columbia; 2011. Available from: http://hdl.handle.net/10355/11526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Victoria

7. Martin, Johannes. Ephedra: a C to Java migration environment.

Degree: Department of Computer Science, 2018, University of Victoria

 The Internet has grown in popularity in recent years, and thus it has gained importance for many current businesses. They need to offer their products… (more)

Subjects/Keywords: Computer hardware description languages; Methodology; Specifications

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APA (6th Edition):

Martin, J. (2018). Ephedra: a C to Java migration environment. (Thesis). University of Victoria. Retrieved from https://dspace.library.uvic.ca//handle/1828/10202

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Martin, Johannes. “Ephedra: a C to Java migration environment.” 2018. Thesis, University of Victoria. Accessed June 24, 2019. https://dspace.library.uvic.ca//handle/1828/10202.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Martin, Johannes. “Ephedra: a C to Java migration environment.” 2018. Web. 24 Jun 2019.

Vancouver:

Martin J. Ephedra: a C to Java migration environment. [Internet] [Thesis]. University of Victoria; 2018. [cited 2019 Jun 24]. Available from: https://dspace.library.uvic.ca//handle/1828/10202.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Martin J. Ephedra: a C to Java migration environment. [Thesis]. University of Victoria; 2018. Available from: https://dspace.library.uvic.ca//handle/1828/10202

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Victoria

8. Costi, Claudio. A methodology for analyzing hardware description language specifications of legacy designs.

Degree: Department of Computer Science, 2018, University of Victoria

 In order to increase productivity, methodologies based on reuse of previously designed components are exploited by the Integrated Circuit (IC) design community. However, designers are… (more)

Subjects/Keywords: Computer hardware description languages; Specifications, Methodology

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APA (6th Edition):

Costi, C. (2018). A methodology for analyzing hardware description language specifications of legacy designs. (Thesis). University of Victoria. Retrieved from https://dspace.library.uvic.ca//handle/1828/9428

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Costi, Claudio. “A methodology for analyzing hardware description language specifications of legacy designs.” 2018. Thesis, University of Victoria. Accessed June 24, 2019. https://dspace.library.uvic.ca//handle/1828/9428.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Costi, Claudio. “A methodology for analyzing hardware description language specifications of legacy designs.” 2018. Web. 24 Jun 2019.

Vancouver:

Costi C. A methodology for analyzing hardware description language specifications of legacy designs. [Internet] [Thesis]. University of Victoria; 2018. [cited 2019 Jun 24]. Available from: https://dspace.library.uvic.ca//handle/1828/9428.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Costi C. A methodology for analyzing hardware description language specifications of legacy designs. [Thesis]. University of Victoria; 2018. Available from: https://dspace.library.uvic.ca//handle/1828/9428

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Kentucky

9. Sparks, Matthew A. A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE.

Degree: 2013, University of Kentucky

 Modern processor architectures suffer from an ever increasing gap between processor and memory performance. The current memory-register model attempts to hide this gap by a… (more)

Subjects/Keywords: Line Associative Registers; Hardware Description Language; Memory Caching; Ambiguous Alias; Computer Arithmetic; Computer and Systems Architecture

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APA (6th Edition):

Sparks, M. A. (2013). A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/26

Chicago Manual of Style (16th Edition):

Sparks, Matthew A. “A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE.” 2013. Masters Thesis, University of Kentucky. Accessed June 24, 2019. http://uknowledge.uky.edu/ece_etds/26.

MLA Handbook (7th Edition):

Sparks, Matthew A. “A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE.” 2013. Web. 24 Jun 2019.

Vancouver:

Sparks MA. A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2019 Jun 24]. Available from: http://uknowledge.uky.edu/ece_etds/26.

Council of Science Editors:

Sparks MA. A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE. [Masters Thesis]. University of Kentucky; 2013. Available from: http://uknowledge.uky.edu/ece_etds/26


Michigan State University

10. Keshavachandra, C. K. Modeling artificial neural networks using VHDL.

Degree: MS, Department of Electrical Engineering, 1990, Michigan State University

Subjects/Keywords: Neural networks (Computer science); VHDL (Computer hardware description language)

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APA (6th Edition):

Keshavachandra, C. K. (1990). Modeling artificial neural networks using VHDL. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:20657

Chicago Manual of Style (16th Edition):

Keshavachandra, C K. “Modeling artificial neural networks using VHDL.” 1990. Masters Thesis, Michigan State University. Accessed June 24, 2019. http://etd.lib.msu.edu/islandora/object/etd:20657.

MLA Handbook (7th Edition):

Keshavachandra, C K. “Modeling artificial neural networks using VHDL.” 1990. Web. 24 Jun 2019.

Vancouver:

Keshavachandra CK. Modeling artificial neural networks using VHDL. [Internet] [Masters thesis]. Michigan State University; 1990. [cited 2019 Jun 24]. Available from: http://etd.lib.msu.edu/islandora/object/etd:20657.

Council of Science Editors:

Keshavachandra CK. Modeling artificial neural networks using VHDL. [Masters Thesis]. Michigan State University; 1990. Available from: http://etd.lib.msu.edu/islandora/object/etd:20657


Michigan State University

11. Pierce, David Barnard. Analysis of neural network response with varied neuron models and interconnection patterns.

Degree: MS, Department of Electrical Engineering, 1991, Michigan State University

Subjects/Keywords: Neural networks (Computer science); VHDL (Computer hardware description language)

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APA (6th Edition):

Pierce, D. B. (1991). Analysis of neural network response with varied neuron models and interconnection patterns. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:21564

Chicago Manual of Style (16th Edition):

Pierce, David Barnard. “Analysis of neural network response with varied neuron models and interconnection patterns.” 1991. Masters Thesis, Michigan State University. Accessed June 24, 2019. http://etd.lib.msu.edu/islandora/object/etd:21564.

MLA Handbook (7th Edition):

Pierce, David Barnard. “Analysis of neural network response with varied neuron models and interconnection patterns.” 1991. Web. 24 Jun 2019.

Vancouver:

Pierce DB. Analysis of neural network response with varied neuron models and interconnection patterns. [Internet] [Masters thesis]. Michigan State University; 1991. [cited 2019 Jun 24]. Available from: http://etd.lib.msu.edu/islandora/object/etd:21564.

Council of Science Editors:

Pierce DB. Analysis of neural network response with varied neuron models and interconnection patterns. [Masters Thesis]. Michigan State University; 1991. Available from: http://etd.lib.msu.edu/islandora/object/etd:21564


Virginia Tech

12. Shah, Sandeep R. A framework for synthesis from VHDL.

Degree: MS, Electrical Engineering, 1991, Virginia Tech

Subjects/Keywords: VHDL (Computer hardware description language); LD5655.V855 1991.S523

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APA (6th Edition):

Shah, S. R. (1991). A framework for synthesis from VHDL. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/41322

Chicago Manual of Style (16th Edition):

Shah, Sandeep R. “A framework for synthesis from VHDL.” 1991. Masters Thesis, Virginia Tech. Accessed June 24, 2019. http://hdl.handle.net/10919/41322.

MLA Handbook (7th Edition):

Shah, Sandeep R. “A framework for synthesis from VHDL.” 1991. Web. 24 Jun 2019.

Vancouver:

Shah SR. A framework for synthesis from VHDL. [Internet] [Masters thesis]. Virginia Tech; 1991. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/10919/41322.

Council of Science Editors:

Shah SR. A framework for synthesis from VHDL. [Masters Thesis]. Virginia Tech; 1991. Available from: http://hdl.handle.net/10919/41322


Virginia Tech

13. Wright, Philip A. Rapid development of VHDL behavioral models.

Degree: MS, Electrical Engineering, 1992, Virginia Tech

Subjects/Keywords: VHDL (Computer hardware description language); LD5655.V855 1992.W754

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APA (6th Edition):

Wright, P. A. (1992). Rapid development of VHDL behavioral models. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/45596

Chicago Manual of Style (16th Edition):

Wright, Philip A. “Rapid development of VHDL behavioral models.” 1992. Masters Thesis, Virginia Tech. Accessed June 24, 2019. http://hdl.handle.net/10919/45596.

MLA Handbook (7th Edition):

Wright, Philip A. “Rapid development of VHDL behavioral models.” 1992. Web. 24 Jun 2019.

Vancouver:

Wright PA. Rapid development of VHDL behavioral models. [Internet] [Masters thesis]. Virginia Tech; 1992. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/10919/45596.

Council of Science Editors:

Wright PA. Rapid development of VHDL behavioral models. [Masters Thesis]. Virginia Tech; 1992. Available from: http://hdl.handle.net/10919/45596


Virginia Tech

14. Dailey, David M. Integration of VHDL simulation and test verification into a Process Model Graph design environment.

Degree: MS, Electrical Engineering, 1994, Virginia Tech

 This thesis discusses the ability to maintain a consistent design, simulation, and test verification environment by use of the Process Model Graph (PMG) throughout the… (more)

Subjects/Keywords: VHDL (Computer hardware description language); LD5655.V855 1994.D355

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APA (6th Edition):

Dailey, D. M. (1994). Integration of VHDL simulation and test verification into a Process Model Graph design environment. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46017

Chicago Manual of Style (16th Edition):

Dailey, David M. “Integration of VHDL simulation and test verification into a Process Model Graph design environment.” 1994. Masters Thesis, Virginia Tech. Accessed June 24, 2019. http://hdl.handle.net/10919/46017.

MLA Handbook (7th Edition):

Dailey, David M. “Integration of VHDL simulation and test verification into a Process Model Graph design environment.” 1994. Web. 24 Jun 2019.

Vancouver:

Dailey DM. Integration of VHDL simulation and test verification into a Process Model Graph design environment. [Internet] [Masters thesis]. Virginia Tech; 1994. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/10919/46017.

Council of Science Editors:

Dailey DM. Integration of VHDL simulation and test verification into a Process Model Graph design environment. [Masters Thesis]. Virginia Tech; 1994. Available from: http://hdl.handle.net/10919/46017


Virginia Tech

15. Chadha, Vikrampal. Simulation of large-scale system-level models.

Degree: MS, Electrical Engineering, 1994, Virginia Tech

see document Advisors/Committee Members: Davis, Nathaniel J. IV (committeechair), Armstrong, James R. (committee member), Gray, Festus Gail (committee member).

Subjects/Keywords: VHDL (Computer hardware description language); LD5655.V855 1994.C522

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APA (6th Edition):

Chadha, V. (1994). Simulation of large-scale system-level models. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46256

Chicago Manual of Style (16th Edition):

Chadha, Vikrampal. “Simulation of large-scale system-level models.” 1994. Masters Thesis, Virginia Tech. Accessed June 24, 2019. http://hdl.handle.net/10919/46256.

MLA Handbook (7th Edition):

Chadha, Vikrampal. “Simulation of large-scale system-level models.” 1994. Web. 24 Jun 2019.

Vancouver:

Chadha V. Simulation of large-scale system-level models. [Internet] [Masters thesis]. Virginia Tech; 1994. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/10919/46256.

Council of Science Editors:

Chadha V. Simulation of large-scale system-level models. [Masters Thesis]. Virginia Tech; 1994. Available from: http://hdl.handle.net/10919/46256


Virginia Tech

16. Rao, Sanat R. A hierarchical approach to effective test generation for VHDL behavioral models.

Degree: MS, Electrical Engineering, 1993, Virginia Tech

Subjects/Keywords: VHDL (Computer hardware description language); LD5655.V855 1993.R36

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APA (6th Edition):

Rao, S. R. (1993). A hierarchical approach to effective test generation for VHDL behavioral models. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/44175

Chicago Manual of Style (16th Edition):

Rao, Sanat R. “A hierarchical approach to effective test generation for VHDL behavioral models.” 1993. Masters Thesis, Virginia Tech. Accessed June 24, 2019. http://hdl.handle.net/10919/44175.

MLA Handbook (7th Edition):

Rao, Sanat R. “A hierarchical approach to effective test generation for VHDL behavioral models.” 1993. Web. 24 Jun 2019.

Vancouver:

Rao SR. A hierarchical approach to effective test generation for VHDL behavioral models. [Internet] [Masters thesis]. Virginia Tech; 1993. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/10919/44175.

Council of Science Editors:

Rao SR. A hierarchical approach to effective test generation for VHDL behavioral models. [Masters Thesis]. Virginia Tech; 1993. Available from: http://hdl.handle.net/10919/44175


Virginia Tech

17. Manek, Meenakshi. Natural language interface to a VHDL modeling tool.

Degree: MS, Electrical Engineering, 1993, Virginia Tech

 This thesis describes a Natural Language (NL) interface to a VHDL modeling tool called the Modeler's Assistant. The primary motivation for the interface developed in… (more)

Subjects/Keywords: VHDL (Computer hardware description language); LD5655.V855 1993.M263

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APA (6th Edition):

Manek, M. (1993). Natural language interface to a VHDL modeling tool. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/43427

Chicago Manual of Style (16th Edition):

Manek, Meenakshi. “Natural language interface to a VHDL modeling tool.” 1993. Masters Thesis, Virginia Tech. Accessed June 24, 2019. http://hdl.handle.net/10919/43427.

MLA Handbook (7th Edition):

Manek, Meenakshi. “Natural language interface to a VHDL modeling tool.” 1993. Web. 24 Jun 2019.

Vancouver:

Manek M. Natural language interface to a VHDL modeling tool. [Internet] [Masters thesis]. Virginia Tech; 1993. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/10919/43427.

Council of Science Editors:

Manek M. Natural language interface to a VHDL modeling tool. [Masters Thesis]. Virginia Tech; 1993. Available from: http://hdl.handle.net/10919/43427


Virginia Tech

18. Sama, Anil. Behavior modeling of RF systems with VHDL.

Degree: MS, Electrical Engineering, 1991, Virginia Tech

Subjects/Keywords: VHDL (Computer hardware description language); LD5655.V855 1991.S262

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APA (6th Edition):

Sama, A. (1991). Behavior modeling of RF systems with VHDL. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/45122

Chicago Manual of Style (16th Edition):

Sama, Anil. “Behavior modeling of RF systems with VHDL.” 1991. Masters Thesis, Virginia Tech. Accessed June 24, 2019. http://hdl.handle.net/10919/45122.

MLA Handbook (7th Edition):

Sama, Anil. “Behavior modeling of RF systems with VHDL.” 1991. Web. 24 Jun 2019.

Vancouver:

Sama A. Behavior modeling of RF systems with VHDL. [Internet] [Masters thesis]. Virginia Tech; 1991. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/10919/45122.

Council of Science Editors:

Sama A. Behavior modeling of RF systems with VHDL. [Masters Thesis]. Virginia Tech; 1991. Available from: http://hdl.handle.net/10919/45122


University of Kentucky

19. Bondehagen, Brent. FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT.

Degree: 2013, University of Kentucky

 Structured Light Illumination (SLI) is the process where spatially varied patterns are projected onto a 3-D surface and based on the distortion by the surface… (more)

Subjects/Keywords: Structured Light Illumination; Phase Measuring Profilometry; 3-D Shape Measurement; Hardware Description Language; Processor Architecture; Computer and Systems Architecture; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Bondehagen, B. (2013). FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/23

Chicago Manual of Style (16th Edition):

Bondehagen, Brent. “FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT.” 2013. Masters Thesis, University of Kentucky. Accessed June 24, 2019. http://uknowledge.uky.edu/ece_etds/23.

MLA Handbook (7th Edition):

Bondehagen, Brent. “FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT.” 2013. Web. 24 Jun 2019.

Vancouver:

Bondehagen B. FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2019 Jun 24]. Available from: http://uknowledge.uky.edu/ece_etds/23.

Council of Science Editors:

Bondehagen B. FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT. [Masters Thesis]. University of Kentucky; 2013. Available from: http://uknowledge.uky.edu/ece_etds/23


Universidade Estadual de Campinas

20. Thiago Massariolli Sigrist. Restructuring of ArchC for integration to TLM-based project.

Degree: Instituto de Computação, 2007, Universidade Estadual de Campinas

The advent of SoCs (Systems-on-Chip) lead to the development of project methodologies based on TLM (Transaction-Level Modelling), which consist of several modelling layers between pure… (more)

Subjects/Keywords: Simulação (Computadores digitais) - Metodos de simulação; Digital computer simulation; Hardware - Linguagens descritivas; Hardware - Arquitetura; Computer hardware description languages; Hardware

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sigrist, T. M. (2007). Restructuring of ArchC for integration to TLM-based project. (Thesis). Universidade Estadual de Campinas. Retrieved from http://libdigi.unicamp.br/document/?code=vtls000417851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sigrist, Thiago Massariolli. “Restructuring of ArchC for integration to TLM-based project.” 2007. Thesis, Universidade Estadual de Campinas. Accessed June 24, 2019. http://libdigi.unicamp.br/document/?code=vtls000417851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sigrist, Thiago Massariolli. “Restructuring of ArchC for integration to TLM-based project.” 2007. Web. 24 Jun 2019.

Vancouver:

Sigrist TM. Restructuring of ArchC for integration to TLM-based project. [Internet] [Thesis]. Universidade Estadual de Campinas; 2007. [cited 2019 Jun 24]. Available from: http://libdigi.unicamp.br/document/?code=vtls000417851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sigrist TM. Restructuring of ArchC for integration to TLM-based project. [Thesis]. Universidade Estadual de Campinas; 2007. Available from: http://libdigi.unicamp.br/document/?code=vtls000417851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kansas State University

21. Bartel, Lester. Computer architecture simulation using a register transfer language.

Degree: MS, Computing and Information Sciences, 1986, Kansas State University

Subjects/Keywords: ASIM II (Computer program language); Computer architecture.; Computer hardware description languages.; Masters theses

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bartel, L. (1986). Computer architecture simulation using a register transfer language. (Masters Thesis). Kansas State University. Retrieved from http://hdl.handle.net/2097/27589

Chicago Manual of Style (16th Edition):

Bartel, Lester. “Computer architecture simulation using a register transfer language.” 1986. Masters Thesis, Kansas State University. Accessed June 24, 2019. http://hdl.handle.net/2097/27589.

MLA Handbook (7th Edition):

Bartel, Lester. “Computer architecture simulation using a register transfer language.” 1986. Web. 24 Jun 2019.

Vancouver:

Bartel L. Computer architecture simulation using a register transfer language. [Internet] [Masters thesis]. Kansas State University; 1986. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/2097/27589.

Council of Science Editors:

Bartel L. Computer architecture simulation using a register transfer language. [Masters Thesis]. Kansas State University; 1986. Available from: http://hdl.handle.net/2097/27589


Brno University of Technology

22. Nouman, Ziad. Užití programovatelných hradlových polí v systémech průmyslové automatizace .

Degree: 2016, Brno University of Technology

 Tato disertační práce se zabývá využitím programovatelných hradlových polí (FPGA) v diagnostice měničů, využívajících spínaných IGBT tranzistorů. Je zaměřena na budiče těchto výkonových tranzistorů a… (more)

Subjects/Keywords: Detekce poruch a diagnostika (FDD); Řízení odolné vůči poruchám (FTC); Programovatelné hradlové pole (FPGA); Tranzistor IGBT; Budič; Analogově-digitální převodník; monitoring; PC deska; redundance; Jazyk VHDL; Verilog; Rychlá Fourierova transformace (FFT); DDR2-SDRAM.; Fault detection and diagnosis (FDD); Fault Tolerant Control (FTC); Field Programmable Gate Arrays (FPGA); Insulated-Gate Bipolar Transistor (IGBT); gate drive; ADC; monitoring; PC board; redundancy; Very High Speed Integrated Circuit Hardware Description Language(VHDL); Verilog; Fast Fourier Transform (FFT); DDR2SDRAM; Industrial automation.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nouman, Z. (2016). Užití programovatelných hradlových polí v systémech průmyslové automatizace . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/51916

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nouman, Ziad. “Užití programovatelných hradlových polí v systémech průmyslové automatizace .” 2016. Thesis, Brno University of Technology. Accessed June 24, 2019. http://hdl.handle.net/11012/51916.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nouman, Ziad. “Užití programovatelných hradlových polí v systémech průmyslové automatizace .” 2016. Web. 24 Jun 2019.

Vancouver:

Nouman Z. Užití programovatelných hradlových polí v systémech průmyslové automatizace . [Internet] [Thesis]. Brno University of Technology; 2016. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/11012/51916.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nouman Z. Užití programovatelných hradlových polí v systémech průmyslové automatizace . [Thesis]. Brno University of Technology; 2016. Available from: http://hdl.handle.net/11012/51916

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Portland State University

23. Palanisamy, Karthikeyan. High Level Preprocessor of a VHDL-based Design System.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 1994, Portland State University

  This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system… (more)

Subjects/Keywords: Electronic digital computers  – Circuits  – Design; VHDL (Computer hardware description language); ADL (Computer hardware description language); Computer algorithms; DIADES (Computer program); Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Palanisamy, K. (1994). High Level Preprocessor of a VHDL-based Design System. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/4776

Chicago Manual of Style (16th Edition):

Palanisamy, Karthikeyan. “High Level Preprocessor of a VHDL-based Design System.” 1994. Masters Thesis, Portland State University. Accessed June 24, 2019. https://pdxscholar.library.pdx.edu/open_access_etds/4776.

MLA Handbook (7th Edition):

Palanisamy, Karthikeyan. “High Level Preprocessor of a VHDL-based Design System.” 1994. Web. 24 Jun 2019.

Vancouver:

Palanisamy K. High Level Preprocessor of a VHDL-based Design System. [Internet] [Masters thesis]. Portland State University; 1994. [cited 2019 Jun 24]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4776.

Council of Science Editors:

Palanisamy K. High Level Preprocessor of a VHDL-based Design System. [Masters Thesis]. Portland State University; 1994. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4776

24. Juliusson, David. Development of a SpaceWire interface in VHDL.

Degree: 2012, Chalmers University of Technology

 In space, as on earth, there is a need for fast, reliable and reusable point-to-point data communication. The SpaceWire standard developed by the European Space… (more)

Subjects/Keywords: VHDL (VHSIC Hardware Description Language); Codec; SpaceWire; ESA

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APA (6th Edition):

Juliusson, D. (2012). Development of a SpaceWire interface in VHDL. (Thesis). Chalmers University of Technology. Retrieved from http://studentarbeten.chalmers.se/publication/157904-development-of-a-spacewire-interface-in-vhdl

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Juliusson, David. “Development of a SpaceWire interface in VHDL.” 2012. Thesis, Chalmers University of Technology. Accessed June 24, 2019. http://studentarbeten.chalmers.se/publication/157904-development-of-a-spacewire-interface-in-vhdl.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Juliusson, David. “Development of a SpaceWire interface in VHDL.” 2012. Web. 24 Jun 2019.

Vancouver:

Juliusson D. Development of a SpaceWire interface in VHDL. [Internet] [Thesis]. Chalmers University of Technology; 2012. [cited 2019 Jun 24]. Available from: http://studentarbeten.chalmers.se/publication/157904-development-of-a-spacewire-interface-in-vhdl.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Juliusson D. Development of a SpaceWire interface in VHDL. [Thesis]. Chalmers University of Technology; 2012. Available from: http://studentarbeten.chalmers.se/publication/157904-development-of-a-spacewire-interface-in-vhdl

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Northeastern University

25. Fang, Xin. Variable precision floating point reciprocal, division and square root for major FPGA vendors.

Degree: MS, Department of Electrical and Computer Engineering, 2013, Northeastern University

 Variable precision floating point operations have various fields of applications including scientific computing and signal processing. Field Programmable Gate Arrays (FPGAs) are a good platform… (more)

Subjects/Keywords: Field Programmable Gate Arrays; variable precision floating point operations; Very High Speed Integrated Circuits Hardware Description Language; Computer Engineering; Electrical and Computer Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fang, X. (2013). Variable precision floating point reciprocal, division and square root for major FPGA vendors. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20003323

Chicago Manual of Style (16th Edition):

Fang, Xin. “Variable precision floating point reciprocal, division and square root for major FPGA vendors.” 2013. Masters Thesis, Northeastern University. Accessed June 24, 2019. http://hdl.handle.net/2047/d20003323.

MLA Handbook (7th Edition):

Fang, Xin. “Variable precision floating point reciprocal, division and square root for major FPGA vendors.” 2013. Web. 24 Jun 2019.

Vancouver:

Fang X. Variable precision floating point reciprocal, division and square root for major FPGA vendors. [Internet] [Masters thesis]. Northeastern University; 2013. [cited 2019 Jun 24]. Available from: http://hdl.handle.net/2047/d20003323.

Council of Science Editors:

Fang X. Variable precision floating point reciprocal, division and square root for major FPGA vendors. [Masters Thesis]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20003323


Michigan State University

26. Yang, Mai. Front end interface for parallel VHDL simulations.

Degree: PhD, Computer Science Dept., 1998, Michigan State University

Subjects/Keywords: VHDL (Computer hardware description language); Digital electronics – Computer simulation; Parallel processing (Electronic computers)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, M. (1998). Front end interface for parallel VHDL simulations. (Doctoral Dissertation). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:26896

Chicago Manual of Style (16th Edition):

Yang, Mai. “Front end interface for parallel VHDL simulations.” 1998. Doctoral Dissertation, Michigan State University. Accessed June 24, 2019. http://etd.lib.msu.edu/islandora/object/etd:26896.

MLA Handbook (7th Edition):

Yang, Mai. “Front end interface for parallel VHDL simulations.” 1998. Web. 24 Jun 2019.

Vancouver:

Yang M. Front end interface for parallel VHDL simulations. [Internet] [Doctoral dissertation]. Michigan State University; 1998. [cited 2019 Jun 24]. Available from: http://etd.lib.msu.edu/islandora/object/etd:26896.

Council of Science Editors:

Yang M. Front end interface for parallel VHDL simulations. [Doctoral Dissertation]. Michigan State University; 1998. Available from: http://etd.lib.msu.edu/islandora/object/etd:26896


Michigan State University

27. Wright, Ronnie Lee. A methodology for behavioral-level switching activity estimation in CMOS circuits.

Degree: PhD, Department of Electrical and Computer Engineering, 1999, Michigan State University

Subjects/Keywords: Metal oxide semiconductors, Complementary – Computer-aided design; VHDL (Computer hardware description language)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wright, R. L. (1999). A methodology for behavioral-level switching activity estimation in CMOS circuits. (Doctoral Dissertation). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:28474

Chicago Manual of Style (16th Edition):

Wright, Ronnie Lee. “A methodology for behavioral-level switching activity estimation in CMOS circuits.” 1999. Doctoral Dissertation, Michigan State University. Accessed June 24, 2019. http://etd.lib.msu.edu/islandora/object/etd:28474.

MLA Handbook (7th Edition):

Wright, Ronnie Lee. “A methodology for behavioral-level switching activity estimation in CMOS circuits.” 1999. Web. 24 Jun 2019.

Vancouver:

Wright RL. A methodology for behavioral-level switching activity estimation in CMOS circuits. [Internet] [Doctoral dissertation]. Michigan State University; 1999. [cited 2019 Jun 24]. Available from: http://etd.lib.msu.edu/islandora/object/etd:28474.

Council of Science Editors:

Wright RL. A methodology for behavioral-level switching activity estimation in CMOS circuits. [Doctoral Dissertation]. Michigan State University; 1999. Available from: http://etd.lib.msu.edu/islandora/object/etd:28474


Michigan State University

28. Choi, Sea H. (Sea Hawon). Design methodology in high level synthesis.

Degree: PhD, Department of Computer Science, 1995, Michigan State University

Subjects/Keywords: System design; Computer-aided design; VHDL (Computer hardware description language)

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APA (6th Edition):

Choi, S. H. (. H. (1995). Design methodology in high level synthesis. (Doctoral Dissertation). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:25385

Chicago Manual of Style (16th Edition):

Choi, Sea H (Sea Hawon). “Design methodology in high level synthesis.” 1995. Doctoral Dissertation, Michigan State University. Accessed June 24, 2019. http://etd.lib.msu.edu/islandora/object/etd:25385.

MLA Handbook (7th Edition):

Choi, Sea H (Sea Hawon). “Design methodology in high level synthesis.” 1995. Web. 24 Jun 2019.

Vancouver:

Choi SH(H. Design methodology in high level synthesis. [Internet] [Doctoral dissertation]. Michigan State University; 1995. [cited 2019 Jun 24]. Available from: http://etd.lib.msu.edu/islandora/object/etd:25385.

Council of Science Editors:

Choi SH(H. Design methodology in high level synthesis. [Doctoral Dissertation]. Michigan State University; 1995. Available from: http://etd.lib.msu.edu/islandora/object/etd:25385


University of Victoria

29. Ibarra, Louis Walter. Dynamic algorithms for chordal and interval graphs.

Degree: Department of Computer Science, 2018, University of Victoria

 We present the first dynamic algorithm that maintains a clique tree representation of a chordal graph and supports the following operations: (1) query whether deleting… (more)

Subjects/Keywords: Computer hardware description languages; Graph theory; Algorithms; Trees (Graph theory)

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APA (6th Edition):

Ibarra, L. W. (2018). Dynamic algorithms for chordal and interval graphs. (Thesis). University of Victoria. Retrieved from https://dspace.library.uvic.ca//handle/1828/9596

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ibarra, Louis Walter. “Dynamic algorithms for chordal and interval graphs.” 2018. Thesis, University of Victoria. Accessed June 24, 2019. https://dspace.library.uvic.ca//handle/1828/9596.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ibarra, Louis Walter. “Dynamic algorithms for chordal and interval graphs.” 2018. Web. 24 Jun 2019.

Vancouver:

Ibarra LW. Dynamic algorithms for chordal and interval graphs. [Internet] [Thesis]. University of Victoria; 2018. [cited 2019 Jun 24]. Available from: https://dspace.library.uvic.ca//handle/1828/9596.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ibarra LW. Dynamic algorithms for chordal and interval graphs. [Thesis]. University of Victoria; 2018. Available from: https://dspace.library.uvic.ca//handle/1828/9596

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

30. Sharma, Vyoma. Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  Arithmetic Square Root is one of the most complex but nevertheless widely used operations in modern computing. A primary reason for the complexity is… (more)

Subjects/Keywords: Logic design; Circuits; Design methodology; Hardware description languages; Computer architecture; Calculators

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sharma, V. (2017). Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9703

Chicago Manual of Style (16th Edition):

Sharma, Vyoma. “Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed June 24, 2019. https://scholarworks.rit.edu/theses/9703.

MLA Handbook (7th Edition):

Sharma, Vyoma. “Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm.” 2017. Web. 24 Jun 2019.

Vancouver:

Sharma V. Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2019 Jun 24]. Available from: https://scholarworks.rit.edu/theses/9703.

Council of Science Editors:

Sharma V. Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9703

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