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You searched for subject:(VLSI). Showing records 1 – 30 of 757 total matches.

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University of Georgia

1. Bahuman, Anil Lakshman. An evolutionary approach to standard cell design automation.

Degree: MS, Artificial Intelligence, 2001, University of Georgia

 The problem of designing the transistor-level layout of cells in a standard cell library is a multi-objective design optimization problem. Contemporary methods are optimization or… (more)

Subjects/Keywords: VLSI

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APA (6th Edition):

Bahuman, A. L. (2001). An evolutionary approach to standard cell design automation. (Masters Thesis). University of Georgia. Retrieved from http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms

Chicago Manual of Style (16th Edition):

Bahuman, Anil Lakshman. “An evolutionary approach to standard cell design automation.” 2001. Masters Thesis, University of Georgia. Accessed January 22, 2020. http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms.

MLA Handbook (7th Edition):

Bahuman, Anil Lakshman. “An evolutionary approach to standard cell design automation.” 2001. Web. 22 Jan 2020.

Vancouver:

Bahuman AL. An evolutionary approach to standard cell design automation. [Internet] [Masters thesis]. University of Georgia; 2001. [cited 2020 Jan 22]. Available from: http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms.

Council of Science Editors:

Bahuman AL. An evolutionary approach to standard cell design automation. [Masters Thesis]. University of Georgia; 2001. Available from: http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms

2. Nakabayashi, Keiji. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: VLSI

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APA (6th Edition):

Nakabayashi, K. (n.d.). A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/6020

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nakabayashi, Keiji. “A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed January 22, 2020. http://hdl.handle.net/10061/6020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nakabayashi, Keiji. “A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ.” Web. 22 Jan 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Nakabayashi K. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2020 Jan 22]. Available from: http://hdl.handle.net/10061/6020.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Nakabayashi K. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/6020

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Georgia Tech

3. Kamdar, Keval Prakash. Performance estimation of large area nanowires.

Degree: MS, Electrical and Computer Engineering, 2019, Georgia Tech

 The focus of the thesis is to extensively model high-performance nanowires, develop Verilog A models of the devices and then simulate them using SPICE to… (more)

Subjects/Keywords: Nanowires; vlsi

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APA (6th Edition):

Kamdar, K. P. (2019). Performance estimation of large area nanowires. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61309

Chicago Manual of Style (16th Edition):

Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Masters Thesis, Georgia Tech. Accessed January 22, 2020. http://hdl.handle.net/1853/61309.

MLA Handbook (7th Edition):

Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Web. 22 Jan 2020.

Vancouver:

Kamdar KP. Performance estimation of large area nanowires. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1853/61309.

Council of Science Editors:

Kamdar KP. Performance estimation of large area nanowires. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61309


Texas A&M University

4. Shah, Pratik Jitendra. Case studies on lithography-friendly vlsi circuit layout.

Degree: 2009, Texas A&M University

 Moore?s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered… (more)

Subjects/Keywords: Lithography; VLSI; layout

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APA (6th Edition):

Shah, P. J. (2009). Case studies on lithography-friendly vlsi circuit layout. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-3120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Thesis, Texas A&M University. Accessed January 22, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-3120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Web. 22 Jan 2020.

Vancouver:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New Mexico

5. Arora, Tamanna. Using ant colony optimization for routing in microprocesors.

Degree: Department of Computer Science, 2009, University of New Mexico

 Power consumption is an important constraint on VLSI systems. With the advancement in technology, it is now possible to pack a large range of functionalities… (more)

Subjects/Keywords: VLSI; Routing; ACO

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APA (6th Edition):

Arora, T. (2009). Using ant colony optimization for routing in microprocesors. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/10258

Chicago Manual of Style (16th Edition):

Arora, Tamanna. “Using ant colony optimization for routing in microprocesors.” 2009. Masters Thesis, University of New Mexico. Accessed January 22, 2020. http://hdl.handle.net/1928/10258.

MLA Handbook (7th Edition):

Arora, Tamanna. “Using ant colony optimization for routing in microprocesors.” 2009. Web. 22 Jan 2020.

Vancouver:

Arora T. Using ant colony optimization for routing in microprocesors. [Internet] [Masters thesis]. University of New Mexico; 2009. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1928/10258.

Council of Science Editors:

Arora T. Using ant colony optimization for routing in microprocesors. [Masters Thesis]. University of New Mexico; 2009. Available from: http://hdl.handle.net/1928/10258


Cornell University

6. Longfield, Stephen. Constructive Verification Of Quasi Delay-Insensitive Circuits .

Degree: 2015, Cornell University

 Self-timed circuits have recently regained active interest as their abilities in avoiding timing and voltage margins, disconnecting pipeline depth from occupancy, and achieving average-case performance… (more)

Subjects/Keywords: VLSI; Verification; Asynchronous

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APA (6th Edition):

Longfield, S. (2015). Constructive Verification Of Quasi Delay-Insensitive Circuits . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/40716

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Longfield, Stephen. “Constructive Verification Of Quasi Delay-Insensitive Circuits .” 2015. Thesis, Cornell University. Accessed January 22, 2020. http://hdl.handle.net/1813/40716.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Longfield, Stephen. “Constructive Verification Of Quasi Delay-Insensitive Circuits .” 2015. Web. 22 Jan 2020.

Vancouver:

Longfield S. Constructive Verification Of Quasi Delay-Insensitive Circuits . [Internet] [Thesis]. Cornell University; 2015. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1813/40716.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Longfield S. Constructive Verification Of Quasi Delay-Insensitive Circuits . [Thesis]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/40716

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Oulu

7. Shahabuddin, S. (Shahriar). MIMO detection and precoding architectures.

Degree: 2019, University of Oulu

Abstract Multiple-input multiple-output (MIMO) techniques have been adopted since the third generation (3G) wireless communication standard to increase the spectral efficiency, data rate and reliability.… (more)

Subjects/Keywords: ASIP; MIMO; VLSI

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APA (6th Edition):

Shahabuddin, S. (. (2019). MIMO detection and precoding architectures. (Doctoral Dissertation). University of Oulu. Retrieved from http://urn.fi/urn:isbn:9789526222837

Chicago Manual of Style (16th Edition):

Shahabuddin, S (Shahriar). “MIMO detection and precoding architectures.” 2019. Doctoral Dissertation, University of Oulu. Accessed January 22, 2020. http://urn.fi/urn:isbn:9789526222837.

MLA Handbook (7th Edition):

Shahabuddin, S (Shahriar). “MIMO detection and precoding architectures.” 2019. Web. 22 Jan 2020.

Vancouver:

Shahabuddin S(. MIMO detection and precoding architectures. [Internet] [Doctoral dissertation]. University of Oulu; 2019. [cited 2020 Jan 22]. Available from: http://urn.fi/urn:isbn:9789526222837.

Council of Science Editors:

Shahabuddin S(. MIMO detection and precoding architectures. [Doctoral Dissertation]. University of Oulu; 2019. Available from: http://urn.fi/urn:isbn:9789526222837


Texas A&M University

8. Wang, Weihuang. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.

Degree: 2009, Texas A&M University

 This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels… (more)

Subjects/Keywords: VLSI; LDPC; low power

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APA (6th Edition):

Wang, W. (2009). Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2504

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Weihuang. “Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.” 2009. Thesis, Texas A&M University. Accessed January 22, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2504.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Weihuang. “Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.” 2009. Web. 22 Jan 2020.

Vancouver:

Wang W. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2504.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang W. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2504

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

9. Hu, Shiyan. Algorithmic techniques for nanometer VLSI design and manufacturing closure.

Degree: 2008, Texas A&M University

 As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip… (more)

Subjects/Keywords: Physical Design; VLSI CAD

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APA (6th Edition):

Hu, S. (2008). Algorithmic techniques for nanometer VLSI design and manufacturing closure. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/85905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hu, Shiyan. “Algorithmic techniques for nanometer VLSI design and manufacturing closure.” 2008. Thesis, Texas A&M University. Accessed January 22, 2020. http://hdl.handle.net/1969.1/85905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hu, Shiyan. “Algorithmic techniques for nanometer VLSI design and manufacturing closure.” 2008. Web. 22 Jan 2020.

Vancouver:

Hu S. Algorithmic techniques for nanometer VLSI design and manufacturing closure. [Internet] [Thesis]. Texas A&M University; 2008. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1969.1/85905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hu S. Algorithmic techniques for nanometer VLSI design and manufacturing closure. [Thesis]. Texas A&M University; 2008. Available from: http://hdl.handle.net/1969.1/85905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

10. Jiang, Zhanyuan. Performance and power optimization in VLSI physical design.

Degree: 2009, Texas A&M University

 As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out… (more)

Subjects/Keywords: VLSI; physical design; buffer insertion

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APA (6th Edition):

Jiang, Z. (2009). Performance and power optimization in VLSI physical design. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jiang, Zhanyuan. “Performance and power optimization in VLSI physical design.” 2009. Thesis, Texas A&M University. Accessed January 22, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jiang, Zhanyuan. “Performance and power optimization in VLSI physical design.” 2009. Web. 22 Jan 2020.

Vancouver:

Jiang Z. Performance and power optimization in VLSI physical design. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jiang Z. Performance and power optimization in VLSI physical design. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

11. Mandal, Ayan. Efficient Design and Clocking for a Network-on-Chip.

Degree: 2013, Texas A&M University

 As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC)… (more)

Subjects/Keywords: Network-on-Chip; Clock; VLSI

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APA (6th Edition):

Mandal, A. (2013). Efficient Design and Clocking for a Network-on-Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Thesis, Texas A&M University. Accessed January 22, 2020. http://hdl.handle.net/1969.1/149325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Web. 22 Jan 2020.

Vancouver:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1969.1/149325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Jain, Shruti. Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;.

Degree: 2013, Jaypee University of Information Technology, Solan

Biological systems can create complex structures from very simple systems. To do this, there must be a method to differentiate different regions where identical systems… (more)

Subjects/Keywords: CMOS; Fuzzy Logic; VLSI

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APA (6th Edition):

Jain, S. (2013). Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;. (Thesis). Jaypee University of Information Technology, Solan. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/11161

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jain, Shruti. “Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;.” 2013. Thesis, Jaypee University of Information Technology, Solan. Accessed January 22, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/11161.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jain, Shruti. “Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;.” 2013. Web. 22 Jan 2020.

Vancouver:

Jain S. Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;. [Internet] [Thesis]. Jaypee University of Information Technology, Solan; 2013. [cited 2020 Jan 22]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11161.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jain S. Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;. [Thesis]. Jaypee University of Information Technology, Solan; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11161

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Florida

13. Sadi, Mehdi Zahid. On-Chip Structures for Reliability Management of System-On-Chips.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Florida

 With aggressive technology scaling in the finfet era the transistor density per unit chip area has increased significantly over the past decade. As a result… (more)

Subjects/Keywords: reliability  – system-on-chip  – vlsi

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APA (6th Edition):

Sadi, M. Z. (2017). On-Chip Structures for Reliability Management of System-On-Chips. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0051010

Chicago Manual of Style (16th Edition):

Sadi, Mehdi Zahid. “On-Chip Structures for Reliability Management of System-On-Chips.” 2017. Doctoral Dissertation, University of Florida. Accessed January 22, 2020. http://ufdc.ufl.edu/UFE0051010.

MLA Handbook (7th Edition):

Sadi, Mehdi Zahid. “On-Chip Structures for Reliability Management of System-On-Chips.” 2017. Web. 22 Jan 2020.

Vancouver:

Sadi MZ. On-Chip Structures for Reliability Management of System-On-Chips. [Internet] [Doctoral dissertation]. University of Florida; 2017. [cited 2020 Jan 22]. Available from: http://ufdc.ufl.edu/UFE0051010.

Council of Science Editors:

Sadi MZ. On-Chip Structures for Reliability Management of System-On-Chips. [Doctoral Dissertation]. University of Florida; 2017. Available from: http://ufdc.ufl.edu/UFE0051010


University of Southern California

14. Kashfi, Fatemeh. Thermal analysis and multiobjective optimization for three dimensional integrated circuits.

Degree: PhD, Electrical Engineering (VLSI Design), 2013, University of Southern California

 Three Dimensional Integrated Circuit (3DIC) technology has been introduced to address the interconnect issues in nanometer circuit design that limit performance improvement and power reduction.… (more)

Subjects/Keywords: 3DIC; optimization; temperature; electronics; VLSI

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APA (6th Edition):

Kashfi, F. (2013). Thermal analysis and multiobjective optimization for three dimensional integrated circuits. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7428

Chicago Manual of Style (16th Edition):

Kashfi, Fatemeh. “Thermal analysis and multiobjective optimization for three dimensional integrated circuits.” 2013. Doctoral Dissertation, University of Southern California. Accessed January 22, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7428.

MLA Handbook (7th Edition):

Kashfi, Fatemeh. “Thermal analysis and multiobjective optimization for three dimensional integrated circuits.” 2013. Web. 22 Jan 2020.

Vancouver:

Kashfi F. Thermal analysis and multiobjective optimization for three dimensional integrated circuits. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2020 Jan 22]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7428.

Council of Science Editors:

Kashfi F. Thermal analysis and multiobjective optimization for three dimensional integrated circuits. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7428


University of Cincinnati

15. SINGH, ARUN. Design of Current Sensors to measure small current signals of pico-amperes to nano-amperes in magnitude.

Degree: MS, Engineering : Electrical Engineering, 2008, University of Cincinnati

 The primary goal of this research work is to amperometrically measure small current signals, in the range of pico-ampere to nano-ampere that are produced by… (more)

Subjects/Keywords: Engineering; Current Sensor; vlsi

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APA (6th Edition):

SINGH, A. (2008). Design of Current Sensors to measure small current signals of pico-amperes to nano-amperes in magnitude. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1205161608

Chicago Manual of Style (16th Edition):

SINGH, ARUN. “Design of Current Sensors to measure small current signals of pico-amperes to nano-amperes in magnitude.” 2008. Masters Thesis, University of Cincinnati. Accessed January 22, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1205161608.

MLA Handbook (7th Edition):

SINGH, ARUN. “Design of Current Sensors to measure small current signals of pico-amperes to nano-amperes in magnitude.” 2008. Web. 22 Jan 2020.

Vancouver:

SINGH A. Design of Current Sensors to measure small current signals of pico-amperes to nano-amperes in magnitude. [Internet] [Masters thesis]. University of Cincinnati; 2008. [cited 2020 Jan 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1205161608.

Council of Science Editors:

SINGH A. Design of Current Sensors to measure small current signals of pico-amperes to nano-amperes in magnitude. [Masters Thesis]. University of Cincinnati; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1205161608


Louisiana State University

16. Mekala, Hemalatha. Third order CMOS decimator design for sigma delta modulators.

Degree: MS, Electrical and Computer Engineering, 2009, Louisiana State University

 A third order Cascaded Integrated Comb (CIC) filter has been designed in 0.5μm n-well CMOS process to interface with a second order oversampling sigma-delta ADC… (more)

Subjects/Keywords: CIC filter; Decimator; VLSI; Hemalatha

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APA (6th Edition):

Mekala, H. (2009). Third order CMOS decimator design for sigma delta modulators. (Masters Thesis). Louisiana State University. Retrieved from etd-11092009-163619 ; https://digitalcommons.lsu.edu/gradschool_theses/858

Chicago Manual of Style (16th Edition):

Mekala, Hemalatha. “Third order CMOS decimator design for sigma delta modulators.” 2009. Masters Thesis, Louisiana State University. Accessed January 22, 2020. etd-11092009-163619 ; https://digitalcommons.lsu.edu/gradschool_theses/858.

MLA Handbook (7th Edition):

Mekala, Hemalatha. “Third order CMOS decimator design for sigma delta modulators.” 2009. Web. 22 Jan 2020.

Vancouver:

Mekala H. Third order CMOS decimator design for sigma delta modulators. [Internet] [Masters thesis]. Louisiana State University; 2009. [cited 2020 Jan 22]. Available from: etd-11092009-163619 ; https://digitalcommons.lsu.edu/gradschool_theses/858.

Council of Science Editors:

Mekala H. Third order CMOS decimator design for sigma delta modulators. [Masters Thesis]. Louisiana State University; 2009. Available from: etd-11092009-163619 ; https://digitalcommons.lsu.edu/gradschool_theses/858


Delft University of Technology

17. Moar Gomez, J. 90 nm VLSI Design of an 8-bits Microcontroller:.

Degree: Electrical Engineering, Mathematics, Computer Sci, Microelectronics, 2009, Delft University of Technology

 Integrated Circuit (IC) design complexity has increased radically since the first "hand-made" designs in the late 50s, with a few transistors. Nowadays, Very Large Scale… (more)

Subjects/Keywords: vlsi; microcontroller; 90nm; wishbone

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APA (6th Edition):

Moar Gomez, J. (2009). 90 nm VLSI Design of an 8-bits Microcontroller:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc

Chicago Manual of Style (16th Edition):

Moar Gomez, J. “90 nm VLSI Design of an 8-bits Microcontroller:.” 2009. Masters Thesis, Delft University of Technology. Accessed January 22, 2020. http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc.

MLA Handbook (7th Edition):

Moar Gomez, J. “90 nm VLSI Design of an 8-bits Microcontroller:.” 2009. Web. 22 Jan 2020.

Vancouver:

Moar Gomez J. 90 nm VLSI Design of an 8-bits Microcontroller:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2020 Jan 22]. Available from: http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc.

Council of Science Editors:

Moar Gomez J. 90 nm VLSI Design of an 8-bits Microcontroller:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc


Texas A&M University

18. Wang, Qian. Architectures and Design of VLSI Machine Learning Systems.

Degree: PhD, Computer Engineering, 2016, Texas A&M University

 Quintillions of bytes of data are generated every day in this era of big data. Machine learning techniques are utilized to perform predictive analysis on… (more)

Subjects/Keywords: Machine learning; VLSI architecture

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APA (6th Edition):

Wang, Q. (2016). Architectures and Design of VLSI Machine Learning Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/158093

Chicago Manual of Style (16th Edition):

Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Doctoral Dissertation, Texas A&M University. Accessed January 22, 2020. http://hdl.handle.net/1969.1/158093.

MLA Handbook (7th Edition):

Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Web. 22 Jan 2020.

Vancouver:

Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1969.1/158093.

Council of Science Editors:

Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/158093


University of Toronto

19. Yu, Jingshu. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.

Degree: 2014, University of Toronto

In this thesis, an integrated H-bridge is presented for continuously optimizing the power conversion efficiency over a wide range of output current. The proposed IC… (more)

Subjects/Keywords: Power Electronics; VLSI; 0544

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APA (6th Edition):

Yu, J. (2014). A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/67870

Chicago Manual of Style (16th Edition):

Yu, Jingshu. “A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.” 2014. Masters Thesis, University of Toronto. Accessed January 22, 2020. http://hdl.handle.net/1807/67870.

MLA Handbook (7th Edition):

Yu, Jingshu. “A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.” 2014. Web. 22 Jan 2020.

Vancouver:

Yu J. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1807/67870.

Council of Science Editors:

Yu J. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/67870

20. Kananen, Asko. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.

Degree: 2007, Helsinki University of Technology

This thesis deals with silicon implementations of an all-transistor analogue parallel processor that emulates the functionality of a resistive network. The problems related to VLSI -implementations… (more)

Subjects/Keywords: analogue parallel processor; VLSI; resistive network; analoginen rinnakkaisprosessori; VLSI; vastusverkko

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APA (6th Edition):

Kananen, A. (2007). A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. (Thesis). Helsinki University of Technology. Retrieved from http://lib.tkk.fi/Diss/2007/isbn9789512286232/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kananen, Asko. “A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.” 2007. Thesis, Helsinki University of Technology. Accessed January 22, 2020. http://lib.tkk.fi/Diss/2007/isbn9789512286232/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kananen, Asko. “A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.” 2007. Web. 22 Jan 2020.

Vancouver:

Kananen A. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. [Internet] [Thesis]. Helsinki University of Technology; 2007. [cited 2020 Jan 22]. Available from: http://lib.tkk.fi/Diss/2007/isbn9789512286232/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kananen A. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. [Thesis]. Helsinki University of Technology; 2007. Available from: http://lib.tkk.fi/Diss/2007/isbn9789512286232/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

21. Reimann, Tiago Jose. Roteamento global de circuitos VLSI.

Degree: 2013, Universidade do Rio Grande do Sul

Este trabalho apresenta a implementação de um roteador global de circuitos integrados capaz de tratar os problemas de roteamento atuais, utilizando como referência para avaliação… (more)

Subjects/Keywords: Microeletrônica; Global routing; Physical synthesis; Vlsi; Roteamento : Circuitos integrados; CAD; VLSI

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APA (6th Edition):

Reimann, T. J. (2013). Roteamento global de circuitos VLSI. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/71269

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reimann, Tiago Jose. “Roteamento global de circuitos VLSI.” 2013. Thesis, Universidade do Rio Grande do Sul. Accessed January 22, 2020. http://hdl.handle.net/10183/71269.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reimann, Tiago Jose. “Roteamento global de circuitos VLSI.” 2013. Web. 22 Jan 2020.

Vancouver:

Reimann TJ. Roteamento global de circuitos VLSI. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2013. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/10183/71269.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reimann TJ. Roteamento global de circuitos VLSI. [Thesis]. Universidade do Rio Grande do Sul; 2013. Available from: http://hdl.handle.net/10183/71269

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

22. Tumelero, Diego. Exploração de paralelismo no roteamento global de circuitos VLSI.

Degree: 2015, Universidade do Rio Grande do Sul

Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos… (more)

Subjects/Keywords: Microeletrônica; Global routing; Parallelism; Paralelismo; Vlsi; EDA; VLSI; Microelectronics

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APA (6th Edition):

Tumelero, D. (2015). Exploração de paralelismo no roteamento global de circuitos VLSI. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/119081

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tumelero, Diego. “Exploração de paralelismo no roteamento global de circuitos VLSI.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed January 22, 2020. http://hdl.handle.net/10183/119081.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tumelero, Diego. “Exploração de paralelismo no roteamento global de circuitos VLSI.” 2015. Web. 22 Jan 2020.

Vancouver:

Tumelero D. Exploração de paralelismo no roteamento global de circuitos VLSI. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/10183/119081.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tumelero D. Exploração de paralelismo no roteamento global de circuitos VLSI. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/119081

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Iowa State University

23. Zhang, Yanheng. Handling the complexity of routing problem in modern VLSI design.

Degree: 2011, Iowa State University

 In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pins and ports of circuit gates and blocks. Traditionally, VLSI(more)

Subjects/Keywords: Physical Design; Routability; VLSI CAD; VLSI Routing; Electrical and Computer Engineering

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APA (6th Edition):

Zhang, Y. (2011). Handling the complexity of routing problem in modern VLSI design. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/11896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Yanheng. “Handling the complexity of routing problem in modern VLSI design.” 2011. Thesis, Iowa State University. Accessed January 22, 2020. https://lib.dr.iastate.edu/etd/11896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Yanheng. “Handling the complexity of routing problem in modern VLSI design.” 2011. Web. 22 Jan 2020.

Vancouver:

Zhang Y. Handling the complexity of routing problem in modern VLSI design. [Internet] [Thesis]. Iowa State University; 2011. [cited 2020 Jan 22]. Available from: https://lib.dr.iastate.edu/etd/11896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang Y. Handling the complexity of routing problem in modern VLSI design. [Thesis]. Iowa State University; 2011. Available from: https://lib.dr.iastate.edu/etd/11896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – San Diego

24. Nath, Siddhartha. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.

Degree: Computer Science, 2016, University of California – San Diego

 In today's leading-edge semiconductor technologies, it is increasingly difficult for IC designers to achieve sufficient improvements of performance, power and area metrics in their next-generation… (more)

Subjects/Keywords: Computer science; Machine Learning; Optimization; VLSI CAD

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APA (6th Edition):

Nath, S. (2016). New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/9jn2c085

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nath, Siddhartha. “New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.” 2016. Thesis, University of California – San Diego. Accessed January 22, 2020. http://www.escholarship.org/uc/item/9jn2c085.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nath, Siddhartha. “New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.” 2016. Web. 22 Jan 2020.

Vancouver:

Nath S. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. [Internet] [Thesis]. University of California – San Diego; 2016. [cited 2020 Jan 22]. Available from: http://www.escholarship.org/uc/item/9jn2c085.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nath S. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. [Thesis]. University of California – San Diego; 2016. Available from: http://www.escholarship.org/uc/item/9jn2c085

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

25. Li, Peng. FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications.

Degree: MS, Electrical/Computer Engineering, 2012, University of Minnesota

University of Minnesota M.S. thesis. October 2012. Major: Electrical/Computer Engineering. Advisor: Hua Tang. 1 computer file (PDF); viii, 47 pages, appendix A.

It is well… (more)

Subjects/Keywords: FPGA; Image processing; Image segmentation; VLSI

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APA (6th Edition):

Li, P. (2012). FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/140237

Chicago Manual of Style (16th Edition):

Li, Peng. “FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications.” 2012. Masters Thesis, University of Minnesota. Accessed January 22, 2020. http://purl.umn.edu/140237.

MLA Handbook (7th Edition):

Li, Peng. “FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications.” 2012. Web. 22 Jan 2020.

Vancouver:

Li P. FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications. [Internet] [Masters thesis]. University of Minnesota; 2012. [cited 2020 Jan 22]. Available from: http://purl.umn.edu/140237.

Council of Science Editors:

Li P. FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications. [Masters Thesis]. University of Minnesota; 2012. Available from: http://purl.umn.edu/140237


University of Minnesota

26. Dalal, Hussain Firoz. Implementation of on-chip thermal sensor using off-leakage current of a transistor.

Degree: MS, Electrical Engineering, 2010, University of Minnesota

University of Minnesota M.S. thesis. January 2010. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF); ii, 38 pages. Ill. (some col.)

Abstract summary not available

Advisors/Committee Members: Chris H. Kim.

Subjects/Keywords: VLSI; CMOS; Leakage Current; Electrical Engineering

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APA (6th Edition):

Dalal, H. F. (2010). Implementation of on-chip thermal sensor using off-leakage current of a transistor. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/59772

Chicago Manual of Style (16th Edition):

Dalal, Hussain Firoz. “Implementation of on-chip thermal sensor using off-leakage current of a transistor.” 2010. Masters Thesis, University of Minnesota. Accessed January 22, 2020. http://purl.umn.edu/59772.

MLA Handbook (7th Edition):

Dalal, Hussain Firoz. “Implementation of on-chip thermal sensor using off-leakage current of a transistor.” 2010. Web. 22 Jan 2020.

Vancouver:

Dalal HF. Implementation of on-chip thermal sensor using off-leakage current of a transistor. [Internet] [Masters thesis]. University of Minnesota; 2010. [cited 2020 Jan 22]. Available from: http://purl.umn.edu/59772.

Council of Science Editors:

Dalal HF. Implementation of on-chip thermal sensor using off-leakage current of a transistor. [Masters Thesis]. University of Minnesota; 2010. Available from: http://purl.umn.edu/59772


Anna University

27. Jayanthy S. Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;.

Degree: algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits, 2014, Anna University

Very Large Scale Integration VLSI is the fabrication of millions newlineof components on the same chip and is an integral part of modern electronic newlinesystems… (more)

Subjects/Keywords: crosstalk delay; electrical engineering; vlsi circuits

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APA (6th Edition):

S, J. (2014). Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/23842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

S, Jayanthy. “Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;.” 2014. Thesis, Anna University. Accessed January 22, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/23842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

S, Jayanthy. “Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;.” 2014. Web. 22 Jan 2020.

Vancouver:

S J. Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Jan 22]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

S J. Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

28. Dash, Rajballav. VLSI Implementation of Low Power Reconfigurable MIMO Detector.

Degree: 2009, Texas A&M University

 Multiple Input Multiple Output (MIMO) systems are a key technology for next generation high speed wireless communication standards like 802.11n, WiMax etc. MIMO enables spatial… (more)

Subjects/Keywords: VLSI; MIMO; IEEE 802.11n; Sphere Decoding; DVFS

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APA (6th Edition):

Dash, R. (2009). VLSI Implementation of Low Power Reconfigurable MIMO Detector. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148444

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dash, Rajballav. “VLSI Implementation of Low Power Reconfigurable MIMO Detector.” 2009. Thesis, Texas A&M University. Accessed January 22, 2020. http://hdl.handle.net/1969.1/148444.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dash, Rajballav. “VLSI Implementation of Low Power Reconfigurable MIMO Detector.” 2009. Web. 22 Jan 2020.

Vancouver:

Dash R. VLSI Implementation of Low Power Reconfigurable MIMO Detector. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1969.1/148444.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dash R. VLSI Implementation of Low Power Reconfigurable MIMO Detector. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/148444

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

29. Ruggeri, Thomas L. TIMR : Time Interleaved Multi Rail.

Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University

 This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic… (more)

Subjects/Keywords: VLSI; Integrated circuits  – Very large scale integration

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APA (6th Edition):

Ruggeri, T. L. (2012). TIMR : Time Interleaved Multi Rail. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29070

Chicago Manual of Style (16th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Masters Thesis, Oregon State University. Accessed January 22, 2020. http://hdl.handle.net/1957/29070.

MLA Handbook (7th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Web. 22 Jan 2020.

Vancouver:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1957/29070.

Council of Science Editors:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29070


Michigan Technological University

30. Chen, Xiaodao. Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design.

Degree: PhD, Department of Electrical and Computer Engineering, 2012, Michigan Technological University

  To tackle the challenges at circuit level and system level VLSI and embedded system design, this dissertation proposes various novel algorithms to explore the… (more)

Subjects/Keywords: CAD; Embedded System; VLSI Design; Computer Engineering

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APA (6th Edition):

Chen, X. (2012). Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design. (Doctoral Dissertation). Michigan Technological University. Retrieved from http://digitalcommons.mtu.edu/etds/709

Chicago Manual of Style (16th Edition):

Chen, Xiaodao. “Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design.” 2012. Doctoral Dissertation, Michigan Technological University. Accessed January 22, 2020. http://digitalcommons.mtu.edu/etds/709.

MLA Handbook (7th Edition):

Chen, Xiaodao. “Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design.” 2012. Web. 22 Jan 2020.

Vancouver:

Chen X. Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design. [Internet] [Doctoral dissertation]. Michigan Technological University; 2012. [cited 2020 Jan 22]. Available from: http://digitalcommons.mtu.edu/etds/709.

Council of Science Editors:

Chen X. Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design. [Doctoral Dissertation]. Michigan Technological University; 2012. Available from: http://digitalcommons.mtu.edu/etds/709

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