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University of Georgia
1.
Bahuman, Anil Lakshman.
An evolutionary approach to standard cell design automation.
Degree: MS, Artificial Intelligence, 2001, University of Georgia
URL: http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms 
► The problem of designing the transistor-level layout of cells in a standard cell library is a multi-objective design optimization problem. Contemporary methods are optimization or…
(more)
▼ The problem of designing the transistor-level layout of cells in a standard cell library is a multi-objective design optimization problem. Contemporary methods are optimization or compaction engines that rely on a schematic representation supplied by a design engineer. We have demonstrated the possibility of applying a modi.ed genetic algorithm (GADO) to design a cell given only a behavioral description. A working inverter is designed as a proof of concept along with other inverters with arbitrary label placements. This is an example of design without human intervention, i.e. a computer design as opposed to a computer-aided design. The complete set of experimental results may be found at the project web site http://james.cs.uga.edu.
Advisors/Committee Members: Khaled Rasheed.
Subjects/Keywords: VLSI
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APA (6th Edition):
Bahuman, A. L. (2001). An evolutionary approach to standard cell design automation. (Masters Thesis). University of Georgia. Retrieved from http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms
Chicago Manual of Style (16th Edition):
Bahuman, Anil Lakshman. “An evolutionary approach to standard cell design automation.” 2001. Masters Thesis, University of Georgia. Accessed January 22, 2020.
http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms.
MLA Handbook (7th Edition):
Bahuman, Anil Lakshman. “An evolutionary approach to standard cell design automation.” 2001. Web. 22 Jan 2020.
Vancouver:
Bahuman AL. An evolutionary approach to standard cell design automation. [Internet] [Masters thesis]. University of Georgia; 2001. [cited 2020 Jan 22].
Available from: http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms.
Council of Science Editors:
Bahuman AL. An evolutionary approach to standard cell design automation. [Masters Thesis]. University of Georgia; 2001. Available from: http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms
2.
Nakabayashi, Keiji.
A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ.
Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学
URL: http://hdl.handle.net/10061/6020
Subjects/Keywords: VLSI
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APA (6th Edition):
Nakabayashi, K. (n.d.). A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/6020
Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Nakabayashi, Keiji. “A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed January 22, 2020.
http://hdl.handle.net/10061/6020.
Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Nakabayashi, Keiji. “A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ.” Web. 22 Jan 2020.
Note: this citation may be lacking information needed for this citation format:
No year of publication.
Vancouver:
Nakabayashi K. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2020 Jan 22].
Available from: http://hdl.handle.net/10061/6020.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.
Council of Science Editors:
Nakabayashi K. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/6020
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.
Georgia Tech
3.
Kamdar, Keval Prakash.
Performance estimation of large area nanowires.
Degree: MS, Electrical and Computer Engineering, 2019, Georgia Tech
URL: http://hdl.handle.net/1853/61309
► The focus of the thesis is to extensively model high-performance nanowires, develop Verilog A models of the devices and then simulate them using SPICE to…
(more)
▼ The focus of the thesis is to extensively model high-performance nanowires, develop Verilog A models of the devices and then simulate them using SPICE to estimate their power-performance trade-offs. Once the device models are created, they will be used in circuits which will have realistic interconnects with necessary parasitic resistance and impedance (inductance and capacitance) and simulated for prototypical digital and mixed signal designs. The device and the circuit simulation infrastructure will be developed in parallel. Synopsys Taurus and Medici will be used for 3D device modelling, Verilog A for circuit-compatible models, and Spice for circuit and system evaluation.
Advisors/Committee Members: Raychowdhury, Arijit (advisor), Lim, Sung-Kyu (committee member), Khan, Asif (committee member).
Subjects/Keywords: Nanowires; vlsi
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APA (6th Edition):
Kamdar, K. P. (2019). Performance estimation of large area nanowires. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61309
Chicago Manual of Style (16th Edition):
Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Masters Thesis, Georgia Tech. Accessed January 22, 2020.
http://hdl.handle.net/1853/61309.
MLA Handbook (7th Edition):
Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Web. 22 Jan 2020.
Vancouver:
Kamdar KP. Performance estimation of large area nanowires. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1853/61309.
Council of Science Editors:
Kamdar KP. Performance estimation of large area nanowires. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61309
Texas A&M University
4.
Shah, Pratik Jitendra.
Case studies on lithography-friendly vlsi circuit layout.
Degree: 2009, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-3120
► Moore?s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered…
(more)
▼ Moore?s Law has driven a continuous demand for decreasing feature sizes used
in Very Large Scale Integrated (
VLSI) technology which has outpaced the solutions
offered by lithography hardware. Currently, a light wavelength of 193nm is being used
to print sub-65nm features. This introduces process variations which cause mismatches
between desired and actual wafer feature sizes. However, the layout which affects the
printability of a circuit can be modified in a manner which can make it more
lithography-friendly.
In this work, we intend to implement these modifications as a series of
perturbations on the initial layout generated by the CAD tool for the circuit. To
implement these changes we first calculate the feature variations offline on the
boundaries of all possible standard cell pairs used in the circuit layout and record them in
a Look-Up Table (LUT). After the CAD tool generates the initial placement of the
circuit, we use the LUT to estimate the variations on the boundaries of all the standard
cells. Depending on the features which may have the highest feature variations we assign
a cost to the layout and our aim is now to reduce the cost of the layout after
implementing perturbations which could be a simple cell flip or swap with a neighboring
cell. The algorithm used to generate a circuit placement with a low cost is Simulated
Annealing which allows a high probability for a solution with a higher cost to be
selected during the initial iterations and as time goes on it tends closer to the greedy
algorithm. The idea here is to avoid a locally optimum solution. It is also essential to minimize the impact of the iterations performed on the initial solution in terms of
wirelength, vias and routing congestion.
We validate our procedure on ISCAS85 benchmark circuits by simulating dose
and defocus variations using the Mentor tool Calibre LFD. We obtain a reduction of
greater 20% in the number of instances with the highest cell boundary feature variations.
The wirelength and the number of vias showed an increase of roughly 2.2-8.8% and 1.2-
7.8% respectively for different circuits. The routing congestion by and large remains
unaffected.
Advisors/Committee Members: Hu, Jiang (advisor), Shi, Weiping (committee member), Walker, Duncan Moore (committee member).
Subjects/Keywords: Lithography; VLSI; layout
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APA (6th Edition):
Shah, P. J. (2009). Case studies on lithography-friendly vlsi circuit layout. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-3120
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Thesis, Texas A&M University. Accessed January 22, 2020.
http://hdl.handle.net/1969.1/ETD-TAMU-3120.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Web. 22 Jan 2020.
Vancouver:
Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of New Mexico
5.
Arora, Tamanna.
Using ant colony optimization for routing in microprocesors.
Degree: Department of Computer Science, 2009, University of New Mexico
URL: http://hdl.handle.net/1928/10258
► Power consumption is an important constraint on VLSI systems. With the advancement in technology, it is now possible to pack a large range of functionalities…
(more)
▼ Power consumption is an important constraint on
VLSI systems. With the advancement in technology, it is now possible to pack a large range of functionalities into
VLSI devices. Hence it is important to find out ways to utilize these functionalities with optimized power consumption. This work focuses on curbing power consumption at the design stage. This work emphasizes minimizing active power consumption by minimizing the load capacitance of the chip. Capacitance of wires and vias can be minimized using Ant Colony Optimization (ACO) algorithms. ACO provides a multi agent framework for combinatorial optimization problems and hence is used to handle multiple constraints of minimizing wire-length and vias to achieve the goal of minimizing capacitance and hence power consumption. The ACO developed here is able to achieve an 8% reduction of wire-length and 7% reduction in vias thereby providing a 7% reduction in total capacitance, compared to other state of the art routers.
Advisors/Committee Members: Moses, Melanie, Luger, George F., Zarkesh-Ha, Payman.
Subjects/Keywords: VLSI; Routing; ACO
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APA (6th Edition):
Arora, T. (2009). Using ant colony optimization for routing in microprocesors. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/10258
Chicago Manual of Style (16th Edition):
Arora, Tamanna. “Using ant colony optimization for routing in microprocesors.” 2009. Masters Thesis, University of New Mexico. Accessed January 22, 2020.
http://hdl.handle.net/1928/10258.
MLA Handbook (7th Edition):
Arora, Tamanna. “Using ant colony optimization for routing in microprocesors.” 2009. Web. 22 Jan 2020.
Vancouver:
Arora T. Using ant colony optimization for routing in microprocesors. [Internet] [Masters thesis]. University of New Mexico; 2009. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1928/10258.
Council of Science Editors:
Arora T. Using ant colony optimization for routing in microprocesors. [Masters Thesis]. University of New Mexico; 2009. Available from: http://hdl.handle.net/1928/10258
Cornell University
6.
Longfield, Stephen.
Constructive Verification Of Quasi Delay-Insensitive Circuits
.
Degree: 2015, Cornell University
URL: http://hdl.handle.net/1813/40716
► Self-timed circuits have recently regained active interest as their abilities in avoiding timing and voltage margins, disconnecting pipeline depth from occupancy, and achieving average-case performance…
(more)
▼ Self-timed circuits have recently regained active interest as their abilities in avoiding timing and voltage margins, disconnecting pipeline depth from occupancy, and achieving average-case performance can help mitigate the challenges of very deep sub-micron design. However, there has been limited industrial adoption of these techniques, significantly due to the lack of commercial Computer Aided Design (CAD) support for synthesis and verification. This thesis presents a novel verification technique for the Quasi Delay-Insensitive (QDI) family of self-timed circuits leveraging properties of these circuits to reconstruct specifications from their implementations, using very little designer effort. The technique is presented in three stages: first, how to extract synchronization information from the gatelevel description, second, a type-and-effect system for ensuring stability and noninterference in the synchronization protocols, and lastly, a method for removing concurrency while maintaining the implementation relation of interest.
Advisors/Committee Members: Myers,Andrew C. (committeeMember), Kozen,Dexter Campbell (committeeMember).
Subjects/Keywords: VLSI;
Verification;
Asynchronous
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APA (6th Edition):
Longfield, S. (2015). Constructive Verification Of Quasi Delay-Insensitive Circuits
. (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/40716
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Longfield, Stephen. “Constructive Verification Of Quasi Delay-Insensitive Circuits
.” 2015. Thesis, Cornell University. Accessed January 22, 2020.
http://hdl.handle.net/1813/40716.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Longfield, Stephen. “Constructive Verification Of Quasi Delay-Insensitive Circuits
.” 2015. Web. 22 Jan 2020.
Vancouver:
Longfield S. Constructive Verification Of Quasi Delay-Insensitive Circuits
. [Internet] [Thesis]. Cornell University; 2015. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1813/40716.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Longfield S. Constructive Verification Of Quasi Delay-Insensitive Circuits
. [Thesis]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/40716
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Oulu
7.
Shahabuddin, S. (Shahriar).
MIMO detection and precoding architectures.
Degree: 2019, University of Oulu
URL: http://urn.fi/urn:isbn:9789526222837
► Abstract Multiple-input multiple-output (MIMO) techniques have been adopted since the third generation (3G) wireless communication standard to increase the spectral efficiency, data rate and reliability.…
(more)
▼ Abstract
Multiple-input multiple-output (MIMO) techniques have been adopted since the third generation (3G) wireless communication standard to increase the spectral efficiency, data rate and reliability. The blessings of MIMO technologies for the baseband transceiver comes with the price of added complexity. Therefore, research on VLSI architectures for MIMO signal processing has generated a lot of interest over the past two decades. The advent of massive MIMO as a key technology for the fifth generation (5G) era also increased the interest in VLSI architectures related to MIMO communication research. In this thesis, we explored different VLSI architectures for MIMO detection and precoding algorithms. The detection and precoding are the most complex parts of a MIMO baseband transceiver. We focused on algorithm and architecture optimization and presented several VLSI architectures for MIMO detection and precoding.
The thesis proposed an application specific instruction-set processor (ASIP) for a multimode small-scale MIMO detector. In a single design the detector supports minimum mean-square error (MMSE), selective spanning with fast enumeration (SSFE) and list sphere detection (LSD). In addition, a multiprocessor architecture is proposed in this thesis for a lattice reduction (LR) algorithm. A modified Lenstra-Lenstra-Lovasz (LLL) algorithm is proposed for LR to reduce the complexity of the original LLL algorithm. We also propose a massive MIMO detection algorithm based on alternating direction method of multipliers (ADMM). The algorithm is referred to as ADMM based infinity norm (ADMIN) constrained equalization. The ADMIN detection algorithm is implemented as an application-specific integrated circuit (ASIC) and for field programmable gate array (FPGA). A multimode precoder ASIP is also proposed in this thesis. In a single design, the ASIP supports norm-based scheduling, QR-decomposition, MMSE precoding and dirty paper coding (DPC) based precoding.
Tiivistelmä
Moni-tulo moni-lähtö (MIMO) -tekniikoita on sopeutettu kolmannen sukupolven (3G) langattomasta viestintästandardista alkaen spektritehokkuuden, tiedonsiirtonopeuden ja luotettavuuden parantamiseksi. MIMO-teknologioilla on useita hyviä puolia suhteessa peruskaistan vastaanottimeen, mutta samalla monimutkaisuus on lisääntynyt. VLSI-arkkitehtuurien tutkimus MIMO-signaalinkäsittelyssä on sen vuoksi herättänyt paljon kiinnostusta viimeisen kahden vuosikymmenen aikana. Myös MIMO:n saavuttama asema viidennen sukupolven (5G) viestintästandardin pääteknologiana on lisännyt kiinnostusta VLSI-arkkitehtuureihin MIMO-viestinnän tutkimuksessa. Tässä tutkielmassa on tutkittu erilaisia VLSI-arkkitehtuureja MIMO-signaalien tunnistus- ja esikoodausalgoritmeissa. Signaalien tunnistus ja esikoodaus ovat peruskaistaa käyttävän MIMO-vastaanottimen monimutkaisimmat osa-alueet. Tutkielmassa on keskitytty algoritmien ja arkkitehtuurien optimointiin ja esitetty useita VLSI-arkkitehtuureja MIMO-signaalien tunnistusta ja esikoodausta varten.
Tutkielmassa on ehdotettu…
Advisors/Committee Members: Juntti, M. (Markku), Studer, C. (Christoph), Silvén, O. (Olli).
Subjects/Keywords: ASIP; MIMO; VLSI
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APA (6th Edition):
Shahabuddin, S. (. (2019). MIMO detection and precoding architectures. (Doctoral Dissertation). University of Oulu. Retrieved from http://urn.fi/urn:isbn:9789526222837
Chicago Manual of Style (16th Edition):
Shahabuddin, S (Shahriar). “MIMO detection and precoding architectures.” 2019. Doctoral Dissertation, University of Oulu. Accessed January 22, 2020.
http://urn.fi/urn:isbn:9789526222837.
MLA Handbook (7th Edition):
Shahabuddin, S (Shahriar). “MIMO detection and precoding architectures.” 2019. Web. 22 Jan 2020.
Vancouver:
Shahabuddin S(. MIMO detection and precoding architectures. [Internet] [Doctoral dissertation]. University of Oulu; 2019. [cited 2020 Jan 22].
Available from: http://urn.fi/urn:isbn:9789526222837.
Council of Science Editors:
Shahabuddin S(. MIMO detection and precoding architectures. [Doctoral Dissertation]. University of Oulu; 2019. Available from: http://urn.fi/urn:isbn:9789526222837
Texas A&M University
8.
Wang, Weihuang.
Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.
Degree: 2009, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2504
► This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels…
(more)
▼ This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading
channels and general AWGN channels. A model of a memory-efficient low-power
high-throughput multi-rate array LDPC decoder as well as its FPGA implementa-
tion results is first presented. Then, I propose a decoding scheme that provides the
feature of constant-time decoding and thus facilitates real-time applications where
guaranteed data rate is required. It pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The
results are then used to dynamically adjust decoder frequency and switch between
multiple-voltage levels; thereby energy use is minimized. This is in contrast to the
conventional fixed-iteration decoding schemes that operate at a fixed voltage level
regardless of the quality of data received. Analysis shows that the proposed decoding
scheme is widely applicable for both two-phase message-passing (TPMP) decoding
algorithm and turbo decoding message passing (TDMP) decoding algorithm in block
fading channels, and it is independent of the specific LDPC decoder architecture. A
decoder architecture utilizing our recently published multi-rate decoding architecture
for general AWGN channels is also presented. The result of this thesis is a decoder
design scheme that provides a judicious trade-off between power consumption and
coding gain.
Advisors/Committee Members: Choi, Gwan (advisor), Chamberland, Jean-Francois (committee member), Reddy, A. L. Narasimha (committee member), Walker, Duncan M. (committee member).
Subjects/Keywords: VLSI; LDPC; low power
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APA (6th Edition):
Wang, W. (2009). Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2504
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Wang, Weihuang. “Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.” 2009. Thesis, Texas A&M University. Accessed January 22, 2020.
http://hdl.handle.net/1969.1/ETD-TAMU-2504.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Wang, Weihuang. “Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.” 2009. Web. 22 Jan 2020.
Vancouver:
Wang W. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2504.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Wang W. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2504
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
9.
Hu, Shiyan.
Algorithmic techniques for nanometer VLSI design and manufacturing closure.
Degree: 2008, Texas A&M University
URL: http://hdl.handle.net/1969.1/85905
► As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip…
(more)
▼ As Very Large Scale Integration (
VLSI) technology moves to the nanoscale
regime, design and manufacturing closure becomes very difficult to achieve due to
increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of
individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's
law as well as the growth of semiconductor industry.
Efforts are needed in both deterministic design stage and variation-aware design
stage. This research proposes various innovative algorithms to address both stages for
obtaining a design with high frequency, low power and high robustness. For deterministic optimizations, new buffer insertion and gate sizing techniques are proposed. For
variation-aware optimizations, new lithography-driven and post-silicon tuning-driven
design techniques are proposed.
For buffer insertion, a new slew buffering formulation is presented and is proved
to be NP-hard. Despite this, a highly efficient algorithm which runs > 90x faster
than the best alternatives is proposed. The algorithm is also extended to handle
continuous buffer locations and blockages.
For gate sizing, a new algorithm is proposed to handle discrete gate library in
contrast to unrealistic continuous gate library assumed by most existing algorithms. Our approach is a continuous solution guided dynamic programming approach, which
integrates the high solution quality of dynamic programming with the short runtime
of rounding continuous solution.
For lithography-driven optimization, the problem of cell placement considering
manufacturability is studied. Three algorithms are proposed to handle cell flipping
and relocation. They are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between variation reduction and wire-
length increase.
For post-silicon tuning-driven optimization, the problem of unified adaptivity
optimization on logical and clock signal tuning is studied, which enables us to significantly save resources. The new algorithm is based on a novel linear programming
formulation which is solved by an advanced robust linear programming technique.
The continuous solution is then discretized using binary search accelerated dynamic
programming, batch based optimization, and Latin Hypercube sampling based fast
simulation.
Advisors/Committee Members: Hu, Jiang (advisor), Cheng, Mosong (committee member), Shi, Weiping (committee member), Friesen, Donald (committee member), Alpert, Charles (committee member).
Subjects/Keywords: Physical Design; VLSI CAD
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APA (6th Edition):
Hu, S. (2008). Algorithmic techniques for nanometer VLSI design and manufacturing closure. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/85905
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Hu, Shiyan. “Algorithmic techniques for nanometer VLSI design and manufacturing closure.” 2008. Thesis, Texas A&M University. Accessed January 22, 2020.
http://hdl.handle.net/1969.1/85905.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Hu, Shiyan. “Algorithmic techniques for nanometer VLSI design and manufacturing closure.” 2008. Web. 22 Jan 2020.
Vancouver:
Hu S. Algorithmic techniques for nanometer VLSI design and manufacturing closure. [Internet] [Thesis]. Texas A&M University; 2008. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1969.1/85905.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Hu S. Algorithmic techniques for nanometer VLSI design and manufacturing closure. [Thesis]. Texas A&M University; 2008. Available from: http://hdl.handle.net/1969.1/85905
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
10.
Jiang, Zhanyuan.
Performance and power optimization in VLSI physical design.
Degree: 2009, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2024
► As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out…
(more)
▼ As
VLSI technology enters the nanoscale regime, a great amount of efforts have
been made to reduce interconnect delay. Among them, buffer insertion stands out
as an effective technique for timing optimization. A dramatic rise in on-chip buffer
density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates
are buffers.
In this thesis, three buffer insertion algorithms are presented for the procedure
of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under
the dynamic programming framework and runs in provably linear time for multiple
buffer types due to two novel techniques: restrictive cost bucketing and efficient delay
update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution
quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter
time and the buffered tree has better timing.
The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce
via variation and signal distortion in twisted differential line. In addition, a new
buffer insertion technique is proposed to synchronize the transmitted signals, thus
further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new
approaches. In contrast, only a 100MHz signal can be reliably transmitted using a
single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45%
as witnessed in our simulation.
The fourth chapter proposes a buffer insertion and gate sizing algorithm for
million plus gates. The algorithm takes a combinational circuit as input instead of
individual nets and greatly reduces the buffer and gate cost of the entire circuit.
The algorithm has two main features: 1) A circuit partition technique based on the
criticality of the primary inputs, which provides the scalability for the algorithm, and
2) A linear programming formulation of non-linear delay versus cost tradeoff, which
formulates the simultaneous buffer insertion and gate sizing into linear programming
problem. Experimental results on ISCAS85 circuits show that even without the circuit
partition technique, the new algorithm achieves 17X speedup compared with path
based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9%
gate cost, 5.8% total cost and results in less circuit delay.
Advisors/Committee Members: Shi, Weiping (advisor), Friesen, Donald K. (committee member), Hu, Jiang (committee member).
Subjects/Keywords: VLSI; physical design; buffer insertion
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Manager
APA (6th Edition):
Jiang, Z. (2009). Performance and power optimization in VLSI physical design. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2024
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Jiang, Zhanyuan. “Performance and power optimization in VLSI physical design.” 2009. Thesis, Texas A&M University. Accessed January 22, 2020.
http://hdl.handle.net/1969.1/ETD-TAMU-2024.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Jiang, Zhanyuan. “Performance and power optimization in VLSI physical design.” 2009. Web. 22 Jan 2020.
Vancouver:
Jiang Z. Performance and power optimization in VLSI physical design. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2024.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Jiang Z. Performance and power optimization in VLSI physical design. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2024
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
11.
Mandal, Ayan.
Efficient Design and Clocking for a Network-on-Chip.
Degree: 2013, Texas A&M University
URL: http://hdl.handle.net/1969.1/149325
► As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC)…
(more)
▼ As
VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC) paradigm has emerged as an efficient and scalable infrastructure to handle the communication needs for such multi-core systems. In most existing NoCs, design decisions are made assuming that the NoC operates at the same or lower clock speed as the cores, which slows down the communication system. A major challenge in designing a high speed NoC is the difficulty of distributing a high speed, low power clock across the chip.
In this dissertation, we first propose several techniques to address the issue of distributing a high-speed, low power, low jitter clock across the IC. We primarily focus our attention on resonant standing wave oscillators (SWOs), which have recently emerged as a promising technique for high-speed, low power clock generation. In addition, we also present a dynamic programming based approach to synthesize a low jitter, low power buffered H-tree for clock distribution. In the second part of this dissertation, we use these efficient clock distribution schemes to present a novel fast NoC design that relies on source synchronous data transfer over a ring. In our source-synchronous design, the clock and data NoC are routed in parallel yielding a fast, robust design.
Architectural simulations on synthetic and real traffic show that our source-synchronous NoC designs can provide significantly lower latency while achieving the same or better bandwidth compared to a state of the art mesh, while consuming lower area. The fact that the our ring-based NoC runs significantly faster than the mesh contributes to these improvements. Moreover, since our proposed NoC designs are fully synchronous, they are very amenable to testing as well.
In the last part of this dissertation, we explore an alternate scheme of achieving high-speed on-chip data transfer using sinusoidal signals of different frequencies. The key advantage of our method is the ability to superimpose such sinusoids and thereby effectively send multiple logic values along the same wire in a clock cycle. Experimental results show that for the same throughput as that of a traditional scheme, we require significantly fewer wires.
Advisors/Committee Members: Khatri, Sunil P (advisor), Mahapatra, Rabi N (advisor), Walker, Duncan M (committee member), Bettati, Riccardo (committee member), Chiou, Derek (committee member).
Subjects/Keywords: Network-on-Chip; Clock; VLSI
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APA (6th Edition):
Mandal, A. (2013). Efficient Design and Clocking for a Network-on-Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149325
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Thesis, Texas A&M University. Accessed January 22, 2020.
http://hdl.handle.net/1969.1/149325.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Web. 22 Jan 2020.
Vancouver:
Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1969.1/149325.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149325
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
12.
Jain, Shruti.
Communication of Signals and Responses Leading to Cell
Survival Cell Death Using Engineered Regulatory Networks;.
Degree: 2013, Jaypee University of Information Technology, Solan
URL: http://shodhganga.inflibnet.ac.in/handle/10603/11161
► Biological systems can create complex structures from very simple systems. To do this, there must be a method to differentiate different regions where identical systems…
(more)
▼ Biological systems can create complex structures
from very simple systems. To do this, there must be a method to
differentiate different regions where identical systems create
different structures, such as the abdomen and the head of a fruit
fly. This thesis highlights an emerging field known as Synthetic
Biology that envisions integrating designed circuits into living
organisms in order to instruct them to make logical decisions based
on the prevailing intracellular and extra cellular conditions and
produce a reliable behavior. Synthetic Biology attempts to
construct and assemble such modules gradually, plug the modules
together and modify them, in order to generate a desired behavior.
Using biological circuit, we can produce a new concentration
gradient that has twice the frequency. If 1 is represented by a
concentration of the chemical within the threshold, and a 0 is
represented by a concentration outside the threshold, then we can
represent any two digit binary number. Thus, we can differentiate
separate regions at certain distances away from a point source.
Logic gates are the basic building blocks in electronic circuits
that perform logical operations. These have input and output
signals in the form of 0 s and 1 s; 0 signifies the absence of
signal while 1 signifies its presence. newlineThe study focuses on
system implementation of a signals and responses triggered by Tumor
Necrosis Factor- and#945; (TNF-and#945;), Epidermal Growth Factor
(EGF) and Insulin factors leading to cell survival/ apoptosis. The
computational techniques that have been used are: VHDL (Xilinx
Tool), CMOS and BiCMOS (SPICE Tool), and Fuzzy Logic (MATLAB Tool),
Non Linear Model (Artificial Neural Networks) and Deterministic
Model taking three input signals. In future we are also trying to
develop bio-simulator that can be used for prediction of status of
the cell leading to cell survival/ apoptosis giving chemotherapy
and radiotherapy treatment. newline
Advisors/Committee Members: Naik, Pradeep Kumar, Bhooshan, Sunil
Vidya.
Subjects/Keywords: CMOS; Fuzzy Logic; VLSI
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APA (6th Edition):
Jain, S. (2013). Communication of Signals and Responses Leading to Cell
Survival Cell Death Using Engineered Regulatory Networks;. (Thesis). Jaypee University of Information Technology, Solan. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/11161
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Jain, Shruti. “Communication of Signals and Responses Leading to Cell
Survival Cell Death Using Engineered Regulatory Networks;.” 2013. Thesis, Jaypee University of Information Technology, Solan. Accessed January 22, 2020.
http://shodhganga.inflibnet.ac.in/handle/10603/11161.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Jain, Shruti. “Communication of Signals and Responses Leading to Cell
Survival Cell Death Using Engineered Regulatory Networks;.” 2013. Web. 22 Jan 2020.
Vancouver:
Jain S. Communication of Signals and Responses Leading to Cell
Survival Cell Death Using Engineered Regulatory Networks;. [Internet] [Thesis]. Jaypee University of Information Technology, Solan; 2013. [cited 2020 Jan 22].
Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11161.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Jain S. Communication of Signals and Responses Leading to Cell
Survival Cell Death Using Engineered Regulatory Networks;. [Thesis]. Jaypee University of Information Technology, Solan; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11161
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Florida
13.
Sadi, Mehdi Zahid.
On-Chip Structures for Reliability Management of System-On-Chips.
Degree: PhD, Electrical and Computer Engineering, 2017, University of Florida
URL: http://ufdc.ufl.edu/UFE0051010
► With aggressive technology scaling in the finfet era the transistor density per unit chip area has increased significantly over the past decade. As a result…
(more)
▼ With aggressive technology scaling in the finfet era the transistor density per unit chip area has increased significantly over the past decade. As a result billion transistor complex System on Chips (SoC) that integrate multicore processors, memory, ASIC on the same die are becoming the trend. The semiconductor design houses actively conform to this trend to remain competitive in the global market. Although the complex design of emerging SoCs offer significant performance boost with innovative features, maintaining lifetime reliable operation of these SoCs are becoming a challenge. To develop an integrated framework for continuous monitoring of key hardware reliability parameters, we explore the design of novel embedded on-chip structures that can collect key reliability data from critical components of the SoC in-field. Moreover, we explore the use of software level machine learning techniques to process the data collected by these on-chip macros for the reliability and integrity management of SoCs. In this presentation the primary focus will be on the reliability challenges stemming from power supply noise, timing delay of critical paths, and in-field aging degradation.
Advisors/Committee Members: TEHRANIPOOR,MARK M (committee chair), BHUNIA,SWARUP (committee member), BUTLER,KEVIN (committee member).
Subjects/Keywords: reliability – system-on-chip – vlsi
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APA (6th Edition):
Sadi, M. Z. (2017). On-Chip Structures for Reliability Management of System-On-Chips. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0051010
Chicago Manual of Style (16th Edition):
Sadi, Mehdi Zahid. “On-Chip Structures for Reliability Management of System-On-Chips.” 2017. Doctoral Dissertation, University of Florida. Accessed January 22, 2020.
http://ufdc.ufl.edu/UFE0051010.
MLA Handbook (7th Edition):
Sadi, Mehdi Zahid. “On-Chip Structures for Reliability Management of System-On-Chips.” 2017. Web. 22 Jan 2020.
Vancouver:
Sadi MZ. On-Chip Structures for Reliability Management of System-On-Chips. [Internet] [Doctoral dissertation]. University of Florida; 2017. [cited 2020 Jan 22].
Available from: http://ufdc.ufl.edu/UFE0051010.
Council of Science Editors:
Sadi MZ. On-Chip Structures for Reliability Management of System-On-Chips. [Doctoral Dissertation]. University of Florida; 2017. Available from: http://ufdc.ufl.edu/UFE0051010
University of Southern California
14.
Kashfi, Fatemeh.
Thermal analysis and multiobjective optimization for three
dimensional integrated circuits.
Degree: PhD, Electrical Engineering (VLSI Design), 2013, University of Southern California
URL: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7428
► Three Dimensional Integrated Circuit (3DIC) technology has been introduced to address the interconnect issues in nanometer circuit design that limit performance improvement and power reduction.…
(more)
▼ Three Dimensional Integrated Circuit (3DIC) technology
has been introduced to address the interconnect issues in nanometer
circuit design that limit performance improvement and power
reduction. However, stacking active layers of silicon leads to
increased power density and overall higher temperatures in a 3D
chip implementation for many designs. New thermal map modeling, and
temperature measurement, mitigation and management techniques
should be introduced for this technology. In this dissertation we
study the thermal correlation between the stacked layers in 3DICs.
We then propose a fast and efficient 3D thermal map modeling based
on scaled hotspot areas, depending on the distance of a stacked
layer from the heatsink and also thermal effects of the layers on
each other. The modeling is 53× faster than the existing method of
temperature compact modeling. The efficiency of the proposed
modeling is demonstrated with its use in a thermal sensor
distribution algorithm. We also show that the thermal sensor
distribution algorithm should be solved as a 3D problem. In this
way for the same sensor reading error the total number of needed
sensors is reduced by 44%. We furthermore propose a new 3D design
for thermal sensor circuits to be shared between layers in a 3DIC.
Using 3D thermal sensors that are shared between adjacent layers
can reduce the total number of needed sensors by half. ❧ We also
study different methods of multiobjective optimization to find the
optimum operating point of a
VLSI circuit. We provide wide
mathematical analyses of different multiobjective optimization
techniques for this purpose. We also study the difference of convex
and non-convex modeling of the objectives in the multiobjective
optimization algorithms. ❧ We apply our multiobjective optimization
methods to optimize three conflicting objectives of cost,
performance and thermal reliability to find an optimum building
block placement in 3DICs. The variables for the optimization are
the number of layers, area of the 3DIC, position of the building
blocks, number of TSVs and total wirelength. We used our proposed
fast 3D thermal map modeling to eliminate the thermal analysis
bottleneck in multiobjective optimization iterations. In comparison
with a previous state-of-the-art multiobjective optimization method
which employs Simulated Annealing, a weighted sum method of
scalarization and compact modeling for thermal analysis, our method
reduces the peak temperature of a representative 3DIC by 4.3% and
total wire length by 5.7% while it is more than 17× faster in
optimization runtime. The execution runtime of the proposed
algorithm also scales linearly with problem size in contrast with
the existing heuristic method of Simulated Annealing, which scales
poorly with problem size.
Advisors/Committee Members: Draper, Jeffrey (Committee Chair), Gupta, Sandeep K. (Committee Member), Nakano, Aiichiro (Committee Member).
Subjects/Keywords: 3DIC; optimization; temperature; electronics; VLSI
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APA (6th Edition):
Kashfi, F. (2013). Thermal analysis and multiobjective optimization for three
dimensional integrated circuits. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7428
Chicago Manual of Style (16th Edition):
Kashfi, Fatemeh. “Thermal analysis and multiobjective optimization for three
dimensional integrated circuits.” 2013. Doctoral Dissertation, University of Southern California. Accessed January 22, 2020.
http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7428.
MLA Handbook (7th Edition):
Kashfi, Fatemeh. “Thermal analysis and multiobjective optimization for three
dimensional integrated circuits.” 2013. Web. 22 Jan 2020.
Vancouver:
Kashfi F. Thermal analysis and multiobjective optimization for three
dimensional integrated circuits. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2020 Jan 22].
Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7428.
Council of Science Editors:
Kashfi F. Thermal analysis and multiobjective optimization for three
dimensional integrated circuits. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7428
University of Cincinnati
15.
SINGH, ARUN.
Design of Current Sensors to measure small current signals
of pico-amperes to nano-amperes in magnitude.
Degree: MS, Engineering : Electrical Engineering, 2008, University of Cincinnati
URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1205161608
► The primary goal of this research work is to amperometrically measure small current signals, in the range of pico-ampere to nano-ampere that are produced by…
(more)
▼ The primary goal of this research work is to
amperometrically measure small current signals, in the range of
pico-ampere to nano-ampere that are produced by electrolytic
reactions of micro-electrode sensors. Two circuit designs viz.
Type-I and Type-II have been described, which are capable of
measuring such small current signals. Simulation results obtained
from this thesis work predict the behavior of these circuits for
three different technologies viz. AMI 1.5 micron, AMI 0.5 micron
and TSMC 0.3 micron. These circuits were laid and fabricated
through the MOSIS foundry service using the AMI 1.5 micron
technology. The circuits were tested after fabrication and
experimental results were reported illustrating the performance of
these circuits in measuring small current signals. Type-I circuit
was found to produce appreciable change in output voltage to detect
currents of magnitude as low as 1nA. The sensitivity of the circuit
for input currents varying from 1nA to 1uA was found to be
reasonably high. The amperometric circuits described in this work
occupy low area and also consume low power in the range of tens of
milli-watts. The ability of these amperometric circuits to measure
small signal currents coupled with low area and power consumption
make them an integral part of any analog system with wide
applications in medical and biological field as well as in optical
sensor areas.
Advisors/Committee Members: Beyette, Fred (Committee Chair).
Subjects/Keywords: Engineering; Current Sensor; vlsi
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Manager
APA (6th Edition):
SINGH, A. (2008). Design of Current Sensors to measure small current signals
of pico-amperes to nano-amperes in magnitude. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1205161608
Chicago Manual of Style (16th Edition):
SINGH, ARUN. “Design of Current Sensors to measure small current signals
of pico-amperes to nano-amperes in magnitude.” 2008. Masters Thesis, University of Cincinnati. Accessed January 22, 2020.
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1205161608.
MLA Handbook (7th Edition):
SINGH, ARUN. “Design of Current Sensors to measure small current signals
of pico-amperes to nano-amperes in magnitude.” 2008. Web. 22 Jan 2020.
Vancouver:
SINGH A. Design of Current Sensors to measure small current signals
of pico-amperes to nano-amperes in magnitude. [Internet] [Masters thesis]. University of Cincinnati; 2008. [cited 2020 Jan 22].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1205161608.
Council of Science Editors:
SINGH A. Design of Current Sensors to measure small current signals
of pico-amperes to nano-amperes in magnitude. [Masters Thesis]. University of Cincinnati; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1205161608
Louisiana State University
16.
Mekala, Hemalatha.
Third order CMOS decimator design for sigma delta modulators.
Degree: MS, Electrical and Computer Engineering, 2009, Louisiana State University
URL: etd-11092009-163619
;
https://digitalcommons.lsu.edu/gradschool_theses/858
► A third order Cascaded Integrated Comb (CIC) filter has been designed in 0.5μm n-well CMOS process to interface with a second order oversampling sigma-delta ADC…
(more)
▼ A third order Cascaded Integrated Comb (CIC) filter has been designed in 0.5μm n-well CMOS process to interface with a second order oversampling sigma-delta ADC modulator. The modulator was designed earlier in 0.5μm technology. The CIC filter is designed to operate with 0 to 5V supply voltages. The modulator is operated with ±2.5V supply voltage and a fixed oversampling ratio of 64. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit, which divides the input clock by 64. The CIC filter is designed to work with an ADC that operates at a maximum oversampling clock frequency of up to 25 MHz and with baseband signal bandwidth of up to 800 kHz. The design and performance of the CIC filter fabricated has been discussed.
Subjects/Keywords: CIC filter; Decimator; VLSI; Hemalatha
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APA (6th Edition):
Mekala, H. (2009). Third order CMOS decimator design for sigma delta modulators. (Masters Thesis). Louisiana State University. Retrieved from etd-11092009-163619 ; https://digitalcommons.lsu.edu/gradschool_theses/858
Chicago Manual of Style (16th Edition):
Mekala, Hemalatha. “Third order CMOS decimator design for sigma delta modulators.” 2009. Masters Thesis, Louisiana State University. Accessed January 22, 2020.
etd-11092009-163619 ; https://digitalcommons.lsu.edu/gradschool_theses/858.
MLA Handbook (7th Edition):
Mekala, Hemalatha. “Third order CMOS decimator design for sigma delta modulators.” 2009. Web. 22 Jan 2020.
Vancouver:
Mekala H. Third order CMOS decimator design for sigma delta modulators. [Internet] [Masters thesis]. Louisiana State University; 2009. [cited 2020 Jan 22].
Available from: etd-11092009-163619 ; https://digitalcommons.lsu.edu/gradschool_theses/858.
Council of Science Editors:
Mekala H. Third order CMOS decimator design for sigma delta modulators. [Masters Thesis]. Louisiana State University; 2009. Available from: etd-11092009-163619 ; https://digitalcommons.lsu.edu/gradschool_theses/858
Delft University of Technology
17.
Moar Gomez, J.
90 nm VLSI Design of an 8-bits Microcontroller:.
Degree: Electrical Engineering, Mathematics, Computer Sci, Microelectronics, 2009, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc
► Integrated Circuit (IC) design complexity has increased radically since the first "hand-made" designs in the late 50s, with a few transistors. Nowadays, Very Large Scale…
(more)
▼ Integrated Circuit (IC) design complexity has increased radically since the first "hand-made" designs in the late 50s, with a few transistors. Nowadays, Very Large Scale Integration (
VLSI) designs contains hundreds thousand, million or even billion transistors and not only the experience of the designer, but also Electronic Design Automation (EDA) tools and some methodology is needed. The purpose of this thesis is the design in 90nm UMC technology of an 8-bit microcontroller for its final manufacture using Modelsim, Design Compiler and SoC Encounter and following a standard cell design methodology. During the different steps of the
VLSI flow (behavioural specification and verification, synthesis and layout generation), it will be shown how to deal with the design issues that arise: (DFT insertion, clock gating, clock\&reset tree generation, etc.). Starting from a tested FPGA implementation in VHDL based on the AVR ATmega103 microcontroller from ATMEL, the final result is an 8-bit microcontroller with the following features: 16k x 16 bits of Program Memory (PM), 8K bytes Data Memory (DM), 256 bytes parameter memory, 3 8bits I/O ports, UART, SPI, JTAG interface, additional PM programming capability (apart from the JTAG) and Wishbone interface including an USB 1.1 slave and another slave to implement and test a simple scan chain prototype. In addition the clock frequency can be increased up to 200 MHz.
Advisors/Committee Members: Van Leuken, T.G.R.M., Van der Veen, A.J., Serdijn, W.A..
Subjects/Keywords: vlsi; microcontroller; 90nm; wishbone
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APA (6th Edition):
Moar Gomez, J. (2009). 90 nm VLSI Design of an 8-bits Microcontroller:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc
Chicago Manual of Style (16th Edition):
Moar Gomez, J. “90 nm VLSI Design of an 8-bits Microcontroller:.” 2009. Masters Thesis, Delft University of Technology. Accessed January 22, 2020.
http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc.
MLA Handbook (7th Edition):
Moar Gomez, J. “90 nm VLSI Design of an 8-bits Microcontroller:.” 2009. Web. 22 Jan 2020.
Vancouver:
Moar Gomez J. 90 nm VLSI Design of an 8-bits Microcontroller:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2020 Jan 22].
Available from: http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc.
Council of Science Editors:
Moar Gomez J. 90 nm VLSI Design of an 8-bits Microcontroller:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:8a569a87-a972-480c-bd7d-11292b3f5cdc
Texas A&M University
18.
Wang, Qian.
Architectures and Design of VLSI Machine Learning Systems.
Degree: PhD, Computer Engineering, 2016, Texas A&M University
URL: http://hdl.handle.net/1969.1/158093
► Quintillions of bytes of data are generated every day in this era of big data. Machine learning techniques are utilized to perform predictive analysis on…
(more)
▼ Quintillions of bytes of data are generated every day in this era of big data. Machine learning techniques are utilized to perform predictive analysis on these data, to reveal hidden relationships and dependencies and perform predictions of outcomes and behaviors. The obtained predictive models are used to interpret the existing data and predict new data information.
Nowadays, most machine learning algorithms are realized by software programs running on general-purpose processors, which usually takes a huge amount of CPU time and introduces unbelievably high energy consumption. In comparison, a dedicated hardware design is usually much more efficient than software programs running on general-purpose processors in terms of runtime and energy consumption. Therefore, the objective of this dissertation is to develop efficient hardware architectures for mainstream machine learning algorithms, to provide a promising solution to addressing the runtime and energy bottlenecks of machine learning applications. However, it is a really challenging task to map complex machine learning algorithms to efficient hardware architectures. In fact, many important design decisions need to be made during the hardware development for efficient tradeoffs.
In this dissertation, a parallel digital
VLSI architecture for combined SVM training and classification is proposed. For the first time, cascade SVM, a powerful training algorithm, is leveraged to significantly improve the scalability of hardware-based SVM training and develop an efficient parallel
VLSI architecture. The parallel SVM processors provide a significant training time speedup and energy reduction compared with the software SVM algorithm running on a general-purpose CPU.
Furthermore, a liquid state machine based neuromorphic learning processor with integrated training and recognition is proposed. A novel theoretical measure of computational power is proposed to facilitate fast design space exploration of the recurrent reservoir. Three low-power techniques are proposed to improve the energy efficiency. Meanwhile, a 2-layer spiking neural network with global inhibition is realized on Silicon.
In addition, we also present architectural design exploration of a brain-inspired digital neuromorphic processor architecture with memristive synaptic crossbar array, and highlight several synaptic memory access styles. Various analog-to-digital converter schemes have been investigated to provide new insights into the tradeoff between the hardware cost and energy consumption.
Advisors/Committee Members: Li, Peng (advisor), Choi, Gwan (advisor), Palermo, Sam (committee member), Choe, Yoonsuck (committee member).
Subjects/Keywords: Machine learning; VLSI architecture
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APA (6th Edition):
Wang, Q. (2016). Architectures and Design of VLSI Machine Learning Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/158093
Chicago Manual of Style (16th Edition):
Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Doctoral Dissertation, Texas A&M University. Accessed January 22, 2020.
http://hdl.handle.net/1969.1/158093.
MLA Handbook (7th Edition):
Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Web. 22 Jan 2020.
Vancouver:
Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1969.1/158093.
Council of Science Editors:
Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/158093
University of Toronto
19.
Yu, Jingshu.
A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.
Degree: 2014, University of Toronto
URL: http://hdl.handle.net/1807/67870
► In this thesis, an integrated H-bridge is presented for continuously optimizing the power conversion efficiency over a wide range of output current. The proposed IC…
(more)
▼ In this thesis, an integrated H-bridge is presented for continuously optimizing the power conversion efficiency over a wide range of output current. The proposed IC incorporates both segmented output transistors and segmented gate drivers. This fully segmentation approach allows to flexibly change the on-resistance of the output stage power transistors and the output resistance of the gate drivers. Dynamic adjustment of these parameters allows to investigate the best combination of output power transistor size and gate driver size for any given load current. The IC chip is fabricated using TSMC's 0.18 um BCD Gen-2 process technology. The presented design when operating as a buck converter with a load current between 0.02 A and 4 A achieves efficiency improvements of 32% and 8% at light and heavy load current, respectively. Furthermore, the dynamically adjustable gate driver output resistance allows for suppression of the peak CEMI by 5.5 dBm.
M.A.S.
Advisors/Committee Members: Ng, Wai Tung, Electrical and Computer Engineering.
Subjects/Keywords: Power Electronics; VLSI; 0544
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APA (6th Edition):
Yu, J. (2014). A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/67870
Chicago Manual of Style (16th Edition):
Yu, Jingshu. “A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.” 2014. Masters Thesis, University of Toronto. Accessed January 22, 2020.
http://hdl.handle.net/1807/67870.
MLA Handbook (7th Edition):
Yu, Jingshu. “A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.” 2014. Web. 22 Jan 2020.
Vancouver:
Yu J. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1807/67870.
Council of Science Editors:
Yu J. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/67870
20.
Kananen, Asko.
A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.
Degree: 2007, Helsinki University of Technology
URL: http://lib.tkk.fi/Diss/2007/isbn9789512286232/
► This thesis deals with silicon implementations of an all-transistor analogue parallel processor that emulates the functionality of a resistive network. The problems related to VLSI -implementations…
(more)
▼ This thesis deals with silicon implementations of an all-transistor analogue parallel processor that emulates the functionality of a resistive network. The problems related to VLSI -implementations of parallel processors are the main concern of this thesis. These problems are first discussed and then to overcome these problems, a new system design is introduced, namely Reduced Cell-row System (RCS). The work started from a resistive network -type spatial filter that was part of a video image compression algorithm. The functionality of this algorithm, as well as the filter, was described in Cellular Neural/Nonlinear Network (CNN) notations and they will be used throughout this thesis in describing the filters and processing operations. In addition to the resistive network array processor, a gradient calculation block was included on the chips to fulfil the original algorithm requirements. Two different array processors were manufactured and measured. The processors had different objectives for their implementation: in the first implementation, the objective was to test the developed Reduced Cell-row System, while in the second implementation the goal was to obtain information on the large-scale implementation of such an array. During the research, a method to include some level of programmability in this type of filters was also developed. For the possible future implementation of such a system, system-level simulations were performed to locate the critical parts that have the most effect on the accuracy of the network.
Tämä työ käsittelee vastusverkkojen toiminnallisuuden toteuttamista analogisena rinnakkaisprosessoritoteutuksena VLSI-piirillä käyttäen ainoastaan MOS-transistoreja. Työssä on ensin käsitelty rinnakkaisprosessorien toteutukseen liittyviä ongelmia, minkä jälkeen esitellään uusi toteutusmenetelmä ongelmien ratkaisuksi. Menetelmää kutsutaan nimellä "Reduced Cell-row System" (RCS). Työn lähtökohta oli vastusverkko-tyyppinen spatiaalisuodatin, joka oli esitetty osana videopakkausalgoritmia. Algoritmin toiminnallisuus, kuten myös suodattimen, oli kuvattu alkuperäisessä algoritmissa epälineaaristen soluverkkojen "Cellular Neural/Nonlinear Network" (CNN) merkintöjä käyttäen ja näitä merkintöjä tullaan käyttämään koko kirjan ajan kuvattaessa suodattimien toiminnallisuutta. Vastusverkkototeutuksen lisäksi myös gradientinlaskentalohko on lisätty piireihin alkuperäisen algoritmin toteuttamiseksi. Kaksi tällaista rinnakkaisprosessoriverkkoa suunniteltiin, valmistutettiin ja mitattiin. Näiden kahden toteutuksen tavoitteet olivat erilaiset: ensimmäinen toteutettiin, jotta voitaisiin todentaa kehitetyn verkon rivien lukumäärää vähentävän menetelmän (RCS) toimivuus, kun taas toisen toteutuksen tavoitteena oli tutkia laajamittaisen toteutuksen ongelmia. Työn aikana kehitettiin myös menetelmä, miten prosessoriverkkoon voidaan lisätä säädettävyyttä ja tällaisen prosessoriverkon toteutukselle suoritettiin simuloinnit, jotta voitaisiin selvittää toteuksen kannalta kriittiset kohdat.
TKK dissertations, ISSN…
Advisors/Committee Members: Helsinki University of Technology, Department of Electrical and Communications Engineering, Electronic Circuit Design Laboratory.
Subjects/Keywords: analogue parallel processor; VLSI; resistive network; analoginen rinnakkaisprosessori; VLSI; vastusverkko
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APA (6th Edition):
Kananen, A. (2007). A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. (Thesis). Helsinki University of Technology. Retrieved from http://lib.tkk.fi/Diss/2007/isbn9789512286232/
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Kananen, Asko. “A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.” 2007. Thesis, Helsinki University of Technology. Accessed January 22, 2020.
http://lib.tkk.fi/Diss/2007/isbn9789512286232/.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Kananen, Asko. “A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.” 2007. Web. 22 Jan 2020.
Vancouver:
Kananen A. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. [Internet] [Thesis]. Helsinki University of Technology; 2007. [cited 2020 Jan 22].
Available from: http://lib.tkk.fi/Diss/2007/isbn9789512286232/.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Kananen A. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. [Thesis]. Helsinki University of Technology; 2007. Available from: http://lib.tkk.fi/Diss/2007/isbn9789512286232/
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
21.
Reimann, Tiago Jose.
Roteamento global de circuitos VLSI.
Degree: 2013, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/71269
► Este trabalho apresenta a implementação de um roteador global de circuitos integrados capaz de tratar os problemas de roteamento atuais, utilizando como referência para avaliação…
(more)
▼ Este trabalho apresenta a implementação de um roteador global de circuitos integrados capaz de tratar os problemas de roteamento atuais, utilizando como referência para avaliação os circuitos de benchmark publicados durante as competições de roteamento global realizadas no ACM International Symposium on Physical Design 2007 e 2008. O roteador global desenvolvido utiliza como ferramenta principal a técnica de ripup and reroute associada às técnicas de roteamento monotônico e maze routing, ambas com grande histórico de uso nas ferramentas acadêmicas descritas também neste trabalho. O desenvolvimento da ferramenta também possui características diferenciadas e únicas, com um novo método de ordenamento das redes durante a fase de rip-up and reroute. Para a geração dos resultados foram definidas duas versões diferentes da ferramenta, sendo estas duas versões analisadas com duas diferentes técnicas de construção das árvores de roteamento, gerando no total quatro configurações da ferramenta. Como decisão de projeto, a versão principal utilizada no desenvolvimento e discussão dos resultados é a versão que prioriza a qualidade do roteamento, utilizando MSTs para construção das árvores de roteamento. Os resultados mostram que o roteador global desenvolvido é capaz de gerar resultados com boa qualidade mesmo sem fazer uso de técnicas de identificação de áreas de congestionamento, sem otimizações pós-roteamento e sem nenhuma forma de ajuste (tuning) para os diferentes circuitos de benchmark, apesar de ainda ter tempo de execução acima dos apresentados por outras ferramentas acadêmicas. O foco durante o processo de desenvolvimento e implementação da ferramenta foram os circuitos mais recentes, entretanto a ferramenta obteve ótimos resultados também para os circuitos publicados no ISPD 1998, gerando soluções com qualidade similar ou melhor que as reportadas na literatura. A diferença dos resultados deste trabalho em relação aos melhores resultados dos roteadores globais com código disponível, para circuitos 3D lançados no ISPD 2008 é de, em média, 1,78%1 na métrica de comprimento de fio sem considerar o custo das vias e de 15,56% considerando o custo da via como uma unidade de comprimento de fio (ISPD 2008), para a versão voltada a qualidade de roteamento. Já para a versão da ferramenta que busca a convergência o mais rápido possível a diferença foi de 3,39% e 16,32%, respectivamente. As maiores diferenças são encontradas nos circuitos mais difíceis de gerar uma solução sem violações. Isso mostra como as técnicas de identificação de região podem contribuir tanto para uma convergência mais rápida quanto para evitar que fios passem por rotas desnecessárias durante a fase de negociação. Na métrica que avalia as vias como custo de uma unidade de comprimento, os resultados obtidos apresentam em média 18,67% maior comprimento de fio que os melhores resultados da literatura, sendo que dois circuitos com solução sem violações2 apresentam resultado com violações utilizando a ferramenta desenvolvida neste trabalho.
This work describes…
Advisors/Committee Members: Reis, Ricardo Augusto da Luz.
Subjects/Keywords: Microeletrônica; Global routing; Physical synthesis; Vlsi; Roteamento : Circuitos integrados; CAD; VLSI
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APA ·
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APA (6th Edition):
Reimann, T. J. (2013). Roteamento global de circuitos VLSI. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/71269
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Reimann, Tiago Jose. “Roteamento global de circuitos VLSI.” 2013. Thesis, Universidade do Rio Grande do Sul. Accessed January 22, 2020.
http://hdl.handle.net/10183/71269.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Reimann, Tiago Jose. “Roteamento global de circuitos VLSI.” 2013. Web. 22 Jan 2020.
Vancouver:
Reimann TJ. Roteamento global de circuitos VLSI. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2013. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/10183/71269.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Reimann TJ. Roteamento global de circuitos VLSI. [Thesis]. Universidade do Rio Grande do Sul; 2013. Available from: http://hdl.handle.net/10183/71269
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
22.
Tumelero, Diego.
Exploração de paralelismo no roteamento global de circuitos VLSI.
Degree: 2015, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/119081
► Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos…
(more)
▼ Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos integrados inclui em um de seus passos o roteamento, que consiste em criar fios que interconectam as células do circuito. Devido à complexidade, o roteamento é dividido em global e detalhado. O roteamento global de circuitos VLSI é uma das tarefas mais complexas do fluxo de síntese física, sendo classificado como um problema NP-completo. Neste trabalho, além de realizar um levantamento de trabalhos que utilizam as principais técnicas de paralelismo com o objetivo de acelerar o processamento do roteamento global, foram realizadas análises nos arquivos de benchmark do ISPD 2007/08. Com base nestas análises foi proposto um método que agrupa as redes para então verificar a existência de dependência de dados em cada grupo. Esta verificação de dependência de dados, que chamamos neste trabalho de colisor, tem por objetivo, criar fluxos de redes independentes umas das outras para o processamento em paralelo, ou seja, ajudar a implementação do roteamento independente de redes. Os resultados demonstram que esta separação em grupos, aliada com a comparação concorrente dos grupos, podem reduzir em 67x o tempo de execução do colisor de redes se comparada com a versão sequencial e sem a utilização de grupos. Também foi obtido um ganho de 10x ao comparar a versão com agrupamentos sequencial com a versão paralela.
With the increasing of the functionality of integrated circuits, there is a consequent increase in the complexity of the design. The IC design flow includes the routing in one of its steps, which is to create wires that interconnect the circuit cells. Because of the complexity, routing is divided into global and detailed. The global routing of VLSI circuits is one of the most complex tasks in the flow of physical synthesis and it's classified as an NP-complete problem. In this work, a parallel computing techniques survey was applied to the VLSI global routing in order to accelerate the global routing processing analyzes. This analyzes was performed on the ISPD 2007/08 benchmark files. We proposed a method that groups the networks and then check for data dependence in each group based on these analyzes. This data dependency checking, we call this checking of collider, aims to create flow nets independent of each other for processing in parallel, or help implement the independent routing networks. The results demonstrate that this separation into groups, together with the competitor comparison of groups, can reduce 67x in the collider networks runtime compared with the sequential release and without the use of groups. It was also obtained a gain of 10x when comparing the version with sequential clusters with the parallel version.
Advisors/Committee Members: Reis, Ricardo Augusto da Luz.
Subjects/Keywords: Microeletrônica; Global routing; Parallelism; Paralelismo; Vlsi; EDA; VLSI; Microelectronics
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APA ·
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APA (6th Edition):
Tumelero, D. (2015). Exploração de paralelismo no roteamento global de circuitos VLSI. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/119081
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Tumelero, Diego. “Exploração de paralelismo no roteamento global de circuitos VLSI.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed January 22, 2020.
http://hdl.handle.net/10183/119081.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Tumelero, Diego. “Exploração de paralelismo no roteamento global de circuitos VLSI.” 2015. Web. 22 Jan 2020.
Vancouver:
Tumelero D. Exploração de paralelismo no roteamento global de circuitos VLSI. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/10183/119081.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Tumelero D. Exploração de paralelismo no roteamento global de circuitos VLSI. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/119081
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Iowa State University
23.
Zhang, Yanheng.
Handling the complexity of routing problem in modern VLSI design.
Degree: 2011, Iowa State University
URL: https://lib.dr.iastate.edu/etd/11896
► In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pins and ports of circuit gates and blocks. Traditionally, VLSI…
(more)
▼ In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pins and ports of circuit gates and blocks. Traditionally, VLSI routing is an important design step in the sense that the quality of routing solution has great impact on various design metrics such as circuit timing, power consumption, chip reliability and manufacturability etc. As the advancing VLSI design enters the nanometer era, the routing success (routability issue) has been arising as one of the most critical problems in back-end design. In one aspect, the degree of design complexity is increasing dramatically as more and more modules are integrated into the chip. Much higher chip density leads to higher routing demands and potentially more risks in routing failure. In another aspect, with decreasing design feature size, there are more complex design rules imposed to ensure manufacturability. These design rules are hard to satisfy and they usually create more barriers for achieving routing closure (i.e., generate DRC free routing solution) and thus affect chip time to market (TTM) plan.
In general, the behavior and performance of routing are affected by three consecutive phases: placement phase, global routing phase and detailed routing phase in a typical VLSI physical design flow. Traditional CAD tools handle each of the three phases independently and the global picture of the routability issue is neglected. Different from conventional approaches which propose tools and algorithms for one particular design phase, this thesis investigates the routability issue from all three phases and proposes a series of systematic solutions to build a more generic flow and improve quality of results (QoR). For the placement phase, we will introduce a mixed-sized placement refinement tool for alleviating congestion after placement. The tool shifts and relocates modules based on a global routing estimation. For the global routing phase, a very fast and effective global router is developed. Its performance surpasses many peer works as verified by ISPD 2008 global routing contest results. In the detailed routing phase, a tool is proposed to perform detailed routing using regular routing patterns based on a correct-by-construction methodology to improve routability as well as satisfy most design rules. Finally, the tool which integrates global routing and detailed routing is developed to remedy the inconsistency between global routing and detailed routing.
To verify the algorithms we proposed, three sets of testcases derived from ISPD98 and ISPD05/06 placement benchmark suites are proposed. The results indicate that our proposed methods construct an integrated and systematic flow for routability improvement which is better than conventional methods.
Subjects/Keywords: Physical Design; Routability; VLSI CAD; VLSI Routing; Electrical and Computer Engineering
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APA ·
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APA (6th Edition):
Zhang, Y. (2011). Handling the complexity of routing problem in modern VLSI design. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/11896
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Zhang, Yanheng. “Handling the complexity of routing problem in modern VLSI design.” 2011. Thesis, Iowa State University. Accessed January 22, 2020.
https://lib.dr.iastate.edu/etd/11896.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Zhang, Yanheng. “Handling the complexity of routing problem in modern VLSI design.” 2011. Web. 22 Jan 2020.
Vancouver:
Zhang Y. Handling the complexity of routing problem in modern VLSI design. [Internet] [Thesis]. Iowa State University; 2011. [cited 2020 Jan 22].
Available from: https://lib.dr.iastate.edu/etd/11896.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Zhang Y. Handling the complexity of routing problem in modern VLSI design. [Thesis]. Iowa State University; 2011. Available from: https://lib.dr.iastate.edu/etd/11896
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of California – San Diego
24.
Nath, Siddhartha.
New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.
Degree: Computer Science, 2016, University of California – San Diego
URL: http://www.escholarship.org/uc/item/9jn2c085
► In today's leading-edge semiconductor technologies, it is increasingly difficult for IC designers to achieve sufficient improvements of performance, power and area metrics in their next-generation…
(more)
▼ In today's leading-edge semiconductor technologies, it is increasingly difficult for IC designers to achieve sufficient improvements of performance, power and area metrics in their next-generation products. One root cause of this difficulty is the increased margins that are used in the design process to guardband for (i) variability and aging, as well as (ii) analysis inaccuracies. Currently, these margins incur huge costs to design companies, because the benefits of deploying the next technology node are only approximately 20% in circuit performance, power and density. To reduce margins, fast and accurate pathfinding of architecture, technology and constraints choices are essential. A second root cause is the high cost (and, therefore, limited supply) of electronic design automation tool licenses, accompanied by the lack of any systematic methodology to optimize the use of available tools within long-duration, highly iterative design processes. This constrains designers to perform only limited design-space exploration, so as to keep within limits on design infrastructure cost and design turnaround time. This thesis presents new techniques to reduce guardbands in optimization loops in the IC design process by using fast and accurate learning-based models. These techniques can be grouped into three main thrusts: (i) design productivity gains through improved design- and implementation-space exploration; (ii) improved accuracy of electrical modeling and enablement of basic physical design optimizations; and (iii) optimizations of design power, energy, project management, and cost.The thrust on design productivity gains through improved design- and implementation space exploration presents four applications of learning-based models for accurate prediction of area, power, timing and routability. To enable area and power estimation of Networks-on-Chip routers, such that architecture-level (RTL-level) design-space exploration can be efficiently performed, this thesis presents an open-source tool, ORION3.0.The thrust on improved accuracy of electrical modeling and enablement of basic physical design optimizations presents new methodologies to perform high-dimensional learning-based modeling of delay, transition time and slack in timing paths. A methodology to develop accurate models of post-routing optimization of signal delays at multiple signoff corners, so as to enable a new optimization of clock skew variation across corners is also described.The thrust on optimizations of design power, energy, project management, and cost presents three distinct works that directly benefit leading-edge SoC design companies. The first work describes a new analytic three-dimensional placement tool using a new objective function that achieves significant wirelength and power reduction relative to two-dimensional implementations. The second work provides two mixed integer-linear programs for optimal multi-project, multi-resource allocation with task precedence and resource co-constraints for IC design management and cost reduction. The…
Subjects/Keywords: Computer science; Machine Learning; Optimization; VLSI CAD
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APA (6th Edition):
Nath, S. (2016). New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/9jn2c085
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Nath, Siddhartha. “New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.” 2016. Thesis, University of California – San Diego. Accessed January 22, 2020.
http://www.escholarship.org/uc/item/9jn2c085.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Nath, Siddhartha. “New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.” 2016. Web. 22 Jan 2020.
Vancouver:
Nath S. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. [Internet] [Thesis]. University of California – San Diego; 2016. [cited 2020 Jan 22].
Available from: http://www.escholarship.org/uc/item/9jn2c085.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Nath S. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. [Thesis]. University of California – San Diego; 2016. Available from: http://www.escholarship.org/uc/item/9jn2c085
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Minnesota
25.
Li, Peng.
FPGA-based hardware implementation of image processing
algorithms for real-time vehicle detection applications.
Degree: MS, Electrical/Computer Engineering, 2012, University of Minnesota
URL: http://purl.umn.edu/140237
► University of Minnesota M.S. thesis. October 2012. Major: Electrical/Computer Engineering. Advisor: Hua Tang. 1 computer file (PDF); viii, 47 pages, appendix A.
It is well…
(more)
▼ University of Minnesota M.S. thesis. October 2012.
Major: Electrical/Computer Engineering. Advisor: Hua Tang. 1
computer file (PDF); viii, 47 pages, appendix A.
It is well known that vehicle tracking processes
are very computationally intensive. Traditionally, vehicle tracking
algorithms have been implemented using software ap- proaches. The
software approaches have a large computational delay, which causes
low frame rate vehicle tracking. However, real-time vehicle
tracking is highly desirable to improve not only tracking accuracy
but also response time, in some ITS (Intelligent Transportation
System) applications such as security monitoring and hazard
warning. For this purpose, this thesis makes an attempt to design a
hardware based system for real-time vehicle detection, which is
typically required in the complete tracking system. The vehicle
detection systems capture pictures using a camera in real-time and
then we apply several image processing algorithms, such as Fixed
Block Size Motion Estima- tion (FBSME), Recongurable Block Size
Motion Estimation (RBSME), Variable Block Size Motion Estimation
(VBSME) and Mixtures of Gaussian, to process these images in
real-time for vehicle detection. We rst propose the
Very-Large-Scale Integration (VLSI) implementation for RB- SME
algorithm, which supports arbitrary block size motion estimation.
Experiment results show that the proposed architecture achieves the
exibility of adjustable block size at the expense of only 5%
hardware overhead compared to the traditional design. We then
propose a low-power VLSI implementation for the VBSME algorithm,
which employs a fast full-search block matching algorithm to reduce
power consumption, while preserving the optimal solutions 1 . The
fast full-search algorithm is based on the com- parison of the
current minimum Sum of Absolute Dierence (SAD) to a conservative
lower bound so that unnecessary SAD calculations can be eliminated.
We rst ex- perimentally decide on the specic conservative lower
bound and then implement the fast full-search algorithm in
Field-Programmable Gate Array (FPGA). To the best of our knowledge,
this is the rst time that a fast full-search block matching
algorithm is explored to reduce power consumption in the context of
VBSME, and designed in hardware. Experiment results show that the
proposed hardware implementation can save power consumption by 45%
compared to conventional VBSME designs based on the non-fast
full-search algorithms. At last, we propose an System-on-a-Chip
(SoC) architecture for an Mixture of Gaus- sian (MoG) based image
segmentation algorithm. The MoG algorithm for video seg- mentation
application is computational intensive. To meet real-time
requirement of high frame rate high resolution video segmentation
tasks, we present a hardware im- plementation of the MoG algorithm.
Moreover, we integrated the hardware IP into an SoC architecture,
so that some key parameters, such as learning rate and thresh- old,
can be congured on-line, which makes the system extremely exible to
adapt to dierent…
Advisors/Committee Members: Hua Tang.
Subjects/Keywords: FPGA; Image processing; Image segmentation; VLSI
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APA (6th Edition):
Li, P. (2012). FPGA-based hardware implementation of image processing
algorithms for real-time vehicle detection applications. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/140237
Chicago Manual of Style (16th Edition):
Li, Peng. “FPGA-based hardware implementation of image processing
algorithms for real-time vehicle detection applications.” 2012. Masters Thesis, University of Minnesota. Accessed January 22, 2020.
http://purl.umn.edu/140237.
MLA Handbook (7th Edition):
Li, Peng. “FPGA-based hardware implementation of image processing
algorithms for real-time vehicle detection applications.” 2012. Web. 22 Jan 2020.
Vancouver:
Li P. FPGA-based hardware implementation of image processing
algorithms for real-time vehicle detection applications. [Internet] [Masters thesis]. University of Minnesota; 2012. [cited 2020 Jan 22].
Available from: http://purl.umn.edu/140237.
Council of Science Editors:
Li P. FPGA-based hardware implementation of image processing
algorithms for real-time vehicle detection applications. [Masters Thesis]. University of Minnesota; 2012. Available from: http://purl.umn.edu/140237
University of Minnesota
26.
Dalal, Hussain Firoz.
Implementation of on-chip thermal sensor using
off-leakage current of a transistor.
Degree: MS, Electrical Engineering, 2010, University of Minnesota
URL: http://purl.umn.edu/59772
University of Minnesota M.S. thesis. January 2010.
Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer
file (PDF); ii, 38 pages. Ill. (some col.)
Abstract summary not available
Advisors/Committee Members: Chris H. Kim.Subjects/Keywords: VLSI; CMOS; Leakage Current; Electrical Engineering
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APA (6th Edition):
Dalal, H. F. (2010). Implementation of on-chip thermal sensor using
off-leakage current of a transistor. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/59772
Chicago Manual of Style (16th Edition):
Dalal, Hussain Firoz. “Implementation of on-chip thermal sensor using
off-leakage current of a transistor.” 2010. Masters Thesis, University of Minnesota. Accessed January 22, 2020.
http://purl.umn.edu/59772.
MLA Handbook (7th Edition):
Dalal, Hussain Firoz. “Implementation of on-chip thermal sensor using
off-leakage current of a transistor.” 2010. Web. 22 Jan 2020.
Vancouver:
Dalal HF. Implementation of on-chip thermal sensor using
off-leakage current of a transistor. [Internet] [Masters thesis]. University of Minnesota; 2010. [cited 2020 Jan 22].
Available from: http://purl.umn.edu/59772.
Council of Science Editors:
Dalal HF. Implementation of on-chip thermal sensor using
off-leakage current of a transistor. [Masters Thesis]. University of Minnesota; 2010. Available from: http://purl.umn.edu/59772
Anna University
27.
Jayanthy S.
Development of algorithms for test generation and
simulation of crosstalk delay faults in vlsi circuits;.
Degree: algorithms for test generation and simulation of
crosstalk delay faults in vlsi circuits, 2014, Anna University
URL: http://shodhganga.inflibnet.ac.in/handle/10603/23842
► Very Large Scale Integration VLSI is the fabrication of millions newlineof components on the same chip and is an integral part of modern electronic newlinesystems…
(more)
▼ Very Large Scale Integration VLSI is the
fabrication of millions newlineof components on the same chip and
is an integral part of modern electronic newlinesystems Due to the
significant advances in VLSI technology new Automatic newlineTest
Pattern Generation ATPG problems are emerging The move towards
newlinedeep submicron technology introduces timing related defects
that change the newlinetiming of the circuit instead of its
function Timing related defects include newlineexternal noise
sources and process variations newlineOf the various noise sources
crosstalk noise will have significant newlineimpact on the
performance of deep submicron systems Crosstalk can induce
newlineboth logic errors and delay faults While many techniques
have been proposed newlineto reduce crosstalk due to limited design
margin and unpredictable process newlinevariations testing for
crosstalk must be performed during manufacturing to newlineenhance
device reliability and yield Hence efficient test generation
newlinemethodologies for crosstalk delay faults have to be
developed newline newline
Reference p.163-172
Advisors/Committee Members: Bhuvaneswari M C.
Subjects/Keywords: crosstalk delay; electrical engineering; vlsi circuits
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Manager
APA (6th Edition):
S, J. (2014). Development of algorithms for test generation and
simulation of crosstalk delay faults in vlsi circuits;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/23842
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
S, Jayanthy. “Development of algorithms for test generation and
simulation of crosstalk delay faults in vlsi circuits;.” 2014. Thesis, Anna University. Accessed January 22, 2020.
http://shodhganga.inflibnet.ac.in/handle/10603/23842.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
S, Jayanthy. “Development of algorithms for test generation and
simulation of crosstalk delay faults in vlsi circuits;.” 2014. Web. 22 Jan 2020.
Vancouver:
S J. Development of algorithms for test generation and
simulation of crosstalk delay faults in vlsi circuits;. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Jan 22].
Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23842.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
S J. Development of algorithms for test generation and
simulation of crosstalk delay faults in vlsi circuits;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23842
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
28.
Dash, Rajballav.
VLSI Implementation of Low Power Reconfigurable MIMO Detector.
Degree: 2009, Texas A&M University
URL: http://hdl.handle.net/1969.1/148444
► Multiple Input Multiple Output (MIMO) systems are a key technology for next generation high speed wireless communication standards like 802.11n, WiMax etc. MIMO enables spatial…
(more)
▼ Multiple Input Multiple Output (MIMO) systems are a key technology for next
generation high speed wireless communication standards like 802.11n, WiMax etc.
MIMO enables spatial multiplexing to increase channel bandwidth which requires the
use of multiple antennas in the receiver and transmitter side. The increase in bandwidth
comes at the cost of high silicon complexity of MIMO detectors which result, due to the
intricate algorithms required for the separation of these spatially multiplexed streams.
Previous implementations of MIMO detector have mainly dealt with the issue of
complexity reduction, latency minimization and throughput enhancement. Although,
these detectors have successfully mapped algorithms to relatively simpler circuits but
still, latency and throughput of these systems need further improvements to meet
standard requirements. Additionally, most of these implementations don?t deal with the
requirements of reconfigurability of the detector to multiple modulation schemes and
different antennae configurations. This necessary requirement provides another
dimension to the implementation of MIMO detector and adds to the implementation
complexity.
This thesis focuses on the efficient
VLSI implementation of the MIMO detector
with an emphasis on performance and re-configurability to different modulation
schemes. MIMO decoding in our detector is based on the fixed sphere decoding
algorithm which has been simplified for an effective
VLSI implementation without
considerably degrading the near optimal bit error rate performance. The regularity of the
architecture makes it suitable for a highly parallel and pipelined implementation. The
decoder has intrinsic traits for dynamic re-configurability to different modulation and
encoding schemes. This detector architecture can be easily tuned for high/low
performance requirements with slight degradation/improvement in Bit Error Rate (BER)
depending on needs of the overlying application. Additionally, various architectural
optimizations like pipelining, parallel processing, hardware scheduling, dynamic voltage
and frequency scaling have been explored to improve the performance, energy
requirements and re-configurability of the design.
Advisors/Committee Members: Choi, Gwan S (advisor), Li, Peng (committee member), Walker, Duncan M (committee member).
Subjects/Keywords: VLSI; MIMO; IEEE 802.11n; Sphere Decoding; DVFS
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APA (6th Edition):
Dash, R. (2009). VLSI Implementation of Low Power Reconfigurable MIMO Detector. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148444
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Dash, Rajballav. “VLSI Implementation of Low Power Reconfigurable MIMO Detector.” 2009. Thesis, Texas A&M University. Accessed January 22, 2020.
http://hdl.handle.net/1969.1/148444.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Dash, Rajballav. “VLSI Implementation of Low Power Reconfigurable MIMO Detector.” 2009. Web. 22 Jan 2020.
Vancouver:
Dash R. VLSI Implementation of Low Power Reconfigurable MIMO Detector. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1969.1/148444.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Dash R. VLSI Implementation of Low Power Reconfigurable MIMO Detector. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/148444
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Oregon State University
29.
Ruggeri, Thomas L.
TIMR : Time Interleaved Multi Rail.
Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University
URL: http://hdl.handle.net/1957/29070
► This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic…
(more)
▼ This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail. We examine the design of TIMR as well as the implementation and considerations. We propose a number of control schemes that range from traditional DVFS to "race to sleep". This thesis also shows simulations of the technique using a existing voltage regulator in order to find the time and energy overhead of implementing the design. We find a 100μs switching time delay and 118μJ energy overhead associated with changing the voltage rail. This work concludes with comparisons to current energy saving techniques.
Advisors/Committee Members: Chiang, Patrick Y. (advisor), Lee, Ben (committee member).
Subjects/Keywords: VLSI; Integrated circuits – Very large scale integration
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APA (6th Edition):
Ruggeri, T. L. (2012). TIMR : Time Interleaved Multi Rail. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29070
Chicago Manual of Style (16th Edition):
Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Masters Thesis, Oregon State University. Accessed January 22, 2020.
http://hdl.handle.net/1957/29070.
MLA Handbook (7th Edition):
Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Web. 22 Jan 2020.
Vancouver:
Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1957/29070.
Council of Science Editors:
Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29070
Michigan Technological University
30.
Chen, Xiaodao.
Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design.
Degree: PhD, Department of Electrical and Computer Engineering, 2012, Michigan Technological University
URL: http://digitalcommons.mtu.edu/etds/709
► To tackle the challenges at circuit level and system level VLSI and embedded system design, this dissertation proposes various novel algorithms to explore the…
(more)
▼ To tackle the challenges at circuit level and system level
VLSI and embedded system design, this dissertation proposes various novel algorithms to explore the efficient solutions. At the circuit level, a new reliability-driven minimum cost Steiner routing and layer assignment scheme is proposed, and the first transceiver insertion algorithmic framework for the optical interconnect is proposed. At the system level, a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems, which optimizes system energy consumption under stochastic fault occurrences, is proposed. The embedded system design is also widely used in the smart home area for improving health, wellbeing and quality of life. The proposed scheduling scheme for multiprocessor embedded systems is hence extended to handle the energy consumption scheduling issues for smart homes. The extended scheme can arrange the household appliances for operation to minimize monetary expense of a customer based on the time-varying pricing model.
Advisors/Committee Members: Shiyan Hu.
Subjects/Keywords: CAD; Embedded System; VLSI Design; Computer Engineering
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APA ·
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Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Chen, X. (2012). Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design. (Doctoral Dissertation). Michigan Technological University. Retrieved from http://digitalcommons.mtu.edu/etds/709
Chicago Manual of Style (16th Edition):
Chen, Xiaodao. “Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design.” 2012. Doctoral Dissertation, Michigan Technological University. Accessed January 22, 2020.
http://digitalcommons.mtu.edu/etds/709.
MLA Handbook (7th Edition):
Chen, Xiaodao. “Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design.” 2012. Web. 22 Jan 2020.
Vancouver:
Chen X. Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design. [Internet] [Doctoral dissertation]. Michigan Technological University; 2012. [cited 2020 Jan 22].
Available from: http://digitalcommons.mtu.edu/etds/709.
Council of Science Editors:
Chen X. Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design. [Doctoral Dissertation]. Michigan Technological University; 2012. Available from: http://digitalcommons.mtu.edu/etds/709
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Open Access Theses and Dissertations