subject:(VLSI)

1. Nakabayashi, Keiji. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップニタイスルアタラシイネツカイセキシュホウ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

URL: http://hdl.handle.net/10061/6020

Subjects/Keywords: VLSI

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APA (6^th Edition):

Nakabayashi, K. (n.d.). A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップニタイスルアタラシイネツカイセキシュホウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/6020

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Nakabayashi, Keiji. “A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップニタイスルアタラシイネツカイセキシュホウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 11, 2021. http://hdl.handle.net/10061/6020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Nakabayashi, Keiji. “A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップニタイスルアタラシイネツカイセキシュホウ.” Web. 11 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Nakabayashi K. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップニタイスルアタラシイネツカイセキシュホウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10061/6020.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Nakabayashi K. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップニタイスルアタラシイネツカイセキシュホウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/6020

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Georgia Tech

2. Kamdar, Keval Prakash. Performance estimation of large area nanowires.

Degree: MS, Electrical and Computer Engineering, 2019, Georgia Tech

URL: http://hdl.handle.net/1853/61309

► The focus of the thesis is to extensively model high-performance nanowires, develop Verilog A models of the devices and then simulate them using SPICE to… (more)

Subjects/Keywords: Nanowires; vlsi

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APA (6^th Edition):

Kamdar, K. P. (2019). Performance estimation of large area nanowires. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61309

Chicago Manual of Style (16^th Edition):

Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Masters Thesis, Georgia Tech. Accessed April 11, 2021. http://hdl.handle.net/1853/61309.

MLA Handbook (7^th Edition):

Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Web. 11 Apr 2021.

Vancouver:

Kamdar KP. Performance estimation of large area nanowires. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1853/61309.

Council of Science Editors:

Kamdar KP. Performance estimation of large area nanowires. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61309

Cornell University

3. Longfield, Stephen. Constructive Verification Of Quasi Delay-Insensitive Circuits.

Degree: PhD, Electrical Engineering, 2015, Cornell University

URL: http://hdl.handle.net/1813/40716

► Self-timed circuits have recently regained active interest as their abilities in avoiding timing and voltage margins, disconnecting pipeline depth from occupancy, and achieving average-case performance… (more)

Subjects/Keywords: VLSI; Verification; Asynchronous

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APA (6^th Edition):

Longfield, S. (2015). Constructive Verification Of Quasi Delay-Insensitive Circuits. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/40716

Chicago Manual of Style (16^th Edition):

Longfield, Stephen. “Constructive Verification Of Quasi Delay-Insensitive Circuits.” 2015. Doctoral Dissertation, Cornell University. Accessed April 11, 2021. http://hdl.handle.net/1813/40716.

MLA Handbook (7^th Edition):

Longfield, Stephen. “Constructive Verification Of Quasi Delay-Insensitive Circuits.” 2015. Web. 11 Apr 2021.

Vancouver:

Longfield S. Constructive Verification Of Quasi Delay-Insensitive Circuits. [Internet] [Doctoral dissertation]. Cornell University; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1813/40716.

Council of Science Editors:

Longfield S. Constructive Verification Of Quasi Delay-Insensitive Circuits. [Doctoral Dissertation]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/40716

University of Oulu

4. Shahabuddin, S. (Shahriar). MIMO detection and precoding architectures.

Degree: 2019, University of Oulu

URL: http://urn.fi/urn:isbn:9789526222837

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Abstract Multiple-input multiple-output (MIMO) techniques have been adopted since the third generation (3G) wireless communication standard to increase the spectral efficiency, data rate and reliability.… (more)

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Abstract Multiple-input multiple-output (MIMO) techniques have been adopted since the third generation (3G) wireless communication standard to increase the spectral efficiency, data rate and reliability. The blessings of MIMO technologies for the baseband transceiver comes with the price of added complexity. Therefore, research on VLSI architectures for MIMO signal processing has generated a lot of interest over the past two decades. The advent of massive MIMO as a key technology for the fifth generation (5G) era also increased the interest in VLSI architectures related to MIMO communication research. In this thesis, we explored different VLSI architectures for MIMO detection and precoding algorithms. The detection and precoding are the most complex parts of a MIMO baseband transceiver. We focused on algorithm and architecture optimization and presented several VLSI architectures for MIMO detection and precoding. The thesis proposed an application specific instruction-set processor (ASIP) for a multimode small-scale MIMO detector. In a single design the detector supports minimum mean-square error (MMSE), selective spanning with fast enumeration (SSFE) and list sphere detection (LSD). In addition, a multiprocessor architecture is proposed in this thesis for a lattice reduction (LR) algorithm. A modified Lenstra-Lenstra-Lovasz (LLL) algorithm is proposed for LR to reduce the complexity of the original LLL algorithm. We also propose a massive MIMO detection algorithm based on alternating direction method of multipliers (ADMM). The algorithm is referred to as ADMM based infinity norm (ADMIN) constrained equalization. The ADMIN detection algorithm is implemented as an application-specific integrated circuit (ASIC) and for field programmable gate array (FPGA). A multimode precoder ASIP is also proposed in this thesis. In a single design, the ASIP supports norm-based scheduling, QR-decomposition, MMSE precoding and dirty paper coding (DPC) based precoding.

Tiivistelmä Moni-tulo moni-lähtö (MIMO) -tekniikoita on sopeutettu kolmannen sukupolven (3G) langattomasta viestintästandardista alkaen spektritehokkuuden, tiedonsiirtonopeuden ja luotettavuuden parantamiseksi. MIMO-teknologioilla on useita hyviä puolia suhteessa peruskaistan vastaanottimeen, mutta samalla monimutkaisuus on lisääntynyt. VLSI-arkkitehtuurien tutkimus MIMO-signaalinkäsittelyssä on sen vuoksi herättänyt paljon kiinnostusta viimeisen kahden vuosikymmenen aikana. Myös MIMO:n saavuttama asema viidennen sukupolven (5G) viestintästandardin pääteknologiana on lisännyt kiinnostusta VLSI-arkkitehtuureihin MIMO-viestinnän tutkimuksessa. Tässä tutkielmassa on tutkittu erilaisia VLSI-arkkitehtuureja MIMO-signaalien tunnistus- ja esikoodausalgoritmeissa. Signaalien tunnistus ja esikoodaus ovat peruskaistaa käyttävän MIMO-vastaanottimen monimutkaisimmat osa-alueet. Tutkielmassa on keskitytty algoritmien ja arkkitehtuurien optimointiin ja esitetty useita VLSI-arkkitehtuureja MIMO-signaalien tunnistusta ja esikoodausta varten. Tutkielmassa on ehdotettu…

Advisors/Committee Members: Juntti, M. (Markku), Studer, C. (Christoph), Silvén, O. (Olli).

Subjects/Keywords: ASIP; MIMO; VLSI

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APA (6^th Edition):

Shahabuddin, S. (. (2019). MIMO detection and precoding architectures. (Doctoral Dissertation). University of Oulu. Retrieved from http://urn.fi/urn:isbn:9789526222837

Chicago Manual of Style (16^th Edition):

Shahabuddin, S (Shahriar). “MIMO detection and precoding architectures.” 2019. Doctoral Dissertation, University of Oulu. Accessed April 11, 2021. http://urn.fi/urn:isbn:9789526222837.

MLA Handbook (7^th Edition):

Shahabuddin, S (Shahriar). “MIMO detection and precoding architectures.” 2019. Web. 11 Apr 2021.

Vancouver:

Shahabuddin S(. MIMO detection and precoding architectures. [Internet] [Doctoral dissertation]. University of Oulu; 2019. [cited 2021 Apr 11]. Available from: http://urn.fi/urn:isbn:9789526222837.

Council of Science Editors:

Shahabuddin S(. MIMO detection and precoding architectures. [Doctoral Dissertation]. University of Oulu; 2019. Available from: http://urn.fi/urn:isbn:9789526222837

5. Jain, Shruti. Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;.

Degree: 2013, Jaypee University of Information Technology, Solan

URL: http://shodhganga.inflibnet.ac.in/handle/10603/11161

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Biological systems can create complex structures from very simple systems. To do this, there must be a method to differentiate different regions where identical systems… (more)

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Biological systems can create complex structures from very simple systems. To do this, there must be a method to differentiate different regions where identical systems create different structures, such as the abdomen and the head of a fruit fly. This thesis highlights an emerging field known as Synthetic Biology that envisions integrating designed circuits into living organisms in order to instruct them to make logical decisions based on the prevailing intracellular and extra cellular conditions and produce a reliable behavior. Synthetic Biology attempts to construct and assemble such modules gradually, plug the modules together and modify them, in order to generate a desired behavior. Using biological circuit, we can produce a new concentration gradient that has twice the frequency. If 1 is represented by a concentration of the chemical within the threshold, and a 0 is represented by a concentration outside the threshold, then we can represent any two digit binary number. Thus, we can differentiate separate regions at certain distances away from a point source. Logic gates are the basic building blocks in electronic circuits that perform logical operations. These have input and output signals in the form of 0 s and 1 s; 0 signifies the absence of signal while 1 signifies its presence. newlineThe study focuses on system implementation of a signals and responses triggered by Tumor Necrosis Factor- and#945; (TNF-and#945;), Epidermal Growth Factor (EGF) and Insulin factors leading to cell survival/ apoptosis. The computational techniques that have been used are: VHDL (Xilinx Tool), CMOS and BiCMOS (SPICE Tool), and Fuzzy Logic (MATLAB Tool), Non Linear Model (Artificial Neural Networks) and Deterministic Model taking three input signals. In future we are also trying to develop bio-simulator that can be used for prediction of status of the cell leading to cell survival/ apoptosis giving chemotherapy and radiotherapy treatment. newline

Advisors/Committee Members: Naik, Pradeep Kumar, Bhooshan, Sunil Vidya.

Subjects/Keywords: CMOS; Fuzzy Logic; VLSI

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APA (6^th Edition):

Jain, S. (2013). Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;. (Thesis). Jaypee University of Information Technology, Solan. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/11161

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Jain, Shruti. “Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;.” 2013. Thesis, Jaypee University of Information Technology, Solan. Accessed April 11, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/11161.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Jain, Shruti. “Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;.” 2013. Web. 11 Apr 2021.

Vancouver:

Jain S. Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;. [Internet] [Thesis]. Jaypee University of Information Technology, Solan; 2013. [cited 2021 Apr 11]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11161.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jain S. Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;. [Thesis]. Jaypee University of Information Technology, Solan; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11161

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Texas A&M University

6. Wang, Qian. Architectures and Design of VLSI Machine Learning Systems.

Degree: PhD, Computer Engineering, 2016, Texas A&M University

URL: http://hdl.handle.net/1969.1/158093

► Quintillions of bytes of data are generated every day in this era of big data. Machine learning techniques are utilized to perform predictive analysis on… (more)

▼ Quintillions of bytes of data are generated every day in this era of big data. Machine learning techniques are utilized to perform predictive analysis on these data, to reveal hidden relationships and dependencies and perform predictions of outcomes and behaviors. The obtained predictive models are used to interpret the existing data and predict new data information. Nowadays, most machine learning algorithms are realized by software programs running on general-purpose processors, which usually takes a huge amount of CPU time and introduces unbelievably high energy consumption. In comparison, a dedicated hardware design is usually much more efficient than software programs running on general-purpose processors in terms of runtime and energy consumption. Therefore, the objective of this dissertation is to develop efficient hardware architectures for mainstream machine learning algorithms, to provide a promising solution to addressing the runtime and energy bottlenecks of machine learning applications. However, it is a really challenging task to map complex machine learning algorithms to efficient hardware architectures. In fact, many important design decisions need to be made during the hardware development for efficient tradeoffs. In this dissertation, a parallel digital VLSI architecture for combined SVM training and classification is proposed. For the first time, cascade SVM, a powerful training algorithm, is leveraged to significantly improve the scalability of hardware-based SVM training and develop an efficient parallel VLSI architecture. The parallel SVM processors provide a significant training time speedup and energy reduction compared with the software SVM algorithm running on a general-purpose CPU. Furthermore, a liquid state machine based neuromorphic learning processor with integrated training and recognition is proposed. A novel theoretical measure of computational power is proposed to facilitate fast design space exploration of the recurrent reservoir. Three low-power techniques are proposed to improve the energy efficiency. Meanwhile, a 2-layer spiking neural network with global inhibition is realized on Silicon. In addition, we also present architectural design exploration of a brain-inspired digital neuromorphic processor architecture with memristive synaptic crossbar array, and highlight several synaptic memory access styles. Various analog-to-digital converter schemes have been investigated to provide new insights into the tradeoff between the hardware cost and energy consumption. Advisors/Committee Members: Li, Peng (advisor), Choi, Gwan (advisor), Palermo, Sam (committee member), Choe, Yoonsuck (committee member).

Subjects/Keywords: Machine learning; VLSI architecture

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APA (6^th Edition):

Wang, Q. (2016). Architectures and Design of VLSI Machine Learning Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/158093

Chicago Manual of Style (16^th Edition):

Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Doctoral Dissertation, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/158093.

MLA Handbook (7^th Edition):

Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Web. 11 Apr 2021.

Vancouver:

Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/158093.

Council of Science Editors:

Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/158093

Texas A&M University

7. Xu, Jingwei. Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes.

Degree: PhD, Computer Engineering, 2016, Texas A&M University

URL: http://hdl.handle.net/1969.1/187409

► With its low error-floor performance, polar codes attract significant attention as the potential standard error correction code (ECC) for future communication and data storage. However,… (more)

▼ With its low error-floor performance, polar codes attract significant attention as the potential standard error correction code (ECC) for future communication and data storage. However, the VLSI implementation complexity of polar codes decoders is largely influenced by its nature of in-series decoding. This dissertation is dedicated to presenting optimal decoder architectures for polar codes. This dissertation addresses several structural properties of polar codes and key properties of decoding algorithms that are not dealt with in the prior researches. The underlying concept of the proposed architectures is a paradigm that simplifies and schedules the computations such that hardware is simplified, latency is minimized and bandwidth is maximized. In pursuit of the above, throughput centric successive cancellation (TCSC) and overlapping path list successive cancellation (OPLSC) VLSI architectures and express journey BP (XJBP) decoders for the polar codes are presented. An arbitrary polar code can be decomposed by a set of shorter polar codes with special characteristics, those shorter polar codes are referred to as constituent polar codes. By exploiting the homogeneousness between decoding processes of different constituent polar codes, TCSC reduces the decoding latency of the SC decoder by 60% for codes with length n = 1024. The error correction performance of SC decoding is inferior to that of list successive cancellation decoding. The LSC decoding algorithm delivers the most reliable decoding results; however, it consumes most hardware resources and decoding cycles. Instead of using multiple instances of decoding cores in the LSC decoders, a single SC decoder is used in the OPLSC architecture. The computations of each path in the LSC are arranged to occupy the decoder hardware stages serially in a streamlined fashion. This yields a significant reduction of hardware complexity. The OPLSC decoder has achieved about 1.4 times hardware efficiency improvement compared with traditional LSC decoders. The hardware efficient VLSI architectures for TCSC and OPLSC polar codes decoders are also introduced. Decoders based on SC or LSC algorithms suffer from high latency and limited throughput due to their serial decoding natures. An alternative approach to decode the polar codes is belief propagation (BP) based algorithm. In BP algorithm, a graph is set up to guide the beliefs propagated and refined, which is usually referred to as factor graph. BP decoding algorithm allows decoding in parallel to achieve much higher throughput. XJBP decoder facilitates belief propagation by utilizing the specific constituent codes that exist in the conventional factor graph, which results in an express journey (XJ) decoder. Compared with the conventional BP decoding algorithm for polar codes, the proposed decoder reduces the computational complexity by about 40.6%. This enables an energy-efficient hardware implementation. To further explore the hardware consumption of the proposed XJBP decoder, the computations scheduling is modeled and… Advisors/Committee Members: Choi, Gwan (advisor), Kim, Eun (committee member), Li, Peng (committee member), Krishna, Narayanan (committee member).

Subjects/Keywords: error correction coding; VLSI

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APA (6^th Edition):

Xu, J. (2016). Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/187409

Chicago Manual of Style (16^th Edition):

Xu, Jingwei. “Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes.” 2016. Doctoral Dissertation, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/187409.

MLA Handbook (7^th Edition):

Xu, Jingwei. “Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes.” 2016. Web. 11 Apr 2021.

Vancouver:

Xu J. Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/187409.

Council of Science Editors:

Xu J. Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/187409

Texas A&M University

8. Mandal, Ayan. Efficient Design and Clocking for a Network-on-Chip.

Degree: PhD, Computer Engineering, 2013, Texas A&M University

URL: http://hdl.handle.net/1969.1/149325

► As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC)… (more)

▼ As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC) paradigm has emerged as an efficient and scalable infrastructure to handle the communication needs for such multi-core systems. In most existing NoCs, design decisions are made assuming that the NoC operates at the same or lower clock speed as the cores, which slows down the communication system. A major challenge in designing a high speed NoC is the difficulty of distributing a high speed, low power clock across the chip. In this dissertation, we first propose several techniques to address the issue of distributing a high-speed, low power, low jitter clock across the IC. We primarily focus our attention on resonant standing wave oscillators (SWOs), which have recently emerged as a promising technique for high-speed, low power clock generation. In addition, we also present a dynamic programming based approach to synthesize a low jitter, low power buffered H-tree for clock distribution. In the second part of this dissertation, we use these efficient clock distribution schemes to present a novel fast NoC design that relies on source synchronous data transfer over a ring. In our source-synchronous design, the clock and data NoC are routed in parallel yielding a fast, robust design. Architectural simulations on synthetic and real traffic show that our source-synchronous NoC designs can provide significantly lower latency while achieving the same or better bandwidth compared to a state of the art mesh, while consuming lower area. The fact that the our ring-based NoC runs significantly faster than the mesh contributes to these improvements. Moreover, since our proposed NoC designs are fully synchronous, they are very amenable to testing as well. In the last part of this dissertation, we explore an alternate scheme of achieving high-speed on-chip data transfer using sinusoidal signals of different frequencies. The key advantage of our method is the ability to superimpose such sinusoids and thereby effectively send multiple logic values along the same wire in a clock cycle. Experimental results show that for the same throughput as that of a traditional scheme, we require significantly fewer wires. Advisors/Committee Members: Khatri, Sunil P (advisor), Mahapatra, Rabi N (advisor), Walker, Duncan M (committee member), Bettati, Riccardo (committee member), Chiou, Derek (committee member).

Subjects/Keywords: Network-on-Chip; Clock; VLSI

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APA (6^th Edition):

Mandal, A. (2013). Efficient Design and Clocking for a Network-on-Chip. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149325

Chicago Manual of Style (16^th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Doctoral Dissertation, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/149325.

MLA Handbook (7^th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Web. 11 Apr 2021.

Vancouver:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Internet] [Doctoral dissertation]. Texas A&M University; 2013. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/149325.

Council of Science Editors:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Doctoral Dissertation]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149325

University of Toronto

9. Yu, Jingshu. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.

Degree: 2014, University of Toronto

URL: http://hdl.handle.net/1807/67870

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In this thesis, an integrated H-bridge is presented for continuously optimizing the power conversion efficiency over a wide range of output current. The proposed IC… (more)

Subjects/Keywords: Power Electronics; VLSI; 0544

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APA (6^th Edition):

Yu, J. (2014). A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/67870

Chicago Manual of Style (16^th Edition):

Yu, Jingshu. “A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.” 2014. Masters Thesis, University of Toronto. Accessed April 11, 2021. http://hdl.handle.net/1807/67870.

MLA Handbook (7^th Edition):

Yu, Jingshu. “A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.” 2014. Web. 11 Apr 2021.

Vancouver:

Yu J. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1807/67870.

Council of Science Editors:

Yu J. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/67870

University of Southern California

10. Kashfi, Fatemeh. Thermal analysis and multiobjective optimization for three dimensional integrated circuits.

Degree: PhD, Electrical Engineering (VLSI Design), 2013, University of Southern California

URL: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7439

► Three Dimensional Integrated Circuit (3DIC) technology has been introduced to address the interconnect issues in nanometer circuit design that limit performance improvement and power reduction.… (more)

▼ Three Dimensional Integrated Circuit (3DIC) technology has been introduced to address the interconnect issues in nanometer circuit design that limit performance improvement and power reduction. However, stacking active layers of silicon leads to increased power density and overall higher temperatures in a 3D chip implementation for many designs. New thermal map modeling, and temperature measurement, mitigation and management techniques should be introduced for this technology. In this dissertation we study the thermal correlation between the stacked layers in 3DICs. We then propose a fast and efficient 3D thermal map modeling based on scaled hotspot areas, depending on the distance of a stacked layer from the heatsink and also thermal effects of the layers on each other. The modeling is 53× faster than the existing method of temperature compact modeling. The efficiency of the proposed modeling is demonstrated with its use in a thermal sensor distribution algorithm. We also show that the thermal sensor distribution algorithm should be solved as a 3D problem. In this way for the same sensor reading error the total number of needed sensors is reduced by 44%. We furthermore propose a new 3D design for thermal sensor circuits to be shared between layers in a 3DIC. Using 3D thermal sensors that are shared between adjacent layers can reduce the total number of needed sensors by half. ❧ We also study different methods of multiobjective optimization to find the optimum operating point of a VLSI circuit. We provide wide mathematical analyses of different multiobjective optimization techniques for this purpose. We also study the difference of convex and non-convex modeling of the objectives in the multiobjective optimization algorithms. ❧ We apply our multiobjective optimization methods to optimize three conflicting objectives of cost, performance and thermal reliability to find an optimum building block placement in 3DICs. The variables for the optimization are the number of layers, area of the 3DIC, position of the building blocks, number of TSVs and total wirelength. We used our proposed fast 3D thermal map modeling to eliminate the thermal analysis bottleneck in multiobjective optimization iterations. In comparison with a previous state-of-the-art multiobjective optimization method which employs Simulated Annealing, a weighted sum method of scalarization and compact modeling for thermal analysis, our method reduces the peak temperature of a representative 3DIC by 4.3% and total wire length by 5.7% while it is more than 17× faster in optimization runtime. The execution runtime of the proposed algorithm also scales linearly with problem size in contrast with the existing heuristic method of Simulated Annealing, which scales poorly with problem size. Advisors/Committee Members: Draper, Jeffrey (Committee Chair), Gupta, Sandeep K. (Committee Member), Nakano, Aiichiro (Committee Member).

Subjects/Keywords: 3DIC; optimization; temperature; electronics; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kashfi, F. (2013). Thermal analysis and multiobjective optimization for three dimensional integrated circuits. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7439

Chicago Manual of Style (16^th Edition):

Kashfi, Fatemeh. “Thermal analysis and multiobjective optimization for three dimensional integrated circuits.” 2013. Doctoral Dissertation, University of Southern California. Accessed April 11, 2021. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7439.

MLA Handbook (7^th Edition):

Kashfi, Fatemeh. “Thermal analysis and multiobjective optimization for three dimensional integrated circuits.” 2013. Web. 11 Apr 2021.

Vancouver:

Kashfi F. Thermal analysis and multiobjective optimization for three dimensional integrated circuits. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2021 Apr 11]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7439.

Council of Science Editors:

Kashfi F. Thermal analysis and multiobjective optimization for three dimensional integrated circuits. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7439

11. Kananen, Asko. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.

Degree: 2007, Helsinki University of Technology

URL: http://lib.tkk.fi/Diss/2007/isbn9789512286232/

►

This thesis deals with silicon implementations of an all-transistor analogue parallel processor that emulates the functionality of a resistive network. The problems related to VLSI -implementations… (more)

▼

This thesis deals with silicon implementations of an all-transistor analogue parallel processor that emulates the functionality of a resistive network. The problems related to VLSI -implementations of parallel processors are the main concern of this thesis. These problems are first discussed and then to overcome these problems, a new system design is introduced, namely Reduced Cell-row System (RCS). The work started from a resistive network -type spatial filter that was part of a video image compression algorithm. The functionality of this algorithm, as well as the filter, was described in Cellular Neural/Nonlinear Network (CNN) notations and they will be used throughout this thesis in describing the filters and processing operations. In addition to the resistive network array processor, a gradient calculation block was included on the chips to fulfil the original algorithm requirements. Two different array processors were manufactured and measured. The processors had different objectives for their implementation: in the first implementation, the objective was to test the developed Reduced Cell-row System, while in the second implementation the goal was to obtain information on the large-scale implementation of such an array. During the research, a method to include some level of programmability in this type of filters was also developed. For the possible future implementation of such a system, system-level simulations were performed to locate the critical parts that have the most effect on the accuracy of the network.

Tämä työ käsittelee vastusverkkojen toiminnallisuuden toteuttamista analogisena rinnakkaisprosessoritoteutuksena VLSI-piirillä käyttäen ainoastaan MOS-transistoreja. Työssä on ensin käsitelty rinnakkaisprosessorien toteutukseen liittyviä ongelmia, minkä jälkeen esitellään uusi toteutusmenetelmä ongelmien ratkaisuksi. Menetelmää kutsutaan nimellä "Reduced Cell-row System" (RCS). Työn lähtökohta oli vastusverkko-tyyppinen spatiaalisuodatin, joka oli esitetty osana videopakkausalgoritmia. Algoritmin toiminnallisuus, kuten myös suodattimen, oli kuvattu alkuperäisessä algoritmissa epälineaaristen soluverkkojen "Cellular Neural/Nonlinear Network" (CNN) merkintöjä käyttäen ja näitä merkintöjä tullaan käyttämään koko kirjan ajan kuvattaessa suodattimien toiminnallisuutta. Vastusverkkototeutuksen lisäksi myös gradientinlaskentalohko on lisätty piireihin alkuperäisen algoritmin toteuttamiseksi. Kaksi tällaista rinnakkaisprosessoriverkkoa suunniteltiin, valmistutettiin ja mitattiin. Näiden kahden toteutuksen tavoitteet olivat erilaiset: ensimmäinen toteutettiin, jotta voitaisiin todentaa kehitetyn verkon rivien lukumäärää vähentävän menetelmän (RCS) toimivuus, kun taas toisen toteutuksen tavoitteena oli tutkia laajamittaisen toteutuksen ongelmia. Työn aikana kehitettiin myös menetelmä, miten prosessoriverkkoon voidaan lisätä säädettävyyttä ja tällaisen prosessoriverkon toteutukselle suoritettiin simuloinnit, jotta voitaisiin selvittää toteuksen kannalta kriittiset kohdat.

TKK dissertations, ISSN…

Advisors/Committee Members: Helsinki University of Technology, Department of Electrical and Communications Engineering, Electronic Circuit Design Laboratory.

Subjects/Keywords: analogue parallel processor; VLSI; resistive network; analoginen rinnakkaisprosessori; VLSI; vastusverkko

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kananen, A. (2007). A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. (Thesis). Helsinki University of Technology. Retrieved from http://lib.tkk.fi/Diss/2007/isbn9789512286232/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kananen, Asko. “A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.” 2007. Thesis, Helsinki University of Technology. Accessed April 11, 2021. http://lib.tkk.fi/Diss/2007/isbn9789512286232/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kananen, Asko. “A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.” 2007. Web. 11 Apr 2021.

Vancouver:

Kananen A. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. [Internet] [Thesis]. Helsinki University of Technology; 2007. [cited 2021 Apr 11]. Available from: http://lib.tkk.fi/Diss/2007/isbn9789512286232/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kananen A. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. [Thesis]. Helsinki University of Technology; 2007. Available from: http://lib.tkk.fi/Diss/2007/isbn9789512286232/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Iowa State University

12. Zhang, Yanheng. Handling the complexity of routing problem in modern VLSI design.

Degree: 2011, Iowa State University

URL: https://lib.dr.iastate.edu/etd/11896

► In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pins and ports of circuit gates and blocks. Traditionally, VLSI… (more)

▼ In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pins and ports of circuit gates and blocks. Traditionally, VLSI routing is an important design step in the sense that the quality of routing solution has great impact on various design metrics such as circuit timing, power consumption, chip reliability and manufacturability etc. As the advancing VLSI design enters the nanometer era, the routing success (routability issue) has been arising as one of the most critical problems in back-end design. In one aspect, the degree of design complexity is increasing dramatically as more and more modules are integrated into the chip. Much higher chip density leads to higher routing demands and potentially more risks in routing failure. In another aspect, with decreasing design feature size, there are more complex design rules imposed to ensure manufacturability. These design rules are hard to satisfy and they usually create more barriers for achieving routing closure (i.e., generate DRC free routing solution) and thus affect chip time to market (TTM) plan. In general, the behavior and performance of routing are affected by three consecutive phases: placement phase, global routing phase and detailed routing phase in a typical VLSI physical design flow. Traditional CAD tools handle each of the three phases independently and the global picture of the routability issue is neglected. Different from conventional approaches which propose tools and algorithms for one particular design phase, this thesis investigates the routability issue from all three phases and proposes a series of systematic solutions to build a more generic flow and improve quality of results (QoR). For the placement phase, we will introduce a mixed-sized placement refinement tool for alleviating congestion after placement. The tool shifts and relocates modules based on a global routing estimation. For the global routing phase, a very fast and effective global router is developed. Its performance surpasses many peer works as verified by ISPD 2008 global routing contest results. In the detailed routing phase, a tool is proposed to perform detailed routing using regular routing patterns based on a correct-by-construction methodology to improve routability as well as satisfy most design rules. Finally, the tool which integrates global routing and detailed routing is developed to remedy the inconsistency between global routing and detailed routing. To verify the algorithms we proposed, three sets of testcases derived from ISPD98 and ISPD05/06 placement benchmark suites are proposed. The results indicate that our proposed methods construct an integrated and systematic flow for routability improvement which is better than conventional methods.

Subjects/Keywords: Physical Design; Routability; VLSI CAD; VLSI Routing; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhang, Y. (2011). Handling the complexity of routing problem in modern VLSI design. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/11896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zhang, Yanheng. “Handling the complexity of routing problem in modern VLSI design.” 2011. Thesis, Iowa State University. Accessed April 11, 2021. https://lib.dr.iastate.edu/etd/11896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zhang, Yanheng. “Handling the complexity of routing problem in modern VLSI design.” 2011. Web. 11 Apr 2021.

Vancouver:

Zhang Y. Handling the complexity of routing problem in modern VLSI design. [Internet] [Thesis]. Iowa State University; 2011. [cited 2021 Apr 11]. Available from: https://lib.dr.iastate.edu/etd/11896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang Y. Handling the complexity of routing problem in modern VLSI design. [Thesis]. Iowa State University; 2011. Available from: https://lib.dr.iastate.edu/etd/11896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Reimann, Tiago Jose. Roteamento global de circuitos VLSI.

Degree: 2013, Brazil

URL: http://hdl.handle.net/10183/71269

►

Este trabalho apresenta a implementação de um roteador global de circuitos integrados capaz de tratar os problemas de roteamento atuais, utilizando como referência para avaliação… (more)

▼

Este trabalho apresenta a implementação de um roteador global de circuitos integrados capaz de tratar os problemas de roteamento atuais, utilizando como referência para avaliação os circuitos de benchmark publicados durante as competições de roteamento global realizadas no ACM International Symposium on Physical Design 2007 e 2008. O roteador global desenvolvido utiliza como ferramenta principal a técnica de ripup and reroute associada às técnicas de roteamento monotônico e maze routing, ambas com grande histórico de uso nas ferramentas acadêmicas descritas também neste trabalho. O desenvolvimento da ferramenta também possui características diferenciadas e únicas, com um novo método de ordenamento das redes durante a fase de rip-up and reroute. Para a geração dos resultados foram definidas duas versões diferentes da ferramenta, sendo estas duas versões analisadas com duas diferentes técnicas de construção das árvores de roteamento, gerando no total quatro configurações da ferramenta. Como decisão de projeto, a versão principal utilizada no desenvolvimento e discussão dos resultados é a versão que prioriza a qualidade do roteamento, utilizando MSTs para construção das árvores de roteamento. Os resultados mostram que o roteador global desenvolvido é capaz de gerar resultados com boa qualidade mesmo sem fazer uso de técnicas de identificação de áreas de congestionamento, sem otimizações pós-roteamento e sem nenhuma forma de ajuste (tuning) para os diferentes circuitos de benchmark, apesar de ainda ter tempo de execução acima dos apresentados por outras ferramentas acadêmicas. O foco durante o processo de desenvolvimento e implementação da ferramenta foram os circuitos mais recentes, entretanto a ferramenta obteve ótimos resultados também para os circuitos publicados no ISPD 1998, gerando soluções com qualidade similar ou melhor que as reportadas na literatura. A diferença dos resultados deste trabalho em relação aos melhores resultados dos roteadores globais com código disponível, para circuitos 3D lançados no ISPD 2008 é de, em média, 1,78%1 na métrica de comprimento de fio sem considerar o custo das vias e de 15,56% considerando o custo da via como uma unidade de comprimento de fio (ISPD 2008), para a versão voltada a qualidade de roteamento. Já para a versão da ferramenta que busca a convergência o mais rápido possível a diferença foi de 3,39% e 16,32%, respectivamente. As maiores diferenças são encontradas nos circuitos mais difíceis de gerar uma solução sem violações. Isso mostra como as técnicas de identificação de região podem contribuir tanto para uma convergência mais rápida quanto para evitar que fios passem por rotas desnecessárias durante a fase de negociação. Na métrica que avalia as vias como custo de uma unidade de comprimento, os resultados obtidos apresentam em média 18,67% maior comprimento de fio que os melhores resultados da literatura, sendo que dois circuitos com solução sem violações2 apresentam resultado com violações utilizando a ferramenta desenvolvida neste trabalho.

This work describes…

Advisors/Committee Members: Reis, Ricardo Augusto da Luz.

Subjects/Keywords: Microeletrônica; Vlsi; Roteamento : Circuitos integrados; Global routing; Physical synthesis; CAD; VLSI

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❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Reimann, T. J. (2013). Roteamento global de circuitos VLSI. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/71269

Chicago Manual of Style (16^th Edition):

Reimann, Tiago Jose. “Roteamento global de circuitos VLSI.” 2013. Masters Thesis, Brazil. Accessed April 11, 2021. http://hdl.handle.net/10183/71269.

MLA Handbook (7^th Edition):

Reimann, Tiago Jose. “Roteamento global de circuitos VLSI.” 2013. Web. 11 Apr 2021.

Vancouver:

Reimann TJ. Roteamento global de circuitos VLSI. [Internet] [Masters thesis]. Brazil; 2013. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10183/71269.

Council of Science Editors:

Reimann TJ. Roteamento global de circuitos VLSI. [Masters Thesis]. Brazil; 2013. Available from: http://hdl.handle.net/10183/71269

14. Tumelero, Diego. Exploração de paralelismo no roteamento global de circuitos VLSI.

Degree: 2015, Brazil

URL: http://hdl.handle.net/10183/119081

►

Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos… (more)

▼

Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos integrados inclui em um de seus passos o roteamento, que consiste em criar fios que interconectam as células do circuito. Devido à complexidade, o roteamento é dividido em global e detalhado. O roteamento global de circuitos VLSI é uma das tarefas mais complexas do fluxo de síntese física, sendo classificado como um problema NP-completo. Neste trabalho, além de realizar um levantamento de trabalhos que utilizam as principais técnicas de paralelismo com o objetivo de acelerar o processamento do roteamento global, foram realizadas análises nos arquivos de benchmark do ISPD 2007/08. Com base nestas análises foi proposto um método que agrupa as redes para então verificar a existência de dependência de dados em cada grupo. Esta verificação de dependência de dados, que chamamos neste trabalho de colisor, tem por objetivo, criar fluxos de redes independentes umas das outras para o processamento em paralelo, ou seja, ajudar a implementação do roteamento independente de redes. Os resultados demonstram que esta separação em grupos, aliada com a comparação concorrente dos grupos, podem reduzir em 67x o tempo de execução do colisor de redes se comparada com a versão sequencial e sem a utilização de grupos. Também foi obtido um ganho de 10x ao comparar a versão com agrupamentos sequencial com a versão paralela.

With the increasing of the functionality of integrated circuits, there is a consequent increase in the complexity of the design. The IC design flow includes the routing in one of its steps, which is to create wires that interconnect the circuit cells. Because of the complexity, routing is divided into global and detailed. The global routing of VLSI circuits is one of the most complex tasks in the flow of physical synthesis and it's classified as an NP-complete problem. In this work, a parallel computing techniques survey was applied to the VLSI global routing in order to accelerate the global routing processing analyzes. This analyzes was performed on the ISPD 2007/08 benchmark files. We proposed a method that groups the networks and then check for data dependence in each group based on these analyzes. This data dependency checking, we call this checking of collider, aims to create flow nets independent of each other for processing in parallel, or help implement the independent routing networks. The results demonstrate that this separation into groups, together with the competitor comparison of groups, can reduce 67x in the collider networks runtime compared with the sequential release and without the use of groups. It was also obtained a gain of 10x when comparing the version with sequential clusters with the parallel version.

Advisors/Committee Members: Reis, Ricardo Augusto da Luz.

Subjects/Keywords: Microeletrônica; Paralelismo; Vlsi; Global routing; Parallelism; EDA; VLSI; Microelectronics

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❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tumelero, D. (2015). Exploração de paralelismo no roteamento global de circuitos VLSI. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/119081

Chicago Manual of Style (16^th Edition):

Tumelero, Diego. “Exploração de paralelismo no roteamento global de circuitos VLSI.” 2015. Masters Thesis, Brazil. Accessed April 11, 2021. http://hdl.handle.net/10183/119081.

MLA Handbook (7^th Edition):

Tumelero, Diego. “Exploração de paralelismo no roteamento global de circuitos VLSI.” 2015. Web. 11 Apr 2021.

Vancouver:

Tumelero D. Exploração de paralelismo no roteamento global de circuitos VLSI. [Internet] [Masters thesis]. Brazil; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10183/119081.

Council of Science Editors:

Tumelero D. Exploração de paralelismo no roteamento global de circuitos VLSI. [Masters Thesis]. Brazil; 2015. Available from: http://hdl.handle.net/10183/119081

University of California – San Diego

15. Nath, Siddhartha. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.

Degree: Computer Science, 2016, University of California – San Diego

URL: http://www.escholarship.org/uc/item/9jn2c085

► In today's leading-edge semiconductor technologies, it is increasingly difficult for IC designers to achieve sufficient improvements of performance, power and area metrics in their next-generation… (more)

▼ In today's leading-edge semiconductor technologies, it is increasingly difficult for IC designers to achieve sufficient improvements of performance, power and area metrics in their next-generation products. One root cause of this difficulty is the increased margins that are used in the design process to guardband for (i) variability and aging, as well as (ii) analysis inaccuracies. Currently, these margins incur huge costs to design companies, because the benefits of deploying the next technology node are only approximately 20% in circuit performance, power and density. To reduce margins, fast and accurate pathfinding of architecture, technology and constraints choices are essential. A second root cause is the high cost (and, therefore, limited supply) of electronic design automation tool licenses, accompanied by the lack of any systematic methodology to optimize the use of available tools within long-duration, highly iterative design processes. This constrains designers to perform only limited design-space exploration, so as to keep within limits on design infrastructure cost and design turnaround time. This thesis presents new techniques to reduce guardbands in optimization loops in the IC design process by using fast and accurate learning-based models. These techniques can be grouped into three main thrusts: (i) design productivity gains through improved design- and implementation-space exploration; (ii) improved accuracy of electrical modeling and enablement of basic physical design optimizations; and (iii) optimizations of design power, energy, project management, and cost.The thrust on design productivity gains through improved design- and implementation space exploration presents four applications of learning-based models for accurate prediction of area, power, timing and routability. To enable area and power estimation of Networks-on-Chip routers, such that architecture-level (RTL-level) design-space exploration can be efficiently performed, this thesis presents an open-source tool, ORION3.0.The thrust on improved accuracy of electrical modeling and enablement of basic physical design optimizations presents new methodologies to perform high-dimensional learning-based modeling of delay, transition time and slack in timing paths. A methodology to develop accurate models of post-routing optimization of signal delays at multiple signoff corners, so as to enable a new optimization of clock skew variation across corners is also described.The thrust on optimizations of design power, energy, project management, and cost presents three distinct works that directly benefit leading-edge SoC design companies. The first work describes a new analytic three-dimensional placement tool using a new objective function that achieves significant wirelength and power reduction relative to two-dimensional implementations. The second work provides two mixed integer-linear programs for optimal multi-project, multi-resource allocation with task precedence and resource co-constraints for IC design management and cost reduction. The…

Subjects/Keywords: Computer science; Machine Learning; Optimization; VLSI CAD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Nath, S. (2016). New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/9jn2c085

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Nath, Siddhartha. “New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.” 2016. Thesis, University of California – San Diego. Accessed April 11, 2021. http://www.escholarship.org/uc/item/9jn2c085.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Nath, Siddhartha. “New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.” 2016. Web. 11 Apr 2021.

Vancouver:

Nath S. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. [Internet] [Thesis]. University of California – San Diego; 2016. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/9jn2c085.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nath S. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. [Thesis]. University of California – San Diego; 2016. Available from: http://www.escholarship.org/uc/item/9jn2c085

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

UCLA

16. Yu, Tsung-Han. Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios.

Degree: Electrical Engineering, 2013, UCLA

URL: http://www.escholarship.org/uc/item/3dc5f3dq

► With the rapid increases in the number of wireless devices, fixed spectrum allocation has shown to be a major limitation to the evolution of wireless… (more)

Subjects/Keywords: Engineering; cognitive radios; FFT; spectrum sensing; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yu, T. (2013). Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/3dc5f3dq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Yu, Tsung-Han. “Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios.” 2013. Thesis, UCLA. Accessed April 11, 2021. http://www.escholarship.org/uc/item/3dc5f3dq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Yu, Tsung-Han. “Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios.” 2013. Web. 11 Apr 2021.

Vancouver:

Yu T. Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios. [Internet] [Thesis]. UCLA; 2013. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/3dc5f3dq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yu T. Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/3dc5f3dq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Rochester Institute of Technology

17. Chomicz, Thecla. A Methodology for NMOS VLSI manufacturing: From design to test.

Degree: Electrical Engineering, 1990, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/5567

► The development of a methodology to integrate design automation with the fabrication of very large scale integrated circuits is presented. A multiplier circuit is used… (more)

Subjects/Keywords: VLSI; Integrated circuits

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APA (6^th Edition):

Chomicz, T. (1990). A Methodology for NMOS VLSI manufacturing: From design to test. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5567

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chomicz, Thecla. “A Methodology for NMOS VLSI manufacturing: From design to test.” 1990. Thesis, Rochester Institute of Technology. Accessed April 11, 2021. https://scholarworks.rit.edu/theses/5567.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chomicz, Thecla. “A Methodology for NMOS VLSI manufacturing: From design to test.” 1990. Web. 11 Apr 2021.

Vancouver:

Chomicz T. A Methodology for NMOS VLSI manufacturing: From design to test. [Internet] [Thesis]. Rochester Institute of Technology; 1990. [cited 2021 Apr 11]. Available from: https://scholarworks.rit.edu/theses/5567.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chomicz T. A Methodology for NMOS VLSI manufacturing: From design to test. [Thesis]. Rochester Institute of Technology; 1990. Available from: https://scholarworks.rit.edu/theses/5567

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Minnesota

18. Li, Peng. FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications.

Degree: MS, Electrical/Computer Engineering, 2012, University of Minnesota

URL: http://purl.umn.edu/140237

►

University of Minnesota M.S. thesis. October 2012. Major: Electrical/Computer Engineering. Advisor: Hua Tang. 1 computer file (PDF); viii, 47 pages, appendix A.

It is well… (more)

▼

University of Minnesota M.S. thesis. October 2012. Major: Electrical/Computer Engineering. Advisor: Hua Tang. 1 computer file (PDF); viii, 47 pages, appendix A.

It is well known that vehicle tracking processes are very computationally intensive. Traditionally, vehicle tracking algorithms have been implemented using software ap- proaches. The software approaches have a large computational delay, which causes low frame rate vehicle tracking. However, real-time vehicle tracking is highly desirable to improve not only tracking accuracy but also response time, in some ITS (Intelligent Transportation System) applications such as security monitoring and hazard warning. For this purpose, this thesis makes an attempt to design a hardware based system for real-time vehicle detection, which is typically required in the complete tracking system. The vehicle detection systems capture pictures using a camera in real-time and then we apply several image processing algorithms, such as Fixed Block Size Motion Estima- tion (FBSME), Recongurable Block Size Motion Estimation (RBSME), Variable Block Size Motion Estimation (VBSME) and Mixtures of Gaussian, to process these images in real-time for vehicle detection. We rst propose the Very-Large-Scale Integration (VLSI) implementation for RB- SME algorithm, which supports arbitrary block size motion estimation. Experiment results show that the proposed architecture achieves the exibility of adjustable block size at the expense of only 5% hardware overhead compared to the traditional design. We then propose a low-power VLSI implementation for the VBSME algorithm, which employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solutions 1 . The fast full-search algorithm is based on the com- parison of the current minimum Sum of Absolute Dierence (SAD) to a conservative lower bound so that unnecessary SAD calculations can be eliminated. We rst ex- perimentally decide on the specic conservative lower bound and then implement the fast full-search algorithm in Field-Programmable Gate Array (FPGA). To the best of our knowledge, this is the rst time that a fast full-search block matching algorithm is explored to reduce power consumption in the context of VBSME, and designed in hardware. Experiment results show that the proposed hardware implementation can save power consumption by 45% compared to conventional VBSME designs based on the non-fast full-search algorithms. At last, we propose an System-on-a-Chip (SoC) architecture for an Mixture of Gaus- sian (MoG) based image segmentation algorithm. The MoG algorithm for video seg- mentation application is computational intensive. To meet real-time requirement of high frame rate high resolution video segmentation tasks, we present a hardware im- plementation of the MoG algorithm. Moreover, we integrated the hardware IP into an SoC architecture, so that some key parameters, such as learning rate and thresh- old, can be congured on-line, which makes the system extremely exible to adapt to dierent…

Advisors/Committee Members: Hua Tang.

Subjects/Keywords: FPGA; Image processing; Image segmentation; VLSI

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APA (6^th Edition):

Li, P. (2012). FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/140237

Chicago Manual of Style (16^th Edition):

Li, Peng. “FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications.” 2012. Masters Thesis, University of Minnesota. Accessed April 11, 2021. http://purl.umn.edu/140237.

MLA Handbook (7^th Edition):

Li, Peng. “FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications.” 2012. Web. 11 Apr 2021.

Vancouver:

Li P. FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications. [Internet] [Masters thesis]. University of Minnesota; 2012. [cited 2021 Apr 11]. Available from: http://purl.umn.edu/140237.

Council of Science Editors:

Li P. FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications. [Masters Thesis]. University of Minnesota; 2012. Available from: http://purl.umn.edu/140237

University of Minnesota

19. Dalal, Hussain Firoz. Implementation of on-chip thermal sensor using off-leakage current of a transistor.

Degree: MS, Electrical Engineering, 2010, University of Minnesota

URL: http://purl.umn.edu/59772

University of Minnesota M.S. thesis. January 2010. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF); ii, 38 pages. Ill. (some col.)

Abstract summary not available

Advisors/Committee Members: Chris H. Kim.

Subjects/Keywords: VLSI; CMOS; Leakage Current; Electrical Engineering

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APA (6^th Edition):

Dalal, H. F. (2010). Implementation of on-chip thermal sensor using off-leakage current of a transistor. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/59772

Chicago Manual of Style (16^th Edition):

Dalal, Hussain Firoz. “Implementation of on-chip thermal sensor using off-leakage current of a transistor.” 2010. Masters Thesis, University of Minnesota. Accessed April 11, 2021. http://purl.umn.edu/59772.

MLA Handbook (7^th Edition):

Dalal, Hussain Firoz. “Implementation of on-chip thermal sensor using off-leakage current of a transistor.” 2010. Web. 11 Apr 2021.

Vancouver:

Dalal HF. Implementation of on-chip thermal sensor using off-leakage current of a transistor. [Internet] [Masters thesis]. University of Minnesota; 2010. [cited 2021 Apr 11]. Available from: http://purl.umn.edu/59772.

Council of Science Editors:

Dalal HF. Implementation of on-chip thermal sensor using off-leakage current of a transistor. [Masters Thesis]. University of Minnesota; 2010. Available from: http://purl.umn.edu/59772

Anna University

20. Jayanthy S. Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;.

Degree: algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits, 2014, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/23842

►

Very Large Scale Integration VLSI is the fabrication of millions newlineof components on the same chip and is an integral part of modern electronic newlinesystems… (more)

Subjects/Keywords: crosstalk delay; electrical engineering; vlsi circuits

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APA (6^th Edition):

S, J. (2014). Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/23842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

S, Jayanthy. “Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;.” 2014. Thesis, Anna University. Accessed April 11, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/23842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

S, Jayanthy. “Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;.” 2014. Web. 11 Apr 2021.

Vancouver:

S J. Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;. [Internet] [Thesis]. Anna University; 2014. [cited 2021 Apr 11]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

S J. Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Oregon State University

21. Ruggeri, Thomas L. TIMR : Time Interleaved Multi Rail.

Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University

URL: http://hdl.handle.net/1957/29070

► This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic… (more)

Subjects/Keywords: VLSI; Integrated circuits – Very large scale integration

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APA (6^th Edition):

Ruggeri, T. L. (2012). TIMR : Time Interleaved Multi Rail. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29070

Chicago Manual of Style (16^th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Masters Thesis, Oregon State University. Accessed April 11, 2021. http://hdl.handle.net/1957/29070.

MLA Handbook (7^th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Web. 11 Apr 2021.

Vancouver:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1957/29070.

Council of Science Editors:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29070

Cornell University

22. Lockhart, Derek. Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization.

Degree: PhD, Electrical Engineering, 2015, Cornell University

URL: http://hdl.handle.net/1813/40914

► The growing complexity and heterogeneity of modern application-specific integrated circuits has made hardware design methodologies a limiting factor in the construction of future computing systems.… (more)

Subjects/Keywords: Hardware Design Methodologies; Computer Architecture; VLSI

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APA (6^th Edition):

Lockhart, D. (2015). Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/40914

Chicago Manual of Style (16^th Edition):

Lockhart, Derek. “Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization.” 2015. Doctoral Dissertation, Cornell University. Accessed April 11, 2021. http://hdl.handle.net/1813/40914.

MLA Handbook (7^th Edition):

Lockhart, Derek. “Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization.” 2015. Web. 11 Apr 2021.

Vancouver:

Lockhart D. Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization. [Internet] [Doctoral dissertation]. Cornell University; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1813/40914.

Council of Science Editors:

Lockhart D. Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization. [Doctoral Dissertation]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/40914

Cornell University

23. Ortega Otero, Carlos. Static Power Reduction Techniques For Asynchronous Circuits.

Degree: M.S., Electrical Engineering, Electrical Engineering, 2012, Cornell University

URL: http://hdl.handle.net/1813/31005

► Power gating techniques are effective in mitigating leakage losses, which represent a significant portion of power consumption in nanoscale circuits. We examine variants of two… (more)

Subjects/Keywords: Asynchronous; static power; vlsi; Integrated Circuits; leakage

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APA (6^th Edition):

Ortega Otero, C. (2012). Static Power Reduction Techniques For Asynchronous Circuits. (Masters Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/31005

Chicago Manual of Style (16^th Edition):

Ortega Otero, Carlos. “Static Power Reduction Techniques For Asynchronous Circuits.” 2012. Masters Thesis, Cornell University. Accessed April 11, 2021. http://hdl.handle.net/1813/31005.

MLA Handbook (7^th Edition):

Ortega Otero, Carlos. “Static Power Reduction Techniques For Asynchronous Circuits.” 2012. Web. 11 Apr 2021.

Vancouver:

Ortega Otero C. Static Power Reduction Techniques For Asynchronous Circuits. [Internet] [Masters thesis]. Cornell University; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1813/31005.

Council of Science Editors:

Ortega Otero C. Static Power Reduction Techniques For Asynchronous Circuits. [Masters Thesis]. Cornell University; 2012. Available from: http://hdl.handle.net/1813/31005

24. Raja J. VLSI implementation of high throughput MIMO OFDM transceiver;.

Degree: High throughput MIMO OFDM transceiver, 2014, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/16442

►

newline Wireless communication has gained momentum during past one newlineand a half decade with invention of digital cellular system. At the beginning, newlinethe wireless system… (more)

▼

newline Wireless communication has gained momentum during past one newlineand a half decade with invention of digital cellular system. At the beginning, newlinethe wireless system was developed and focused to enable a voice newlinecommunication for minimum data rate requirement. Today, it has emerged newlinerapidly in the market because of a tremendous growth in demand of wireless newlineservices which includes network mobility, scalability and connectivity to the newlineusers. Thus recent and future generations of wireless communication systems newlineare characterized by variety of application ranging from low rate voice data to newlinevery high rate real time streaming video data. There exists a strong trend of newlineshifting towards all in one service, i.e. one system supporting many of the newlineapplications. The applications include e-mail, web browsing, video newlineconferencing, internet telephony, multimedia video streaming, IP TV etc. Consequently, wireless designers face the task of limited availability of Radio newlineFrequency (RF) spectrum and complex time varying problems in the wireless newlinechannel, such as fading and multipath, as well as meeting the demand for high newlinedata rates along with better Quality of Service (QoS). All these applications newlineimpose different QoS constraints to deliver the service appropriately. Some applications like internet telephony require low delay service newlinewhereas web browsing or file sharing applications can tolerate a certain newlineamount of delay. In the case of IP TV and video conferencing, both high data newlinerate and low delay service are required. The wireless system designers are newlinesmart and developed the system which has satisfied these applications with a newlinequite reasonable error. Orthogonal Frequency Division Multiplexing (OFDM) newlineis a special form of multicarrier technique where all the subcarriers are newlineorthogonal to each other. OFDM promises higher data rate and great newlineresistance to the frequency selective fading at the reasonable cost and newlinecomplexity in implementation.

References p.159-173.

Advisors/Committee Members: Kannan M.

Subjects/Keywords: Electrical engineering; Orthogonal Frequency Division Multiplexing; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

J, R. (2014). VLSI implementation of high throughput MIMO OFDM transceiver;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/16442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

J, Raja. “VLSI implementation of high throughput MIMO OFDM transceiver;.” 2014. Thesis, Anna University. Accessed April 11, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/16442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

J, Raja. “VLSI implementation of high throughput MIMO OFDM transceiver;.” 2014. Web. 11 Apr 2021.

Vancouver:

J R. VLSI implementation of high throughput MIMO OFDM transceiver;. [Internet] [Thesis]. Anna University; 2014. [cited 2021 Apr 11]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/16442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

J R. VLSI implementation of high throughput MIMO OFDM transceiver;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/16442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Rajakumar, G. Design and vlsi implementation of digital image processing applications;.

Degree: 2015, Manonmaniam Sundaranar University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/38366

►

Applications of digital image processing dip have become common in our day newlineto day life exploitation of digital image processing systems for real time applications… (more)

Subjects/Keywords: Design; digital image; science; vlsi implementation

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APA (6^th Edition):

Rajakumar, G. (2015). Design and vlsi implementation of digital image processing applications;. (Thesis). Manonmaniam Sundaranar University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/38366

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Rajakumar, G. “Design and vlsi implementation of digital image processing applications;.” 2015. Thesis, Manonmaniam Sundaranar University. Accessed April 11, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/38366.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Rajakumar, G. “Design and vlsi implementation of digital image processing applications;.” 2015. Web. 11 Apr 2021.

Vancouver:

Rajakumar G. Design and vlsi implementation of digital image processing applications;. [Internet] [Thesis]. Manonmaniam Sundaranar University; 2015. [cited 2021 Apr 11]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/38366.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rajakumar G. Design and vlsi implementation of digital image processing applications;. [Thesis]. Manonmaniam Sundaranar University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/38366

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Texas A&M University

26. Shah, Pratik Jitendra. Case studies on lithography-friendly vlsi circuit layout.

Degree: MS, Computer Engineering, 2009, Texas A&M University

URL: http://hdl.handle.net/1969.1/ETD-TAMU-3120

► Moore’s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered… (more)

▼ Moore’s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered by lithography hardware. Currently, a light wavelength of 193nm is being used to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual wafer feature sizes. However, the layout which affects the printability of a circuit can be modified in a manner which can make it more lithography-friendly. In this work, we intend to implement these modifications as a series of perturbations on the initial layout generated by the CAD tool for the circuit. To implement these changes we first calculate the feature variations offline on the boundaries of all possible standard cell pairs used in the circuit layout and record them in a Look-Up Table (LUT). After the CAD tool generates the initial placement of the circuit, we use the LUT to estimate the variations on the boundaries of all the standard cells. Depending on the features which may have the highest feature variations we assign a cost to the layout and our aim is now to reduce the cost of the layout after implementing perturbations which could be a simple cell flip or swap with a neighboring cell. The algorithm used to generate a circuit placement with a low cost is Simulated Annealing which allows a high probability for a solution with a higher cost to be selected during the initial iterations and as time goes on it tends closer to the greedy algorithm. The idea here is to avoid a locally optimum solution. It is also essential to minimize the impact of the iterations performed on the initial solution in terms of wirelength, vias and routing congestion. We validate our procedure on ISCAS85 benchmark circuits by simulating dose and defocus variations using the Mentor tool Calibre LFD. We obtain a reduction of greater 20% in the number of instances with the highest cell boundary feature variations. The wirelength and the number of vias showed an increase of roughly 2.2-8.8% and 1.2- 7.8% respectively for different circuits. The routing congestion by and large remains unaffected. Advisors/Committee Members: Hu, Jiang (advisor), Shi, Weiping (committee member), Walker, Duncan Moore (committee member).

Subjects/Keywords: Lithography; VLSI; layout

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Shah, P. J. (2009). Case studies on lithography-friendly vlsi circuit layout. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-3120

Chicago Manual of Style (16^th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Masters Thesis, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-3120.

MLA Handbook (7^th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Web. 11 Apr 2021.

Vancouver:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Internet] [Masters thesis]. Texas A&M University; 2009. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120.

Council of Science Editors:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Masters Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120

Texas A&M University

27. Rohani, Ehsan. Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation.

Degree: PhD, Computer Engineering, 2017, Texas A&M University

URL: http://hdl.handle.net/1969.1/187296

► In telecommunication systems the goal is to increase the throughput of data communication. Multiple input and multiple output antennas (MIMO) can be used to increase… (more)

▼ In telecommunication systems the goal is to increase the throughput of data communication. Multiple input and multiple output antennas (MIMO) can be used to increase the SNR of the system and as the result increase the throughput via increasing the quality of the service (QoS) or it can be used to increase the speed of transmitted data and the throughput as the result. This trade-off can be used as advantage when dealing with a system design to better utilize hardware/software resources as well as to optimally exploit the environmental factors associated with communication medium. We studied the iterative detection and decoding of the received signals. In this case the received signals are being detected and decoded multiple times which results in higher complexity, and QoS. Considering the original complexity of the MIMO detectors hardware implementation of this method is challenging. To reduce the complexity while expecting performance gain over traditional receivers like Minimum Mean Square of Errors (MMSE) and Zero Forcing (ZF) detectors we had to look at more recent detectors and accept some performance loss. These are detectors with close to ML performance like Kbest or amended versions or linear detectors like the LR aided (lattice reduction) MMSE, or LORD (layered orthogonal lattice detector) detector. Following this approach we considered Integer Forcing (IF) detectors. The IF detectors are categorized as linear detectors; however, there is a search involved in calculating and generating the inverse of the channel matrix that searches for inverse of any full rank integer combination of transmitted data with minimum effect on channel noise. We introduce an algorithm that is able to provide LLRs (soft values) for the detected signal. We show that these type of detectors can reduce the gap between Zero Forcing (ZF) linear detector and maximum likelihood (ML) detector to 48% with only 2.96× more complexity while ML detector is 28.86× more complex. We have implemented an IF processor to evaluate the hardware performance of this detector. To accomplish this task we have improved the existing designs for singular value decomposer (SYD) and advanced the decomposer to achieve a high performance IF detector. We finally present a proof of consent for asynchronous implementation of MIMO satellite communication. Advisors/Committee Members: Choi, Gwan S. (advisor), Lu, Mi (advisor), Narayanan, Krishna (committee member), Walker, Duncan M. (committee member).

Subjects/Keywords: MIMO; 5G; Telecommunication; Integer Forcing; VLSI Implementation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Rohani, E. (2017). Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/187296

Chicago Manual of Style (16^th Edition):

Rohani, Ehsan. “Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation.” 2017. Doctoral Dissertation, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/187296.

MLA Handbook (7^th Edition):

Rohani, Ehsan. “Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation.” 2017. Web. 11 Apr 2021.

Vancouver:

Rohani E. Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation. [Internet] [Doctoral dissertation]. Texas A&M University; 2017. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/187296.

Council of Science Editors:

Rohani E. Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation. [Doctoral Dissertation]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/187296

University of California – San Diego

28. Li, Jiajia. Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality.

Degree: Electrical Engineering (Computer Engineering), 2017, University of California – San Diego

URL: http://www.escholarship.org/uc/item/59z0584c

► In the late CMOS era, integrated-circuit physical design and signoff face three major challenges – (i) complex operating conditions, (ii) low-power demand, and (iii) growing… (more)

▼ In the late CMOS era, integrated-circuit physical design and signoff face three major challenges – (i) complex operating conditions, (ii) low-power demand, and (iii) growing design margin. Future scaling of designs and the continuation of Moore’s Law itself require better physical design optimization and signoff methodologies. Toward this end, this thesis presents novel optimization techniques and signoff methodologies to respectively address these challenges in three main thrusts.In modern SoC implementations, multi-mode design is commonly used to achieve bettercircuit performance and power across voltage scaling, “turbo” and other operating modes. Furthermore, PVT variations result in a large number of corners for circuit design and signoff. To mitigate the impact of complex operating conditions and corner explosion, in the multi-mode multi-corner optimization thrust, this thesis presents approaches to optimize signoff corner selection, reduce skew variation in clock network, and perform scan timing optimization without causing any QoR degradation in functional mode.Energy and battery lifetime constraints induce new and critical challenges to IC designs, especially for mobile and “Internet of Things” (IoT) applications. To achieve power autonomy in the era of a slowing Moore’s law, low-power techniques must be exploited. To minimize design power and energy, in the low-power optimization thrust, this thesis presents a stacked power domain scheme to align SoC power domain voltages with battery voltages for power delivery efficiency and battery lifetime improvements, a novel flop tray generation technique for clock power reduction, and a low-cost resilient design flow to enable better than worst-case design for energy savings.The 2013 ITRS update of system driver models reveal a “scaling gap” since 2008. Oneroot cause of the density scaling slowdown is the growing design margins due to variability, reliability, etc. To reduce the design margins and to pursue design-based equivalent scaling, in the mixed-fabric optimization thrust, this thesis describes the concept of “mixed-fabric optimization” and presents several novel optimization techniques for improved design performance, power, area, reliability and turnaround time. First, we propose an optimization flow for implementation of design blocks with mixed non-integer multiple cell heights, achieving an improved tradeoff of performance, power and area. Second, we exploit the dual-Vth libraries and propose a “no-loop” predictive useful skew optimization flow. Last, we integrate dies with different process conditions in a 3DIC, and apply mix-and-match-aware design optimization to improve performance and reliability of 3DICs.

Subjects/Keywords: Computer engineering; Optimization; Physical design; Signoff; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Li, J. (2017). Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/59z0584c

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Jiajia. “Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality.” 2017. Thesis, University of California – San Diego. Accessed April 11, 2021. http://www.escholarship.org/uc/item/59z0584c.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Jiajia. “Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality.” 2017. Web. 11 Apr 2021.

Vancouver:

Li J. Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality. [Internet] [Thesis]. University of California – San Diego; 2017. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/59z0584c.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li J. Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality. [Thesis]. University of California – San Diego; 2017. Available from: http://www.escholarship.org/uc/item/59z0584c

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Oregon State University

29. He, Jinjin. Efficient decoder design for error correction codes.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

URL: http://hdl.handle.net/1957/15937

► Error correction codes (ECCs) have been widely used in communication systems and storage devices. Nowadays, the rapid development of integrated circuit technologies makes feasible the… (more)

▼ Error correction codes (ECCs) have been widely used in communication systems and storage devices. Nowadays, the rapid development of integrated circuit technologies makes feasible the implementation of powerful ECCs such as turbo code and low-density parity-check (LDPC) code. However, these high-performance codes require complex decoding algorithms, resulting in large hardware area and high power consumption. Furthermore, some of these decoders require an iterative decoding process, which leads to a long decoding latency. Therefore, low-complexity, low-power and high-speed very-large-scale integration (VLSI) architecture design for the ECC decoder is of great importance. This dissertation focuses on efficient VLSI implementation for the decoders of convolutional codes and two advanced coding schemes based on convolutional code: trellis-coded modulation (TCM) and convolutional turbo code (CTC). The first part of this dissertation is dedicated to low-complexity, low-power decoders design for a 4-dimensional, 8-ary phase-shift keying (4-D 8PSK) TCM system. We propose a low-complexity architecture for the transition-metric unit (TMU) to reduce the hardware area without performance loss. Then, a power-efficient scheme by applying T-algorithm on branch metrics (BMs) is proposed for the Viterbi decoder (VD) embedded in the 4-D 8PSK TCM decoder. Unlike the conventional T-algorithm, the proposed scheme does not affect the clock speed of the decoder. Finally, a hybrid T-algorithm is developed by applying T-algorithm on both BMs and path metrics (PMs), which reduces significantly more computations than the conventional T-algorithm applied on PMs. The VLSI design for VDs has been an active research area for decades. In the second part of the dissertation, we extend our research to a more general topic of VDs, where novel architectures are explored to efficiently reduce the power consumption, while still maintaining a high decoding speed and a low decoding latency. CTCs are constructed from parallel convolutional encoding of the same message in different sequences and have the error-correcting capability near the Shannon bound. Practical decoding schemes normally require an iterative decoding process employing the soft-in soft-out (SISO) decoder. The third part of this dissertation is focused on the SISO decoder design for double-binary (DB) CTCs. We propose a low-complexity, memory-reduced architecture by partitioning BMs into two independent portions: information metrics and parity metrics. Furthermore, high-speed recursion architectures for logarithm domain maximum a posteriori probability (log-MAP) algorithm are proposed to increase the decoding speed by algorithmic approximation and bit-level optimization. Advisors/Committee Members: Liu, Huaping (advisor), Bose, Bella (committee member).

Subjects/Keywords: VLSI; Error-correcting codes (Information theory)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

He, J. (2010). Efficient decoder design for error correction codes. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/15937

Chicago Manual of Style (16^th Edition):

He, Jinjin. “Efficient decoder design for error correction codes.” 2010. Doctoral Dissertation, Oregon State University. Accessed April 11, 2021. http://hdl.handle.net/1957/15937.

MLA Handbook (7^th Edition):

He, Jinjin. “Efficient decoder design for error correction codes.” 2010. Web. 11 Apr 2021.

Vancouver:

He J. Efficient decoder design for error correction codes. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1957/15937.

Council of Science Editors:

He J. Efficient decoder design for error correction codes. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/15937

30. L. Frontini. DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS.

Degree: 2019, Università degli Studi di Milano

URL: http://hdl.handle.net/2434/612117

► Gordon E. Moore, a co-founder of Fairchild Semiconductor, and later of Intel, predicted that after 1980 the complexity of an Integrated Circuit would be expected… (more)

▼ Gordon E. Moore, a co-founder of Fairchild Semiconductor, and later of Intel, predicted that after 1980 the complexity of an Integrated Circuit would be expected to double every two years. The prevision made by Moore held for decades, for this reason it is also called “Moore’s law”. The trend in ICs is driven by a reduction of area and power consumption. Today scaled CMOS technologies are the main solution for digital processing. However, the interconnection scaling is not optimal. At every new technology node, the number of metal layers and their thickness increases, exploiting the vertical direction. The reduction of the minimum distance between interconnections and the growth in vertical dimension increase the parasitic capacitance and consequently the dynamic power consumption. Moreover, due to the non-optimal scaling of the interconnections, signal routing is becoming more and more challenging at every technology node advancement. Very scaled technologies make possible to reach a great transistor density. However, the design must comply to strict rules for metal interconnections. The aim of this thesis is to find possible solutions to the disadvantages of scaled CMOS technologies. This goal is obtained in two different ways: using ad-hoc design techniques on today CMOS technologies and finding new approaches to logic synthesis of nanocrossbars, that are an emerging post-CMOS technology. The two approaches used corresponds to the two parts of this thesis. The first part presents the design of an Associative Memory focusing the attention on develop design and logic synthesis techniques to reduce power consumption. The field of applicability of AMs is real-time pattern-recognition tasks. The possible uses range from scientific calculations to image processing for intelligent autonomous devices to image reconstruction for electro-medical apparatuses. In particular AMs are used in High Energy Physics (HEP) experiments to detect particle tracks. HEP experiments generate a huge amount of data, but it is necessary to select and save only the most interesting tracks. Being the data compared in parallel, AMs are synchronous ICs that have a very peaked power consumption, and therefore it is necessary to minimize the power consumption. This AM is designed within the projects IMPART and HTT in 28 nm CMOS technology, using a fully-CMOS approach. The logic is based on the propagation of a “kill signal” that, if one of the bits in a word is not matching, inhibits the switching of the following cells. Thanks to this feature, the designed AM array consumes less than 0.7 fJ/bit. A prototype has been fabricated and it has proven to be functional. The final chip will be installed in the data acquisition chain of ATLAS experiment on HL-LHC at CERN. In the future nanocrossbars are expected to reduce device dimensions and interconnection complexity with respect to CMOS. Logic functions are obtained with switching lattices of four-terminal switches. The research activity on nanocrossbars is done within the project NANOxCOMP. To… Advisors/Committee Members: tutor: G. Trucco, co-tutor: V. Ciriani, coordinatore: P. Boldi, TRUCCO, GABRIELLA, BOLDI, PAOLO.

Subjects/Keywords: cmos; vlsi; nanocrossbars; Settore INF/01 - Informatica

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Frontini, L. (2019). DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS. (Thesis). Università degli Studi di Milano. Retrieved from http://hdl.handle.net/2434/612117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Frontini, L.. “DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS.” 2019. Thesis, Università degli Studi di Milano. Accessed April 11, 2021. http://hdl.handle.net/2434/612117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Frontini, L.. “DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS.” 2019. Web. 11 Apr 2021.

Vancouver:

Frontini L. DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS. [Internet] [Thesis]. Università degli Studi di Milano; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2434/612117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Frontini L. DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS. [Thesis]. Università degli Studi di Milano; 2019. Available from: http://hdl.handle.net/2434/612117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations