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You searched for subject:(VLSI). Showing records 1 – 30 of 847 total matches.

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1. Nakabayashi, Keiji. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nakabayashi, K. (n.d.). A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/6020

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nakabayashi, Keiji. “A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 11, 2021. http://hdl.handle.net/10061/6020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nakabayashi, Keiji. “A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ.” Web. 11 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Nakabayashi K. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10061/6020.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Nakabayashi K. A New Technique of Thermal Analysis for VLSI Chips : VLSIチップに対する新しい熱解析手法; VLSI チップ ニ タイスル アタラシイ ネツ カイセキ シュホウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/6020

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Georgia Tech

2. Kamdar, Keval Prakash. Performance estimation of large area nanowires.

Degree: MS, Electrical and Computer Engineering, 2019, Georgia Tech

 The focus of the thesis is to extensively model high-performance nanowires, develop Verilog A models of the devices and then simulate them using SPICE to… (more)

Subjects/Keywords: Nanowires; vlsi

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APA (6th Edition):

Kamdar, K. P. (2019). Performance estimation of large area nanowires. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61309

Chicago Manual of Style (16th Edition):

Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Masters Thesis, Georgia Tech. Accessed April 11, 2021. http://hdl.handle.net/1853/61309.

MLA Handbook (7th Edition):

Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Web. 11 Apr 2021.

Vancouver:

Kamdar KP. Performance estimation of large area nanowires. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1853/61309.

Council of Science Editors:

Kamdar KP. Performance estimation of large area nanowires. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61309


Cornell University

3. Longfield, Stephen. Constructive Verification Of Quasi Delay-Insensitive Circuits.

Degree: PhD, Electrical Engineering, 2015, Cornell University

 Self-timed circuits have recently regained active interest as their abilities in avoiding timing and voltage margins, disconnecting pipeline depth from occupancy, and achieving average-case performance… (more)

Subjects/Keywords: VLSI; Verification; Asynchronous

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APA (6th Edition):

Longfield, S. (2015). Constructive Verification Of Quasi Delay-Insensitive Circuits. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/40716

Chicago Manual of Style (16th Edition):

Longfield, Stephen. “Constructive Verification Of Quasi Delay-Insensitive Circuits.” 2015. Doctoral Dissertation, Cornell University. Accessed April 11, 2021. http://hdl.handle.net/1813/40716.

MLA Handbook (7th Edition):

Longfield, Stephen. “Constructive Verification Of Quasi Delay-Insensitive Circuits.” 2015. Web. 11 Apr 2021.

Vancouver:

Longfield S. Constructive Verification Of Quasi Delay-Insensitive Circuits. [Internet] [Doctoral dissertation]. Cornell University; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1813/40716.

Council of Science Editors:

Longfield S. Constructive Verification Of Quasi Delay-Insensitive Circuits. [Doctoral Dissertation]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/40716


University of Oulu

4. Shahabuddin, S. (Shahriar). MIMO detection and precoding architectures.

Degree: 2019, University of Oulu

Abstract Multiple-input multiple-output (MIMO) techniques have been adopted since the third generation (3G) wireless communication standard to increase the spectral efficiency, data rate and reliability.… (more)

Subjects/Keywords: ASIP; MIMO; VLSI

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APA (6th Edition):

Shahabuddin, S. (. (2019). MIMO detection and precoding architectures. (Doctoral Dissertation). University of Oulu. Retrieved from http://urn.fi/urn:isbn:9789526222837

Chicago Manual of Style (16th Edition):

Shahabuddin, S (Shahriar). “MIMO detection and precoding architectures.” 2019. Doctoral Dissertation, University of Oulu. Accessed April 11, 2021. http://urn.fi/urn:isbn:9789526222837.

MLA Handbook (7th Edition):

Shahabuddin, S (Shahriar). “MIMO detection and precoding architectures.” 2019. Web. 11 Apr 2021.

Vancouver:

Shahabuddin S(. MIMO detection and precoding architectures. [Internet] [Doctoral dissertation]. University of Oulu; 2019. [cited 2021 Apr 11]. Available from: http://urn.fi/urn:isbn:9789526222837.

Council of Science Editors:

Shahabuddin S(. MIMO detection and precoding architectures. [Doctoral Dissertation]. University of Oulu; 2019. Available from: http://urn.fi/urn:isbn:9789526222837

5. Jain, Shruti. Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;.

Degree: 2013, Jaypee University of Information Technology, Solan

Biological systems can create complex structures from very simple systems. To do this, there must be a method to differentiate different regions where identical systems… (more)

Subjects/Keywords: CMOS; Fuzzy Logic; VLSI

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APA (6th Edition):

Jain, S. (2013). Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;. (Thesis). Jaypee University of Information Technology, Solan. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/11161

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jain, Shruti. “Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;.” 2013. Thesis, Jaypee University of Information Technology, Solan. Accessed April 11, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/11161.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jain, Shruti. “Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;.” 2013. Web. 11 Apr 2021.

Vancouver:

Jain S. Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;. [Internet] [Thesis]. Jaypee University of Information Technology, Solan; 2013. [cited 2021 Apr 11]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11161.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jain S. Communication of Signals and Responses Leading to Cell Survival Cell Death Using Engineered Regulatory Networks;. [Thesis]. Jaypee University of Information Technology, Solan; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11161

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

6. Wang, Qian. Architectures and Design of VLSI Machine Learning Systems.

Degree: PhD, Computer Engineering, 2016, Texas A&M University

 Quintillions of bytes of data are generated every day in this era of big data. Machine learning techniques are utilized to perform predictive analysis on… (more)

Subjects/Keywords: Machine learning; VLSI architecture

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APA (6th Edition):

Wang, Q. (2016). Architectures and Design of VLSI Machine Learning Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/158093

Chicago Manual of Style (16th Edition):

Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Doctoral Dissertation, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/158093.

MLA Handbook (7th Edition):

Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Web. 11 Apr 2021.

Vancouver:

Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/158093.

Council of Science Editors:

Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/158093


Texas A&M University

7. Xu, Jingwei. Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes.

Degree: PhD, Computer Engineering, 2016, Texas A&M University

 With its low error-floor performance, polar codes attract significant attention as the potential standard error correction code (ECC) for future communication and data storage. However,… (more)

Subjects/Keywords: error correction coding; VLSI

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APA (6th Edition):

Xu, J. (2016). Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/187409

Chicago Manual of Style (16th Edition):

Xu, Jingwei. “Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes.” 2016. Doctoral Dissertation, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/187409.

MLA Handbook (7th Edition):

Xu, Jingwei. “Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes.” 2016. Web. 11 Apr 2021.

Vancouver:

Xu J. Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/187409.

Council of Science Editors:

Xu J. Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/187409


Texas A&M University

8. Mandal, Ayan. Efficient Design and Clocking for a Network-on-Chip.

Degree: PhD, Computer Engineering, 2013, Texas A&M University

 As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC)… (more)

Subjects/Keywords: Network-on-Chip; Clock; VLSI

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APA (6th Edition):

Mandal, A. (2013). Efficient Design and Clocking for a Network-on-Chip. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149325

Chicago Manual of Style (16th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Doctoral Dissertation, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/149325.

MLA Handbook (7th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Web. 11 Apr 2021.

Vancouver:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Internet] [Doctoral dissertation]. Texas A&M University; 2013. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/149325.

Council of Science Editors:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Doctoral Dissertation]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149325


University of Toronto

9. Yu, Jingshu. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.

Degree: 2014, University of Toronto

In this thesis, an integrated H-bridge is presented for continuously optimizing the power conversion efficiency over a wide range of output current. The proposed IC… (more)

Subjects/Keywords: Power Electronics; VLSI; 0544

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APA (6th Edition):

Yu, J. (2014). A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/67870

Chicago Manual of Style (16th Edition):

Yu, Jingshu. “A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.” 2014. Masters Thesis, University of Toronto. Accessed April 11, 2021. http://hdl.handle.net/1807/67870.

MLA Handbook (7th Edition):

Yu, Jingshu. “A Segmented Output Stage H-Bridge IC with Tunable Gate Driver.” 2014. Web. 11 Apr 2021.

Vancouver:

Yu J. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1807/67870.

Council of Science Editors:

Yu J. A Segmented Output Stage H-Bridge IC with Tunable Gate Driver. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/67870


University of Southern California

10. Kashfi, Fatemeh. Thermal analysis and multiobjective optimization for three dimensional integrated circuits.

Degree: PhD, Electrical Engineering (VLSI Design), 2013, University of Southern California

 Three Dimensional Integrated Circuit (3DIC) technology has been introduced to address the interconnect issues in nanometer circuit design that limit performance improvement and power reduction.… (more)

Subjects/Keywords: 3DIC; optimization; temperature; electronics; VLSI

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APA (6th Edition):

Kashfi, F. (2013). Thermal analysis and multiobjective optimization for three dimensional integrated circuits. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7439

Chicago Manual of Style (16th Edition):

Kashfi, Fatemeh. “Thermal analysis and multiobjective optimization for three dimensional integrated circuits.” 2013. Doctoral Dissertation, University of Southern California. Accessed April 11, 2021. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7439.

MLA Handbook (7th Edition):

Kashfi, Fatemeh. “Thermal analysis and multiobjective optimization for three dimensional integrated circuits.” 2013. Web. 11 Apr 2021.

Vancouver:

Kashfi F. Thermal analysis and multiobjective optimization for three dimensional integrated circuits. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2021 Apr 11]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7439.

Council of Science Editors:

Kashfi F. Thermal analysis and multiobjective optimization for three dimensional integrated circuits. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/325495/rec/7439

11. Kananen, Asko. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.

Degree: 2007, Helsinki University of Technology

This thesis deals with silicon implementations of an all-transistor analogue parallel processor that emulates the functionality of a resistive network. The problems related to VLSI -implementations… (more)

Subjects/Keywords: analogue parallel processor; VLSI; resistive network; analoginen rinnakkaisprosessori; VLSI; vastusverkko

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APA (6th Edition):

Kananen, A. (2007). A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. (Thesis). Helsinki University of Technology. Retrieved from http://lib.tkk.fi/Diss/2007/isbn9789512286232/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kananen, Asko. “A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.” 2007. Thesis, Helsinki University of Technology. Accessed April 11, 2021. http://lib.tkk.fi/Diss/2007/isbn9789512286232/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kananen, Asko. “A VLSI Array Processor Architecture for Emulating Resistive Network Filtering.” 2007. Web. 11 Apr 2021.

Vancouver:

Kananen A. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. [Internet] [Thesis]. Helsinki University of Technology; 2007. [cited 2021 Apr 11]. Available from: http://lib.tkk.fi/Diss/2007/isbn9789512286232/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kananen A. A VLSI Array Processor Architecture for Emulating Resistive Network Filtering. [Thesis]. Helsinki University of Technology; 2007. Available from: http://lib.tkk.fi/Diss/2007/isbn9789512286232/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Iowa State University

12. Zhang, Yanheng. Handling the complexity of routing problem in modern VLSI design.

Degree: 2011, Iowa State University

 In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pins and ports of circuit gates and blocks. Traditionally, VLSI(more)

Subjects/Keywords: Physical Design; Routability; VLSI CAD; VLSI Routing; Electrical and Computer Engineering

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APA (6th Edition):

Zhang, Y. (2011). Handling the complexity of routing problem in modern VLSI design. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/11896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Yanheng. “Handling the complexity of routing problem in modern VLSI design.” 2011. Thesis, Iowa State University. Accessed April 11, 2021. https://lib.dr.iastate.edu/etd/11896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Yanheng. “Handling the complexity of routing problem in modern VLSI design.” 2011. Web. 11 Apr 2021.

Vancouver:

Zhang Y. Handling the complexity of routing problem in modern VLSI design. [Internet] [Thesis]. Iowa State University; 2011. [cited 2021 Apr 11]. Available from: https://lib.dr.iastate.edu/etd/11896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang Y. Handling the complexity of routing problem in modern VLSI design. [Thesis]. Iowa State University; 2011. Available from: https://lib.dr.iastate.edu/etd/11896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Reimann, Tiago Jose. Roteamento global de circuitos VLSI.

Degree: 2013, Brazil

Este trabalho apresenta a implementação de um roteador global de circuitos integrados capaz de tratar os problemas de roteamento atuais, utilizando como referência para avaliação… (more)

Subjects/Keywords: Microeletrônica; Vlsi; Roteamento : Circuitos integrados; Global routing; Physical synthesis; CAD; VLSI

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APA (6th Edition):

Reimann, T. J. (2013). Roteamento global de circuitos VLSI. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/71269

Chicago Manual of Style (16th Edition):

Reimann, Tiago Jose. “Roteamento global de circuitos VLSI.” 2013. Masters Thesis, Brazil. Accessed April 11, 2021. http://hdl.handle.net/10183/71269.

MLA Handbook (7th Edition):

Reimann, Tiago Jose. “Roteamento global de circuitos VLSI.” 2013. Web. 11 Apr 2021.

Vancouver:

Reimann TJ. Roteamento global de circuitos VLSI. [Internet] [Masters thesis]. Brazil; 2013. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10183/71269.

Council of Science Editors:

Reimann TJ. Roteamento global de circuitos VLSI. [Masters Thesis]. Brazil; 2013. Available from: http://hdl.handle.net/10183/71269

14. Tumelero, Diego. Exploração de paralelismo no roteamento global de circuitos VLSI.

Degree: 2015, Brazil

Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos… (more)

Subjects/Keywords: Microeletrônica; Paralelismo; Vlsi; Global routing; Parallelism; EDA; VLSI; Microelectronics

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APA (6th Edition):

Tumelero, D. (2015). Exploração de paralelismo no roteamento global de circuitos VLSI. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/119081

Chicago Manual of Style (16th Edition):

Tumelero, Diego. “Exploração de paralelismo no roteamento global de circuitos VLSI.” 2015. Masters Thesis, Brazil. Accessed April 11, 2021. http://hdl.handle.net/10183/119081.

MLA Handbook (7th Edition):

Tumelero, Diego. “Exploração de paralelismo no roteamento global de circuitos VLSI.” 2015. Web. 11 Apr 2021.

Vancouver:

Tumelero D. Exploração de paralelismo no roteamento global de circuitos VLSI. [Internet] [Masters thesis]. Brazil; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10183/119081.

Council of Science Editors:

Tumelero D. Exploração de paralelismo no roteamento global de circuitos VLSI. [Masters Thesis]. Brazil; 2015. Available from: http://hdl.handle.net/10183/119081


University of California – San Diego

15. Nath, Siddhartha. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.

Degree: Computer Science, 2016, University of California – San Diego

 In today's leading-edge semiconductor technologies, it is increasingly difficult for IC designers to achieve sufficient improvements of performance, power and area metrics in their next-generation… (more)

Subjects/Keywords: Computer science; Machine Learning; Optimization; VLSI CAD

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APA (6th Edition):

Nath, S. (2016). New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/9jn2c085

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nath, Siddhartha. “New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.” 2016. Thesis, University of California – San Diego. Accessed April 11, 2021. http://www.escholarship.org/uc/item/9jn2c085.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nath, Siddhartha. “New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.” 2016. Web. 11 Apr 2021.

Vancouver:

Nath S. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. [Internet] [Thesis]. University of California – San Diego; 2016. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/9jn2c085.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nath S. New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. [Thesis]. University of California – San Diego; 2016. Available from: http://www.escholarship.org/uc/item/9jn2c085

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

16. Yu, Tsung-Han. Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios.

Degree: Electrical Engineering, 2013, UCLA

 With the rapid increases in the number of wireless devices, fixed spectrum allocation has shown to be a major limitation to the evolution of wireless… (more)

Subjects/Keywords: Engineering; cognitive radios; FFT; spectrum sensing; VLSI

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APA (6th Edition):

Yu, T. (2013). Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/3dc5f3dq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yu, Tsung-Han. “Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios.” 2013. Thesis, UCLA. Accessed April 11, 2021. http://www.escholarship.org/uc/item/3dc5f3dq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yu, Tsung-Han. “Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios.” 2013. Web. 11 Apr 2021.

Vancouver:

Yu T. Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios. [Internet] [Thesis]. UCLA; 2013. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/3dc5f3dq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yu T. Energy-Efficient VLSI Signal Processing for Wideband Spectrum Sensing in Cognitive Radios. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/3dc5f3dq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

17. Chomicz, Thecla. A Methodology for NMOS VLSI manufacturing: From design to test.

Degree: Electrical Engineering, 1990, Rochester Institute of Technology

 The development of a methodology to integrate design automation with the fabrication of very large scale integrated circuits is presented. A multiplier circuit is used… (more)

Subjects/Keywords: VLSI; Integrated circuits

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APA (6th Edition):

Chomicz, T. (1990). A Methodology for NMOS VLSI manufacturing: From design to test. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5567

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chomicz, Thecla. “A Methodology for NMOS VLSI manufacturing: From design to test.” 1990. Thesis, Rochester Institute of Technology. Accessed April 11, 2021. https://scholarworks.rit.edu/theses/5567.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chomicz, Thecla. “A Methodology for NMOS VLSI manufacturing: From design to test.” 1990. Web. 11 Apr 2021.

Vancouver:

Chomicz T. A Methodology for NMOS VLSI manufacturing: From design to test. [Internet] [Thesis]. Rochester Institute of Technology; 1990. [cited 2021 Apr 11]. Available from: https://scholarworks.rit.edu/theses/5567.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chomicz T. A Methodology for NMOS VLSI manufacturing: From design to test. [Thesis]. Rochester Institute of Technology; 1990. Available from: https://scholarworks.rit.edu/theses/5567

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

18. Li, Peng. FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications.

Degree: MS, Electrical/Computer Engineering, 2012, University of Minnesota

University of Minnesota M.S. thesis. October 2012. Major: Electrical/Computer Engineering. Advisor: Hua Tang. 1 computer file (PDF); viii, 47 pages, appendix A.

It is well… (more)

Subjects/Keywords: FPGA; Image processing; Image segmentation; VLSI

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APA (6th Edition):

Li, P. (2012). FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/140237

Chicago Manual of Style (16th Edition):

Li, Peng. “FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications.” 2012. Masters Thesis, University of Minnesota. Accessed April 11, 2021. http://purl.umn.edu/140237.

MLA Handbook (7th Edition):

Li, Peng. “FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications.” 2012. Web. 11 Apr 2021.

Vancouver:

Li P. FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications. [Internet] [Masters thesis]. University of Minnesota; 2012. [cited 2021 Apr 11]. Available from: http://purl.umn.edu/140237.

Council of Science Editors:

Li P. FPGA-based hardware implementation of image processing algorithms for real-time vehicle detection applications. [Masters Thesis]. University of Minnesota; 2012. Available from: http://purl.umn.edu/140237


University of Minnesota

19. Dalal, Hussain Firoz. Implementation of on-chip thermal sensor using off-leakage current of a transistor.

Degree: MS, Electrical Engineering, 2010, University of Minnesota

University of Minnesota M.S. thesis. January 2010. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF); ii, 38 pages. Ill. (some col.)

Abstract summary not available

Advisors/Committee Members: Chris H. Kim.

Subjects/Keywords: VLSI; CMOS; Leakage Current; Electrical Engineering

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APA (6th Edition):

Dalal, H. F. (2010). Implementation of on-chip thermal sensor using off-leakage current of a transistor. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/59772

Chicago Manual of Style (16th Edition):

Dalal, Hussain Firoz. “Implementation of on-chip thermal sensor using off-leakage current of a transistor.” 2010. Masters Thesis, University of Minnesota. Accessed April 11, 2021. http://purl.umn.edu/59772.

MLA Handbook (7th Edition):

Dalal, Hussain Firoz. “Implementation of on-chip thermal sensor using off-leakage current of a transistor.” 2010. Web. 11 Apr 2021.

Vancouver:

Dalal HF. Implementation of on-chip thermal sensor using off-leakage current of a transistor. [Internet] [Masters thesis]. University of Minnesota; 2010. [cited 2021 Apr 11]. Available from: http://purl.umn.edu/59772.

Council of Science Editors:

Dalal HF. Implementation of on-chip thermal sensor using off-leakage current of a transistor. [Masters Thesis]. University of Minnesota; 2010. Available from: http://purl.umn.edu/59772


Anna University

20. Jayanthy S. Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;.

Degree: algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits, 2014, Anna University

Very Large Scale Integration VLSI is the fabrication of millions newlineof components on the same chip and is an integral part of modern electronic newlinesystems… (more)

Subjects/Keywords: crosstalk delay; electrical engineering; vlsi circuits

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APA (6th Edition):

S, J. (2014). Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/23842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

S, Jayanthy. “Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;.” 2014. Thesis, Anna University. Accessed April 11, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/23842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

S, Jayanthy. “Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;.” 2014. Web. 11 Apr 2021.

Vancouver:

S J. Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;. [Internet] [Thesis]. Anna University; 2014. [cited 2021 Apr 11]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

S J. Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

21. Ruggeri, Thomas L. TIMR : Time Interleaved Multi Rail.

Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University

 This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic… (more)

Subjects/Keywords: VLSI; Integrated circuits  – Very large scale integration

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APA (6th Edition):

Ruggeri, T. L. (2012). TIMR : Time Interleaved Multi Rail. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29070

Chicago Manual of Style (16th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Masters Thesis, Oregon State University. Accessed April 11, 2021. http://hdl.handle.net/1957/29070.

MLA Handbook (7th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Web. 11 Apr 2021.

Vancouver:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1957/29070.

Council of Science Editors:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29070


Cornell University

22. Lockhart, Derek. Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization.

Degree: PhD, Electrical Engineering, 2015, Cornell University

 The growing complexity and heterogeneity of modern application-specific integrated circuits has made hardware design methodologies a limiting factor in the construction of future computing systems.… (more)

Subjects/Keywords: Hardware Design Methodologies; Computer Architecture; VLSI

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APA (6th Edition):

Lockhart, D. (2015). Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/40914

Chicago Manual of Style (16th Edition):

Lockhart, Derek. “Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization.” 2015. Doctoral Dissertation, Cornell University. Accessed April 11, 2021. http://hdl.handle.net/1813/40914.

MLA Handbook (7th Edition):

Lockhart, Derek. “Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization.” 2015. Web. 11 Apr 2021.

Vancouver:

Lockhart D. Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization. [Internet] [Doctoral dissertation]. Cornell University; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1813/40914.

Council of Science Editors:

Lockhart D. Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization. [Doctoral Dissertation]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/40914


Cornell University

23. Ortega Otero, Carlos. Static Power Reduction Techniques For Asynchronous Circuits.

Degree: M.S., Electrical Engineering, Electrical Engineering, 2012, Cornell University

 Power gating techniques are effective in mitigating leakage losses, which represent a significant portion of power consumption in nanoscale circuits. We examine variants of two… (more)

Subjects/Keywords: Asynchronous; static power; vlsi; Integrated Circuits; leakage

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APA (6th Edition):

Ortega Otero, C. (2012). Static Power Reduction Techniques For Asynchronous Circuits. (Masters Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/31005

Chicago Manual of Style (16th Edition):

Ortega Otero, Carlos. “Static Power Reduction Techniques For Asynchronous Circuits.” 2012. Masters Thesis, Cornell University. Accessed April 11, 2021. http://hdl.handle.net/1813/31005.

MLA Handbook (7th Edition):

Ortega Otero, Carlos. “Static Power Reduction Techniques For Asynchronous Circuits.” 2012. Web. 11 Apr 2021.

Vancouver:

Ortega Otero C. Static Power Reduction Techniques For Asynchronous Circuits. [Internet] [Masters thesis]. Cornell University; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1813/31005.

Council of Science Editors:

Ortega Otero C. Static Power Reduction Techniques For Asynchronous Circuits. [Masters Thesis]. Cornell University; 2012. Available from: http://hdl.handle.net/1813/31005

24. Raja J. VLSI implementation of high throughput MIMO OFDM transceiver;.

Degree: High throughput MIMO OFDM transceiver, 2014, Anna University

newline Wireless communication has gained momentum during past one newlineand a half decade with invention of digital cellular system. At the beginning, newlinethe wireless system… (more)

Subjects/Keywords: Electrical engineering; Orthogonal Frequency Division Multiplexing; VLSI

Page 1

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

J, R. (2014). VLSI implementation of high throughput MIMO OFDM transceiver;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/16442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

J, Raja. “VLSI implementation of high throughput MIMO OFDM transceiver;.” 2014. Thesis, Anna University. Accessed April 11, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/16442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

J, Raja. “VLSI implementation of high throughput MIMO OFDM transceiver;.” 2014. Web. 11 Apr 2021.

Vancouver:

J R. VLSI implementation of high throughput MIMO OFDM transceiver;. [Internet] [Thesis]. Anna University; 2014. [cited 2021 Apr 11]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/16442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

J R. VLSI implementation of high throughput MIMO OFDM transceiver;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/16442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Rajakumar, G. Design and vlsi implementation of digital image processing applications;.

Degree: 2015, Manonmaniam Sundaranar University

Applications of digital image processing dip have become common in our day newlineto day life exploitation of digital image processing systems for real time applications… (more)

Subjects/Keywords: Design; digital image; science; vlsi implementation

Page 1

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APA (6th Edition):

Rajakumar, G. (2015). Design and vlsi implementation of digital image processing applications;. (Thesis). Manonmaniam Sundaranar University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/38366

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rajakumar, G. “Design and vlsi implementation of digital image processing applications;.” 2015. Thesis, Manonmaniam Sundaranar University. Accessed April 11, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/38366.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rajakumar, G. “Design and vlsi implementation of digital image processing applications;.” 2015. Web. 11 Apr 2021.

Vancouver:

Rajakumar G. Design and vlsi implementation of digital image processing applications;. [Internet] [Thesis]. Manonmaniam Sundaranar University; 2015. [cited 2021 Apr 11]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/38366.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rajakumar G. Design and vlsi implementation of digital image processing applications;. [Thesis]. Manonmaniam Sundaranar University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/38366

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

26. Shah, Pratik Jitendra. Case studies on lithography-friendly vlsi circuit layout.

Degree: MS, Computer Engineering, 2009, Texas A&M University

 Moore’s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered… (more)

Subjects/Keywords: Lithography; VLSI; layout

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APA (6th Edition):

Shah, P. J. (2009). Case studies on lithography-friendly vlsi circuit layout. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-3120

Chicago Manual of Style (16th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Masters Thesis, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-3120.

MLA Handbook (7th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Web. 11 Apr 2021.

Vancouver:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Internet] [Masters thesis]. Texas A&M University; 2009. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120.

Council of Science Editors:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Masters Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120


Texas A&M University

27. Rohani, Ehsan. Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation.

Degree: PhD, Computer Engineering, 2017, Texas A&M University

 In telecommunication systems the goal is to increase the throughput of data communication. Multiple input and multiple output antennas (MIMO) can be used to increase… (more)

Subjects/Keywords: MIMO; 5G; Telecommunication; Integer Forcing; VLSI Implementation

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APA (6th Edition):

Rohani, E. (2017). Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/187296

Chicago Manual of Style (16th Edition):

Rohani, Ehsan. “Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation.” 2017. Doctoral Dissertation, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/187296.

MLA Handbook (7th Edition):

Rohani, Ehsan. “Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation.” 2017. Web. 11 Apr 2021.

Vancouver:

Rohani E. Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation. [Internet] [Doctoral dissertation]. Texas A&M University; 2017. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/187296.

Council of Science Editors:

Rohani E. Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation. [Doctoral Dissertation]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/187296


University of California – San Diego

28. Li, Jiajia. Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality.

Degree: Electrical Engineering (Computer Engineering), 2017, University of California – San Diego

 In the late CMOS era, integrated-circuit physical design and signoff face three major challenges – (i) complex operating conditions, (ii) low-power demand, and (iii) growing… (more)

Subjects/Keywords: Computer engineering; Optimization; Physical design; Signoff; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, J. (2017). Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/59z0584c

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Jiajia. “Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality.” 2017. Thesis, University of California – San Diego. Accessed April 11, 2021. http://www.escholarship.org/uc/item/59z0584c.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Jiajia. “Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality.” 2017. Web. 11 Apr 2021.

Vancouver:

Li J. Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality. [Internet] [Thesis]. University of California – San Diego; 2017. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/59z0584c.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li J. Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality. [Thesis]. University of California – San Diego; 2017. Available from: http://www.escholarship.org/uc/item/59z0584c

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

29. He, Jinjin. Efficient decoder design for error correction codes.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Error correction codes (ECCs) have been widely used in communication systems and storage devices. Nowadays, the rapid development of integrated circuit technologies makes feasible the… (more)

Subjects/Keywords: VLSI; Error-correcting codes (Information theory)

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APA (6th Edition):

He, J. (2010). Efficient decoder design for error correction codes. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/15937

Chicago Manual of Style (16th Edition):

He, Jinjin. “Efficient decoder design for error correction codes.” 2010. Doctoral Dissertation, Oregon State University. Accessed April 11, 2021. http://hdl.handle.net/1957/15937.

MLA Handbook (7th Edition):

He, Jinjin. “Efficient decoder design for error correction codes.” 2010. Web. 11 Apr 2021.

Vancouver:

He J. Efficient decoder design for error correction codes. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1957/15937.

Council of Science Editors:

He J. Efficient decoder design for error correction codes. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/15937

30. L. Frontini. DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS.

Degree: 2019, Università degli Studi di Milano

 Gordon E. Moore, a co-founder of Fairchild Semiconductor, and later of Intel, predicted that after 1980 the complexity of an Integrated Circuit would be expected… (more)

Subjects/Keywords: cmos; vlsi; nanocrossbars; Settore INF/01 - Informatica

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APA (6th Edition):

Frontini, L. (2019). DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS. (Thesis). Università degli Studi di Milano. Retrieved from http://hdl.handle.net/2434/612117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Frontini, L.. “DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS.” 2019. Thesis, Università degli Studi di Milano. Accessed April 11, 2021. http://hdl.handle.net/2434/612117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Frontini, L.. “DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS.” 2019. Web. 11 Apr 2021.

Vancouver:

Frontini L. DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS. [Internet] [Thesis]. Università degli Studi di Milano; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2434/612117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Frontini L. DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS. [Thesis]. Università degli Studi di Milano; 2019. Available from: http://hdl.handle.net/2434/612117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [29]

.