subject:(VLSI AND Circuits Embedded AND Hardware Systems)

Cal Poly

1. Zaveri, Jainish K. Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology.

Degree: MS, Electrical Engineering, 2018, Cal Poly

URL: https://digitalcommons.calpoly.edu/theses/1940 ; 10.15368/theses.2018.118

► Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6^th Edition):

Zaveri, J. K. (2018). Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1940 ; 10.15368/theses.2018.118

Chicago Manual of Style (16^th Edition):

Zaveri, Jainish K. “Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology.” 2018. Masters Thesis, Cal Poly. Accessed February 27, 2021. https://digitalcommons.calpoly.edu/theses/1940 ; 10.15368/theses.2018.118.

MLA Handbook (7^th Edition):

Zaveri, Jainish K. “Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology.” 2018. Web. 27 Feb 2021.

Vancouver:

Zaveri JK. Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology. [Internet] [Masters thesis]. Cal Poly; 2018. [cited 2021 Feb 27]. Available from: https://digitalcommons.calpoly.edu/theses/1940 ; 10.15368/theses.2018.118.

Council of Science Editors:

Zaveri JK. Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology. [Masters Thesis]. Cal Poly; 2018. Available from: https://digitalcommons.calpoly.edu/theses/1940 ; 10.15368/theses.2018.118

University of Tennessee – Knoxville

2. Kilambi, Supriya. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.

Degree: MS, Computer Engineering, 2011, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/888

► This thesis presents the low power design of a 916MHz Gilbert cell mixer and a Class-A power amplifier for the Bioluminescent Bioreporter Integrated Circuit (BBIC)… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6^th Edition):

Kilambi, S. (2011). Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Web. 27 Feb 2021.

Vancouver:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Tennessee – Knoxville

3. Tham, Kevin Vun Kiat. PVT Compensation for Single-Slope Measurement Systems.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/915

► A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6^th Edition):

Tham, K. V. K. (2011). PVT Compensation for Single-Slope Measurement Systems. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Web. 27 Feb 2021.

Vancouver:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Tennessee – Knoxville

4. Mudhasani, Shanthan. GPU-based Implementation of the Variational Path Integral Method.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/932

► Any system in the world constitutes particles like electrons. To analyze the behaviors of these systems the behavior of these particles must be predicted.… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6^th Edition):

Mudhasani, S. (2011). GPU-based Implementation of the Variational Path Integral Method. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Web. 27 Feb 2021.

Vancouver:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Virginia Commonwealth University

5. Khairullah, Shawkat Sabah. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.

Degree: PhD, Electrical & Computer Engineering, 2018, Virginia Commonwealth University

URL: https://doi.org/10.25772/7QKK-M119 ; https://scholarscompass.vcu.edu/etd/5671

► Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes.… (more)

▼ Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation community where a significant need exists. This dissertation presents a new self-healing digital I&C architecture called BioSymPLe, inspired from the way nature responds, defends and heals: the stem cells in the immune system of living organisms, the life cycle of the living cell, and the pathway from Deoxyribonucleic acid (DNA) to protein. The BioSymPLe architecture is integrating biological concepts, fault tolerance techniques, and operational schematics for the international standard IEC 61131-3 to facilitate adoption in the automation industry. BioSymPLe is organized into three hierarchical levels: the local function migration layer from the top side, the critical service layer in the middle, and the global function migration layer from the bottom side. The local layer is used to monitor the correct execution of functions at the cellular level and to activate healing mechanisms at the critical service level. The critical layer is allocating a group of functional B cells which represent the building block that executes the intended functionality of critical application based on the expression for DNA genetic codes stored inside each cell. The global layer uses a concept of embryonic stem cells by differentiating these type of cells to repair the faulty T cells and supervising all repair mechanisms. Finally, two industrial applications have been mapped on the proposed architecture, which are capable of tolerating a significant number of faults (transient, permanent, and hardware common cause failures CCFs) that can stem from environmental disturbances and we believe the nexus of its concepts can positively impact the next generation of critical systems in the automation industry. Advisors/Committee Members: Dr. Carl R. Elks, Dr. Robert H. Klenke, Dr. Alen Docef, Dr. Tim Bakker, Dr. Fadi Obeidat.

Subjects/Keywords: Computer and Systems Architecture; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Khairullah, S. S. (2018). Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. (Doctoral Dissertation). Virginia Commonwealth University. Retrieved from https://doi.org/10.25772/7QKK-M119 ; https://scholarscompass.vcu.edu/etd/5671

Chicago Manual of Style (16^th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Doctoral Dissertation, Virginia Commonwealth University. Accessed February 27, 2021. https://doi.org/10.25772/7QKK-M119 ; https://scholarscompass.vcu.edu/etd/5671.

MLA Handbook (7^th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Web. 27 Feb 2021.

Vancouver:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Internet] [Doctoral dissertation]. Virginia Commonwealth University; 2018. [cited 2021 Feb 27]. Available from: https://doi.org/10.25772/7QKK-M119 ; https://scholarscompass.vcu.edu/etd/5671.

Council of Science Editors:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Doctoral Dissertation]. Virginia Commonwealth University; 2018. Available from: https://doi.org/10.25772/7QKK-M119 ; https://scholarscompass.vcu.edu/etd/5671

University of Arkansas

6. McGeehan, Brendan. Hardware IP Classification through Weighted Characteristics.

Degree: MSCmpE, 2019, University of Arkansas

URL: https://scholarworks.uark.edu/etd/3166

► Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For… (more)

▼ Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For instance, outsourcing certain components of an overall design can reduce time-to-market by allowing each party to specialize and perfect a specific part of the overall design. However, allowing third-party involvement also increases the possibility of malicious attacks, such as hardware Trojan insertion. Trojan insertion is a particularly dangerous security threat because testing the functionality of an IP can often leave the Trojan undetected. Therefore, this thesis work provides an improvement on a Trojan detection method known as Structural Checking which analyzes Register-Transfer Level (RTL) and gate-level soft IPs. Given an unknown IP, the Structural Checking tool will break down the design primary ports and internal signals into assets that fall into six characteristics. These characteristics organize how the IP is structured and provide information about the unknown IP’s overall function. The tool also provides a library of known designs referred to as the Golden Reference Library (GRL). All entries in the library are also broken down into the same six characteristics and are either known to be clean or known to have a Trojan inserted. An overall percent match for each library entry against the unknown IP is calculated by first computing a percent match within each characteristic. A weighted average of these percent matches makes up the final percentage. If the library entry with the best match is known to have a Trojan inserted, then the unknown design is likely to have a Trojan as well and vice versa. Due to the structural variability of soft IP designs, it is vital to provide the best possible weighting of the six characteristics to best match the unknown IP to the most similar library entry. This thesis work provides a statistical approach to finding the best weights to optimize the Structural Checking tool’s matching algorithm. Advisors/Committee Members: Jia Di, James P. Parkerson, Dale Thompson.

Subjects/Keywords: Classifcation; Hardware; Trojans; Hardware Systems; Information Security; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

McGeehan, B. (2019). Hardware IP Classification through Weighted Characteristics. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3166

Chicago Manual of Style (16^th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/3166.

MLA Handbook (7^th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Web. 27 Feb 2021.

Vancouver:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/3166.

Council of Science Editors:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3166

Boise State University

7. Henderson, Edward Nelson. An Inertial Measurement System for Hand and Finger Tracking.

Degree: 2011, Boise State University

URL: https://scholarworks.boisestate.edu/td/233

► The primary Human Computer Interfaces (HCI) today are the keyboard and mouse. These interfaces do not facilitate a fluid flow of thought and intent from… (more)

Subjects/Keywords: inertial; glove; IMU; algorithm; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Henderson, E. N. (2011). An Inertial Measurement System for Hand and Finger Tracking. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Henderson, Edward Nelson. “An Inertial Measurement System for Hand and Finger Tracking.” 2011. Thesis, Boise State University. Accessed February 27, 2021. https://scholarworks.boisestate.edu/td/233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Henderson, Edward Nelson. “An Inertial Measurement System for Hand and Finger Tracking.” 2011. Web. 27 Feb 2021.

Vancouver:

Henderson EN. An Inertial Measurement System for Hand and Finger Tracking. [Internet] [Thesis]. Boise State University; 2011. [cited 2021 Feb 27]. Available from: https://scholarworks.boisestate.edu/td/233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Henderson EN. An Inertial Measurement System for Hand and Finger Tracking. [Thesis]. Boise State University; 2011. Available from: https://scholarworks.boisestate.edu/td/233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arkansas

8. Barlow, Matthew. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.

Degree: MSEE, 2012, University of Arkansas

URL: https://scholarworks.uark.edu/etd/362

► This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1… (more)

Subjects/Keywords: Applied sciences; ASIC; SRAM; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Barlow, M. (2012). Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/362

Chicago Manual of Style (16^th Edition):

Barlow, Matthew. “Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.” 2012. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/362.

MLA Handbook (7^th Edition):

Barlow, Matthew. “Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.” 2012. Web. 27 Feb 2021.

Vancouver:

Barlow M. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. [Internet] [Masters thesis]. University of Arkansas; 2012. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/362.

Council of Science Editors:

Barlow M. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. [Masters Thesis]. University of Arkansas; 2012. Available from: https://scholarworks.uark.edu/etd/362

University of Tennessee – Knoxville

9. Fandrich, Cory Lynn. An On-Chip Transformer-Based Digital Isolator System.

Degree: MS, Electrical Engineering, 2013, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/2602

► An on-chip transformer-based digital isolator has been designed, fabricated, and tested. This isolation technique is designed to function between a low voltage microcontroller and… (more)

Subjects/Keywords: Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Fandrich, C. L. (2013). An On-Chip Transformer-Based Digital Isolator System. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/2602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Fandrich, Cory Lynn. “An On-Chip Transformer-Based Digital Isolator System.” 2013. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/2602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Fandrich, Cory Lynn. “An On-Chip Transformer-Based Digital Isolator System.” 2013. Web. 27 Feb 2021.

Vancouver:

Fandrich CL. An On-Chip Transformer-Based Digital Isolator System. [Internet] [Thesis]. University of Tennessee – Knoxville; 2013. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/2602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fandrich CL. An On-Chip Transformer-Based Digital Isolator System. [Thesis]. University of Tennessee – Knoxville; 2013. Available from: https://trace.tennessee.edu/utk_gradthes/2602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Michigan Technological University

10. Zhao, Xueqian. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.

Degree: PhD, Department of Electrical and Computer Engineering, 2018, Michigan Technological University

URL: https://digitalcommons.mtu.edu/etdr/637

► To evaluate and verify the functional correction and reliability of circuit designs, circuit components (e.g. resistors, capacitors, etc) need to be accurately modeled (e.g.… (more)

▼ To evaluate and verify the functional correction and reliability of circuit designs, circuit components (e.g. resistors, capacitors, etc) need to be accurately modeled (e.g. parasitic extraction) and circuit performance requires precise analysis (e.g. simulation and verification). As the technology scaling of nowadays integrated circuits enters nano-scale regime, the traditional flow of circuit designs becomes increasingly challenging due to the rapid growth of circuit complexity brought by more than billions on-chip components. To this end, during the past decades, endless effort has been made to increase the design efficiency via various directions that include but not limited to exploration of advanced algorithms, leveraging the benefits of multi-core/many-core heterogeneous computation platforms. For full chip parasitic extraction, we propose GPU-friendly data structures and single-instruction-multiple-data (SIMD) parallel algorithm flows to facilitate the FMM-based 3-D capacitance extraction on GPU. Effective GPU performance modeling methods are also proposed to properly balance the workload of each critical kernel in our FMMGpu implementation, by taking advantage of the GPU's concurrent kernel execution technique. Our experimental results show that FMMGpu brings 22X to 30X speedups in capacitance extractions for various test cases. For circuit simulations, based on recent graph sparsification research, we propose a circuit-oriented general-purpose support-circuit preconditioning (GPSCP) approach to improve the matrix solving time and reduce the memory consumption during SPICE-accurate integrated circuit simulations. Additionally, a performance model-guided graph sparsification approach is proposed to facilitate automatically building a near-optimal preconditioner. Our experimental results for a variety of large-scale integrated circuit designs show that the proposed technique can achieve up to 18X runtime speedups and 7X memory reduction in DC and transient Simulations. Besides accelerating the analysis by effective preconditioners, we also explore a scalable power grid reduction method for reducing large-scale flip-chip power grids based on recent spectral graph sparsification techniques. In our work, Schur complement and spectral graph sparsification methods are combined to reduce the original large power grid into a much smaller grid while keeping affordable grid density for fast analysis. Extensive experimental results show that our method can scale linearly with power grid sizes and efficiently reduce industrial power grids sizes by 20X without loss of much accuracy in both DC and transient analysis. Advisors/Committee Members: Zhuo Feng.

Subjects/Keywords: VLSI; SIMULATION; PRECONDITIONER; GPU; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Zhao, X. (2018). FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. (Doctoral Dissertation). Michigan Technological University. Retrieved from https://digitalcommons.mtu.edu/etdr/637

Chicago Manual of Style (16^th Edition):

Zhao, Xueqian. “FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.” 2018. Doctoral Dissertation, Michigan Technological University. Accessed February 27, 2021. https://digitalcommons.mtu.edu/etdr/637.

MLA Handbook (7^th Edition):

Zhao, Xueqian. “FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.” 2018. Web. 27 Feb 2021.

Vancouver:

Zhao X. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. [Internet] [Doctoral dissertation]. Michigan Technological University; 2018. [cited 2021 Feb 27]. Available from: https://digitalcommons.mtu.edu/etdr/637.

Council of Science Editors:

Zhao X. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. [Doctoral Dissertation]. Michigan Technological University; 2018. Available from: https://digitalcommons.mtu.edu/etdr/637

Cal Poly

11. YU, RUN BIN. Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz.

Degree: MS, Electrical Engineering, 2016, Cal Poly

URL: https://digitalcommons.calpoly.edu/theses/1685 ; 10.15368/theses.2016.164

► The clock signal is considered as the “heartbeat” of a digital system yet jitter which is a variation on the arrival time of the… (more)

Subjects/Keywords: Jitter reduction; VLSI; Clock; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

YU, R. B. (2016). Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1685 ; 10.15368/theses.2016.164

Chicago Manual of Style (16^th Edition):

YU, RUN BIN. “Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz.” 2016. Masters Thesis, Cal Poly. Accessed February 27, 2021. https://digitalcommons.calpoly.edu/theses/1685 ; 10.15368/theses.2016.164.

MLA Handbook (7^th Edition):

YU, RUN BIN. “Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz.” 2016. Web. 27 Feb 2021.

Vancouver:

YU RB. Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz. [Internet] [Masters thesis]. Cal Poly; 2016. [cited 2021 Feb 27]. Available from: https://digitalcommons.calpoly.edu/theses/1685 ; 10.15368/theses.2016.164.

Council of Science Editors:

YU RB. Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz. [Masters Thesis]. Cal Poly; 2016. Available from: https://digitalcommons.calpoly.edu/theses/1685 ; 10.15368/theses.2016.164

University of Tennessee – Knoxville

12. Daffron, Christopher Paul. DANNA A Neuromorphic Computing VLSI Chip.

Degree: MS, Computer Engineering, 2015, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/3467

► Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly… (more)

Subjects/Keywords: VLSI; ASIC; Spiking Neural Networks; FPGA; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Daffron, C. P. (2015). DANNA A Neuromorphic Computing VLSI Chip. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/3467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Daffron, Christopher Paul. “DANNA A Neuromorphic Computing VLSI Chip.” 2015. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/3467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Daffron, Christopher Paul. “DANNA A Neuromorphic Computing VLSI Chip.” 2015. Web. 27 Feb 2021.

Vancouver:

Daffron CP. DANNA A Neuromorphic Computing VLSI Chip. [Internet] [Thesis]. University of Tennessee – Knoxville; 2015. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/3467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Daffron CP. DANNA A Neuromorphic Computing VLSI Chip. [Thesis]. University of Tennessee – Knoxville; 2015. Available from: https://trace.tennessee.edu/utk_gradthes/3467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Tennessee – Knoxville

13. Yang, Depeng. Turbo Bayesian Compressed Sensing.

Degree: 2011, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_graddiss/1145

► Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist… (more)

Subjects/Keywords: Compressed Sensing; Hardware Implementation; FPGA; GPU; Signal Processing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Yang, D. (2011). Turbo Bayesian Compressed Sensing. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/1145

Chicago Manual of Style (16^th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_graddiss/1145.

MLA Handbook (7^th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Web. 27 Feb 2021.

Vancouver:

Yang D. Turbo Bayesian Compressed Sensing. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2011. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_graddiss/1145.

Council of Science Editors:

Yang D. Turbo Bayesian Compressed Sensing. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_graddiss/1145

14. Merchant, Murtaza. Testing and Validation of a Prototype Gpgpu Design for FPGAs.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

URL: https://scholarworks.umass.edu/theses/1012

► Due to their suitability for highly parallel and pipelined computation, field programmable gate arrays (FPGAs) and general-purpose graphics processing units (GPGPUs) have emerged as… (more)

Subjects/Keywords: GPGPU; FPGA; hardware acceleration; CUDA compatible; scalable; flexible; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Merchant, M. (2013). Testing and Validation of a Prototype Gpgpu Design for FPGAs. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1012

Chicago Manual of Style (16^th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Masters Thesis, University of Massachusetts. Accessed February 27, 2021. https://scholarworks.umass.edu/theses/1012.

MLA Handbook (7^th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Web. 27 Feb 2021.

Vancouver:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2021 Feb 27]. Available from: https://scholarworks.umass.edu/theses/1012.

Council of Science Editors:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1012

University of Arkansas

15. Mize, Nicholas Renoudet. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.

Degree: MSCmpE, 2019, University of Arkansas

URL: https://scholarworks.uark.edu/etd/3168

► As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away… (more)

Subjects/Keywords: Asynchronous; Circuit; Digital; MTNCL; Synthesis; VHDL; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Mize, N. R. (2019). Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3168

Chicago Manual of Style (16^th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/3168.

MLA Handbook (7^th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Web. 27 Feb 2021.

Vancouver:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/3168.

Council of Science Editors:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3168

University of Kentucky

16. Munoz-Coreas, Edgard. RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS.

Degree: 2020, University of Kentucky

URL: https://uknowledge.uky.edu/ece_etds/157

► Quantum computers offer the potential to extend our abilities to tackle computational problems in fields such as number theory, encryption, search and scientific computation. Up… (more)

▼ Quantum computers offer the potential to extend our abilities to tackle computational problems in fields such as number theory, encryption, search and scientific computation. Up to a superpolynomial speedup has been reported for quantum algorithms in these areas. Motivated by the promise of faster computations, the development of quantum machines has caught the attention of both academics and industry researchers. Quantum machines are now at sizes where implementations of quantum algorithms or their components are now becoming possible. In order to implement quantum algorithms on quantum machines, resource efficient circuits and functional blocks must be designed. In this work, we propose quantum circuits for Galois and integer arithmetic. These quantum circuits are necessary building blocks to realize quantum algorithms. The design of resource efficient quantum circuits requires the designer takes into account the gate cost, quantum bit (qubit) cost, depth and garbage outputs of a quantum circuit. Existing quantum machines do not have many qubits meaning that circuits with high qubit cost cannot be implemented. In addition, quantum circuits are more prone to errors and garbage output removal adds to overall cost. As more gates are used, a quantum circuit sees an increased rate of failure. Failures and error rates can be countered by using quantum error correcting codes and fault tolerant implementations of universal gate sets (such as Clifford+T gates). However, Clifford+T gates are costly to implement with the T gate being significantly more costly than the Clifford gates. As a result, designers working with Clifford+T gates seek to minimize the number of T gates (T-count) and the depth of T gates (T-depth). In this work, we propose quantum circuits for Galois and integer arithmetic with lower T-count, T-depth and qubit cost than existing work. This work presents novel quantum circuits for squaring and exponentiation over binary extension fields (Galois fields of form GF(2 m )). The proposed circuits are shown to have lower depth, qubit and gate cost to existing work. We also present quantum circuits for the core operations of multiplication and division which enjoy lower T-count, T-depth and qubit costs compared to existing work. This work also illustrates the design of a T-count and qubit cost efficient design for the square root. This work concludes with an illustration of how the arithmetic circuits can be combined into a functional block to implement quantum image processing algorithms.

Subjects/Keywords: Quantum computation; Arithmetic circuits; Emerging computer architectures; Electrical and Electronics; Hardware Systems; Quantum Physics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Munoz-Coreas, E. (2020). RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS. (Doctoral Dissertation). University of Kentucky. Retrieved from https://uknowledge.uky.edu/ece_etds/157

Chicago Manual of Style (16^th Edition):

Munoz-Coreas, Edgard. “RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS.” 2020. Doctoral Dissertation, University of Kentucky. Accessed February 27, 2021. https://uknowledge.uky.edu/ece_etds/157.

MLA Handbook (7^th Edition):

Munoz-Coreas, Edgard. “RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS.” 2020. Web. 27 Feb 2021.

Vancouver:

Munoz-Coreas E. RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS. [Internet] [Doctoral dissertation]. University of Kentucky; 2020. [cited 2021 Feb 27]. Available from: https://uknowledge.uky.edu/ece_etds/157.

Council of Science Editors:

Munoz-Coreas E. RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS. [Doctoral Dissertation]. University of Kentucky; 2020. Available from: https://uknowledge.uky.edu/ece_etds/157

University of Arkansas

17. Munasib, Sharthak. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.

Degree: MSEE, 2017, University of Arkansas

URL: https://scholarworks.uark.edu/etd/1875

► Proper short-circuit protection in dc distribution systems has provided an austere challenge to researchers as the development of commercially-viable equipment providing fast operation, coordination… (more)

Subjects/Keywords: Applied sciences; Systems and Communications; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Munasib, S. (2017). Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1875

Chicago Manual of Style (16^th Edition):

Munasib, Sharthak. “Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.” 2017. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/1875.

MLA Handbook (7^th Edition):

Munasib, Sharthak. “Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.” 2017. Web. 27 Feb 2021.

Vancouver:

Munasib S. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. [Internet] [Masters thesis]. University of Arkansas; 2017. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/1875.

Council of Science Editors:

Munasib S. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. [Masters Thesis]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1875

18. Phanibhushana, Bharath. An Interconnection Network Topology Generation Scheme for Multicore Systems.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

URL: https://scholarworks.umass.edu/theses/1146

► Multi-Processor System on Chip (MPSoC) consisting of multiple processing cores connected via a Network on Chip (NoC) has gained prominence over the last decade.… (more)

Subjects/Keywords: NoC; Multicore; SoC; Realtime systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Phanibhushana, B. (2013). An Interconnection Network Topology Generation Scheme for Multicore Systems. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1146

Chicago Manual of Style (16^th Edition):

Phanibhushana, Bharath. “An Interconnection Network Topology Generation Scheme for Multicore Systems.” 2013. Masters Thesis, University of Massachusetts. Accessed February 27, 2021. https://scholarworks.umass.edu/theses/1146.

MLA Handbook (7^th Edition):

Phanibhushana, Bharath. “An Interconnection Network Topology Generation Scheme for Multicore Systems.” 2013. Web. 27 Feb 2021.

Vancouver:

Phanibhushana B. An Interconnection Network Topology Generation Scheme for Multicore Systems. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2021 Feb 27]. Available from: https://scholarworks.umass.edu/theses/1146.

Council of Science Editors:

Phanibhushana B. An Interconnection Network Topology Generation Scheme for Multicore Systems. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1146

University of Arkansas

19. Mead, Joshua. Prevention of Drone Jamming Using Hardware Sandboxing.

Degree: MSCmpE, 2016, University of Arkansas

URL: https://scholarworks.uark.edu/etd/2643

► In this thesis, we concern ourselves with the security of drone systems under jamming-based attacks. We explore a relatively new concept we previously devised,… (more)

Subjects/Keywords: Drone Security; FPGA Development; Hardware Sandboxing; RF Jamming; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Mead, J. (2016). Prevention of Drone Jamming Using Hardware Sandboxing. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2643

Chicago Manual of Style (16^th Edition):

Mead, Joshua. “Prevention of Drone Jamming Using Hardware Sandboxing.” 2016. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/2643.

MLA Handbook (7^th Edition):

Mead, Joshua. “Prevention of Drone Jamming Using Hardware Sandboxing.” 2016. Web. 27 Feb 2021.

Vancouver:

Mead J. Prevention of Drone Jamming Using Hardware Sandboxing. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/2643.

Council of Science Editors:

Mead J. Prevention of Drone Jamming Using Hardware Sandboxing. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/2643

Northeastern University

20. Agarwal, Akash. Integrating instruction set simulator into a system level design environment.

Degree: MS, Department of Electrical and Computer Engineering, 2013, Northeastern University

URL: http://hdl.handle.net/2047/d20003043

► Design of Embedded System, which today comprises of both Hardware and Software (HW/SW) has become complex with the advancement of technology and with the ever… (more)

▼ Design of Embedded System, which today comprises of both Hardware and Software (HW/SW) has become complex with the advancement of technology and with the ever increasing demand for complex and low cost features. Systems developed today should arrive must arrive at market quickly and at the same time meet the constraints of power, memory and cost.; As one solution, designers are moving to higher level of abstraction or System Level design which covers both Hardware (HW) and Software (SW). This is realized through a model based design methodology which utilizes virtual environment for early validation of the specification and at the same time also provides for verification of functionality of the system. It also augments the design process by providing a pre-silicon prototype of the final physical system for software development and allows for and helps in performance tuning of these complex systems. Furthermore, virtual platforms can also serve as inputs to Register Transfer Level (RTL) and software component synthesis for the system.; Modern Embedded Systems are heterogeneous as they have both a programmable processor core and dedicated hardware units that is the virtual platform which simulates the system. Instruction Set Simulator (ISS) provide a simulation environment for programmable processors and are utilized in a virtual environment to validate software running on programmable processor. Today there are many stand-alone ISS which are available in the open source community, however they are not integrated with a system design tool suite making it impossible to utilize them to validate SW. Manual effort to individually add them to a system-level design tool suite requires work for each addition and is prone to error.; In this thesis we focus on providing a generalized guidelines for integrating ISS's to a system-level design tool. The guidelines are developed in order to simplify the process of adding an ISS to a system level design tool. The developed guidelines takes into account the requirements to model communication between processor and other computing components in an System on Chip (SoC), and also provide to interrupt based synchronization capability between components. It also takes into account the requirements to reduce simulation time which is a major bottleneck and which limits the use of system simulation. The guidelines developed also take into account different types of ISS, one which simulate only the processor core and the other ones which simulate both the core and peripheral of the processor together.; We validate the generalized guidelines by integrating a Blackfin family processor ISS available under GNU tool chain with a system level design tool System on Chip Environment (SCE), which support modeling, synthesis and validation of Heterogeneous Embedded Systems.

Subjects/Keywords: ESL; ISS; SpecC; Electrical and Computer Engineering; Engineering; VLSI and circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Agarwal, A. (2013). Integrating instruction set simulator into a system level design environment. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20003043

Chicago Manual of Style (16^th Edition):

Agarwal, Akash. “Integrating instruction set simulator into a system level design environment.” 2013. Masters Thesis, Northeastern University. Accessed February 27, 2021. http://hdl.handle.net/2047/d20003043.

MLA Handbook (7^th Edition):

Agarwal, Akash. “Integrating instruction set simulator into a system level design environment.” 2013. Web. 27 Feb 2021.

Vancouver:

Agarwal A. Integrating instruction set simulator into a system level design environment. [Internet] [Masters thesis]. Northeastern University; 2013. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2047/d20003043.

Council of Science Editors:

Agarwal A. Integrating instruction set simulator into a system level design environment. [Masters Thesis]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20003043

21. Hilgers, Brandon. SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies.

Degree: MS, Electrical Engineering, 2015, Cal Poly

URL: https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125

► This research details the design of an SRAM compiler for quickly creating SRAM blocks for Cal Poly integrated circuit (IC) designs. The compiler generates… (more)

▼ This research details the design of an SRAM compiler for quickly creating SRAM blocks for Cal Poly integrated circuit (IC) designs. The compiler generates memory for two process technologies (IBM 180nm cmrf7sf and ON Semiconductor 600nm SCMOS) and requires a minimum number of specifications from the user for ease of use, while still offering the option to customize the performance for speed or area of the generated SRAM cell. By automatically creating SRAM arrays, the compiler saves the user time from having to layout and test memory and allows for quick updates and changes to a design. Memory compilers with various features already exist, but they have several disadvantages. Most memory compilers are expensive, usually only generate memory for one process technology, and don’t allow for user-defined custom SRAM cell optimizations. This free design makes it available for students and institutions that would not be able to afford an industry-made compiler. A compiler that offers multiple process technologies allows for more freedom to design in other processes if needed or desired. An attempt was made for this design to be modular for different process technologies so new processes could be added with ease; however, different process technologies have different DRC rules, making that option very difficult to attain. A customizable SRAM cell based on transistor sizing ratios allows for optimized designs in speed, area, or power, and for academic research. Even for an experienced designer, the layout of a single SRAM cell (1 bit) can take an hour. This command-line-based tool can draw a 1Kb SRAM block in seconds and a 1Mb SRAM block in about 15 minutes. In addition, this compiler also adds a manually laid out precharge circuit to each of the SRAM columns for an enhanced read operation by ensuring the bit lines have valid logic output values. Finally, an analysis on SRAM cell stability is done for creating a robust cell as the default design for the compiler. The default cell design is verified for stability during read and write operations, and has an area of 14.067 µm² for the cmrf7sf process and 246.42 µm² for the SCMOS process. All factors considered, this SRAM compiler design overcomes several of the drawbacks of other existing memory compilers. Advisors/Committee Members: Tina Smilkstein.

Subjects/Keywords: SRAM; Compiler; Memory; Automated; Layout; VLSI and Circuits, Embedded and Hardware Systems

13 more images…

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APA (6^th Edition):

Hilgers, B. (2015). SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125

Chicago Manual of Style (16^th Edition):

Hilgers, Brandon. “SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies.” 2015. Masters Thesis, Cal Poly. Accessed February 27, 2021. https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125.

MLA Handbook (7^th Edition):

Hilgers, Brandon. “SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies.” 2015. Web. 27 Feb 2021.

Vancouver:

Hilgers B. SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies. [Internet] [Masters thesis]. Cal Poly; 2015. [cited 2021 Feb 27]. Available from: https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125.

Council of Science Editors:

Hilgers B. SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies. [Masters Thesis]. Cal Poly; 2015. Available from: https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125

Boise State University

22. Pook, Michael. A Small Acoustic Goniometer for General Purpose Research.

Degree: 2015, Boise State University

URL: https://scholarworks.boisestate.edu/td/1052

► Understanding acoustic events and monitoring their occurrence is a useful aspect of many research projects. In particular, acoustic goniometry allows researchers to determine the source… (more)

Subjects/Keywords: Acoustic Goniometer; infrasound; general purpose; real-time; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Pook, M. (2015). A Small Acoustic Goniometer for General Purpose Research. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/1052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pook, Michael. “A Small Acoustic Goniometer for General Purpose Research.” 2015. Thesis, Boise State University. Accessed February 27, 2021. https://scholarworks.boisestate.edu/td/1052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pook, Michael. “A Small Acoustic Goniometer for General Purpose Research.” 2015. Web. 27 Feb 2021.

Vancouver:

Pook M. A Small Acoustic Goniometer for General Purpose Research. [Internet] [Thesis]. Boise State University; 2015. [cited 2021 Feb 27]. Available from: https://scholarworks.boisestate.edu/td/1052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pook M. A Small Acoustic Goniometer for General Purpose Research. [Thesis]. Boise State University; 2015. Available from: https://scholarworks.boisestate.edu/td/1052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arkansas

23. Bhuyan, Shaila Amin. Design of a High Performance Silicon Carbide CMOS Operational Amplifier.

Degree: MSEE, 2014, University of Arkansas

URL: https://scholarworks.uark.edu/etd/2042

► This thesis presents the design, simulation, layout and test results of a silicon carbide (SiC) CMOS two-stage operational amplifier (op amp) with NMOS input… (more)

Subjects/Keywords: Electronic Devices and Semiconductor Manufacturing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Bhuyan, S. A. (2014). Design of a High Performance Silicon Carbide CMOS Operational Amplifier. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2042

Chicago Manual of Style (16^th Edition):

Bhuyan, Shaila Amin. “Design of a High Performance Silicon Carbide CMOS Operational Amplifier.” 2014. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/2042.

MLA Handbook (7^th Edition):

Bhuyan, Shaila Amin. “Design of a High Performance Silicon Carbide CMOS Operational Amplifier.” 2014. Web. 27 Feb 2021.

Vancouver:

Bhuyan SA. Design of a High Performance Silicon Carbide CMOS Operational Amplifier. [Internet] [Masters thesis]. University of Arkansas; 2014. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/2042.

Council of Science Editors:

Bhuyan SA. Design of a High Performance Silicon Carbide CMOS Operational Amplifier. [Masters Thesis]. University of Arkansas; 2014. Available from: https://scholarworks.uark.edu/etd/2042

University of Arkansas

24. Williams, Ethan Storm. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.

Degree: MSEE, 2016, University of Arkansas

URL: https://scholarworks.uark.edu/etd/1503

► A new assistive technology switch for people with disabilities was developed utilizing an Inertial Measurement Unit (IMU) as the sensor technology. The hardware can… (more)

Subjects/Keywords: Applied sciences; Assistive technology; Inertial measurement unit; Biomedical; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Williams, E. S. (2016). Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1503

Chicago Manual of Style (16^th Edition):

Williams, Ethan Storm. “Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.” 2016. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/1503.

MLA Handbook (7^th Edition):

Williams, Ethan Storm. “Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.” 2016. Web. 27 Feb 2021.

Vancouver:

Williams ES. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/1503.

Council of Science Editors:

Williams ES. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1503

University of Tennessee – Knoxville

25. Watson, Trevor. An Analog CMOS Particle Filter.

Degree: MS, Electrical Engineering, 2017, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/4962

► Particle filters are used in a variety of image processing and machine learning applications. Their main use in these applications is to gather information… (more)

Subjects/Keywords: Analog; CMOS; Machine Learning; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Watson, T. (2017). An Analog CMOS Particle Filter. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/4962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Watson, Trevor. “An Analog CMOS Particle Filter.” 2017. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/4962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Watson, Trevor. “An Analog CMOS Particle Filter.” 2017. Web. 27 Feb 2021.

Vancouver:

Watson T. An Analog CMOS Particle Filter. [Internet] [Thesis]. University of Tennessee – Knoxville; 2017. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/4962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Watson T. An Analog CMOS Particle Filter. [Thesis]. University of Tennessee – Knoxville; 2017. Available from: https://trace.tennessee.edu/utk_gradthes/4962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Tennessee – Knoxville

26. Brantley, Jeremy. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.

Degree: MS, Electrical Engineering, 2012, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/1306

► Testing circuits is a hands-on, time intensive process; it is also one of the most important steps in a design cycle. The most well… (more)

Subjects/Keywords: Labview; Characterization; Model Extraction; Automation; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Brantley, J. (2012). Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/1306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Brantley, Jeremy. “Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.” 2012. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/1306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Brantley, Jeremy. “Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.” 2012. Web. 27 Feb 2021.

Vancouver:

Brantley J. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. [Internet] [Thesis]. University of Tennessee – Knoxville; 2012. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/1306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Brantley J. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. [Thesis]. University of Tennessee – Knoxville; 2012. Available from: https://trace.tennessee.edu/utk_gradthes/1306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Kentucky

27. Jacobs, Zachary A. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.

Degree: 2013, University of Kentucky

URL: https://uknowledge.uky.edu/ece_etds/16

► The CubeLab is a new payload standard that greatly improves access to the International Space Station (ISS) for small, rapid turn-around microgravity experiments. CubeLabs are… (more)

Subjects/Keywords: CubeSat; CubeLab; NanoRacks; Plug and Play; Distributed Computing; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Jacobs, Z. A. (2013). PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. (Masters Thesis). University of Kentucky. Retrieved from https://uknowledge.uky.edu/ece_etds/16

Chicago Manual of Style (16^th Edition):

Jacobs, Zachary A. “PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.” 2013. Masters Thesis, University of Kentucky. Accessed February 27, 2021. https://uknowledge.uky.edu/ece_etds/16.

MLA Handbook (7^th Edition):

Jacobs, Zachary A. “PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.” 2013. Web. 27 Feb 2021.

Vancouver:

Jacobs ZA. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2021 Feb 27]. Available from: https://uknowledge.uky.edu/ece_etds/16.

Council of Science Editors:

Jacobs ZA. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. [Masters Thesis]. University of Kentucky; 2013. Available from: https://uknowledge.uky.edu/ece_etds/16

University of Kentucky

28. Zhang, Xiaowei. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.

Degree: 2015, University of Kentucky

URL: https://uknowledge.uky.edu/ece_etds/75

► SRAM is a significant component in high speed computer design, which serves mainly as high speed storage elements like register files in microprocessors, or the… (more)

Subjects/Keywords: SRAM; Timing Parameters; SPICE; Liberty File; DFF; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhang, X. (2015). A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. (Masters Thesis). University of Kentucky. Retrieved from https://uknowledge.uky.edu/ece_etds/75

Chicago Manual of Style (16^th Edition):

Zhang, Xiaowei. “A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.” 2015. Masters Thesis, University of Kentucky. Accessed February 27, 2021. https://uknowledge.uky.edu/ece_etds/75.

MLA Handbook (7^th Edition):

Zhang, Xiaowei. “A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.” 2015. Web. 27 Feb 2021.

Vancouver:

Zhang X. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. [Internet] [Masters thesis]. University of Kentucky; 2015. [cited 2021 Feb 27]. Available from: https://uknowledge.uky.edu/ece_etds/75.

Council of Science Editors:

Zhang X. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. [Masters Thesis]. University of Kentucky; 2015. Available from: https://uknowledge.uky.edu/ece_etds/75

29. Vyas, Shruti S. Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories.

Degree: MS, Electrical & Computer Engineering, 2011, University of Massachusetts

URL: https://scholarworks.umass.edu/theses/548

► NAND flash memories are popular due to their density and lower cost. However, due to serial access, NAND flash memories have low read and write… (more)

Subjects/Keywords: Nand; Flash; Search; data deduplication; MISR; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Vyas, S. S. (2011). Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/548

Chicago Manual of Style (16^th Edition):

Vyas, Shruti S. “Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories.” 2011. Masters Thesis, University of Massachusetts. Accessed February 27, 2021. https://scholarworks.umass.edu/theses/548.

MLA Handbook (7^th Edition):

Vyas, Shruti S. “Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories.” 2011. Web. 27 Feb 2021.

Vancouver:

Vyas SS. Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories. [Internet] [Masters thesis]. University of Massachusetts; 2011. [cited 2021 Feb 27]. Available from: https://scholarworks.umass.edu/theses/548.

Council of Science Editors:

Vyas SS. Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories. [Masters Thesis]. University of Massachusetts; 2011. Available from: https://scholarworks.umass.edu/theses/548

Portland State University

30. Chandorkar, Chaitrali Santosh. Data Driven Feed Forward Adaptive Testing.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2013, Portland State University

URL: https://pdxscholar.library.pdx.edu/open_access_etds/1049

► Test cost is a critical component in the overall cost of the product. Test cost varies in direct proportion with test time. This thesis… (more)

Subjects/Keywords: Integrated circuits – Testing; Integrated circuits – Quality control; Production management; Electrical and Computer Engineering; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chandorkar, C. S. (2013). Data Driven Feed Forward Adaptive Testing. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/1049

Chicago Manual of Style (16^th Edition):

Chandorkar, Chaitrali Santosh. “Data Driven Feed Forward Adaptive Testing.” 2013. Masters Thesis, Portland State University. Accessed February 27, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/1049.

MLA Handbook (7^th Edition):

Chandorkar, Chaitrali Santosh. “Data Driven Feed Forward Adaptive Testing.” 2013. Web. 27 Feb 2021.

Vancouver:

Chandorkar CS. Data Driven Feed Forward Adaptive Testing. [Internet] [Masters thesis]. Portland State University; 2013. [cited 2021 Feb 27]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/1049.

Council of Science Editors:

Chandorkar CS. Data Driven Feed Forward Adaptive Testing. [Masters Thesis]. Portland State University; 2013. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/1049

Open Access Theses and Dissertations