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You searched for subject:(VLSI AND Circuits Embedded AND Hardware Systems). Showing records 1 – 30 of 226 total matches.

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Cal Poly

1. Zaveri, Jainish K. Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology.

Degree: MS, Electrical Engineering, 2018, Cal Poly

  Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zaveri, J. K. (2018). Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1940 ; 10.15368/theses.2018.118

Chicago Manual of Style (16th Edition):

Zaveri, Jainish K. “Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology.” 2018. Masters Thesis, Cal Poly. Accessed February 27, 2021. https://digitalcommons.calpoly.edu/theses/1940 ; 10.15368/theses.2018.118.

MLA Handbook (7th Edition):

Zaveri, Jainish K. “Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology.” 2018. Web. 27 Feb 2021.

Vancouver:

Zaveri JK. Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology. [Internet] [Masters thesis]. Cal Poly; 2018. [cited 2021 Feb 27]. Available from: https://digitalcommons.calpoly.edu/theses/1940 ; 10.15368/theses.2018.118.

Council of Science Editors:

Zaveri JK. Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology. [Masters Thesis]. Cal Poly; 2018. Available from: https://digitalcommons.calpoly.edu/theses/1940 ; 10.15368/theses.2018.118


University of Tennessee – Knoxville

2. Kilambi, Supriya. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.

Degree: MS, Computer Engineering, 2011, University of Tennessee – Knoxville

 This thesis presents the low power design of a 916MHz Gilbert cell mixer and a Class-A power amplifier for the Bioluminescent Bioreporter Integrated Circuit (BBIC)… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Kilambi, S. (2011). Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Web. 27 Feb 2021.

Vancouver:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

3. Tham, Kevin Vun Kiat. PVT Compensation for Single-Slope Measurement Systems.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

  A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Tham, K. V. K. (2011). PVT Compensation for Single-Slope Measurement Systems. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Web. 27 Feb 2021.

Vancouver:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

4. Mudhasani, Shanthan. GPU-based Implementation of the Variational Path Integral Method.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

  Any system in the world constitutes particles like electrons. To analyze the behaviors of these systems the behavior of these particles must be predicted.… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Mudhasani, S. (2011). GPU-based Implementation of the Variational Path Integral Method. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Web. 27 Feb 2021.

Vancouver:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Commonwealth University

5. Khairullah, Shawkat Sabah. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.

Degree: PhD, Electrical & Computer Engineering, 2018, Virginia Commonwealth University

  Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes.… (more)

Subjects/Keywords: Computer and Systems Architecture; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Khairullah, S. S. (2018). Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. (Doctoral Dissertation). Virginia Commonwealth University. Retrieved from https://doi.org/10.25772/7QKK-M119 ; https://scholarscompass.vcu.edu/etd/5671

Chicago Manual of Style (16th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Doctoral Dissertation, Virginia Commonwealth University. Accessed February 27, 2021. https://doi.org/10.25772/7QKK-M119 ; https://scholarscompass.vcu.edu/etd/5671.

MLA Handbook (7th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Web. 27 Feb 2021.

Vancouver:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Internet] [Doctoral dissertation]. Virginia Commonwealth University; 2018. [cited 2021 Feb 27]. Available from: https://doi.org/10.25772/7QKK-M119 ; https://scholarscompass.vcu.edu/etd/5671.

Council of Science Editors:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Doctoral Dissertation]. Virginia Commonwealth University; 2018. Available from: https://doi.org/10.25772/7QKK-M119 ; https://scholarscompass.vcu.edu/etd/5671


University of Arkansas

6. McGeehan, Brendan. Hardware IP Classification through Weighted Characteristics.

Degree: MSCmpE, 2019, University of Arkansas

  Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For… (more)

Subjects/Keywords: Classifcation; Hardware; Trojans; Hardware Systems; Information Security; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

McGeehan, B. (2019). Hardware IP Classification through Weighted Characteristics. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3166

Chicago Manual of Style (16th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/3166.

MLA Handbook (7th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Web. 27 Feb 2021.

Vancouver:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/3166.

Council of Science Editors:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3166


Boise State University

7. Henderson, Edward Nelson. An Inertial Measurement System for Hand and Finger Tracking.

Degree: 2011, Boise State University

 The primary Human Computer Interfaces (HCI) today are the keyboard and mouse. These interfaces do not facilitate a fluid flow of thought and intent from… (more)

Subjects/Keywords: inertial; glove; IMU; algorithm; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Henderson, E. N. (2011). An Inertial Measurement System for Hand and Finger Tracking. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Henderson, Edward Nelson. “An Inertial Measurement System for Hand and Finger Tracking.” 2011. Thesis, Boise State University. Accessed February 27, 2021. https://scholarworks.boisestate.edu/td/233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Henderson, Edward Nelson. “An Inertial Measurement System for Hand and Finger Tracking.” 2011. Web. 27 Feb 2021.

Vancouver:

Henderson EN. An Inertial Measurement System for Hand and Finger Tracking. [Internet] [Thesis]. Boise State University; 2011. [cited 2021 Feb 27]. Available from: https://scholarworks.boisestate.edu/td/233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Henderson EN. An Inertial Measurement System for Hand and Finger Tracking. [Thesis]. Boise State University; 2011. Available from: https://scholarworks.boisestate.edu/td/233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

8. Barlow, Matthew. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.

Degree: MSEE, 2012, University of Arkansas

  This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1… (more)

Subjects/Keywords: Applied sciences; ASIC; SRAM; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Barlow, M. (2012). Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/362

Chicago Manual of Style (16th Edition):

Barlow, Matthew. “Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.” 2012. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/362.

MLA Handbook (7th Edition):

Barlow, Matthew. “Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.” 2012. Web. 27 Feb 2021.

Vancouver:

Barlow M. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. [Internet] [Masters thesis]. University of Arkansas; 2012. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/362.

Council of Science Editors:

Barlow M. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. [Masters Thesis]. University of Arkansas; 2012. Available from: https://scholarworks.uark.edu/etd/362


University of Tennessee – Knoxville

9. Fandrich, Cory Lynn. An On-Chip Transformer-Based Digital Isolator System.

Degree: MS, Electrical Engineering, 2013, University of Tennessee – Knoxville

  An on-chip transformer-based digital isolator has been designed, fabricated, and tested. This isolation technique is designed to function between a low voltage microcontroller and… (more)

Subjects/Keywords: Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Fandrich, C. L. (2013). An On-Chip Transformer-Based Digital Isolator System. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/2602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fandrich, Cory Lynn. “An On-Chip Transformer-Based Digital Isolator System.” 2013. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/2602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fandrich, Cory Lynn. “An On-Chip Transformer-Based Digital Isolator System.” 2013. Web. 27 Feb 2021.

Vancouver:

Fandrich CL. An On-Chip Transformer-Based Digital Isolator System. [Internet] [Thesis]. University of Tennessee – Knoxville; 2013. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/2602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fandrich CL. An On-Chip Transformer-Based Digital Isolator System. [Thesis]. University of Tennessee – Knoxville; 2013. Available from: https://trace.tennessee.edu/utk_gradthes/2602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Michigan Technological University

10. Zhao, Xueqian. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.

Degree: PhD, Department of Electrical and Computer Engineering, 2018, Michigan Technological University

  To evaluate and verify the functional correction and reliability of circuit designs, circuit components (e.g. resistors, capacitors, etc) need to be accurately modeled (e.g.… (more)

Subjects/Keywords: VLSI; SIMULATION; PRECONDITIONER; GPU; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Zhao, X. (2018). FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. (Doctoral Dissertation). Michigan Technological University. Retrieved from https://digitalcommons.mtu.edu/etdr/637

Chicago Manual of Style (16th Edition):

Zhao, Xueqian. “FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.” 2018. Doctoral Dissertation, Michigan Technological University. Accessed February 27, 2021. https://digitalcommons.mtu.edu/etdr/637.

MLA Handbook (7th Edition):

Zhao, Xueqian. “FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.” 2018. Web. 27 Feb 2021.

Vancouver:

Zhao X. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. [Internet] [Doctoral dissertation]. Michigan Technological University; 2018. [cited 2021 Feb 27]. Available from: https://digitalcommons.mtu.edu/etdr/637.

Council of Science Editors:

Zhao X. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. [Doctoral Dissertation]. Michigan Technological University; 2018. Available from: https://digitalcommons.mtu.edu/etdr/637


Cal Poly

11. YU, RUN BIN. Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz.

Degree: MS, Electrical Engineering, 2016, Cal Poly

  The clock signal is considered as the “heartbeat” of a digital system yet jitter which is a variation on the arrival time of the… (more)

Subjects/Keywords: Jitter reduction; VLSI; Clock; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

YU, R. B. (2016). Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1685 ; 10.15368/theses.2016.164

Chicago Manual of Style (16th Edition):

YU, RUN BIN. “Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz.” 2016. Masters Thesis, Cal Poly. Accessed February 27, 2021. https://digitalcommons.calpoly.edu/theses/1685 ; 10.15368/theses.2016.164.

MLA Handbook (7th Edition):

YU, RUN BIN. “Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz.” 2016. Web. 27 Feb 2021.

Vancouver:

YU RB. Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz. [Internet] [Masters thesis]. Cal Poly; 2016. [cited 2021 Feb 27]. Available from: https://digitalcommons.calpoly.edu/theses/1685 ; 10.15368/theses.2016.164.

Council of Science Editors:

YU RB. Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz. [Masters Thesis]. Cal Poly; 2016. Available from: https://digitalcommons.calpoly.edu/theses/1685 ; 10.15368/theses.2016.164


University of Tennessee – Knoxville

12. Daffron, Christopher Paul. DANNA A Neuromorphic Computing VLSI Chip.

Degree: MS, Computer Engineering, 2015, University of Tennessee – Knoxville

  Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly… (more)

Subjects/Keywords: VLSI; ASIC; Spiking Neural Networks; FPGA; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Daffron, C. P. (2015). DANNA A Neuromorphic Computing VLSI Chip. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/3467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Daffron, Christopher Paul. “DANNA A Neuromorphic Computing VLSI Chip.” 2015. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/3467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Daffron, Christopher Paul. “DANNA A Neuromorphic Computing VLSI Chip.” 2015. Web. 27 Feb 2021.

Vancouver:

Daffron CP. DANNA A Neuromorphic Computing VLSI Chip. [Internet] [Thesis]. University of Tennessee – Knoxville; 2015. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/3467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Daffron CP. DANNA A Neuromorphic Computing VLSI Chip. [Thesis]. University of Tennessee – Knoxville; 2015. Available from: https://trace.tennessee.edu/utk_gradthes/3467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

13. Yang, Depeng. Turbo Bayesian Compressed Sensing.

Degree: 2011, University of Tennessee – Knoxville

 Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist… (more)

Subjects/Keywords: Compressed Sensing; Hardware Implementation; FPGA; GPU; Signal Processing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Yang, D. (2011). Turbo Bayesian Compressed Sensing. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/1145

Chicago Manual of Style (16th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_graddiss/1145.

MLA Handbook (7th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Web. 27 Feb 2021.

Vancouver:

Yang D. Turbo Bayesian Compressed Sensing. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2011. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_graddiss/1145.

Council of Science Editors:

Yang D. Turbo Bayesian Compressed Sensing. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_graddiss/1145

14. Merchant, Murtaza. Testing and Validation of a Prototype Gpgpu Design for FPGAs.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  Due to their suitability for highly parallel and pipelined computation, field programmable gate arrays (FPGAs) and general-purpose graphics processing units (GPGPUs) have emerged as… (more)

Subjects/Keywords: GPGPU; FPGA; hardware acceleration; CUDA compatible; scalable; flexible; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Merchant, M. (2013). Testing and Validation of a Prototype Gpgpu Design for FPGAs. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1012

Chicago Manual of Style (16th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Masters Thesis, University of Massachusetts. Accessed February 27, 2021. https://scholarworks.umass.edu/theses/1012.

MLA Handbook (7th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Web. 27 Feb 2021.

Vancouver:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2021 Feb 27]. Available from: https://scholarworks.umass.edu/theses/1012.

Council of Science Editors:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1012


University of Arkansas

15. Mize, Nicholas Renoudet. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.

Degree: MSCmpE, 2019, University of Arkansas

  As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away… (more)

Subjects/Keywords: Asynchronous; Circuit; Digital; MTNCL; Synthesis; VHDL; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Mize, N. R. (2019). Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3168

Chicago Manual of Style (16th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/3168.

MLA Handbook (7th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Web. 27 Feb 2021.

Vancouver:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/3168.

Council of Science Editors:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3168


University of Kentucky

16. Munoz-Coreas, Edgard. RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS.

Degree: 2020, University of Kentucky

 Quantum computers offer the potential to extend our abilities to tackle computational problems in fields such as number theory, encryption, search and scientific computation. Up… (more)

Subjects/Keywords: Quantum computation; Arithmetic circuits; Emerging computer architectures; Electrical and Electronics; Hardware Systems; Quantum Physics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Munoz-Coreas, E. (2020). RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS. (Doctoral Dissertation). University of Kentucky. Retrieved from https://uknowledge.uky.edu/ece_etds/157

Chicago Manual of Style (16th Edition):

Munoz-Coreas, Edgard. “RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS.” 2020. Doctoral Dissertation, University of Kentucky. Accessed February 27, 2021. https://uknowledge.uky.edu/ece_etds/157.

MLA Handbook (7th Edition):

Munoz-Coreas, Edgard. “RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS.” 2020. Web. 27 Feb 2021.

Vancouver:

Munoz-Coreas E. RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS. [Internet] [Doctoral dissertation]. University of Kentucky; 2020. [cited 2021 Feb 27]. Available from: https://uknowledge.uky.edu/ece_etds/157.

Council of Science Editors:

Munoz-Coreas E. RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS. [Doctoral Dissertation]. University of Kentucky; 2020. Available from: https://uknowledge.uky.edu/ece_etds/157


University of Arkansas

17. Munasib, Sharthak. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.

Degree: MSEE, 2017, University of Arkansas

  Proper short-circuit protection in dc distribution systems has provided an austere challenge to researchers as the development of commercially-viable equipment providing fast operation, coordination… (more)

Subjects/Keywords: Applied sciences; Systems and Communications; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Munasib, S. (2017). Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1875

Chicago Manual of Style (16th Edition):

Munasib, Sharthak. “Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.” 2017. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/1875.

MLA Handbook (7th Edition):

Munasib, Sharthak. “Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.” 2017. Web. 27 Feb 2021.

Vancouver:

Munasib S. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. [Internet] [Masters thesis]. University of Arkansas; 2017. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/1875.

Council of Science Editors:

Munasib S. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. [Masters Thesis]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1875

18. Phanibhushana, Bharath. An Interconnection Network Topology Generation Scheme for Multicore Systems.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  Multi-Processor System on Chip (MPSoC) consisting of multiple processing cores connected via a Network on Chip (NoC) has gained prominence over the last decade.… (more)

Subjects/Keywords: NoC; Multicore; SoC; Realtime systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Phanibhushana, B. (2013). An Interconnection Network Topology Generation Scheme for Multicore Systems. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1146

Chicago Manual of Style (16th Edition):

Phanibhushana, Bharath. “An Interconnection Network Topology Generation Scheme for Multicore Systems.” 2013. Masters Thesis, University of Massachusetts. Accessed February 27, 2021. https://scholarworks.umass.edu/theses/1146.

MLA Handbook (7th Edition):

Phanibhushana, Bharath. “An Interconnection Network Topology Generation Scheme for Multicore Systems.” 2013. Web. 27 Feb 2021.

Vancouver:

Phanibhushana B. An Interconnection Network Topology Generation Scheme for Multicore Systems. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2021 Feb 27]. Available from: https://scholarworks.umass.edu/theses/1146.

Council of Science Editors:

Phanibhushana B. An Interconnection Network Topology Generation Scheme for Multicore Systems. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1146


University of Arkansas

19. Mead, Joshua. Prevention of Drone Jamming Using Hardware Sandboxing.

Degree: MSCmpE, 2016, University of Arkansas

  In this thesis, we concern ourselves with the security of drone systems under jamming-based attacks. We explore a relatively new concept we previously devised,… (more)

Subjects/Keywords: Drone Security; FPGA Development; Hardware Sandboxing; RF Jamming; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Mead, J. (2016). Prevention of Drone Jamming Using Hardware Sandboxing. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2643

Chicago Manual of Style (16th Edition):

Mead, Joshua. “Prevention of Drone Jamming Using Hardware Sandboxing.” 2016. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/2643.

MLA Handbook (7th Edition):

Mead, Joshua. “Prevention of Drone Jamming Using Hardware Sandboxing.” 2016. Web. 27 Feb 2021.

Vancouver:

Mead J. Prevention of Drone Jamming Using Hardware Sandboxing. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/2643.

Council of Science Editors:

Mead J. Prevention of Drone Jamming Using Hardware Sandboxing. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/2643


Northeastern University

20. Agarwal, Akash. Integrating instruction set simulator into a system level design environment.

Degree: MS, Department of Electrical and Computer Engineering, 2013, Northeastern University

 Design of Embedded System, which today comprises of both Hardware and Software (HW/SW) has become complex with the advancement of technology and with the ever… (more)

Subjects/Keywords: ESL; ISS; SpecC; Electrical and Computer Engineering; Engineering; VLSI and circuits, Embedded and Hardware Systems

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APA (6th Edition):

Agarwal, A. (2013). Integrating instruction set simulator into a system level design environment. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20003043

Chicago Manual of Style (16th Edition):

Agarwal, Akash. “Integrating instruction set simulator into a system level design environment.” 2013. Masters Thesis, Northeastern University. Accessed February 27, 2021. http://hdl.handle.net/2047/d20003043.

MLA Handbook (7th Edition):

Agarwal, Akash. “Integrating instruction set simulator into a system level design environment.” 2013. Web. 27 Feb 2021.

Vancouver:

Agarwal A. Integrating instruction set simulator into a system level design environment. [Internet] [Masters thesis]. Northeastern University; 2013. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2047/d20003043.

Council of Science Editors:

Agarwal A. Integrating instruction set simulator into a system level design environment. [Masters Thesis]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20003043

21. Hilgers, Brandon. SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies.

Degree: MS, Electrical Engineering, 2015, Cal Poly

  This research details the design of an SRAM compiler for quickly creating SRAM blocks for Cal Poly integrated circuit (IC) designs. The compiler generates… (more)

Subjects/Keywords: SRAM; Compiler; Memory; Automated; Layout; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Hilgers, B. (2015). SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125

Chicago Manual of Style (16th Edition):

Hilgers, Brandon. “SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies.” 2015. Masters Thesis, Cal Poly. Accessed February 27, 2021. https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125.

MLA Handbook (7th Edition):

Hilgers, Brandon. “SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies.” 2015. Web. 27 Feb 2021.

Vancouver:

Hilgers B. SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies. [Internet] [Masters thesis]. Cal Poly; 2015. [cited 2021 Feb 27]. Available from: https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125.

Council of Science Editors:

Hilgers B. SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies. [Masters Thesis]. Cal Poly; 2015. Available from: https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125


Boise State University

22. Pook, Michael. A Small Acoustic Goniometer for General Purpose Research.

Degree: 2015, Boise State University

 Understanding acoustic events and monitoring their occurrence is a useful aspect of many research projects. In particular, acoustic goniometry allows researchers to determine the source… (more)

Subjects/Keywords: Acoustic Goniometer; infrasound; general purpose; real-time; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Pook, M. (2015). A Small Acoustic Goniometer for General Purpose Research. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/1052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pook, Michael. “A Small Acoustic Goniometer for General Purpose Research.” 2015. Thesis, Boise State University. Accessed February 27, 2021. https://scholarworks.boisestate.edu/td/1052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pook, Michael. “A Small Acoustic Goniometer for General Purpose Research.” 2015. Web. 27 Feb 2021.

Vancouver:

Pook M. A Small Acoustic Goniometer for General Purpose Research. [Internet] [Thesis]. Boise State University; 2015. [cited 2021 Feb 27]. Available from: https://scholarworks.boisestate.edu/td/1052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pook M. A Small Acoustic Goniometer for General Purpose Research. [Thesis]. Boise State University; 2015. Available from: https://scholarworks.boisestate.edu/td/1052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

23. Bhuyan, Shaila Amin. Design of a High Performance Silicon Carbide CMOS Operational Amplifier.

Degree: MSEE, 2014, University of Arkansas

  This thesis presents the design, simulation, layout and test results of a silicon carbide (SiC) CMOS two-stage operational amplifier (op amp) with NMOS input… (more)

Subjects/Keywords: Electronic Devices and Semiconductor Manufacturing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Bhuyan, S. A. (2014). Design of a High Performance Silicon Carbide CMOS Operational Amplifier. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2042

Chicago Manual of Style (16th Edition):

Bhuyan, Shaila Amin. “Design of a High Performance Silicon Carbide CMOS Operational Amplifier.” 2014. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/2042.

MLA Handbook (7th Edition):

Bhuyan, Shaila Amin. “Design of a High Performance Silicon Carbide CMOS Operational Amplifier.” 2014. Web. 27 Feb 2021.

Vancouver:

Bhuyan SA. Design of a High Performance Silicon Carbide CMOS Operational Amplifier. [Internet] [Masters thesis]. University of Arkansas; 2014. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/2042.

Council of Science Editors:

Bhuyan SA. Design of a High Performance Silicon Carbide CMOS Operational Amplifier. [Masters Thesis]. University of Arkansas; 2014. Available from: https://scholarworks.uark.edu/etd/2042


University of Arkansas

24. Williams, Ethan Storm. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.

Degree: MSEE, 2016, University of Arkansas

  A new assistive technology switch for people with disabilities was developed utilizing an Inertial Measurement Unit (IMU) as the sensor technology. The hardware can… (more)

Subjects/Keywords: Applied sciences; Assistive technology; Inertial measurement unit; Biomedical; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Williams, E. S. (2016). Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1503

Chicago Manual of Style (16th Edition):

Williams, Ethan Storm. “Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.” 2016. Masters Thesis, University of Arkansas. Accessed February 27, 2021. https://scholarworks.uark.edu/etd/1503.

MLA Handbook (7th Edition):

Williams, Ethan Storm. “Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.” 2016. Web. 27 Feb 2021.

Vancouver:

Williams ES. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2021 Feb 27]. Available from: https://scholarworks.uark.edu/etd/1503.

Council of Science Editors:

Williams ES. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1503


University of Tennessee – Knoxville

25. Watson, Trevor. An Analog CMOS Particle Filter.

Degree: MS, Electrical Engineering, 2017, University of Tennessee – Knoxville

  Particle filters are used in a variety of image processing and machine learning applications. Their main use in these applications is to gather information… (more)

Subjects/Keywords: Analog; CMOS; Machine Learning; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Watson, T. (2017). An Analog CMOS Particle Filter. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/4962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Watson, Trevor. “An Analog CMOS Particle Filter.” 2017. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/4962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Watson, Trevor. “An Analog CMOS Particle Filter.” 2017. Web. 27 Feb 2021.

Vancouver:

Watson T. An Analog CMOS Particle Filter. [Internet] [Thesis]. University of Tennessee – Knoxville; 2017. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/4962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Watson T. An Analog CMOS Particle Filter. [Thesis]. University of Tennessee – Knoxville; 2017. Available from: https://trace.tennessee.edu/utk_gradthes/4962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

26. Brantley, Jeremy. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.

Degree: MS, Electrical Engineering, 2012, University of Tennessee – Knoxville

  Testing circuits is a hands-on, time intensive process; it is also one of the most important steps in a design cycle. The most well… (more)

Subjects/Keywords: Labview; Characterization; Model Extraction; Automation; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Brantley, J. (2012). Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/1306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Brantley, Jeremy. “Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.” 2012. Thesis, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_gradthes/1306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Brantley, Jeremy. “Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.” 2012. Web. 27 Feb 2021.

Vancouver:

Brantley J. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. [Internet] [Thesis]. University of Tennessee – Knoxville; 2012. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_gradthes/1306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Brantley J. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. [Thesis]. University of Tennessee – Knoxville; 2012. Available from: https://trace.tennessee.edu/utk_gradthes/1306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Kentucky

27. Jacobs, Zachary A. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.

Degree: 2013, University of Kentucky

 The CubeLab is a new payload standard that greatly improves access to the International Space Station (ISS) for small, rapid turn-around microgravity experiments. CubeLabs are… (more)

Subjects/Keywords: CubeSat; CubeLab; NanoRacks; Plug and Play; Distributed Computing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Jacobs, Z. A. (2013). PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. (Masters Thesis). University of Kentucky. Retrieved from https://uknowledge.uky.edu/ece_etds/16

Chicago Manual of Style (16th Edition):

Jacobs, Zachary A. “PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.” 2013. Masters Thesis, University of Kentucky. Accessed February 27, 2021. https://uknowledge.uky.edu/ece_etds/16.

MLA Handbook (7th Edition):

Jacobs, Zachary A. “PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.” 2013. Web. 27 Feb 2021.

Vancouver:

Jacobs ZA. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2021 Feb 27]. Available from: https://uknowledge.uky.edu/ece_etds/16.

Council of Science Editors:

Jacobs ZA. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. [Masters Thesis]. University of Kentucky; 2013. Available from: https://uknowledge.uky.edu/ece_etds/16


University of Kentucky

28. Zhang, Xiaowei. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.

Degree: 2015, University of Kentucky

 SRAM is a significant component in high speed computer design, which serves mainly as high speed storage elements like register files in microprocessors, or the… (more)

Subjects/Keywords: SRAM; Timing Parameters; SPICE; Liberty File; DFF; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Zhang, X. (2015). A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. (Masters Thesis). University of Kentucky. Retrieved from https://uknowledge.uky.edu/ece_etds/75

Chicago Manual of Style (16th Edition):

Zhang, Xiaowei. “A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.” 2015. Masters Thesis, University of Kentucky. Accessed February 27, 2021. https://uknowledge.uky.edu/ece_etds/75.

MLA Handbook (7th Edition):

Zhang, Xiaowei. “A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.” 2015. Web. 27 Feb 2021.

Vancouver:

Zhang X. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. [Internet] [Masters thesis]. University of Kentucky; 2015. [cited 2021 Feb 27]. Available from: https://uknowledge.uky.edu/ece_etds/75.

Council of Science Editors:

Zhang X. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. [Masters Thesis]. University of Kentucky; 2015. Available from: https://uknowledge.uky.edu/ece_etds/75

29. Vyas, Shruti S. Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories.

Degree: MS, Electrical & Computer Engineering, 2011, University of Massachusetts

 NAND flash memories are popular due to their density and lower cost. However, due to serial access, NAND flash memories have low read and write… (more)

Subjects/Keywords: Nand; Flash; Search; data deduplication; MISR; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Vyas, S. S. (2011). Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/548

Chicago Manual of Style (16th Edition):

Vyas, Shruti S. “Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories.” 2011. Masters Thesis, University of Massachusetts. Accessed February 27, 2021. https://scholarworks.umass.edu/theses/548.

MLA Handbook (7th Edition):

Vyas, Shruti S. “Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories.” 2011. Web. 27 Feb 2021.

Vancouver:

Vyas SS. Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories. [Internet] [Masters thesis]. University of Massachusetts; 2011. [cited 2021 Feb 27]. Available from: https://scholarworks.umass.edu/theses/548.

Council of Science Editors:

Vyas SS. Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories. [Masters Thesis]. University of Massachusetts; 2011. Available from: https://scholarworks.umass.edu/theses/548


Portland State University

30. Chandorkar, Chaitrali Santosh. Data Driven Feed Forward Adaptive Testing.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2013, Portland State University

  Test cost is a critical component in the overall cost of the product. Test cost varies in direct proportion with test time. This thesis… (more)

Subjects/Keywords: Integrated circuits  – Testing; Integrated circuits  – Quality control; Production management; Electrical and Computer Engineering; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chandorkar, C. S. (2013). Data Driven Feed Forward Adaptive Testing. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/1049

Chicago Manual of Style (16th Edition):

Chandorkar, Chaitrali Santosh. “Data Driven Feed Forward Adaptive Testing.” 2013. Masters Thesis, Portland State University. Accessed February 27, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/1049.

MLA Handbook (7th Edition):

Chandorkar, Chaitrali Santosh. “Data Driven Feed Forward Adaptive Testing.” 2013. Web. 27 Feb 2021.

Vancouver:

Chandorkar CS. Data Driven Feed Forward Adaptive Testing. [Internet] [Masters thesis]. Portland State University; 2013. [cited 2021 Feb 27]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/1049.

Council of Science Editors:

Chandorkar CS. Data Driven Feed Forward Adaptive Testing. [Masters Thesis]. Portland State University; 2013. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/1049

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