subject:(VLSI AND Circuits Embedded AND Hardware Systems)

University of Tennessee – Knoxville

1. Tham, Kevin Vun Kiat. PVT Compensation for Single-Slope Measurement Systems.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/915

► A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6^th Edition):

Tham, K. V. K. (2011). PVT Compensation for Single-Slope Measurement Systems. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Web. 23 Sep 2019.

Vancouver:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Tennessee – Knoxville

2. Kilambi, Supriya. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.

Degree: MS, Computer Engineering, 2011, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/888

► This thesis presents the low power design of a 916MHz Gilbert cell mixer and a Class-A power amplifier for the Bioluminescent Bioreporter Integrated Circuit (BBIC)… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6^th Edition):

Kilambi, S. (2011). Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Web. 23 Sep 2019.

Vancouver:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Tennessee – Knoxville

3. Mudhasani, Shanthan. GPU-based Implementation of the Variational Path Integral Method.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/932

► Any system in the world constitutes particles like electrons. To analyze the behaviors of these systems the behavior of these particles must be predicted.… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6^th Edition):

Mudhasani, S. (2011). GPU-based Implementation of the Variational Path Integral Method. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Web. 23 Sep 2019.

Vancouver:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Cal Poly

4. Zaveri, Jainish K. ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY.

Degree: MS, Electrical Engineering, 2018, Cal Poly

URL: https://digitalcommons.calpoly.edu/theses/1940

► Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6^th Edition):

Zaveri, J. K. (2018). ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1940

Chicago Manual of Style (16^th Edition):

Zaveri, Jainish K. “ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY.” 2018. Masters Thesis, Cal Poly. Accessed September 23, 2019. https://digitalcommons.calpoly.edu/theses/1940.

MLA Handbook (7^th Edition):

Zaveri, Jainish K. “ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY.” 2018. Web. 23 Sep 2019.

Vancouver:

Zaveri JK. ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY. [Internet] [Masters thesis]. Cal Poly; 2018. [cited 2019 Sep 23]. Available from: https://digitalcommons.calpoly.edu/theses/1940.

Council of Science Editors:

Zaveri JK. ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY. [Masters Thesis]. Cal Poly; 2018. Available from: https://digitalcommons.calpoly.edu/theses/1940

Virginia Commonwealth University

5. Khairullah, Shawkat Sabah. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.

Degree: PhD, Electrical & Computer Engineering, 2018, Virginia Commonwealth University

URL: https://scholarscompass.vcu.edu/etd/5671

► Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes.… (more)

▼ Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation community where a significant need exists. This dissertation presents a new self-healing digital I&C architecture called BioSymPLe, inspired from the way nature responds, defends and heals: the stem cells in the immune system of living organisms, the life cycle of the living cell, and the pathway from Deoxyribonucleic acid (DNA) to protein. The BioSymPLe architecture is integrating biological concepts, fault tolerance techniques, and operational schematics for the international standard IEC 61131-3 to facilitate adoption in the automation industry. BioSymPLe is organized into three hierarchical levels: the local function migration layer from the top side, the critical service layer in the middle, and the global function migration layer from the bottom side. The local layer is used to monitor the correct execution of functions at the cellular level and to activate healing mechanisms at the critical service level. The critical layer is allocating a group of functional B cells which represent the building block that executes the intended functionality of critical application based on the expression for DNA genetic codes stored inside each cell. The global layer uses a concept of embryonic stem cells by differentiating these type of cells to repair the faulty T cells and supervising all repair mechanisms. Finally, two industrial applications have been mapped on the proposed architecture, which are capable of tolerating a significant number of faults (transient, permanent, and hardware common cause failures CCFs) that can stem from environmental disturbances and we believe the nexus of its concepts can positively impact the next generation of critical systems in the automation industry. Advisors/Committee Members: Dr. Carl R. Elks, Dr. Robert H. Klenke, Dr. Alen Docef, Dr. Tim Bakker, Dr. Fadi Obeidat.

Subjects/Keywords: Computer and Systems Architecture; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Khairullah, S. S. (2018). Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. (Doctoral Dissertation). Virginia Commonwealth University. Retrieved from https://scholarscompass.vcu.edu/etd/5671

Chicago Manual of Style (16^th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Doctoral Dissertation, Virginia Commonwealth University. Accessed September 23, 2019. https://scholarscompass.vcu.edu/etd/5671.

MLA Handbook (7^th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Web. 23 Sep 2019.

Vancouver:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Internet] [Doctoral dissertation]. Virginia Commonwealth University; 2018. [cited 2019 Sep 23]. Available from: https://scholarscompass.vcu.edu/etd/5671.

Council of Science Editors:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Doctoral Dissertation]. Virginia Commonwealth University; 2018. Available from: https://scholarscompass.vcu.edu/etd/5671

University of Arkansas

6. McGeehan, Brendan. Hardware IP Classification through Weighted Characteristics.

Degree: MSCmpE, 2019, University of Arkansas

URL: https://scholarworks.uark.edu/etd/3166

► Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For… (more)

▼ Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For instance, outsourcing certain components of an overall design can reduce time-to-market by allowing each party to specialize and perfect a specific part of the overall design. However, allowing third-party involvement also increases the possibility of malicious attacks, such as hardware Trojan insertion. Trojan insertion is a particularly dangerous security threat because testing the functionality of an IP can often leave the Trojan undetected. Therefore, this thesis work provides an improvement on a Trojan detection method known as Structural Checking which analyzes Register-Transfer Level (RTL) and gate-level soft IPs. Given an unknown IP, the Structural Checking tool will break down the design primary ports and internal signals into assets that fall into six characteristics. These characteristics organize how the IP is structured and provide information about the unknown IP’s overall function. The tool also provides a library of known designs referred to as the Golden Reference Library (GRL). All entries in the library are also broken down into the same six characteristics and are either known to be clean or known to have a Trojan inserted. An overall percent match for each library entry against the unknown IP is calculated by first computing a percent match within each characteristic. A weighted average of these percent matches makes up the final percentage. If the library entry with the best match is known to have a Trojan inserted, then the unknown design is likely to have a Trojan as well and vice versa. Due to the structural variability of soft IP designs, it is vital to provide the best possible weighting of the six characteristics to best match the unknown IP to the most similar library entry. This thesis work provides a statistical approach to finding the best weights to optimize the Structural Checking tool’s matching algorithm. Advisors/Committee Members: Jia Di, James P. Parkerson, Dale Thompson.

Subjects/Keywords: Classifcation; Hardware; Trojans; Hardware Systems; Information Security; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

McGeehan, B. (2019). Hardware IP Classification through Weighted Characteristics. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3166

Chicago Manual of Style (16^th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/3166.

MLA Handbook (7^th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Web. 23 Sep 2019.

Vancouver:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/3166.

Council of Science Editors:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3166

7. zhang, xiangyu. ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS.

Degree: 2017, University of Massachusetts

URL: https://scholarworks.umass.edu/masters_theses_2/551

► This study comprises two tasks. The ﬁrst is to implement gate-level circuit camouﬂage techniques. The second is to implement the Oracle-guided incremental de-camouﬂage algorithm… (more)

Subjects/Keywords: Reverse engineer; Algorithm; Hardware; Camouflage; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

zhang, x. (2017). ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

zhang, xiangyu. “ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS.” 2017. Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/masters_theses_2/551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

zhang, xiangyu. “ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS.” 2017. Web. 23 Sep 2019.

Vancouver:

zhang x. ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS. [Internet] [Thesis]. University of Massachusetts; 2017. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/masters_theses_2/551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

zhang x. ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS. [Thesis]. University of Massachusetts; 2017. Available from: https://scholarworks.umass.edu/masters_theses_2/551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Boise State University

8. Henderson, Edward Nelson. An Inertial Measurement System for Hand and Finger Tracking.

Degree: 2011, Boise State University

URL: https://scholarworks.boisestate.edu/td/233

► The primary Human Computer Interfaces (HCI) today are the keyboard and mouse. These interfaces do not facilitate a fluid flow of thought and intent from… (more)

Subjects/Keywords: inertial; glove; IMU; algorithm; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Henderson, E. N. (2011). An Inertial Measurement System for Hand and Finger Tracking. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Henderson, Edward Nelson. “An Inertial Measurement System for Hand and Finger Tracking.” 2011. Thesis, Boise State University. Accessed September 23, 2019. https://scholarworks.boisestate.edu/td/233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Henderson, Edward Nelson. “An Inertial Measurement System for Hand and Finger Tracking.” 2011. Web. 23 Sep 2019.

Vancouver:

Henderson EN. An Inertial Measurement System for Hand and Finger Tracking. [Internet] [Thesis]. Boise State University; 2011. [cited 2019 Sep 23]. Available from: https://scholarworks.boisestate.edu/td/233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Henderson EN. An Inertial Measurement System for Hand and Finger Tracking. [Thesis]. Boise State University; 2011. Available from: https://scholarworks.boisestate.edu/td/233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arkansas

9. Barlow, Matthew. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.

Degree: MSEE, 2012, University of Arkansas

URL: https://scholarworks.uark.edu/etd/362

► This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1… (more)

Subjects/Keywords: Applied sciences; ASIC; SRAM; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Barlow, M. (2012). Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/362

Chicago Manual of Style (16^th Edition):

Barlow, Matthew. “Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.” 2012. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/362.

MLA Handbook (7^th Edition):

Barlow, Matthew. “Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.” 2012. Web. 23 Sep 2019.

Vancouver:

Barlow M. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. [Internet] [Masters thesis]. University of Arkansas; 2012. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/362.

Council of Science Editors:

Barlow M. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. [Masters Thesis]. University of Arkansas; 2012. Available from: https://scholarworks.uark.edu/etd/362

University of Tennessee – Knoxville

10. Fandrich, Cory Lynn. An On-Chip Transformer-Based Digital Isolator System.

Degree: MS, Electrical Engineering, 2013, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/2602

► An on-chip transformer-based digital isolator has been designed, fabricated, and tested. This isolation technique is designed to function between a low voltage microcontroller and… (more)

Subjects/Keywords: Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Fandrich, C. L. (2013). An On-Chip Transformer-Based Digital Isolator System. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/2602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Fandrich, Cory Lynn. “An On-Chip Transformer-Based Digital Isolator System.” 2013. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/2602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Fandrich, Cory Lynn. “An On-Chip Transformer-Based Digital Isolator System.” 2013. Web. 23 Sep 2019.

Vancouver:

Fandrich CL. An On-Chip Transformer-Based Digital Isolator System. [Internet] [Thesis]. University of Tennessee – Knoxville; 2013. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/2602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fandrich CL. An On-Chip Transformer-Based Digital Isolator System. [Thesis]. University of Tennessee – Knoxville; 2013. Available from: https://trace.tennessee.edu/utk_gradthes/2602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Usmani, Mohammad. Applications Of Physical Unclonable Functions on ASICS and FPGAs.

Degree: 2018, University of Massachusetts

URL: https://scholarworks.umass.edu/masters_theses_2/619

► With the ever-increasing demand for security in embedded systems and wireless sensor networks, we require integrating security primitives for authentication in these devices. One… (more)

▼ With the ever-increasing demand for security in embedded systems and wireless sensor networks, we require integrating security primitives for authentication in these devices. One such primitive is known as a Physically Unclonable Function. This entity can be used to provide security at a low cost, as the key or digital signature can be generated by dedicating a small part of the silicon die to these primitives which produces a fingerprint unique to each device. This fingerprint produced by a PUF is called its response. The response of PUFs depends upon the process variation that occurs during the manufacturing process. In embedded systems and especially wireless sensor networks, there is a need to secure the data the collected from the sensors. To tackle this problem, we propose the use of SRAM-based PUFs to detect the temperature of the system. This is done by taking the PUF response to generate temperature based keys. The key would act as proofs of the temperature of the system. In SRAM PUFs, it is experimentally determined that at varying temperatures there is a shift in the response of the cells from zero to one and vice-versa. This variation can be exploited to generate random but repeatable keys at different temperatures. To evaluate our approach, we first analyze the key metrics of a PUF, namely, reliability and uniqueness. In order to test the idea of using the PUF as a temperature based key generator, we collect data from a total of ten SRAM chips at fixed temperatures steps. We first calculate the reliability, which is related to bit error rate, an important parameter with respect to error correction, at various temperatures to verify the stability of the responses. We then identify the temperature of the system by using a temperature sensor and then encode the key offset by PUF response at that temperature using BCH codes. This key-temperature pair can then be used to establish secure communication between the nodes. Thus, this scheme helps in establishing secure keys as the generation has an extra variable to produce confusion. We developed a novel PUF for Xilinx FPGAs and evaluated its quality metrics. It is very compact and has high uniqueness and reliability. We also implement 2 different PUF configurations to allow per-device selection of best PUFs to reduce the area and power required for key-generation. We also evaluate the temperature response of this PUF and show improvement in the response by using per-device selection. Advisors/Committee Members: Daniel E Holcomb, Russell G Tessier, Jay Taneja.

Subjects/Keywords: Electrical and Computer Engineering; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Usmani, M. (2018). Applications Of Physical Unclonable Functions on ASICS and FPGAs. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Usmani, Mohammad. “Applications Of Physical Unclonable Functions on ASICS and FPGAs.” 2018. Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/masters_theses_2/619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Usmani, Mohammad. “Applications Of Physical Unclonable Functions on ASICS and FPGAs.” 2018. Web. 23 Sep 2019.

Vancouver:

Usmani M. Applications Of Physical Unclonable Functions on ASICS and FPGAs. [Internet] [Thesis]. University of Massachusetts; 2018. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/masters_theses_2/619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Usmani M. Applications Of Physical Unclonable Functions on ASICS and FPGAs. [Thesis]. University of Massachusetts; 2018. Available from: https://scholarworks.umass.edu/masters_theses_2/619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Tennessee – Knoxville

12. Vanguri, Phani Bharadwaj. An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm.

Degree: MS, Computer Engineering, 2010, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/837

► Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which… (more)

Subjects/Keywords: stochastic; FPGA; vlsi; simulation; algorithm; hpc; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Vanguri, P. B. (2010). An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/837

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Vanguri, Phani Bharadwaj. “An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm.” 2010. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/837.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Vanguri, Phani Bharadwaj. “An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm.” 2010. Web. 23 Sep 2019.

Vancouver:

Vanguri PB. An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm. [Internet] [Thesis]. University of Tennessee – Knoxville; 2010. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/837.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vanguri PB. An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm. [Thesis]. University of Tennessee – Knoxville; 2010. Available from: https://trace.tennessee.edu/utk_gradthes/837

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Michigan Technological University

13. Zhao, Xueqian. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.

Degree: PhD, Department of Electrical and Computer Engineering, 2018, Michigan Technological University

URL: http://digitalcommons.mtu.edu/etdr/637

► To evaluate and verify the functional correction and reliability of circuit designs, circuit components (e.g. resistors, capacitors, etc) need to be accurately modeled (e.g.… (more)

▼ To evaluate and verify the functional correction and reliability of circuit designs, circuit components (e.g. resistors, capacitors, etc) need to be accurately modeled (e.g. parasitic extraction) and circuit performance requires precise analysis (e.g. simulation and verification). As the technology scaling of nowadays integrated circuits enters nano-scale regime, the traditional flow of circuit designs becomes increasingly challenging due to the rapid growth of circuit complexity brought by more than billions on-chip components. To this end, during the past decades, endless effort has been made to increase the design efficiency via various directions that include but not limited to exploration of advanced algorithms, leveraging the benefits of multi-core/many-core heterogeneous computation platforms. For full chip parasitic extraction, we propose GPU-friendly data structures and single-instruction-multiple-data (SIMD) parallel algorithm flows to facilitate the FMM-based 3-D capacitance extraction on GPU. Effective GPU performance modeling methods are also proposed to properly balance the workload of each critical kernel in our FMMGpu implementation, by taking advantage of the GPU's concurrent kernel execution technique. Our experimental results show that FMMGpu brings 22X to 30X speedups in capacitance extractions for various test cases. For circuit simulations, based on recent graph sparsification research, we propose a circuit-oriented general-purpose support-circuit preconditioning (GPSCP) approach to improve the matrix solving time and reduce the memory consumption during SPICE-accurate integrated circuit simulations. Additionally, a performance model-guided graph sparsification approach is proposed to facilitate automatically building a near-optimal preconditioner. Our experimental results for a variety of large-scale integrated circuit designs show that the proposed technique can achieve up to 18X runtime speedups and 7X memory reduction in DC and transient Simulations. Besides accelerating the analysis by effective preconditioners, we also explore a scalable power grid reduction method for reducing large-scale flip-chip power grids based on recent spectral graph sparsification techniques. In our work, Schur complement and spectral graph sparsification methods are combined to reduce the original large power grid into a much smaller grid while keeping affordable grid density for fast analysis. Extensive experimental results show that our method can scale linearly with power grid sizes and efficiently reduce industrial power grids sizes by 20X without loss of much accuracy in both DC and transient analysis. Advisors/Committee Members: Zhuo Feng.

Subjects/Keywords: VLSI; SIMULATION; PRECONDITIONER; GPU; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhao, X. (2018). FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. (Doctoral Dissertation). Michigan Technological University. Retrieved from http://digitalcommons.mtu.edu/etdr/637

Chicago Manual of Style (16^th Edition):

Zhao, Xueqian. “FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.” 2018. Doctoral Dissertation, Michigan Technological University. Accessed September 23, 2019. http://digitalcommons.mtu.edu/etdr/637.

MLA Handbook (7^th Edition):

Zhao, Xueqian. “FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.” 2018. Web. 23 Sep 2019.

Vancouver:

Zhao X. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. [Internet] [Doctoral dissertation]. Michigan Technological University; 2018. [cited 2019 Sep 23]. Available from: http://digitalcommons.mtu.edu/etdr/637.

Council of Science Editors:

Zhao X. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. [Doctoral Dissertation]. Michigan Technological University; 2018. Available from: http://digitalcommons.mtu.edu/etdr/637

University of Tennessee – Knoxville

14. Daffron, Christopher Paul. DANNA A Neuromorphic Computing VLSI Chip.

Degree: MS, Computer Engineering, 2015, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/3467

► Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly… (more)

Subjects/Keywords: VLSI; ASIC; Spiking Neural Networks; FPGA; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Daffron, C. P. (2015). DANNA A Neuromorphic Computing VLSI Chip. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/3467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Daffron, Christopher Paul. “DANNA A Neuromorphic Computing VLSI Chip.” 2015. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/3467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Daffron, Christopher Paul. “DANNA A Neuromorphic Computing VLSI Chip.” 2015. Web. 23 Sep 2019.

Vancouver:

Daffron CP. DANNA A Neuromorphic Computing VLSI Chip. [Internet] [Thesis]. University of Tennessee – Knoxville; 2015. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/3467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Daffron CP. DANNA A Neuromorphic Computing VLSI Chip. [Thesis]. University of Tennessee – Knoxville; 2015. Available from: https://trace.tennessee.edu/utk_gradthes/3467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Cal Poly

15. YU, RUN BIN. Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz.

Degree: MS, Electrical Engineering, 2016, Cal Poly

URL: https://digitalcommons.calpoly.edu/theses/1685

► The clock signal is considered as the “heartbeat” of a digital system yet jitter which is a variation on the arrival time of the… (more)

Subjects/Keywords: Jitter reduction; VLSI; Clock; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

YU, R. B. (2016). Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1685

Chicago Manual of Style (16^th Edition):

YU, RUN BIN. “Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz.” 2016. Masters Thesis, Cal Poly. Accessed September 23, 2019. https://digitalcommons.calpoly.edu/theses/1685.

MLA Handbook (7^th Edition):

YU, RUN BIN. “Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz.” 2016. Web. 23 Sep 2019.

Vancouver:

YU RB. Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz. [Internet] [Masters thesis]. Cal Poly; 2016. [cited 2019 Sep 23]. Available from: https://digitalcommons.calpoly.edu/theses/1685.

Council of Science Editors:

YU RB. Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz. [Masters Thesis]. Cal Poly; 2016. Available from: https://digitalcommons.calpoly.edu/theses/1685

University of Tennessee – Knoxville

16. Yang, Depeng. Turbo Bayesian Compressed Sensing.

Degree: 2011, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_graddiss/1145

► Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist… (more)

Subjects/Keywords: Compressed Sensing; Hardware Implementation; FPGA; GPU; Signal Processing; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yang, D. (2011). Turbo Bayesian Compressed Sensing. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/1145

Chicago Manual of Style (16^th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_graddiss/1145.

MLA Handbook (7^th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Web. 23 Sep 2019.

Vancouver:

Yang D. Turbo Bayesian Compressed Sensing. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_graddiss/1145.

Council of Science Editors:

Yang D. Turbo Bayesian Compressed Sensing. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_graddiss/1145

17. Merchant, Murtaza. Testing and Validation of a Prototype Gpgpu Design for FPGAs.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

URL: https://scholarworks.umass.edu/theses/1012

► Due to their suitability for highly parallel and pipelined computation, field programmable gate arrays (FPGAs) and general-purpose graphics processing units (GPGPUs) have emerged as… (more)

Subjects/Keywords: GPGPU; FPGA; hardware acceleration; CUDA compatible; scalable; flexible; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Merchant, M. (2013). Testing and Validation of a Prototype Gpgpu Design for FPGAs. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1012

Chicago Manual of Style (16^th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Masters Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/theses/1012.

MLA Handbook (7^th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Web. 23 Sep 2019.

Vancouver:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/theses/1012.

Council of Science Editors:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1012

University of Arkansas

18. Mize, Nicholas Renoudet. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.

Degree: MSCmpE, 2019, University of Arkansas

URL: https://scholarworks.uark.edu/etd/3168

► As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away… (more)

Subjects/Keywords: Asynchronous; Circuit; Digital; MTNCL; Synthesis; VHDL; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mize, N. R. (2019). Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3168

Chicago Manual of Style (16^th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/3168.

MLA Handbook (7^th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Web. 23 Sep 2019.

Vancouver:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/3168.

Council of Science Editors:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3168

University of Arkansas

19. Munasib, Sharthak. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.

Degree: MSEE, 2017, University of Arkansas

URL: https://scholarworks.uark.edu/etd/1875

► Proper short-circuit protection in dc distribution systems has provided an austere challenge to researchers as the development of commercially-viable equipment providing fast operation, coordination… (more)

Subjects/Keywords: Applied sciences; Systems and Communications; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Munasib, S. (2017). Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1875

Chicago Manual of Style (16^th Edition):

Munasib, Sharthak. “Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.” 2017. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/1875.

MLA Handbook (7^th Edition):

Munasib, Sharthak. “Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.” 2017. Web. 23 Sep 2019.

Vancouver:

Munasib S. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. [Internet] [Masters thesis]. University of Arkansas; 2017. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/1875.

Council of Science Editors:

Munasib S. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. [Masters Thesis]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1875

20. Phanibhushana, Bharath. An Interconnection Network Topology Generation Scheme for Multicore Systems.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

URL: https://scholarworks.umass.edu/theses/1146

► Multi-Processor System on Chip (MPSoC) consisting of multiple processing cores connected via a Network on Chip (NoC) has gained prominence over the last decade.… (more)

Subjects/Keywords: NoC; Multicore; SoC; Realtime systems; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Phanibhushana, B. (2013). An Interconnection Network Topology Generation Scheme for Multicore Systems. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1146

Chicago Manual of Style (16^th Edition):

Phanibhushana, Bharath. “An Interconnection Network Topology Generation Scheme for Multicore Systems.” 2013. Masters Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/theses/1146.

MLA Handbook (7^th Edition):

Phanibhushana, Bharath. “An Interconnection Network Topology Generation Scheme for Multicore Systems.” 2013. Web. 23 Sep 2019.

Vancouver:

Phanibhushana B. An Interconnection Network Topology Generation Scheme for Multicore Systems. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/theses/1146.

Council of Science Editors:

Phanibhushana B. An Interconnection Network Topology Generation Scheme for Multicore Systems. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1146

University of Nevada – Las Vegas

21. Suseela, Jaya. Parameterizable network-on-chip emulation framework.

Degree: MSE, Electrical Engineering, 2010, University of Nevada – Las Vegas

URL: https://digitalscholarship.unlv.edu/thesesdissertations/714

► Networks-on-Chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. But there is no public accessible HDL synthesizable NoC framework… (more)

▼ Networks-on-Chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. But there is no public accessible HDL synthesizable NoC framework which connects industrial level cores and runs real applications on them. Moreover, many challenging research problems remain unsolved at all levels of design abstraction; design exploration of NoC architecture for applications, scheduling and mapping algorithms, evaluation of switching, topology or routing algorithm for efficient execution of application and optimizing communication cost, area, energy etc Solution to solve the above problem calls for the development of synthesizable, parameterizable NoC Framework that would evaluate and implement the above outstanding research problems and algorithms with minimum ease and flexibility. The proposed NoC Framework has been used to specifically evaluate the following algorithms or variations in architecture: i) Evaluate Switching Algorithms compare latency, congestion, area and power of Wormhole (WH) and Store and Forward (SF) switching, ii) Efficient Router Architecture: Proposed an efficient Virtual Channel architecture with loopback for SF routing is introduced to improve throughput, latency and area, iii) Static routing algorithm: Proposed a simple and efficient routing algorithm called “Mirror Routing” for Torus architectures. This helps in reducing congestion and the routing algorithm is also deadlock free, iv) Adaptive Routing Algorithm: Proposed and evaluated an adaptive routing algorithm for WK topology. The simulation results show Wormhole Routing with better latency than Store and Forward. Area and Power usage is also relatively less for Wormhole Routing. Study on different traffic scenarios with different Virtual Channel architectures in Store and Forward routing shows considerable improvement in latency in Virtual Channel architecture with loopback. Also it is proved that the proposed Mirror Routing algorithm is able to handle a single congestion or fault in routing path. The latency increases with increase in size of Torus structure. The Adaptive routing algorithm proposed for WK Topology results in increase in latency but can be considered in scenarios where the receiver node at the congested link is comparatively slow or when the fault in link is permanent. Advisors/Committee Members: Venkatesan Muthukumar, Chair, Emma Regentova, Mei Yang.

Subjects/Keywords: Electrical and Computer Engineering; Systems and Communications; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Suseela, J. (2010). Parameterizable network-on-chip emulation framework. (Masters Thesis). University of Nevada – Las Vegas. Retrieved from https://digitalscholarship.unlv.edu/thesesdissertations/714

Chicago Manual of Style (16^th Edition):

Suseela, Jaya. “Parameterizable network-on-chip emulation framework.” 2010. Masters Thesis, University of Nevada – Las Vegas. Accessed September 23, 2019. https://digitalscholarship.unlv.edu/thesesdissertations/714.

MLA Handbook (7^th Edition):

Suseela, Jaya. “Parameterizable network-on-chip emulation framework.” 2010. Web. 23 Sep 2019.

Vancouver:

Suseela J. Parameterizable network-on-chip emulation framework. [Internet] [Masters thesis]. University of Nevada – Las Vegas; 2010. [cited 2019 Sep 23]. Available from: https://digitalscholarship.unlv.edu/thesesdissertations/714.

Council of Science Editors:

Suseela J. Parameterizable network-on-chip emulation framework. [Masters Thesis]. University of Nevada – Las Vegas; 2010. Available from: https://digitalscholarship.unlv.edu/thesesdissertations/714

22. Vyas, Shrikant S. Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems.

Degree: 2016, University of Massachusetts

URL: https://scholarworks.umass.edu/masters_theses_2/452

► With the importance of data security at its peak today, many reconfigurable systems are used to provide security. This protection is often provided by… (more)

Subjects/Keywords: Physical Unclonable Functions; FPGAs; Error Correction; Variation Aware; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Vyas, S. S. (2016). Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Vyas, Shrikant S. “Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems.” 2016. Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/masters_theses_2/452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Vyas, Shrikant S. “Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems.” 2016. Web. 23 Sep 2019.

Vancouver:

Vyas SS. Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems. [Internet] [Thesis]. University of Massachusetts; 2016. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/masters_theses_2/452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vyas SS. Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems. [Thesis]. University of Massachusetts; 2016. Available from: https://scholarworks.umass.edu/masters_theses_2/452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Kentucky

23. Jacobs, Zachary A. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.

Degree: 2013, University of Kentucky

URL: http://uknowledge.uky.edu/ece_etds/16

► The CubeLab is a new payload standard that greatly improves access to the International Space Station (ISS) for small, rapid turn-around microgravity experiments. CubeLabs are… (more)

Subjects/Keywords: CubeSat; CubeLab; NanoRacks; Plug and Play; Distributed Computing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Jacobs, Z. A. (2013). PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/16

Chicago Manual of Style (16^th Edition):

Jacobs, Zachary A. “PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.” 2013. Masters Thesis, University of Kentucky. Accessed September 23, 2019. http://uknowledge.uky.edu/ece_etds/16.

MLA Handbook (7^th Edition):

Jacobs, Zachary A. “PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.” 2013. Web. 23 Sep 2019.

Vancouver:

Jacobs ZA. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2019 Sep 23]. Available from: http://uknowledge.uky.edu/ece_etds/16.

Council of Science Editors:

Jacobs ZA. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. [Masters Thesis]. University of Kentucky; 2013. Available from: http://uknowledge.uky.edu/ece_etds/16

University of Kentucky

24. Zhang, Xiaowei. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.

Degree: 2015, University of Kentucky

URL: http://uknowledge.uky.edu/ece_etds/75

► SRAM is a significant component in high speed computer design, which serves mainly as high speed storage elements like register files in microprocessors, or the… (more)

Subjects/Keywords: SRAM; Timing Parameters; SPICE; Liberty File; DFF; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Zhang, X. (2015). A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/75

Chicago Manual of Style (16^th Edition):

Zhang, Xiaowei. “A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.” 2015. Masters Thesis, University of Kentucky. Accessed September 23, 2019. http://uknowledge.uky.edu/ece_etds/75.

MLA Handbook (7^th Edition):

Zhang, Xiaowei. “A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.” 2015. Web. 23 Sep 2019.

Vancouver:

Zhang X. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. [Internet] [Masters thesis]. University of Kentucky; 2015. [cited 2019 Sep 23]. Available from: http://uknowledge.uky.edu/ece_etds/75.

Council of Science Editors:

Zhang X. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. [Masters Thesis]. University of Kentucky; 2015. Available from: http://uknowledge.uky.edu/ece_etds/75

University of Western Ontario

25. Hariri, Arash. Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability.

Degree: 2010, University of Western Ontario

URL: https://ir.lib.uwo.ca/etd/75

► The elliptic curve cryptography is an important branch in public-key cryptography. In this thesis, we consider the elliptic curve cryptography over binary extension fields from… (more)

Subjects/Keywords: Finite Field Arithmetic; Elliptic Curve Cryptography; Montgomery Multiplication; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hariri, A. (2010). Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability. (Thesis). University of Western Ontario. Retrieved from https://ir.lib.uwo.ca/etd/75

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hariri, Arash. “Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability.” 2010. Thesis, University of Western Ontario. Accessed September 23, 2019. https://ir.lib.uwo.ca/etd/75.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hariri, Arash. “Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability.” 2010. Web. 23 Sep 2019.

Vancouver:

Hariri A. Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability. [Internet] [Thesis]. University of Western Ontario; 2010. [cited 2019 Sep 23]. Available from: https://ir.lib.uwo.ca/etd/75.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hariri A. Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability. [Thesis]. University of Western Ontario; 2010. Available from: https://ir.lib.uwo.ca/etd/75

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Boise State University

26. Pook, Michael. A Small Acoustic Goniometer for General Purpose Research.

Degree: 2015, Boise State University

URL: https://scholarworks.boisestate.edu/td/1052

► Understanding acoustic events and monitoring their occurrence is a useful aspect of many research projects. In particular, acoustic goniometry allows researchers to determine the source… (more)

Subjects/Keywords: Acoustic Goniometer; infrasound; general purpose; real-time; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Pook, M. (2015). A Small Acoustic Goniometer for General Purpose Research. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/1052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pook, Michael. “A Small Acoustic Goniometer for General Purpose Research.” 2015. Thesis, Boise State University. Accessed September 23, 2019. https://scholarworks.boisestate.edu/td/1052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pook, Michael. “A Small Acoustic Goniometer for General Purpose Research.” 2015. Web. 23 Sep 2019.

Vancouver:

Pook M. A Small Acoustic Goniometer for General Purpose Research. [Internet] [Thesis]. Boise State University; 2015. [cited 2019 Sep 23]. Available from: https://scholarworks.boisestate.edu/td/1052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pook M. A Small Acoustic Goniometer for General Purpose Research. [Thesis]. Boise State University; 2015. Available from: https://scholarworks.boisestate.edu/td/1052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arkansas

27. Williams, Ethan Storm. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.

Degree: MSEE, 2016, University of Arkansas

URL: https://scholarworks.uark.edu/etd/1503

► A new assistive technology switch for people with disabilities was developed utilizing an Inertial Measurement Unit (IMU) as the sensor technology. The hardware can… (more)

Subjects/Keywords: Applied sciences; Assistive technology; Inertial measurement unit; Biomedical; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Williams, E. S. (2016). Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1503

Chicago Manual of Style (16^th Edition):

Williams, Ethan Storm. “Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.” 2016. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/1503.

MLA Handbook (7^th Edition):

Williams, Ethan Storm. “Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.” 2016. Web. 23 Sep 2019.

Vancouver:

Williams ES. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/1503.

Council of Science Editors:

Williams ES. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1503

University of Arkansas

28. Bhuyan, Shaila Amin. Design of a High Performance Silicon Carbide CMOS Operational Amplifier.

Degree: MSEE, 2014, University of Arkansas

URL: https://scholarworks.uark.edu/etd/2042

► This thesis presents the design, simulation, layout and test results of a silicon carbide (SiC) CMOS two-stage operational amplifier (op amp) with NMOS input… (more)

Subjects/Keywords: Electronic Devices and Semiconductor Manufacturing; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bhuyan, S. A. (2014). Design of a High Performance Silicon Carbide CMOS Operational Amplifier. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2042

Chicago Manual of Style (16^th Edition):

Bhuyan, Shaila Amin. “Design of a High Performance Silicon Carbide CMOS Operational Amplifier.” 2014. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/2042.

MLA Handbook (7^th Edition):

Bhuyan, Shaila Amin. “Design of a High Performance Silicon Carbide CMOS Operational Amplifier.” 2014. Web. 23 Sep 2019.

Vancouver:

Bhuyan SA. Design of a High Performance Silicon Carbide CMOS Operational Amplifier. [Internet] [Masters thesis]. University of Arkansas; 2014. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/2042.

Council of Science Editors:

Bhuyan SA. Design of a High Performance Silicon Carbide CMOS Operational Amplifier. [Masters Thesis]. University of Arkansas; 2014. Available from: https://scholarworks.uark.edu/etd/2042

University of Tennessee – Knoxville

29. Brantley, Jeremy. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.

Degree: MS, Electrical Engineering, 2012, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/1306

► Testing circuits is a hands-on, time intensive process; it is also one of the most important steps in a design cycle. The most well… (more)

Subjects/Keywords: Labview; Characterization; Model Extraction; Automation; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Brantley, J. (2012). Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/1306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Brantley, Jeremy. “Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.” 2012. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/1306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Brantley, Jeremy. “Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.” 2012. Web. 23 Sep 2019.

Vancouver:

Brantley J. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. [Internet] [Thesis]. University of Tennessee – Knoxville; 2012. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/1306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Brantley J. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. [Thesis]. University of Tennessee – Knoxville; 2012. Available from: https://trace.tennessee.edu/utk_gradthes/1306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Tennessee – Knoxville

30. Watson, Trevor. An Analog CMOS Particle Filter.

Degree: MS, Electrical Engineering, 2017, University of Tennessee – Knoxville

URL: https://trace.tennessee.edu/utk_gradthes/4962

► Particle filters are used in a variety of image processing and machine learning applications. Their main use in these applications is to gather information… (more)

Subjects/Keywords: Analog; CMOS; Machine Learning; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Watson, T. (2017). An Analog CMOS Particle Filter. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/4962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Watson, Trevor. “An Analog CMOS Particle Filter.” 2017. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/4962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Watson, Trevor. “An Analog CMOS Particle Filter.” 2017. Web. 23 Sep 2019.

Vancouver:

Watson T. An Analog CMOS Particle Filter. [Internet] [Thesis]. University of Tennessee – Knoxville; 2017. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/4962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Watson T. An Analog CMOS Particle Filter. [Thesis]. University of Tennessee – Knoxville; 2017. Available from: https://trace.tennessee.edu/utk_gradthes/4962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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Open Access Theses and Dissertations