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You searched for subject:(VLSI AND Circuits Embedded AND Hardware Systems). Showing records 1 – 30 of 204 total matches.

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University of Tennessee – Knoxville

1. Tham, Kevin Vun Kiat. PVT Compensation for Single-Slope Measurement Systems.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

  A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tham, K. V. K. (2011). PVT Compensation for Single-Slope Measurement Systems. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Web. 23 Sep 2019.

Vancouver:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

2. Kilambi, Supriya. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.

Degree: MS, Computer Engineering, 2011, University of Tennessee – Knoxville

 This thesis presents the low power design of a 916MHz Gilbert cell mixer and a Class-A power amplifier for the Bioluminescent Bioreporter Integrated Circuit (BBIC)… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Kilambi, S. (2011). Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Web. 23 Sep 2019.

Vancouver:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

3. Mudhasani, Shanthan. GPU-based Implementation of the Variational Path Integral Method.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

  Any system in the world constitutes particles like electrons. To analyze the behaviors of these systems the behavior of these particles must be predicted.… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Mudhasani, S. (2011). GPU-based Implementation of the Variational Path Integral Method. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Web. 23 Sep 2019.

Vancouver:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cal Poly

4. Zaveri, Jainish K. ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY.

Degree: MS, Electrical Engineering, 2018, Cal Poly

  Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Zaveri, J. K. (2018). ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1940

Chicago Manual of Style (16th Edition):

Zaveri, Jainish K. “ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY.” 2018. Masters Thesis, Cal Poly. Accessed September 23, 2019. https://digitalcommons.calpoly.edu/theses/1940.

MLA Handbook (7th Edition):

Zaveri, Jainish K. “ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY.” 2018. Web. 23 Sep 2019.

Vancouver:

Zaveri JK. ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY. [Internet] [Masters thesis]. Cal Poly; 2018. [cited 2019 Sep 23]. Available from: https://digitalcommons.calpoly.edu/theses/1940.

Council of Science Editors:

Zaveri JK. ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY. [Masters Thesis]. Cal Poly; 2018. Available from: https://digitalcommons.calpoly.edu/theses/1940


Virginia Commonwealth University

5. Khairullah, Shawkat Sabah. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.

Degree: PhD, Electrical & Computer Engineering, 2018, Virginia Commonwealth University

  Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes.… (more)

Subjects/Keywords: Computer and Systems Architecture; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Khairullah, S. S. (2018). Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. (Doctoral Dissertation). Virginia Commonwealth University. Retrieved from https://scholarscompass.vcu.edu/etd/5671

Chicago Manual of Style (16th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Doctoral Dissertation, Virginia Commonwealth University. Accessed September 23, 2019. https://scholarscompass.vcu.edu/etd/5671.

MLA Handbook (7th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Web. 23 Sep 2019.

Vancouver:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Internet] [Doctoral dissertation]. Virginia Commonwealth University; 2018. [cited 2019 Sep 23]. Available from: https://scholarscompass.vcu.edu/etd/5671.

Council of Science Editors:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Doctoral Dissertation]. Virginia Commonwealth University; 2018. Available from: https://scholarscompass.vcu.edu/etd/5671


University of Arkansas

6. McGeehan, Brendan. Hardware IP Classification through Weighted Characteristics.

Degree: MSCmpE, 2019, University of Arkansas

  Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For… (more)

Subjects/Keywords: Classifcation; Hardware; Trojans; Hardware Systems; Information Security; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

McGeehan, B. (2019). Hardware IP Classification through Weighted Characteristics. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3166

Chicago Manual of Style (16th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/3166.

MLA Handbook (7th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Web. 23 Sep 2019.

Vancouver:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/3166.

Council of Science Editors:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3166

7. zhang, xiangyu. ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS.

Degree: 2017, University of Massachusetts

  This study comprises two tasks. The first is to implement gate-level circuit camouflage techniques. The second is to implement the Oracle-guided incremental de-camouflage algorithm… (more)

Subjects/Keywords: Reverse engineer; Algorithm; Hardware; Camouflage; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

zhang, x. (2017). ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

zhang, xiangyu. “ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS.” 2017. Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/masters_theses_2/551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

zhang, xiangyu. “ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS.” 2017. Web. 23 Sep 2019.

Vancouver:

zhang x. ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS. [Internet] [Thesis]. University of Massachusetts; 2017. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/masters_theses_2/551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

zhang x. ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS. [Thesis]. University of Massachusetts; 2017. Available from: https://scholarworks.umass.edu/masters_theses_2/551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boise State University

8. Henderson, Edward Nelson. An Inertial Measurement System for Hand and Finger Tracking.

Degree: 2011, Boise State University

 The primary Human Computer Interfaces (HCI) today are the keyboard and mouse. These interfaces do not facilitate a fluid flow of thought and intent from… (more)

Subjects/Keywords: inertial; glove; IMU; algorithm; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Henderson, E. N. (2011). An Inertial Measurement System for Hand and Finger Tracking. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Henderson, Edward Nelson. “An Inertial Measurement System for Hand and Finger Tracking.” 2011. Thesis, Boise State University. Accessed September 23, 2019. https://scholarworks.boisestate.edu/td/233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Henderson, Edward Nelson. “An Inertial Measurement System for Hand and Finger Tracking.” 2011. Web. 23 Sep 2019.

Vancouver:

Henderson EN. An Inertial Measurement System for Hand and Finger Tracking. [Internet] [Thesis]. Boise State University; 2011. [cited 2019 Sep 23]. Available from: https://scholarworks.boisestate.edu/td/233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Henderson EN. An Inertial Measurement System for Hand and Finger Tracking. [Thesis]. Boise State University; 2011. Available from: https://scholarworks.boisestate.edu/td/233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

9. Barlow, Matthew. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.

Degree: MSEE, 2012, University of Arkansas

  This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1… (more)

Subjects/Keywords: Applied sciences; ASIC; SRAM; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Barlow, M. (2012). Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/362

Chicago Manual of Style (16th Edition):

Barlow, Matthew. “Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.” 2012. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/362.

MLA Handbook (7th Edition):

Barlow, Matthew. “Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications.” 2012. Web. 23 Sep 2019.

Vancouver:

Barlow M. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. [Internet] [Masters thesis]. University of Arkansas; 2012. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/362.

Council of Science Editors:

Barlow M. Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications. [Masters Thesis]. University of Arkansas; 2012. Available from: https://scholarworks.uark.edu/etd/362


University of Tennessee – Knoxville

10. Fandrich, Cory Lynn. An On-Chip Transformer-Based Digital Isolator System.

Degree: MS, Electrical Engineering, 2013, University of Tennessee – Knoxville

  An on-chip transformer-based digital isolator has been designed, fabricated, and tested. This isolation technique is designed to function between a low voltage microcontroller and… (more)

Subjects/Keywords: Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Fandrich, C. L. (2013). An On-Chip Transformer-Based Digital Isolator System. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/2602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fandrich, Cory Lynn. “An On-Chip Transformer-Based Digital Isolator System.” 2013. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/2602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fandrich, Cory Lynn. “An On-Chip Transformer-Based Digital Isolator System.” 2013. Web. 23 Sep 2019.

Vancouver:

Fandrich CL. An On-Chip Transformer-Based Digital Isolator System. [Internet] [Thesis]. University of Tennessee – Knoxville; 2013. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/2602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fandrich CL. An On-Chip Transformer-Based Digital Isolator System. [Thesis]. University of Tennessee – Knoxville; 2013. Available from: https://trace.tennessee.edu/utk_gradthes/2602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Usmani, Mohammad. Applications Of Physical Unclonable Functions on ASICS and FPGAs.

Degree: 2018, University of Massachusetts

  With the ever-increasing demand for security in embedded systems and wireless sensor networks, we require integrating security primitives for authentication in these devices. One… (more)

Subjects/Keywords: Electrical and Computer Engineering; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Usmani, M. (2018). Applications Of Physical Unclonable Functions on ASICS and FPGAs. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Usmani, Mohammad. “Applications Of Physical Unclonable Functions on ASICS and FPGAs.” 2018. Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/masters_theses_2/619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Usmani, Mohammad. “Applications Of Physical Unclonable Functions on ASICS and FPGAs.” 2018. Web. 23 Sep 2019.

Vancouver:

Usmani M. Applications Of Physical Unclonable Functions on ASICS and FPGAs. [Internet] [Thesis]. University of Massachusetts; 2018. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/masters_theses_2/619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Usmani M. Applications Of Physical Unclonable Functions on ASICS and FPGAs. [Thesis]. University of Massachusetts; 2018. Available from: https://scholarworks.umass.edu/masters_theses_2/619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

12. Vanguri, Phani Bharadwaj. An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm.

Degree: MS, Computer Engineering, 2010, University of Tennessee – Knoxville

 Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which… (more)

Subjects/Keywords: stochastic; FPGA; vlsi; simulation; algorithm; hpc; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vanguri, P. B. (2010). An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/837

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vanguri, Phani Bharadwaj. “An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm.” 2010. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/837.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vanguri, Phani Bharadwaj. “An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm.” 2010. Web. 23 Sep 2019.

Vancouver:

Vanguri PB. An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm. [Internet] [Thesis]. University of Tennessee – Knoxville; 2010. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/837.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vanguri PB. An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm. [Thesis]. University of Tennessee – Knoxville; 2010. Available from: https://trace.tennessee.edu/utk_gradthes/837

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Michigan Technological University

13. Zhao, Xueqian. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.

Degree: PhD, Department of Electrical and Computer Engineering, 2018, Michigan Technological University

  To evaluate and verify the functional correction and reliability of circuit designs, circuit components (e.g. resistors, capacitors, etc) need to be accurately modeled (e.g.… (more)

Subjects/Keywords: VLSI; SIMULATION; PRECONDITIONER; GPU; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Zhao, X. (2018). FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. (Doctoral Dissertation). Michigan Technological University. Retrieved from http://digitalcommons.mtu.edu/etdr/637

Chicago Manual of Style (16th Edition):

Zhao, Xueqian. “FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.” 2018. Doctoral Dissertation, Michigan Technological University. Accessed September 23, 2019. http://digitalcommons.mtu.edu/etdr/637.

MLA Handbook (7th Edition):

Zhao, Xueqian. “FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS.” 2018. Web. 23 Sep 2019.

Vancouver:

Zhao X. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. [Internet] [Doctoral dissertation]. Michigan Technological University; 2018. [cited 2019 Sep 23]. Available from: http://digitalcommons.mtu.edu/etdr/637.

Council of Science Editors:

Zhao X. FAST VERY-LARGE-SCALE INTEGRATED (VLSI) CIRCUITS SIMULATIONS. [Doctoral Dissertation]. Michigan Technological University; 2018. Available from: http://digitalcommons.mtu.edu/etdr/637


University of Tennessee – Knoxville

14. Daffron, Christopher Paul. DANNA A Neuromorphic Computing VLSI Chip.

Degree: MS, Computer Engineering, 2015, University of Tennessee – Knoxville

  Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly… (more)

Subjects/Keywords: VLSI; ASIC; Spiking Neural Networks; FPGA; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Daffron, C. P. (2015). DANNA A Neuromorphic Computing VLSI Chip. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/3467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Daffron, Christopher Paul. “DANNA A Neuromorphic Computing VLSI Chip.” 2015. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/3467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Daffron, Christopher Paul. “DANNA A Neuromorphic Computing VLSI Chip.” 2015. Web. 23 Sep 2019.

Vancouver:

Daffron CP. DANNA A Neuromorphic Computing VLSI Chip. [Internet] [Thesis]. University of Tennessee – Knoxville; 2015. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/3467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Daffron CP. DANNA A Neuromorphic Computing VLSI Chip. [Thesis]. University of Tennessee – Knoxville; 2015. Available from: https://trace.tennessee.edu/utk_gradthes/3467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cal Poly

15. YU, RUN BIN. Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz.

Degree: MS, Electrical Engineering, 2016, Cal Poly

  The clock signal is considered as the “heartbeat” of a digital system yet jitter which is a variation on the arrival time of the… (more)

Subjects/Keywords: Jitter reduction; VLSI; Clock; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

YU, R. B. (2016). Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1685

Chicago Manual of Style (16th Edition):

YU, RUN BIN. “Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz.” 2016. Masters Thesis, Cal Poly. Accessed September 23, 2019. https://digitalcommons.calpoly.edu/theses/1685.

MLA Handbook (7th Edition):

YU, RUN BIN. “Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz.” 2016. Web. 23 Sep 2019.

Vancouver:

YU RB. Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz. [Internet] [Masters thesis]. Cal Poly; 2016. [cited 2019 Sep 23]. Available from: https://digitalcommons.calpoly.edu/theses/1685.

Council of Science Editors:

YU RB. Design, analysis and simulation of a Jitter Reduction Circuit (JRC) system at 1GHz. [Masters Thesis]. Cal Poly; 2016. Available from: https://digitalcommons.calpoly.edu/theses/1685


University of Tennessee – Knoxville

16. Yang, Depeng. Turbo Bayesian Compressed Sensing.

Degree: 2011, University of Tennessee – Knoxville

 Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist… (more)

Subjects/Keywords: Compressed Sensing; Hardware Implementation; FPGA; GPU; Signal Processing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Yang, D. (2011). Turbo Bayesian Compressed Sensing. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/1145

Chicago Manual of Style (16th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_graddiss/1145.

MLA Handbook (7th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Web. 23 Sep 2019.

Vancouver:

Yang D. Turbo Bayesian Compressed Sensing. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_graddiss/1145.

Council of Science Editors:

Yang D. Turbo Bayesian Compressed Sensing. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_graddiss/1145

17. Merchant, Murtaza. Testing and Validation of a Prototype Gpgpu Design for FPGAs.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  Due to their suitability for highly parallel and pipelined computation, field programmable gate arrays (FPGAs) and general-purpose graphics processing units (GPGPUs) have emerged as… (more)

Subjects/Keywords: GPGPU; FPGA; hardware acceleration; CUDA compatible; scalable; flexible; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Merchant, M. (2013). Testing and Validation of a Prototype Gpgpu Design for FPGAs. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1012

Chicago Manual of Style (16th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Masters Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/theses/1012.

MLA Handbook (7th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Web. 23 Sep 2019.

Vancouver:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/theses/1012.

Council of Science Editors:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1012


University of Arkansas

18. Mize, Nicholas Renoudet. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.

Degree: MSCmpE, 2019, University of Arkansas

  As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away… (more)

Subjects/Keywords: Asynchronous; Circuit; Digital; MTNCL; Synthesis; VHDL; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mize, N. R. (2019). Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3168

Chicago Manual of Style (16th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/3168.

MLA Handbook (7th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Web. 23 Sep 2019.

Vancouver:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/3168.

Council of Science Editors:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3168


University of Arkansas

19. Munasib, Sharthak. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.

Degree: MSEE, 2017, University of Arkansas

  Proper short-circuit protection in dc distribution systems has provided an austere challenge to researchers as the development of commercially-viable equipment providing fast operation, coordination… (more)

Subjects/Keywords: Applied sciences; Systems and Communications; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Munasib, S. (2017). Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1875

Chicago Manual of Style (16th Edition):

Munasib, Sharthak. “Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.” 2017. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/1875.

MLA Handbook (7th Edition):

Munasib, Sharthak. “Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers.” 2017. Web. 23 Sep 2019.

Vancouver:

Munasib S. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. [Internet] [Masters thesis]. University of Arkansas; 2017. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/1875.

Council of Science Editors:

Munasib S. Short-Circuit Protection for Low-Voltage DC Distribution Systems Based on Solid-State Circuit Breakers. [Masters Thesis]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1875

20. Phanibhushana, Bharath. An Interconnection Network Topology Generation Scheme for Multicore Systems.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  Multi-Processor System on Chip (MPSoC) consisting of multiple processing cores connected via a Network on Chip (NoC) has gained prominence over the last decade.… (more)

Subjects/Keywords: NoC; Multicore; SoC; Realtime systems; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Phanibhushana, B. (2013). An Interconnection Network Topology Generation Scheme for Multicore Systems. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1146

Chicago Manual of Style (16th Edition):

Phanibhushana, Bharath. “An Interconnection Network Topology Generation Scheme for Multicore Systems.” 2013. Masters Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/theses/1146.

MLA Handbook (7th Edition):

Phanibhushana, Bharath. “An Interconnection Network Topology Generation Scheme for Multicore Systems.” 2013. Web. 23 Sep 2019.

Vancouver:

Phanibhushana B. An Interconnection Network Topology Generation Scheme for Multicore Systems. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/theses/1146.

Council of Science Editors:

Phanibhushana B. An Interconnection Network Topology Generation Scheme for Multicore Systems. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1146


University of Nevada – Las Vegas

21. Suseela, Jaya. Parameterizable network-on-chip emulation framework.

Degree: MSE, Electrical Engineering, 2010, University of Nevada – Las Vegas

  Networks-on-Chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. But there is no public accessible HDL synthesizable NoC framework… (more)

Subjects/Keywords: Electrical and Computer Engineering; Systems and Communications; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Suseela, J. (2010). Parameterizable network-on-chip emulation framework. (Masters Thesis). University of Nevada – Las Vegas. Retrieved from https://digitalscholarship.unlv.edu/thesesdissertations/714

Chicago Manual of Style (16th Edition):

Suseela, Jaya. “Parameterizable network-on-chip emulation framework.” 2010. Masters Thesis, University of Nevada – Las Vegas. Accessed September 23, 2019. https://digitalscholarship.unlv.edu/thesesdissertations/714.

MLA Handbook (7th Edition):

Suseela, Jaya. “Parameterizable network-on-chip emulation framework.” 2010. Web. 23 Sep 2019.

Vancouver:

Suseela J. Parameterizable network-on-chip emulation framework. [Internet] [Masters thesis]. University of Nevada – Las Vegas; 2010. [cited 2019 Sep 23]. Available from: https://digitalscholarship.unlv.edu/thesesdissertations/714.

Council of Science Editors:

Suseela J. Parameterizable network-on-chip emulation framework. [Masters Thesis]. University of Nevada – Las Vegas; 2010. Available from: https://digitalscholarship.unlv.edu/thesesdissertations/714

22. Vyas, Shrikant S. Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems.

Degree: 2016, University of Massachusetts

  With the importance of data security at its peak today, many reconfigurable systems are used to provide security. This protection is often provided by… (more)

Subjects/Keywords: Physical Unclonable Functions; FPGAs; Error Correction; Variation Aware; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vyas, S. S. (2016). Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vyas, Shrikant S. “Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems.” 2016. Thesis, University of Massachusetts. Accessed September 23, 2019. https://scholarworks.umass.edu/masters_theses_2/452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vyas, Shrikant S. “Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems.” 2016. Web. 23 Sep 2019.

Vancouver:

Vyas SS. Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems. [Internet] [Thesis]. University of Massachusetts; 2016. [cited 2019 Sep 23]. Available from: https://scholarworks.umass.edu/masters_theses_2/452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vyas SS. Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems. [Thesis]. University of Massachusetts; 2016. Available from: https://scholarworks.umass.edu/masters_theses_2/452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Kentucky

23. Jacobs, Zachary A. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.

Degree: 2013, University of Kentucky

 The CubeLab is a new payload standard that greatly improves access to the International Space Station (ISS) for small, rapid turn-around microgravity experiments. CubeLabs are… (more)

Subjects/Keywords: CubeSat; CubeLab; NanoRacks; Plug and Play; Distributed Computing; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jacobs, Z. A. (2013). PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/16

Chicago Manual of Style (16th Edition):

Jacobs, Zachary A. “PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.” 2013. Masters Thesis, University of Kentucky. Accessed September 23, 2019. http://uknowledge.uky.edu/ece_etds/16.

MLA Handbook (7th Edition):

Jacobs, Zachary A. “PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION.” 2013. Web. 23 Sep 2019.

Vancouver:

Jacobs ZA. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2019 Sep 23]. Available from: http://uknowledge.uky.edu/ece_etds/16.

Council of Science Editors:

Jacobs ZA. PROVIDING A PERSISTENT SPACE PLUG-AND-PLAY AVIONICS NETWORK ON THE INTERNATIONAL SPACE STATION. [Masters Thesis]. University of Kentucky; 2013. Available from: http://uknowledge.uky.edu/ece_etds/16


University of Kentucky

24. Zhang, Xiaowei. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.

Degree: 2015, University of Kentucky

 SRAM is a significant component in high speed computer design, which serves mainly as high speed storage elements like register files in microprocessors, or the… (more)

Subjects/Keywords: SRAM; Timing Parameters; SPICE; Liberty File; DFF; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Zhang, X. (2015). A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/75

Chicago Manual of Style (16th Edition):

Zhang, Xiaowei. “A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.” 2015. Masters Thesis, University of Kentucky. Accessed September 23, 2019. http://uknowledge.uky.edu/ece_etds/75.

MLA Handbook (7th Edition):

Zhang, Xiaowei. “A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION.” 2015. Web. 23 Sep 2019.

Vancouver:

Zhang X. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. [Internet] [Masters thesis]. University of Kentucky; 2015. [cited 2019 Sep 23]. Available from: http://uknowledge.uky.edu/ece_etds/75.

Council of Science Editors:

Zhang X. A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION. [Masters Thesis]. University of Kentucky; 2015. Available from: http://uknowledge.uky.edu/ece_etds/75


University of Western Ontario

25. Hariri, Arash. Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability.

Degree: 2010, University of Western Ontario

 The elliptic curve cryptography is an important branch in public-key cryptography. In this thesis, we consider the elliptic curve cryptography over binary extension fields from… (more)

Subjects/Keywords: Finite Field Arithmetic; Elliptic Curve Cryptography; Montgomery Multiplication; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Hariri, A. (2010). Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability. (Thesis). University of Western Ontario. Retrieved from https://ir.lib.uwo.ca/etd/75

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hariri, Arash. “Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability.” 2010. Thesis, University of Western Ontario. Accessed September 23, 2019. https://ir.lib.uwo.ca/etd/75.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hariri, Arash. “Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability.” 2010. Web. 23 Sep 2019.

Vancouver:

Hariri A. Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability. [Internet] [Thesis]. University of Western Ontario; 2010. [cited 2019 Sep 23]. Available from: https://ir.lib.uwo.ca/etd/75.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hariri A. Arithmetic Units for the Elliptic Curve Cryptography with Concurrent Error Detection Capability. [Thesis]. University of Western Ontario; 2010. Available from: https://ir.lib.uwo.ca/etd/75

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boise State University

26. Pook, Michael. A Small Acoustic Goniometer for General Purpose Research.

Degree: 2015, Boise State University

 Understanding acoustic events and monitoring their occurrence is a useful aspect of many research projects. In particular, acoustic goniometry allows researchers to determine the source… (more)

Subjects/Keywords: Acoustic Goniometer; infrasound; general purpose; real-time; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pook, M. (2015). A Small Acoustic Goniometer for General Purpose Research. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/1052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pook, Michael. “A Small Acoustic Goniometer for General Purpose Research.” 2015. Thesis, Boise State University. Accessed September 23, 2019. https://scholarworks.boisestate.edu/td/1052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pook, Michael. “A Small Acoustic Goniometer for General Purpose Research.” 2015. Web. 23 Sep 2019.

Vancouver:

Pook M. A Small Acoustic Goniometer for General Purpose Research. [Internet] [Thesis]. Boise State University; 2015. [cited 2019 Sep 23]. Available from: https://scholarworks.boisestate.edu/td/1052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pook M. A Small Acoustic Goniometer for General Purpose Research. [Thesis]. Boise State University; 2015. Available from: https://scholarworks.boisestate.edu/td/1052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

27. Williams, Ethan Storm. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.

Degree: MSEE, 2016, University of Arkansas

  A new assistive technology switch for people with disabilities was developed utilizing an Inertial Measurement Unit (IMU) as the sensor technology. The hardware can… (more)

Subjects/Keywords: Applied sciences; Assistive technology; Inertial measurement unit; Biomedical; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Williams, E. S. (2016). Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1503

Chicago Manual of Style (16th Edition):

Williams, Ethan Storm. “Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.” 2016. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/1503.

MLA Handbook (7th Edition):

Williams, Ethan Storm. “Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit.” 2016. Web. 23 Sep 2019.

Vancouver:

Williams ES. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/1503.

Council of Science Editors:

Williams ES. Design of an Assistive Technology Adaptive Switch using an Inertial Measurement Unit. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1503


University of Arkansas

28. Bhuyan, Shaila Amin. Design of a High Performance Silicon Carbide CMOS Operational Amplifier.

Degree: MSEE, 2014, University of Arkansas

  This thesis presents the design, simulation, layout and test results of a silicon carbide (SiC) CMOS two-stage operational amplifier (op amp) with NMOS input… (more)

Subjects/Keywords: Electronic Devices and Semiconductor Manufacturing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Bhuyan, S. A. (2014). Design of a High Performance Silicon Carbide CMOS Operational Amplifier. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2042

Chicago Manual of Style (16th Edition):

Bhuyan, Shaila Amin. “Design of a High Performance Silicon Carbide CMOS Operational Amplifier.” 2014. Masters Thesis, University of Arkansas. Accessed September 23, 2019. https://scholarworks.uark.edu/etd/2042.

MLA Handbook (7th Edition):

Bhuyan, Shaila Amin. “Design of a High Performance Silicon Carbide CMOS Operational Amplifier.” 2014. Web. 23 Sep 2019.

Vancouver:

Bhuyan SA. Design of a High Performance Silicon Carbide CMOS Operational Amplifier. [Internet] [Masters thesis]. University of Arkansas; 2014. [cited 2019 Sep 23]. Available from: https://scholarworks.uark.edu/etd/2042.

Council of Science Editors:

Bhuyan SA. Design of a High Performance Silicon Carbide CMOS Operational Amplifier. [Masters Thesis]. University of Arkansas; 2014. Available from: https://scholarworks.uark.edu/etd/2042


University of Tennessee – Knoxville

29. Brantley, Jeremy. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.

Degree: MS, Electrical Engineering, 2012, University of Tennessee – Knoxville

  Testing circuits is a hands-on, time intensive process; it is also one of the most important steps in a design cycle. The most well… (more)

Subjects/Keywords: Labview; Characterization; Model Extraction; Automation; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Brantley, J. (2012). Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/1306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Brantley, Jeremy. “Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.” 2012. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/1306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Brantley, Jeremy. “Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation.” 2012. Web. 23 Sep 2019.

Vancouver:

Brantley J. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. [Internet] [Thesis]. University of Tennessee – Knoxville; 2012. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/1306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Brantley J. Analog Testing, Characterization, and Low-Order Model Extraction using LabVIEW Automation. [Thesis]. University of Tennessee – Knoxville; 2012. Available from: https://trace.tennessee.edu/utk_gradthes/1306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

30. Watson, Trevor. An Analog CMOS Particle Filter.

Degree: MS, Electrical Engineering, 2017, University of Tennessee – Knoxville

  Particle filters are used in a variety of image processing and machine learning applications. Their main use in these applications is to gather information… (more)

Subjects/Keywords: Analog; CMOS; Machine Learning; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Watson, T. (2017). An Analog CMOS Particle Filter. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/4962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Watson, Trevor. “An Analog CMOS Particle Filter.” 2017. Thesis, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_gradthes/4962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Watson, Trevor. “An Analog CMOS Particle Filter.” 2017. Web. 23 Sep 2019.

Vancouver:

Watson T. An Analog CMOS Particle Filter. [Internet] [Thesis]. University of Tennessee – Knoxville; 2017. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_gradthes/4962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Watson T. An Analog CMOS Particle Filter. [Thesis]. University of Tennessee – Knoxville; 2017. Available from: https://trace.tennessee.edu/utk_gradthes/4962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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