Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(VLSI Architecture). Showing records 1 – 30 of 57 total matches.

[1] [2]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

▼ Search Limiters


Texas A&M University

1. Wang, Qian. Architectures and Design of VLSI Machine Learning Systems.

Degree: PhD, Computer Engineering, 2016, Texas A&M University

 Quintillions of bytes of data are generated every day in this era of big data. Machine learning techniques are utilized to perform predictive analysis on… (more)

Subjects/Keywords: Machine learning; VLSI architecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, Q. (2016). Architectures and Design of VLSI Machine Learning Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/158093

Chicago Manual of Style (16th Edition):

Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Doctoral Dissertation, Texas A&M University. Accessed October 20, 2019. http://hdl.handle.net/1969.1/158093.

MLA Handbook (7th Edition):

Wang, Qian. “Architectures and Design of VLSI Machine Learning Systems.” 2016. Web. 20 Oct 2019.

Vancouver:

Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1969.1/158093.

Council of Science Editors:

Wang Q. Architectures and Design of VLSI Machine Learning Systems. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/158093


Cornell University

2. Lockhart, Derek. Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization .

Degree: 2015, Cornell University

 The growing complexity and heterogeneity of modern application-specific integrated circuits has made hardware design methodologies a limiting factor in the construction of future computing systems.… (more)

Subjects/Keywords: Hardware Design Methodologies; Computer Architecture; VLSI

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lockhart, D. (2015). Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/40914

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lockhart, Derek. “Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization .” 2015. Thesis, Cornell University. Accessed October 20, 2019. http://hdl.handle.net/1813/40914.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lockhart, Derek. “Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization .” 2015. Web. 20 Oct 2019.

Vancouver:

Lockhart D. Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization . [Internet] [Thesis]. Cornell University; 2015. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1813/40914.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lockhart D. Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization . [Thesis]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/40914

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

3. Kim, Sangmin. Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

 This thesis proposes efficient algorithm and architecture aspects for binary and nonbinary low- density parity-check (LDPC) codes by developing optimal quantization approaches, decoding algorithms, decoding… (more)

Subjects/Keywords: Architecture; Decoding; LDPC; VLSI; Electrical Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, S. (2010). Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/96825

Chicago Manual of Style (16th Edition):

Kim, Sangmin. “Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.” 2010. Doctoral Dissertation, University of Minnesota. Accessed October 20, 2019. http://purl.umn.edu/96825.

MLA Handbook (7th Edition):

Kim, Sangmin. “Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.” 2010. Web. 20 Oct 2019.

Vancouver:

Kim S. Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2019 Oct 20]. Available from: http://purl.umn.edu/96825.

Council of Science Editors:

Kim S. Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://purl.umn.edu/96825


Delft University of Technology

4. Jonker, P.P. Morphological image processing: Architecture and VLSI design.

Degree: 1992, Delft University of Technology

Subjects/Keywords: computer architecture; VLSI

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jonker, P. P. (1992). Morphological image processing: Architecture and VLSI design. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; urn:NBN:nl:ui:24-uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; urn:NBN:nl:ui:24-uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; http://resolver.tudelft.nl/uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d

Chicago Manual of Style (16th Edition):

Jonker, P P. “Morphological image processing: Architecture and VLSI design.” 1992. Doctoral Dissertation, Delft University of Technology. Accessed October 20, 2019. http://resolver.tudelft.nl/uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; urn:NBN:nl:ui:24-uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; urn:NBN:nl:ui:24-uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; http://resolver.tudelft.nl/uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d.

MLA Handbook (7th Edition):

Jonker, P P. “Morphological image processing: Architecture and VLSI design.” 1992. Web. 20 Oct 2019.

Vancouver:

Jonker PP. Morphological image processing: Architecture and VLSI design. [Internet] [Doctoral dissertation]. Delft University of Technology; 1992. [cited 2019 Oct 20]. Available from: http://resolver.tudelft.nl/uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; urn:NBN:nl:ui:24-uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; urn:NBN:nl:ui:24-uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; http://resolver.tudelft.nl/uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d.

Council of Science Editors:

Jonker PP. Morphological image processing: Architecture and VLSI design. [Doctoral Dissertation]. Delft University of Technology; 1992. Available from: http://resolver.tudelft.nl/uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; urn:NBN:nl:ui:24-uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; urn:NBN:nl:ui:24-uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d ; http://resolver.tudelft.nl/uuid:f3a2b8ff-5b9b-4180-9504-9e054699e73d


Université Montpellier II

5. Cargnini, Luís Vitório. Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy.

Degree: Docteur es, SYAM - Systèmes Automatiques et Microélectroniques, 2013, Université Montpellier II

 Le secteur Semi-conducteurs avec l'avènement de fabrication submicroniques coule dessous de 45 nm ont commencé à relever de nouveaux défis pour continuer à évoluer en… (more)

Subjects/Keywords: Architecture de Processeur; Mram; Vlsi; Hiérarchie Mémoire; Semiconductors; Systèmes sur Puce; Processor Architecture; Mram; Vlsi; Memory Hierarchy; Semiconductors; System on Chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cargnini, L. V. (2013). Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy. (Doctoral Dissertation). Université Montpellier II. Retrieved from http://www.theses.fr/2013MON20091

Chicago Manual of Style (16th Edition):

Cargnini, Luís Vitório. “Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy.” 2013. Doctoral Dissertation, Université Montpellier II. Accessed October 20, 2019. http://www.theses.fr/2013MON20091.

MLA Handbook (7th Edition):

Cargnini, Luís Vitório. “Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy.” 2013. Web. 20 Oct 2019.

Vancouver:

Cargnini LV. Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy. [Internet] [Doctoral dissertation]. Université Montpellier II; 2013. [cited 2019 Oct 20]. Available from: http://www.theses.fr/2013MON20091.

Council of Science Editors:

Cargnini LV. Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy. [Doctoral Dissertation]. Université Montpellier II; 2013. Available from: http://www.theses.fr/2013MON20091

6. Saini, Ravi. Application specific VLSI processor design for parametric speech synthesis; -.

Degree: Electronic Science, 2012, Kurukshetra University

Application Specific Instruction set Processor (ASIP) is a comparatively new approach to realize programmable processors which for the targeted application domain can deliver very significant… (more)

Subjects/Keywords: Electronic Science; Architectures; Computer Architecture; VLSI processor; speech synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Saini, R. (2012). Application specific VLSI processor design for parametric speech synthesis; -. (Thesis). Kurukshetra University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/9752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Saini, Ravi. “Application specific VLSI processor design for parametric speech synthesis; -.” 2012. Thesis, Kurukshetra University. Accessed October 20, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/9752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Saini, Ravi. “Application specific VLSI processor design for parametric speech synthesis; -.” 2012. Web. 20 Oct 2019.

Vancouver:

Saini R. Application specific VLSI processor design for parametric speech synthesis; -. [Internet] [Thesis]. Kurukshetra University; 2012. [cited 2019 Oct 20]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/9752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Saini R. Application specific VLSI processor design for parametric speech synthesis; -. [Thesis]. Kurukshetra University; 2012. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/9752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

7. Toriyama, Yuta. High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes.

Degree: Electrical Engineering, 2016, UCLA

 Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the… (more)

Subjects/Keywords: Electrical engineering; ASIC; Digital Architecture; LDPC; Min-Max; Nonbinary; VLSI

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Toriyama, Y. (2016). High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/42c0g73r

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Toriyama, Yuta. “High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes.” 2016. Thesis, UCLA. Accessed October 20, 2019. http://www.escholarship.org/uc/item/42c0g73r.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Toriyama, Yuta. “High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes.” 2016. Web. 20 Oct 2019.

Vancouver:

Toriyama Y. High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes. [Internet] [Thesis]. UCLA; 2016. [cited 2019 Oct 20]. Available from: http://www.escholarship.org/uc/item/42c0g73r.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Toriyama Y. High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes. [Thesis]. UCLA; 2016. Available from: http://www.escholarship.org/uc/item/42c0g73r

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rice University

8. Wang, Guohui. Design Space Exploration of Parallel Algorithms and Architectures for Wireless Communication and Mobile Computing Systems.

Degree: PhD, Engineering, 2014, Rice University

 During past several years, there has been a trend that the modern mobile SoC (system-on-chip) chipsets start to incorporate in one single chip the functionality… (more)

Subjects/Keywords: Mobile computing; parallel algorithm; parallel architecture; VLSI; GPU

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, G. (2014). Design Space Exploration of Parallel Algorithms and Architectures for Wireless Communication and Mobile Computing Systems. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/88381

Chicago Manual of Style (16th Edition):

Wang, Guohui. “Design Space Exploration of Parallel Algorithms and Architectures for Wireless Communication and Mobile Computing Systems.” 2014. Doctoral Dissertation, Rice University. Accessed October 20, 2019. http://hdl.handle.net/1911/88381.

MLA Handbook (7th Edition):

Wang, Guohui. “Design Space Exploration of Parallel Algorithms and Architectures for Wireless Communication and Mobile Computing Systems.” 2014. Web. 20 Oct 2019.

Vancouver:

Wang G. Design Space Exploration of Parallel Algorithms and Architectures for Wireless Communication and Mobile Computing Systems. [Internet] [Doctoral dissertation]. Rice University; 2014. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1911/88381.

Council of Science Editors:

Wang G. Design Space Exploration of Parallel Algorithms and Architectures for Wireless Communication and Mobile Computing Systems. [Doctoral Dissertation]. Rice University; 2014. Available from: http://hdl.handle.net/1911/88381


Universidade do Rio Grande do Norte

9. Duarte, José Marcelo Lima. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .

Degree: 2012, Universidade do Rio Grande do Norte

 The use of Multiple Input Multiple Output (MIMO) systems has permitted the recent evolution of wireless communication standards. The Spatial Multiplexing MIMO technique, in particular,… (more)

Subjects/Keywords: MIMO; deteccão; demodulacão; processamento digital de sinais; arquitetura; VLSI; ASIC; FPGA; MIMO; detection; demodulation; digital signal processing; architecture; VLSI; ASIC; FPGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Duarte, J. M. L. (2012). Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . (Doctoral Dissertation). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18575

Chicago Manual of Style (16th Edition):

Duarte, José Marcelo Lima. “Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .” 2012. Doctoral Dissertation, Universidade do Rio Grande do Norte. Accessed October 20, 2019. http://repositorio.ufrn.br/handle/123456789/18575.

MLA Handbook (7th Edition):

Duarte, José Marcelo Lima. “Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .” 2012. Web. 20 Oct 2019.

Vancouver:

Duarte JML. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . [Internet] [Doctoral dissertation]. Universidade do Rio Grande do Norte; 2012. [cited 2019 Oct 20]. Available from: http://repositorio.ufrn.br/handle/123456789/18575.

Council of Science Editors:

Duarte JML. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . [Doctoral Dissertation]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/18575


Universidade do Rio Grande do Norte

10. Duarte, José Marcelo Lima. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .

Degree: 2012, Universidade do Rio Grande do Norte

 The use of Multiple Input Multiple Output (MIMO) systems has permitted the recent evolution of wireless communication standards. The Spatial Multiplexing MIMO technique, in particular,… (more)

Subjects/Keywords: MIMO; deteccão; demodulacão; processamento digital de sinais; arquitetura; VLSI; ASIC; FPGA; MIMO; detection; demodulation; digital signal processing; architecture; VLSI; ASIC; FPGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Duarte, J. M. L. (2012). Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18575

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Duarte, José Marcelo Lima. “Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .” 2012. Thesis, Universidade do Rio Grande do Norte. Accessed October 20, 2019. http://repositorio.ufrn.br/handle/123456789/18575.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Duarte, José Marcelo Lima. “Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .” 2012. Web. 20 Oct 2019.

Vancouver:

Duarte JML. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2012. [cited 2019 Oct 20]. Available from: http://repositorio.ufrn.br/handle/123456789/18575.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Duarte JML. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . [Thesis]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/18575

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

11. Walter, Fábio Leandro. Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264.

Degree: 2011, Universidade do Rio Grande do Sul

Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC… (more)

Subjects/Keywords: VLSI architecture; Vídeo digital; Codificacao : Video digital; Low-power CMOS; Intra-only decoder; Clock gating

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Walter, F. L. (2011). Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/67848

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Walter, Fábio Leandro. “Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264.” 2011. Thesis, Universidade do Rio Grande do Sul. Accessed October 20, 2019. http://hdl.handle.net/10183/67848.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Walter, Fábio Leandro. “Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264.” 2011. Web. 20 Oct 2019.

Vancouver:

Walter FL. Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2011. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/10183/67848.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Walter FL. Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264. [Thesis]. Universidade do Rio Grande do Sul; 2011. Available from: http://hdl.handle.net/10183/67848

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Commonwealth University

12. Khairullah, Shawkat Sabah. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.

Degree: PhD, Electrical & Computer Engineering, 2018, Virginia Commonwealth University

  Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes.… (more)

Subjects/Keywords: Computer and Systems Architecture; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khairullah, S. S. (2018). Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. (Doctoral Dissertation). Virginia Commonwealth University. Retrieved from https://scholarscompass.vcu.edu/etd/5671

Chicago Manual of Style (16th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Doctoral Dissertation, Virginia Commonwealth University. Accessed October 20, 2019. https://scholarscompass.vcu.edu/etd/5671.

MLA Handbook (7th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Web. 20 Oct 2019.

Vancouver:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Internet] [Doctoral dissertation]. Virginia Commonwealth University; 2018. [cited 2019 Oct 20]. Available from: https://scholarscompass.vcu.edu/etd/5671.

Council of Science Editors:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Doctoral Dissertation]. Virginia Commonwealth University; 2018. Available from: https://scholarscompass.vcu.edu/etd/5671

13. Buckler, Mark. Network-on-Chip Synchronization.

Degree: 2014, University of Massachusetts

  Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using… (more)

Subjects/Keywords: Network-on-Chip; Synchronizer; VLSI; Computer and Systems Architecture; Digital Circuits; Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Buckler, M. (2014). Network-on-Chip Synchronization. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/74

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Buckler, Mark. “Network-on-Chip Synchronization.” 2014. Thesis, University of Massachusetts. Accessed October 20, 2019. https://scholarworks.umass.edu/masters_theses_2/74.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Buckler, Mark. “Network-on-Chip Synchronization.” 2014. Web. 20 Oct 2019.

Vancouver:

Buckler M. Network-on-Chip Synchronization. [Internet] [Thesis]. University of Massachusetts; 2014. [cited 2019 Oct 20]. Available from: https://scholarworks.umass.edu/masters_theses_2/74.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Buckler M. Network-on-Chip Synchronization. [Thesis]. University of Massachusetts; 2014. Available from: https://scholarworks.umass.edu/masters_theses_2/74

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Madhavan, Advait. Abusing Hardware Race Conditions for High Throughput Energy Efficient Computation.

Degree: 2016, University of California – eScholarship, University of California

 We propose a novel computing approach, called “Race Logic”, which utilizes a new data representation to accelerate a broad class of optimization problems, such as… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Approximate Computing; Computer Architecture; Race Conditions; Temporal Computation; VLSI

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Madhavan, A. (2016). Abusing Hardware Race Conditions for High Throughput Energy Efficient Computation. (Thesis). University of California – eScholarship, University of California. Retrieved from http://www.escholarship.org/uc/item/5263j7b1

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Madhavan, Advait. “Abusing Hardware Race Conditions for High Throughput Energy Efficient Computation.” 2016. Thesis, University of California – eScholarship, University of California. Accessed October 20, 2019. http://www.escholarship.org/uc/item/5263j7b1.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Madhavan, Advait. “Abusing Hardware Race Conditions for High Throughput Energy Efficient Computation.” 2016. Web. 20 Oct 2019.

Vancouver:

Madhavan A. Abusing Hardware Race Conditions for High Throughput Energy Efficient Computation. [Internet] [Thesis]. University of California – eScholarship, University of California; 2016. [cited 2019 Oct 20]. Available from: http://www.escholarship.org/uc/item/5263j7b1.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Madhavan A. Abusing Hardware Race Conditions for High Throughput Energy Efficient Computation. [Thesis]. University of California – eScholarship, University of California; 2016. Available from: http://www.escholarship.org/uc/item/5263j7b1

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

15. Martins, André Luis Del Mestre. Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC.

Degree: 2011, Universidade do Rio Grande do Sul

O codificador aritmético binário adaptativo ao contexto adotado (CABAC – Context-based Adaptive Binary Arithmetic Coding) pelo padrão H.264/AVC a partir de perfil Main é o… (more)

Subjects/Keywords: Microeletrônica; Binarization and context modeling; Entropy encoding; Vlsi; Compressao : Video; VLSI dedicated architecture; Context-based adaptive binary arithmetic coding; H.264/AVC video compression

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Martins, A. L. D. M. (2011). Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/28742

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Martins, André Luis Del Mestre. “Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC.” 2011. Thesis, Universidade do Rio Grande do Sul. Accessed October 20, 2019. http://hdl.handle.net/10183/28742.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Martins, André Luis Del Mestre. “Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC.” 2011. Web. 20 Oct 2019.

Vancouver:

Martins ALDM. Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2011. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/10183/28742.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Martins ALDM. Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC. [Thesis]. Universidade do Rio Grande do Sul; 2011. Available from: http://hdl.handle.net/10183/28742

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boise State University

16. Wu, Xinyu. Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing.

Degree: 2016, Boise State University

 Human society is now facing grand challenges to satisfy the growing demand for computing power, at the same time, sustain energy consumption. By the end… (more)

Subjects/Keywords: neuromorphic; spiking neural network; VLSI; emerging memory device; machine learning; pattern recongnition; Bioelectrical and Neuroengineering; Computer and Systems Architecture; Nanoscience and Nanotechnology; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, X. (2016). Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/1239

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Xinyu. “Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing.” 2016. Thesis, Boise State University. Accessed October 20, 2019. https://scholarworks.boisestate.edu/td/1239.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Xinyu. “Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing.” 2016. Web. 20 Oct 2019.

Vancouver:

Wu X. Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing. [Internet] [Thesis]. Boise State University; 2016. [cited 2019 Oct 20]. Available from: https://scholarworks.boisestate.edu/td/1239.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu X. Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing. [Thesis]. Boise State University; 2016. Available from: https://scholarworks.boisestate.edu/td/1239

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

17. KATAM, SHRAVANTHI. A SCALABLE ARCHITECTURE FOR HIGH SPEED DNA PATTERN MATCHING.

Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati

 The DNA sequence databases have been doubling in size every 18 months or so. This has forced the development of software and hardware systems for… (more)

Subjects/Keywords: DNA pattern matching; VLSI architecture; Hardnare Pattern Matching

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

KATAM, S. (2002). A SCALABLE ARCHITECTURE FOR HIGH SPEED DNA PATTERN MATCHING. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1021910429

Chicago Manual of Style (16th Edition):

KATAM, SHRAVANTHI. “A SCALABLE ARCHITECTURE FOR HIGH SPEED DNA PATTERN MATCHING.” 2002. Masters Thesis, University of Cincinnati. Accessed October 20, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1021910429.

MLA Handbook (7th Edition):

KATAM, SHRAVANTHI. “A SCALABLE ARCHITECTURE FOR HIGH SPEED DNA PATTERN MATCHING.” 2002. Web. 20 Oct 2019.

Vancouver:

KATAM S. A SCALABLE ARCHITECTURE FOR HIGH SPEED DNA PATTERN MATCHING. [Internet] [Masters thesis]. University of Cincinnati; 2002. [cited 2019 Oct 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1021910429.

Council of Science Editors:

KATAM S. A SCALABLE ARCHITECTURE FOR HIGH SPEED DNA PATTERN MATCHING. [Masters Thesis]. University of Cincinnati; 2002. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1021910429


University of Cincinnati

18. MAL, PROSENJIT. DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE.

Degree: PhD, Engineering : Electrical Engineering, 2004, University of Cincinnati

 In the last and present decade, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics and communication industry. Though the FPGA… (more)

Subjects/Keywords: FPGA; MULTI-TECHNOLOGY; ARCHITECTURE; CMOS; VLSI; CIRCUIT; PHOTORECEIVER; RECONFIGURABLEE

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

MAL, P. (2004). DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1081274672

Chicago Manual of Style (16th Edition):

MAL, PROSENJIT. “DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE.” 2004. Doctoral Dissertation, University of Cincinnati. Accessed October 20, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1081274672.

MLA Handbook (7th Edition):

MAL, PROSENJIT. “DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE.” 2004. Web. 20 Oct 2019.

Vancouver:

MAL P. DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE. [Internet] [Doctoral dissertation]. University of Cincinnati; 2004. [cited 2019 Oct 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1081274672.

Council of Science Editors:

MAL P. DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE. [Doctoral Dissertation]. University of Cincinnati; 2004. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1081274672


Case Western Reserve University

19. Chen, Bainan. Hardware Implementation of Error Control Decoders.

Degree: MSs, Computer Engineering, 2008, Case Western Reserve University

  In this thesis, an FPGA implementation of a factorization processor for algebraic soft-decision Reed-Solomon (RS) decoding is first presented. The design is based on… (more)

Subjects/Keywords: Electrical Engineering; Reed-Solomon codes; factorization; algebraic soft-decision decoding; BCH codes; VLSI architecture; flash memory

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, B. (2008). Hardware Implementation of Error Control Decoders. (Masters Thesis). Case Western Reserve University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1209531418

Chicago Manual of Style (16th Edition):

Chen, Bainan. “Hardware Implementation of Error Control Decoders.” 2008. Masters Thesis, Case Western Reserve University. Accessed October 20, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=case1209531418.

MLA Handbook (7th Edition):

Chen, Bainan. “Hardware Implementation of Error Control Decoders.” 2008. Web. 20 Oct 2019.

Vancouver:

Chen B. Hardware Implementation of Error Control Decoders. [Internet] [Masters thesis]. Case Western Reserve University; 2008. [cited 2019 Oct 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1209531418.

Council of Science Editors:

Chen B. Hardware Implementation of Error Control Decoders. [Masters Thesis]. Case Western Reserve University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1209531418


UCLA

20. Ren, Fengbo. A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems.

Degree: Electrical Engineering, 2014, UCLA

 Digital electronic industry today relies on Nyquist sampling theorem, which requires to double the size (sampling rate) of the signal representation on the Fourier basis… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Compressive Sensing; Energy-Efficient Design; Integrated Circuit; Sparse Approximation; VLSI Architecture; Wireless Health

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ren, F. (2014). A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/73p6w2zv

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ren, Fengbo. “A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems.” 2014. Thesis, UCLA. Accessed October 20, 2019. http://www.escholarship.org/uc/item/73p6w2zv.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ren, Fengbo. “A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems.” 2014. Web. 20 Oct 2019.

Vancouver:

Ren F. A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems. [Internet] [Thesis]. UCLA; 2014. [cited 2019 Oct 20]. Available from: http://www.escholarship.org/uc/item/73p6w2zv.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ren F. A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/73p6w2zv

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

21. Liang, Getao. ARITHMETIC LOGIC UNIT ARCHITECTURES WITH DYNAMICALLY DEFINED PRECISION.

Degree: 2015, University of Tennessee – Knoxville

 Modern central processing units (CPUs) employ arithmetic logic units (ALUs) that support statically defined precisions, often adhering to industry standards. Although CPU manufacturers highly optimize… (more)

Subjects/Keywords: Dynamic Precision; Floating-Point; ALU; SIMD; Computer and Systems Architecture; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liang, G. (2015). ARITHMETIC LOGIC UNIT ARCHITECTURES WITH DYNAMICALLY DEFINED PRECISION. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/3592

Chicago Manual of Style (16th Edition):

Liang, Getao. “ARITHMETIC LOGIC UNIT ARCHITECTURES WITH DYNAMICALLY DEFINED PRECISION.” 2015. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed October 20, 2019. https://trace.tennessee.edu/utk_graddiss/3592.

MLA Handbook (7th Edition):

Liang, Getao. “ARITHMETIC LOGIC UNIT ARCHITECTURES WITH DYNAMICALLY DEFINED PRECISION.” 2015. Web. 20 Oct 2019.

Vancouver:

Liang G. ARITHMETIC LOGIC UNIT ARCHITECTURES WITH DYNAMICALLY DEFINED PRECISION. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2015. [cited 2019 Oct 20]. Available from: https://trace.tennessee.edu/utk_graddiss/3592.

Council of Science Editors:

Liang G. ARITHMETIC LOGIC UNIT ARCHITECTURES WITH DYNAMICALLY DEFINED PRECISION. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2015. Available from: https://trace.tennessee.edu/utk_graddiss/3592

22. Jain, Abhinna. Computational Delay in Vehicles and Its Effect on Real Time Scheduling.

Degree: MSin Electrical and Computer Engineering (M.S.E.C.E.), Electrical & Computer Engineering, 2012, U of Massachusetts : Masters

  Present research into critical embedded control systems tends to focus on the computational elements and largely ignore the link between the computational and physical… (more)

Subjects/Keywords: CPS; Real time systems; delay; scheduling; dvs; cost function; Computer and Systems Architecture; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jain, A. (2012). Computational Delay in Vehicles and Its Effect on Real Time Scheduling. (Masters Thesis). U of Massachusetts : Masters. Retrieved from http://scholarworks.umass.edu/theses/823

Chicago Manual of Style (16th Edition):

Jain, Abhinna. “Computational Delay in Vehicles and Its Effect on Real Time Scheduling.” 2012. Masters Thesis, U of Massachusetts : Masters. Accessed October 20, 2019. http://scholarworks.umass.edu/theses/823.

MLA Handbook (7th Edition):

Jain, Abhinna. “Computational Delay in Vehicles and Its Effect on Real Time Scheduling.” 2012. Web. 20 Oct 2019.

Vancouver:

Jain A. Computational Delay in Vehicles and Its Effect on Real Time Scheduling. [Internet] [Masters thesis]. U of Massachusetts : Masters; 2012. [cited 2019 Oct 20]. Available from: http://scholarworks.umass.edu/theses/823.

Council of Science Editors:

Jain A. Computational Delay in Vehicles and Its Effect on Real Time Scheduling. [Masters Thesis]. U of Massachusetts : Masters; 2012. Available from: http://scholarworks.umass.edu/theses/823

23. Chhablani, Mayank. PROCESSOR TEMPERATURE AND RELIABILITY ESTIMATION USING ACTIVITY COUNTERS.

Degree: 2016, University of Massachusetts

  With the advent of technology scaling lifetime reliability is an emerging threat in high-performance and deadline-critical systems. High on-chip thermal gradients accelerates localised thermal… (more)

Subjects/Keywords: Reliability Estimation; Temperature Monitoring; Performance Counters; Localized hotspots; Temperature Estimation; Computer and Systems Architecture; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chhablani, M. (2016). PROCESSOR TEMPERATURE AND RELIABILITY ESTIMATION USING ACTIVITY COUNTERS. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chhablani, Mayank. “PROCESSOR TEMPERATURE AND RELIABILITY ESTIMATION USING ACTIVITY COUNTERS.” 2016. Thesis, University of Massachusetts. Accessed October 20, 2019. https://scholarworks.umass.edu/masters_theses_2/318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chhablani, Mayank. “PROCESSOR TEMPERATURE AND RELIABILITY ESTIMATION USING ACTIVITY COUNTERS.” 2016. Web. 20 Oct 2019.

Vancouver:

Chhablani M. PROCESSOR TEMPERATURE AND RELIABILITY ESTIMATION USING ACTIVITY COUNTERS. [Internet] [Thesis]. University of Massachusetts; 2016. [cited 2019 Oct 20]. Available from: https://scholarworks.umass.edu/masters_theses_2/318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chhablani M. PROCESSOR TEMPERATURE AND RELIABILITY ESTIMATION USING ACTIVITY COUNTERS. [Thesis]. University of Massachusetts; 2016. Available from: https://scholarworks.umass.edu/masters_theses_2/318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Jenkal, Ravi Somnath. Architectures and Design Methodology for Energy Efficient MIMO Decoders.

Degree: PhD, Computer Engineering, 2009, North Carolina State University

 This work focuses on the design and implementation aspects of Multi-Input Multi-Output (MIMO) decoders for multi-antenna communications. These decoders are used to determine, either optimally… (more)

Subjects/Keywords: VLSI; ASIC; Energy-efficient; MIMO; Architecture; Methodology

…3.3.1 Multi-Context Processing of SD Algorithm . . . . . . . . . . 3.4 Base Architecture… …multiplexed SD: Base Architecture results . . . . . . . . . . . . . . . 3.5.1 Algorithm Verification… …of 4x4 Decoder Architecture . . . . . . . . . . . . . . . . . . . 4.3.1 Delay Constrained… …4.5.1 Search space minimization: Sorting and the 2-phase architecture . 4.5.2 Cost Space for… …Scalability issues in present architecture . . . . . . . . . . . . . . . . . . . 5.2.1 Constellation… 

Page 1 Page 2 Page 3 Page 4 Page 5

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jenkal, R. S. (2009). Architectures and Design Methodology for Energy Efficient MIMO Decoders. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3897

Chicago Manual of Style (16th Edition):

Jenkal, Ravi Somnath. “Architectures and Design Methodology for Energy Efficient MIMO Decoders.” 2009. Doctoral Dissertation, North Carolina State University. Accessed October 20, 2019. http://www.lib.ncsu.edu/resolver/1840.16/3897.

MLA Handbook (7th Edition):

Jenkal, Ravi Somnath. “Architectures and Design Methodology for Energy Efficient MIMO Decoders.” 2009. Web. 20 Oct 2019.

Vancouver:

Jenkal RS. Architectures and Design Methodology for Energy Efficient MIMO Decoders. [Internet] [Doctoral dissertation]. North Carolina State University; 2009. [cited 2019 Oct 20]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3897.

Council of Science Editors:

Jenkal RS. Architectures and Design Methodology for Energy Efficient MIMO Decoders. [Doctoral Dissertation]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3897


University of Michigan

25. Wu, Hsi-Shou. Energy-Efficient Neural Network Architectures.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Michigan

 Emerging systems for artificial intelligence (AI) are expected to rely on deep neural networks (DNNs) to achieve high accuracy for a broad variety of applications,… (more)

Subjects/Keywords: Computer Architecture; Energy-Efficient Computing; Neural Networks; Machine Learning; Image and Audio Processing; VLSI Design; Electrical Engineering; Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, H. (2018). Energy-Efficient Neural Network Architectures. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/147614

Chicago Manual of Style (16th Edition):

Wu, Hsi-Shou. “Energy-Efficient Neural Network Architectures.” 2018. Doctoral Dissertation, University of Michigan. Accessed October 20, 2019. http://hdl.handle.net/2027.42/147614.

MLA Handbook (7th Edition):

Wu, Hsi-Shou. “Energy-Efficient Neural Network Architectures.” 2018. Web. 20 Oct 2019.

Vancouver:

Wu H. Energy-Efficient Neural Network Architectures. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/2027.42/147614.

Council of Science Editors:

Wu H. Energy-Efficient Neural Network Architectures. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/147614


University of Kentucky

26. Bondehagen, Brent. FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT.

Degree: 2013, University of Kentucky

 Structured Light Illumination (SLI) is the process where spatially varied patterns are projected onto a 3-D surface and based on the distortion by the surface… (more)

Subjects/Keywords: Structured Light Illumination; Phase Measuring Profilometry; 3-D Shape Measurement; Hardware Description Language; Processor Architecture; Computer and Systems Architecture; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bondehagen, B. (2013). FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/23

Chicago Manual of Style (16th Edition):

Bondehagen, Brent. “FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT.” 2013. Masters Thesis, University of Kentucky. Accessed October 20, 2019. http://uknowledge.uky.edu/ece_etds/23.

MLA Handbook (7th Edition):

Bondehagen, Brent. “FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT.” 2013. Web. 20 Oct 2019.

Vancouver:

Bondehagen B. FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2019 Oct 20]. Available from: http://uknowledge.uky.edu/ece_etds/23.

Council of Science Editors:

Bondehagen B. FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT. [Masters Thesis]. University of Kentucky; 2013. Available from: http://uknowledge.uky.edu/ece_etds/23

27. Prakash, Nitin. Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  Energy consumption and speed of execution have long been recognized as conflicting requirements for processor design. In this work, we have developed a low-cost… (more)

Subjects/Keywords: Drowsy cache; Architecture Adaptation; Low Power; Leakage Reduction; Dynamic Schemes; Computer and Systems Architecture; Hardware Systems; Power and Energy; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prakash, N. (2013). Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/980

Chicago Manual of Style (16th Edition):

Prakash, Nitin. “Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management.” 2013. Masters Thesis, University of Massachusetts. Accessed October 20, 2019. https://scholarworks.umass.edu/theses/980.

MLA Handbook (7th Edition):

Prakash, Nitin. “Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management.” 2013. Web. 20 Oct 2019.

Vancouver:

Prakash N. Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2019 Oct 20]. Available from: https://scholarworks.umass.edu/theses/980.

Council of Science Editors:

Prakash N. Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/980

28. Frye, John A. inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices.

Degree: MS, Computer Engineering, 2015, Rochester Institute of Technology

  Transistor technology scaling has been the driving force in improving the size, speed, and power consumption of digital systems. As devices approach atomic size,… (more)

Subjects/Keywords: Fault tolerant architecture; Transistor technology; Variation tolerant architecture; VLSI

…18 4 Proposed inSense Architecture . . . . . . . . . . . . 4.1 Delay Monitor Unit… …13 15 16 17 3.1 3.2 3.3 3.4 elastIC Adaptive Architecture [10]… …Razor II Architecture and Timing Diagram [11] Bulletproof Architecture [12]… …StageNet CMP Architecture [13]… …inSense Architecture inSense Exoskeleton . . . . . . . . . . . . . . . . . . inSense… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Frye, J. A. (2015). inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8998

Chicago Manual of Style (16th Edition):

Frye, John A. “inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed October 20, 2019. https://scholarworks.rit.edu/theses/8998.

MLA Handbook (7th Edition):

Frye, John A. “inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices.” 2015. Web. 20 Oct 2019.

Vancouver:

Frye JA. inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2019 Oct 20]. Available from: https://scholarworks.rit.edu/theses/8998.

Council of Science Editors:

Frye JA. inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: https://scholarworks.rit.edu/theses/8998


Cal Poly

29. Webb, Robert L. ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS.

Degree: MS, Computer Science, 2010, Cal Poly

 The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew,… (more)

Subjects/Keywords: Asynchronous; architecture; logic; Computer and Systems Architecture; Computer Engineering; Computer Sciences; Digital Circuits; Electrical and Electronics; Power and Energy; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Webb, R. L. (2010). ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/381 ; 10.15368/theses.2010.144

Chicago Manual of Style (16th Edition):

Webb, Robert L. “ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS.” 2010. Masters Thesis, Cal Poly. Accessed October 20, 2019. https://digitalcommons.calpoly.edu/theses/381 ; 10.15368/theses.2010.144.

MLA Handbook (7th Edition):

Webb, Robert L. “ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS.” 2010. Web. 20 Oct 2019.

Vancouver:

Webb RL. ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS. [Internet] [Masters thesis]. Cal Poly; 2010. [cited 2019 Oct 20]. Available from: https://digitalcommons.calpoly.edu/theses/381 ; 10.15368/theses.2010.144.

Council of Science Editors:

Webb RL. ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS. [Masters Thesis]. Cal Poly; 2010. Available from: https://digitalcommons.calpoly.edu/theses/381 ; 10.15368/theses.2010.144


Indian Institute of Science

30. Tudu, Jaynarayan Thakurdas. Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation.

Degree: 2016, Indian Institute of Science

 Test power, data volume, and test time have been long-standing problems for sequential scan based testing of system-on-chip (SoC) design. The modern SoCs fabricated at… (more)

Subjects/Keywords: Aware Scan Architecture; Random Access Scan; Power Aware Test; BILP Programming; VLSI Testing; Power Estimation; System-On-Chip (SOC); Sequential Scan Chain Ordering; JScan; Integer Linear Programming; Design-for-Test (DFT) Architecture; Congestion Aware Scan Architecture; Joint Scan Design-for-Test (DFT) Architecture; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tudu, J. T. (2016). Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/3003

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tudu, Jaynarayan Thakurdas. “Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation.” 2016. Thesis, Indian Institute of Science. Accessed October 20, 2019. http://hdl.handle.net/2005/3003.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tudu, Jaynarayan Thakurdas. “Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation.” 2016. Web. 20 Oct 2019.

Vancouver:

Tudu JT. Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation. [Internet] [Thesis]. Indian Institute of Science; 2016. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/2005/3003.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tudu JT. Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation. [Thesis]. Indian Institute of Science; 2016. Available from: http://hdl.handle.net/2005/3003

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2]

.