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Dept: Electrical and Computer Engineering

You searched for subject:(Universal design for learning). Showing records 1 – 30 of 1215 total matches.

[1] [2] [3] [4] [5] … [41]

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University of Texas – Austin

1. -0977-2774. Bridging design and manufacturing gap through machine learning and machine-generated layout.

Degree: Electrical and Computer Engineering, 2018, University of Texas – Austin

 Very-large-scale integrated (VLSI) circuits have entered the era of 1x nm technology node and beyond. Emerging manufacturing processes such as multiple patterning lithography, E-beam lithography… (more)

Subjects/Keywords: VLSI design automation; Design for manufacturability; Machine learning; Physical design; Post-layout optimization; Mask synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

-0977-2774. (2018). Bridging design and manufacturing gap through machine learning and machine-generated layout. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65900

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

-0977-2774. “Bridging design and manufacturing gap through machine learning and machine-generated layout.” 2018. Thesis, University of Texas – Austin. Accessed August 19, 2019. http://hdl.handle.net/2152/65900.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

-0977-2774. “Bridging design and manufacturing gap through machine learning and machine-generated layout.” 2018. Web. 19 Aug 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-0977-2774. Bridging design and manufacturing gap through machine learning and machine-generated layout. [Internet] [Thesis]. University of Texas – Austin; 2018. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2152/65900.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

-0977-2774. Bridging design and manufacturing gap through machine learning and machine-generated layout. [Thesis]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/65900

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

2. Ou, Jiaojiao. Design for manufacturing with directed self-assembly lithography.

Degree: Electrical and Computer Engineering, 2018, University of Texas – Austin

 In ultra-scaled very-large-scale integration (VLSI), lithography has become the bottleneck in integrated circuit (IC) fabrication. Since the conventional 193nm immersion lithography has reached the resolution… (more)

Subjects/Keywords: Directed self-assembly; Physical design; Design for manufacturability

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APA (6th Edition):

Ou, J. (2018). Design for manufacturing with directed self-assembly lithography. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/67706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ou, Jiaojiao. “Design for manufacturing with directed self-assembly lithography.” 2018. Thesis, University of Texas – Austin. Accessed August 19, 2019. http://hdl.handle.net/2152/67706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ou, Jiaojiao. “Design for manufacturing with directed self-assembly lithography.” 2018. Web. 19 Aug 2019.

Vancouver:

Ou J. Design for manufacturing with directed self-assembly lithography. [Internet] [Thesis]. University of Texas – Austin; 2018. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2152/67706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ou J. Design for manufacturing with directed self-assembly lithography. [Thesis]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/67706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

3. Rahagude, Nikhil Prakash. Integrated Enhancement of Testability and Diagnosability for Digital Circuits.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best… (more)

Subjects/Keywords: Fault Coverage; Diagnostic Resolution; Weighted Average; Test Point Insertion; Design for Testability; Design for Diagnosability; Built-in Self Test

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rahagude, N. P. (2010). Integrated Enhancement of Testability and Diagnosability for Digital Circuits. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35609

Chicago Manual of Style (16th Edition):

Rahagude, Nikhil Prakash. “Integrated Enhancement of Testability and Diagnosability for Digital Circuits.” 2010. Masters Thesis, Virginia Tech. Accessed August 19, 2019. http://hdl.handle.net/10919/35609.

MLA Handbook (7th Edition):

Rahagude, Nikhil Prakash. “Integrated Enhancement of Testability and Diagnosability for Digital Circuits.” 2010. Web. 19 Aug 2019.

Vancouver:

Rahagude NP. Integrated Enhancement of Testability and Diagnosability for Digital Circuits. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/10919/35609.

Council of Science Editors:

Rahagude NP. Integrated Enhancement of Testability and Diagnosability for Digital Circuits. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/35609


University of Texas – Austin

4. Zhang, Bin. IC design for reliability.

Degree: Electrical and Computer Engineering, 2009, University of Texas – Austin

 As the feature size of integrated circuits goes down to the nanometer scale, transient and permanent reliability issues are becoming a significant concern for circuit… (more)

Subjects/Keywords: Design for reliability; Circuits; Transient errors; Single event upset

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APA (6th Edition):

Zhang, B. (2009). IC design for reliability. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/6655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Bin. “IC design for reliability.” 2009. Thesis, University of Texas – Austin. Accessed August 19, 2019. http://hdl.handle.net/2152/6655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Bin. “IC design for reliability.” 2009. Web. 19 Aug 2019.

Vancouver:

Zhang B. IC design for reliability. [Internet] [Thesis]. University of Texas – Austin; 2009. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2152/6655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang B. IC design for reliability. [Thesis]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/6655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Windsor

5. Badrous, Sameh Nozhy Samy. COMPLEXITY OF PRODUCTS AND THEIR ASSEMBLY SYSTEMS.

Degree: PhD, Electrical and Computer Engineering, 2011, University of Windsor

  Many manufacturing and assembly challenges emerged due to the increased demand for products variety. Increased product variety caused by product evolution, customization and changes… (more)

Subjects/Keywords: Applied sciences; Assembly; Product complexity; Design for assembly; Manufacturing; Mapping

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Badrous, S. N. S. (2011). COMPLEXITY OF PRODUCTS AND THEIR ASSEMBLY SYSTEMS. (Doctoral Dissertation). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/4775

Chicago Manual of Style (16th Edition):

Badrous, Sameh Nozhy Samy. “COMPLEXITY OF PRODUCTS AND THEIR ASSEMBLY SYSTEMS.” 2011. Doctoral Dissertation, University of Windsor. Accessed August 19, 2019. https://scholar.uwindsor.ca/etd/4775.

MLA Handbook (7th Edition):

Badrous, Sameh Nozhy Samy. “COMPLEXITY OF PRODUCTS AND THEIR ASSEMBLY SYSTEMS.” 2011. Web. 19 Aug 2019.

Vancouver:

Badrous SNS. COMPLEXITY OF PRODUCTS AND THEIR ASSEMBLY SYSTEMS. [Internet] [Doctoral dissertation]. University of Windsor; 2011. [cited 2019 Aug 19]. Available from: https://scholar.uwindsor.ca/etd/4775.

Council of Science Editors:

Badrous SNS. COMPLEXITY OF PRODUCTS AND THEIR ASSEMBLY SYSTEMS. [Doctoral Dissertation]. University of Windsor; 2011. Available from: https://scholar.uwindsor.ca/etd/4775


University of Windsor

6. Mashkovtsev, Vladimir Spartakovich. A DLL Based Test Solution for 3D ICs.

Degree: MA, Electrical and Computer Engineering, 2015, University of Windsor

  Integrated circuits (ICs) are rapidly changing and vertical integration and packaging strategies have already become an important research topic. 2.5D and 3D IC integrations… (more)

Subjects/Keywords: 2.5D IC Integration; 3D IC Integration; Delay locked loop (DLL); Design-for-test; Parametric faults; Test for interposers

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mashkovtsev, V. S. (2015). A DLL Based Test Solution for 3D ICs. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5295

Chicago Manual of Style (16th Edition):

Mashkovtsev, Vladimir Spartakovich. “A DLL Based Test Solution for 3D ICs.” 2015. Masters Thesis, University of Windsor. Accessed August 19, 2019. https://scholar.uwindsor.ca/etd/5295.

MLA Handbook (7th Edition):

Mashkovtsev, Vladimir Spartakovich. “A DLL Based Test Solution for 3D ICs.” 2015. Web. 19 Aug 2019.

Vancouver:

Mashkovtsev VS. A DLL Based Test Solution for 3D ICs. [Internet] [Masters thesis]. University of Windsor; 2015. [cited 2019 Aug 19]. Available from: https://scholar.uwindsor.ca/etd/5295.

Council of Science Editors:

Mashkovtsev VS. A DLL Based Test Solution for 3D ICs. [Masters Thesis]. University of Windsor; 2015. Available from: https://scholar.uwindsor.ca/etd/5295


Virginia Tech

7. Xiao, Yao. Vehicle Detection in Deep Learning.

Degree: MS, Electrical and Computer Engineering, 2019, Virginia Tech

 Computer vision techniques are becoming increasingly popular. For example, face recognition is used to help police find criminals, vehicle detection is used to prevent drivers… (more)

Subjects/Keywords: Vehicle Detection; Deep Learning; Convolutional Neural Networks; Image Processing; Architecture Design

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APA (6th Edition):

Xiao, Y. (2019). Vehicle Detection in Deep Learning. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/91375

Chicago Manual of Style (16th Edition):

Xiao, Yao. “Vehicle Detection in Deep Learning.” 2019. Masters Thesis, Virginia Tech. Accessed August 19, 2019. http://hdl.handle.net/10919/91375.

MLA Handbook (7th Edition):

Xiao, Yao. “Vehicle Detection in Deep Learning.” 2019. Web. 19 Aug 2019.

Vancouver:

Xiao Y. Vehicle Detection in Deep Learning. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/10919/91375.

Council of Science Editors:

Xiao Y. Vehicle Detection in Deep Learning. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/91375


Virginia Tech

8. Banga, Mainak. Testing and Verification Strategies for Enhancing Trust in Third Party IPs.

Degree: PhD, Electrical and Computer Engineering, 2010, Virginia Tech

 Globalization in semiconductor industry has surged up the trend of outsourcing component design and manufacturing process across geographical boundaries. While cost reduction and short time… (more)

Subjects/Keywords: Design for Testability; Side-Channel Analysis; Sequential Equivalence Checking; Trojans; Third party IP

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APA (6th Edition):

Banga, M. (2010). Testing and Verification Strategies for Enhancing Trust in Third Party IPs. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/30085

Chicago Manual of Style (16th Edition):

Banga, Mainak. “Testing and Verification Strategies for Enhancing Trust in Third Party IPs.” 2010. Doctoral Dissertation, Virginia Tech. Accessed August 19, 2019. http://hdl.handle.net/10919/30085.

MLA Handbook (7th Edition):

Banga, Mainak. “Testing and Verification Strategies for Enhancing Trust in Third Party IPs.” 2010. Web. 19 Aug 2019.

Vancouver:

Banga M. Testing and Verification Strategies for Enhancing Trust in Third Party IPs. [Internet] [Doctoral dissertation]. Virginia Tech; 2010. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/10919/30085.

Council of Science Editors:

Banga M. Testing and Verification Strategies for Enhancing Trust in Third Party IPs. [Doctoral Dissertation]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/30085


University of Texas – Austin

9. Santa Maria, Daniel Ruiz. Identifying post-silicon bugs and their root causes through a hardware introspection engine.

Degree: Electrical and Computer Engineering, 2017, University of Texas – Austin

 The goal of this project is to design, build, and evaluate new hardware mechanisms to debug post-silicon bugs in Systems-on-Chip (SoCs). Specifically, we aim to… (more)

Subjects/Keywords: Design-for-debug; Anomaly detection; System deadlock; Post-silicon bugs; Hardware introspection engine

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Santa Maria, D. R. (2017). Identifying post-silicon bugs and their root causes through a hardware introspection engine. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63952

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Santa Maria, Daniel Ruiz. “Identifying post-silicon bugs and their root causes through a hardware introspection engine.” 2017. Thesis, University of Texas – Austin. Accessed August 19, 2019. http://hdl.handle.net/2152/63952.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Santa Maria, Daniel Ruiz. “Identifying post-silicon bugs and their root causes through a hardware introspection engine.” 2017. Web. 19 Aug 2019.

Vancouver:

Santa Maria DR. Identifying post-silicon bugs and their root causes through a hardware introspection engine. [Internet] [Thesis]. University of Texas – Austin; 2017. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2152/63952.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santa Maria DR. Identifying post-silicon bugs and their root causes through a hardware introspection engine. [Thesis]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/63952

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

10. Yang, Joon Sung. Enhancing silicon debug techniques via DFD hardware insertion.

Degree: Electrical and Computer Engineering, 2009, University of Texas – Austin

 As technology is advancing, larger and denser devices are being manufactured with shorter time to market requirements. Identifying and resolving problems in integrated circuits (ICs)… (more)

Subjects/Keywords: Debug techniques; Silicon debug process; DFD hardware insertion; Design for Debug hardware insertion

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APA (6th Edition):

Yang, J. S. (2009). Enhancing silicon debug techniques via DFD hardware insertion. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/6622

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Joon Sung. “Enhancing silicon debug techniques via DFD hardware insertion.” 2009. Thesis, University of Texas – Austin. Accessed August 19, 2019. http://hdl.handle.net/2152/6622.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Joon Sung. “Enhancing silicon debug techniques via DFD hardware insertion.” 2009. Web. 19 Aug 2019.

Vancouver:

Yang JS. Enhancing silicon debug techniques via DFD hardware insertion. [Internet] [Thesis]. University of Texas – Austin; 2009. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2152/6622.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang JS. Enhancing silicon debug techniques via DFD hardware insertion. [Thesis]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/6622

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

11. Cha, Soonyoung. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to extract NBTI and GOBD model parameters to enable the estimation of the degradation and the remaining life of… (more)

Subjects/Keywords: Design for reliability and yield enhancement; Device-level and system-level reliability modeling

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APA (6th Edition):

Cha, S. (2017). Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59748

Chicago Manual of Style (16th Edition):

Cha, Soonyoung. “Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.” 2017. Doctoral Dissertation, Georgia Tech. Accessed August 19, 2019. http://hdl.handle.net/1853/59748.

MLA Handbook (7th Edition):

Cha, Soonyoung. “Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.” 2017. Web. 19 Aug 2019.

Vancouver:

Cha S. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/1853/59748.

Council of Science Editors:

Cha S. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59748


University of Iowa

12. Tang, Xun. Diagnosis Of VLSI circuit defects: defects in scan chain and circuit logic.

Degree: PhD, Electrical and Computer Engineering, 2010, University of Iowa

  Given a logic circuit that fails a test, diagnosis is the process of narrowing down the possible locations of the defects. Diagnosis to locate… (more)

Subjects/Keywords: Design For Test; Diagnosis; Scan Chain; Test; VLSI Defects; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tang, X. (2010). Diagnosis Of VLSI circuit defects: defects in scan chain and circuit logic. (Doctoral Dissertation). University of Iowa. Retrieved from https://ir.uiowa.edu/etd/894

Chicago Manual of Style (16th Edition):

Tang, Xun. “Diagnosis Of VLSI circuit defects: defects in scan chain and circuit logic.” 2010. Doctoral Dissertation, University of Iowa. Accessed August 19, 2019. https://ir.uiowa.edu/etd/894.

MLA Handbook (7th Edition):

Tang, Xun. “Diagnosis Of VLSI circuit defects: defects in scan chain and circuit logic.” 2010. Web. 19 Aug 2019.

Vancouver:

Tang X. Diagnosis Of VLSI circuit defects: defects in scan chain and circuit logic. [Internet] [Doctoral dissertation]. University of Iowa; 2010. [cited 2019 Aug 19]. Available from: https://ir.uiowa.edu/etd/894.

Council of Science Editors:

Tang X. Diagnosis Of VLSI circuit defects: defects in scan chain and circuit logic. [Doctoral Dissertation]. University of Iowa; 2010. Available from: https://ir.uiowa.edu/etd/894


University of New Mexico

13. Appel, Titus. The development of a robotic test bed with applications in Q-learning.

Degree: Electrical and Computer Engineering, 2012, University of New Mexico

 In this work, we show the design, development, and testing of an autonomous ground vehicle for experiments in learning and intelligent transportation research. We then… (more)

Subjects/Keywords: Autonomous robots – Design and construction; Reinforcement learning; Feedback control systems; Intelligent transportation systems – Design and construction.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Appel, T. (2012). The development of a robotic test bed with applications in Q-learning. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/17331

Chicago Manual of Style (16th Edition):

Appel, Titus. “The development of a robotic test bed with applications in Q-learning.” 2012. Masters Thesis, University of New Mexico. Accessed August 19, 2019. http://hdl.handle.net/1928/17331.

MLA Handbook (7th Edition):

Appel, Titus. “The development of a robotic test bed with applications in Q-learning.” 2012. Web. 19 Aug 2019.

Vancouver:

Appel T. The development of a robotic test bed with applications in Q-learning. [Internet] [Masters thesis]. University of New Mexico; 2012. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/1928/17331.

Council of Science Editors:

Appel T. The development of a robotic test bed with applications in Q-learning. [Masters Thesis]. University of New Mexico; 2012. Available from: http://hdl.handle.net/1928/17331


Portland State University

14. Cherupally, Sai Kiran. Hierarchical Random Boolean Network Reservoirs.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2018, Portland State University

  Reservoir Computing (RC) is an emerging Machine Learning (ML) paradigm. RC systems contain randomly assembled computing devices and can be trained to solve complex… (more)

Subjects/Keywords: Neural networks (Computer science)  – Design and construction; Machine learning; Electrical and Computer Engineering

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APA (6th Edition):

Cherupally, S. K. (2018). Hierarchical Random Boolean Network Reservoirs. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/4345

Chicago Manual of Style (16th Edition):

Cherupally, Sai Kiran. “Hierarchical Random Boolean Network Reservoirs.” 2018. Masters Thesis, Portland State University. Accessed August 19, 2019. https://pdxscholar.library.pdx.edu/open_access_etds/4345.

MLA Handbook (7th Edition):

Cherupally, Sai Kiran. “Hierarchical Random Boolean Network Reservoirs.” 2018. Web. 19 Aug 2019.

Vancouver:

Cherupally SK. Hierarchical Random Boolean Network Reservoirs. [Internet] [Masters thesis]. Portland State University; 2018. [cited 2019 Aug 19]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4345.

Council of Science Editors:

Cherupally SK. Hierarchical Random Boolean Network Reservoirs. [Masters Thesis]. Portland State University; 2018. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4345


University of Windsor

15. Richard, Donatus Silva. Phase Locking Authentication for Scan Architecture.

Degree: Electrical and Computer Engineering, 2017, University of Windsor

 Scan design is a widely used Design for Testability (DfT) approach for digital circuits. It provides a high level of controllability and observability resulting in… (more)

Subjects/Keywords: Clock and Data Recovery; Delay Locked Loop; Design for Testability; Hardware Security; Phase Locked Loop; Scan Architecture; Engineering

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APA (6th Edition):

Richard, D. S. (2017). Phase Locking Authentication for Scan Architecture. (Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/7338

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Richard, Donatus Silva. “Phase Locking Authentication for Scan Architecture.” 2017. Thesis, University of Windsor. Accessed August 19, 2019. https://scholar.uwindsor.ca/etd/7338.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Richard, Donatus Silva. “Phase Locking Authentication for Scan Architecture.” 2017. Web. 19 Aug 2019.

Vancouver:

Richard DS. Phase Locking Authentication for Scan Architecture. [Internet] [Thesis]. University of Windsor; 2017. [cited 2019 Aug 19]. Available from: https://scholar.uwindsor.ca/etd/7338.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Richard DS. Phase Locking Authentication for Scan Architecture. [Thesis]. University of Windsor; 2017. Available from: https://scholar.uwindsor.ca/etd/7338

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

16. Sanyal, Alodeep. On Detection, Analysis and Characterization of Transient and Parametric Failures in Nano-scale CMOS VLSI.

Degree: PhD, Electrical and Computer Engineering, 2010, U of Massachusetts : PhD

 As we move deep into nanometer regime of CMOS VLSI (45nm node and below), the device noise margin gets sharply eroded because of continuous lowering… (more)

Subjects/Keywords: Automatic Test Pattern Generation; Crosstalk; Design-for-Testability; Integrated Circuit; Intermittent Failure; Soft Error; Electrical and Computer Engineering

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APA (6th Edition):

Sanyal, A. (2010). On Detection, Analysis and Characterization of Transient and Parametric Failures in Nano-scale CMOS VLSI. (Doctoral Dissertation). U of Massachusetts : PhD. Retrieved from https://scholarworks.umass.edu/open_access_dissertations/243

Chicago Manual of Style (16th Edition):

Sanyal, Alodeep. “On Detection, Analysis and Characterization of Transient and Parametric Failures in Nano-scale CMOS VLSI.” 2010. Doctoral Dissertation, U of Massachusetts : PhD. Accessed August 19, 2019. https://scholarworks.umass.edu/open_access_dissertations/243.

MLA Handbook (7th Edition):

Sanyal, Alodeep. “On Detection, Analysis and Characterization of Transient and Parametric Failures in Nano-scale CMOS VLSI.” 2010. Web. 19 Aug 2019.

Vancouver:

Sanyal A. On Detection, Analysis and Characterization of Transient and Parametric Failures in Nano-scale CMOS VLSI. [Internet] [Doctoral dissertation]. U of Massachusetts : PhD; 2010. [cited 2019 Aug 19]. Available from: https://scholarworks.umass.edu/open_access_dissertations/243.

Council of Science Editors:

Sanyal A. On Detection, Analysis and Characterization of Transient and Parametric Failures in Nano-scale CMOS VLSI. [Doctoral Dissertation]. U of Massachusetts : PhD; 2010. Available from: https://scholarworks.umass.edu/open_access_dissertations/243


University of Texas – Austin

17. Ban, Yong Chan. Lithography variability driven cell characterization and layout optimization for manufacturability.

Degree: Electrical and Computer Engineering, 2011, University of Texas – Austin

 Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How… (more)

Subjects/Keywords: Lithography; Variability; Standard cell; Characterization; Layout optimization; Patterning; Manufacturing; Design automation; SADP; Self-aligned double patterning; Design for manufacturing; Line-edge roughness

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ban, Y. C. (2011). Lithography variability driven cell characterization and layout optimization for manufacturability. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-05-3372

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ban, Yong Chan. “Lithography variability driven cell characterization and layout optimization for manufacturability.” 2011. Thesis, University of Texas – Austin. Accessed August 19, 2019. http://hdl.handle.net/2152/ETD-UT-2011-05-3372.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ban, Yong Chan. “Lithography variability driven cell characterization and layout optimization for manufacturability.” 2011. Web. 19 Aug 2019.

Vancouver:

Ban YC. Lithography variability driven cell characterization and layout optimization for manufacturability. [Internet] [Thesis]. University of Texas – Austin; 2011. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3372.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ban YC. Lithography variability driven cell characterization and layout optimization for manufacturability. [Thesis]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3372

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

18. Ding, Duo. CAD for nanolithography and nanophotonics.

Degree: Electrical and Computer Engineering, 2011, University of Texas – Austin

 As the semiconductor technology roadmap further extends, the development of next generation silicon systems becomes critically challenged. On the one hand, design and manufacturing closures… (more)

Subjects/Keywords: Computer-Aided Design; VLSI; Mathematical optimization; Algorithms; Nanolithography; Design for manufacturability/yield/reliability; Lithography hotspot detection; Nanophotonics interconnect; Low-power thermal-reliable interconnect synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ding, D. (2011). CAD for nanolithography and nanophotonics. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-08-4030

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ding, Duo. “CAD for nanolithography and nanophotonics.” 2011. Thesis, University of Texas – Austin. Accessed August 19, 2019. http://hdl.handle.net/2152/ETD-UT-2011-08-4030.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ding, Duo. “CAD for nanolithography and nanophotonics.” 2011. Web. 19 Aug 2019.

Vancouver:

Ding D. CAD for nanolithography and nanophotonics. [Internet] [Thesis]. University of Texas – Austin; 2011. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-4030.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ding D. CAD for nanolithography and nanophotonics. [Thesis]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-4030

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


New Jersey Institute of Technology

19. He, Jun. A CAD-MLCA interface for next-generation DFE tools.

Degree: MSin Computer Engineering - (M.S.), Electrical and Computer Engineering, 2001, New Jersey Institute of Technology

  Environmental concerns and rising product disposal costs have pressed manufactures to make more environmentally friendly products and customers to use and dispose of them… (more)

Subjects/Keywords: Design For Environment (DFE); Life Cycle Assessment (LCA); Product Design; Computer Engineering

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APA (6th Edition):

He, J. (2001). A CAD-MLCA interface for next-generation DFE tools. (Thesis). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/theses/735

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

He, Jun. “A CAD-MLCA interface for next-generation DFE tools.” 2001. Thesis, New Jersey Institute of Technology. Accessed August 19, 2019. https://digitalcommons.njit.edu/theses/735.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

He, Jun. “A CAD-MLCA interface for next-generation DFE tools.” 2001. Web. 19 Aug 2019.

Vancouver:

He J. A CAD-MLCA interface for next-generation DFE tools. [Internet] [Thesis]. New Jersey Institute of Technology; 2001. [cited 2019 Aug 19]. Available from: https://digitalcommons.njit.edu/theses/735.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

He J. A CAD-MLCA interface for next-generation DFE tools. [Thesis]. New Jersey Institute of Technology; 2001. Available from: https://digitalcommons.njit.edu/theses/735

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Clemson University

20. Nahar, Dixit Sohanraj. Dynamic Environmental Monitoring using Intelligent Tendril Robots.

Degree: MS, Electrical and Computer Engineering, 2017, Clemson University

 Traditional robots are constructed from rigid links which facilitate both stiffness and accuracy. However, these systems operate best in open, highly structured spaces, and environments… (more)

Subjects/Keywords: Adapting to changing environments; Body mounted sensors for decision-making; Intelligent Continuum Robots; Long thin Tendril robots for inspection and search on space and ecological environment; Machine Learning and robotics; Neural Networks for Continuum robot adaptation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nahar, D. S. (2017). Dynamic Environmental Monitoring using Intelligent Tendril Robots. (Masters Thesis). Clemson University. Retrieved from https://tigerprints.clemson.edu/all_theses/2661

Chicago Manual of Style (16th Edition):

Nahar, Dixit Sohanraj. “Dynamic Environmental Monitoring using Intelligent Tendril Robots.” 2017. Masters Thesis, Clemson University. Accessed August 19, 2019. https://tigerprints.clemson.edu/all_theses/2661.

MLA Handbook (7th Edition):

Nahar, Dixit Sohanraj. “Dynamic Environmental Monitoring using Intelligent Tendril Robots.” 2017. Web. 19 Aug 2019.

Vancouver:

Nahar DS. Dynamic Environmental Monitoring using Intelligent Tendril Robots. [Internet] [Masters thesis]. Clemson University; 2017. [cited 2019 Aug 19]. Available from: https://tigerprints.clemson.edu/all_theses/2661.

Council of Science Editors:

Nahar DS. Dynamic Environmental Monitoring using Intelligent Tendril Robots. [Masters Thesis]. Clemson University; 2017. Available from: https://tigerprints.clemson.edu/all_theses/2661

21. Krishnasamy, Subhashini. Online learning and decision-making from implicit feedback.

Degree: Electrical and Computer Engineering, 2017, University of Texas – Austin

 This thesis focuses on designing learning and control algorithms for emerging resource allocation platforms like recommender systems, 5G wireless networks, and online marketplaces. These systems… (more)

Subjects/Keywords: Online learning; Resource allocation; Learning algorithm design; Implicit feedback; Incremental feedback; Sponsored content; Sponsored content detection; Scheduling algorithm design; Stochastic multi-armed bandit; Base station activation; Learning algorithms; Online decision-making; Online control

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Krishnasamy, S. (2017). Online learning and decision-making from implicit feedback. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/47285

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Krishnasamy, Subhashini. “Online learning and decision-making from implicit feedback.” 2017. Thesis, University of Texas – Austin. Accessed August 19, 2019. http://hdl.handle.net/2152/47285.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Krishnasamy, Subhashini. “Online learning and decision-making from implicit feedback.” 2017. Web. 19 Aug 2019.

Vancouver:

Krishnasamy S. Online learning and decision-making from implicit feedback. [Internet] [Thesis]. University of Texas – Austin; 2017. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2152/47285.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Krishnasamy S. Online learning and decision-making from implicit feedback. [Thesis]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/47285

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Florida

22. Christensen, Michael. Pedagogical Reforms of Digital Signal Processing Education.

Degree: PhD, Electrical and Computer Engineering, 2009, University of Florida

 The future of the engineering discipline is arguably predicated heavily upon appealing to the future generation, in all its sensibilities. The greatest burden in doing… (more)

Subjects/Keywords: Design engineering; Educational research; Engineering; Engineering education; Jammers; Learning; Learning modules; Signal processing; Signals; Students; adobe, captivate, digital, education, electrical, engineering, interactive, processing, signal

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Christensen, M. (2009). Pedagogical Reforms of Digital Signal Processing Education. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0024317

Chicago Manual of Style (16th Edition):

Christensen, Michael. “Pedagogical Reforms of Digital Signal Processing Education.” 2009. Doctoral Dissertation, University of Florida. Accessed August 19, 2019. http://ufdc.ufl.edu/UFE0024317.

MLA Handbook (7th Edition):

Christensen, Michael. “Pedagogical Reforms of Digital Signal Processing Education.” 2009. Web. 19 Aug 2019.

Vancouver:

Christensen M. Pedagogical Reforms of Digital Signal Processing Education. [Internet] [Doctoral dissertation]. University of Florida; 2009. [cited 2019 Aug 19]. Available from: http://ufdc.ufl.edu/UFE0024317.

Council of Science Editors:

Christensen M. Pedagogical Reforms of Digital Signal Processing Education. [Doctoral Dissertation]. University of Florida; 2009. Available from: http://ufdc.ufl.edu/UFE0024317


University of Michigan

23. Wu, Hsi-Shou. Energy-Efficient Neural Network Architectures.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Michigan

 Emerging systems for artificial intelligence (AI) are expected to rely on deep neural networks (DNNs) to achieve high accuracy for a broad variety of applications,… (more)

Subjects/Keywords: Computer Architecture; Energy-Efficient Computing; Neural Networks; Machine Learning; Image and Audio Processing; VLSI Design; Electrical Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, H. (2018). Energy-Efficient Neural Network Architectures. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/147614

Chicago Manual of Style (16th Edition):

Wu, Hsi-Shou. “Energy-Efficient Neural Network Architectures.” 2018. Doctoral Dissertation, University of Michigan. Accessed August 19, 2019. http://hdl.handle.net/2027.42/147614.

MLA Handbook (7th Edition):

Wu, Hsi-Shou. “Energy-Efficient Neural Network Architectures.” 2018. Web. 19 Aug 2019.

Vancouver:

Wu H. Energy-Efficient Neural Network Architectures. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2027.42/147614.

Council of Science Editors:

Wu H. Energy-Efficient Neural Network Architectures. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/147614


Georgia Tech

24. Bae, Soo Hyun. Information retrieval via universal source coding.

Degree: PhD, Electrical and Computer Engineering, 2008, Georgia Tech

 This dissertation explores the intersection of information retrieval and universal source coding techniques and studies an optimal multidimensional source representation from an information theoretic point… (more)

Subjects/Keywords: Image retrieval; Image compression; Information retrieval; Machine learning; Universal source coding; Data compression; Incremental parsing; Pattern recognition; Natural language processing; Pattern recognition systems; Pattern perception; Computer science; Information storage and retrieval systems; Multidimensional databases

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bae, S. H. (2008). Information retrieval via universal source coding. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26573

Chicago Manual of Style (16th Edition):

Bae, Soo Hyun. “Information retrieval via universal source coding.” 2008. Doctoral Dissertation, Georgia Tech. Accessed August 19, 2019. http://hdl.handle.net/1853/26573.

MLA Handbook (7th Edition):

Bae, Soo Hyun. “Information retrieval via universal source coding.” 2008. Web. 19 Aug 2019.

Vancouver:

Bae SH. Information retrieval via universal source coding. [Internet] [Doctoral dissertation]. Georgia Tech; 2008. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/1853/26573.

Council of Science Editors:

Bae SH. Information retrieval via universal source coding. [Doctoral Dissertation]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26573


University of Canterbury

25. Raffensperger, Peter Abraham. Measuring and Influencing Sequential Joint Agent Behaviours.

Degree: Electrical and Computer Engineering, 2013, University of Canterbury

 Algorithmically designed reward functions can influence groups of learning agents toward measurable desired sequential joint behaviours. Influencing learning agents toward desirable behaviours is non-trivial due… (more)

Subjects/Keywords: multi-agent systems; multi-agent reinforcement learning; decentralised systems; resource allocation; turn-taking; Nash equilibria; emergent behaviour; reward functions; reward design; Markov decision processes; Markov chains

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Raffensperger, P. A. (2013). Measuring and Influencing Sequential Joint Agent Behaviours. (Thesis). University of Canterbury. Retrieved from http://hdl.handle.net/10092/7472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Raffensperger, Peter Abraham. “Measuring and Influencing Sequential Joint Agent Behaviours.” 2013. Thesis, University of Canterbury. Accessed August 19, 2019. http://hdl.handle.net/10092/7472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Raffensperger, Peter Abraham. “Measuring and Influencing Sequential Joint Agent Behaviours.” 2013. Web. 19 Aug 2019.

Vancouver:

Raffensperger PA. Measuring and Influencing Sequential Joint Agent Behaviours. [Internet] [Thesis]. University of Canterbury; 2013. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/10092/7472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Raffensperger PA. Measuring and Influencing Sequential Joint Agent Behaviours. [Thesis]. University of Canterbury; 2013. Available from: http://hdl.handle.net/10092/7472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Zutty, Jason Paul. Automated machine learning: A biologically inspired approach.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 Machine learning is a robust process by which a computer can discover characteristics of underlying data that enable it to create a model for making… (more)

Subjects/Keywords: Machine learning; AutoML; Genetic programing; Automated algorithm design

…of the design of a machine learning pipeline. Here, the parameters used for each step of… …of machine learning pipeline design, the field of automated machine learning (autoML… …objective Algorithm Design Engine (EMADE), an opensource framework for the automated… …Truth is fed to the machine learning model for fitting and scoring purposes. In this sense… …features, allowing for the prediction of a continuous value. Machine learning is broken up into a… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zutty, J. P. (2018). Automated machine learning: A biologically inspired approach. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60768

Chicago Manual of Style (16th Edition):

Zutty, Jason Paul. “Automated machine learning: A biologically inspired approach.” 2018. Doctoral Dissertation, Georgia Tech. Accessed August 19, 2019. http://hdl.handle.net/1853/60768.

MLA Handbook (7th Edition):

Zutty, Jason Paul. “Automated machine learning: A biologically inspired approach.” 2018. Web. 19 Aug 2019.

Vancouver:

Zutty JP. Automated machine learning: A biologically inspired approach. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/1853/60768.

Council of Science Editors:

Zutty JP. Automated machine learning: A biologically inspired approach. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60768


University of Texas – Austin

27. Srour, Malek. Data-dependent cycle-accurate power modeling of RTL-level IPs using machine learning.

Degree: Electrical and Computer Engineering, 2018, University of Texas – Austin

 In a chip design project, early design planning has a strong impact on the schedule and the cost of design. Power estimation is part of… (more)

Subjects/Keywords: Cycle-accurate power modeling; Power modeling; Machine learning; Chip design; Power estimation; Register transfer level; Abstraction level; Power predictions; Cycle-specific models

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srour, M. (2018). Data-dependent cycle-accurate power modeling of RTL-level IPs using machine learning. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65980

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srour, Malek. “Data-dependent cycle-accurate power modeling of RTL-level IPs using machine learning.” 2018. Thesis, University of Texas – Austin. Accessed August 19, 2019. http://hdl.handle.net/2152/65980.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srour, Malek. “Data-dependent cycle-accurate power modeling of RTL-level IPs using machine learning.” 2018. Web. 19 Aug 2019.

Vancouver:

Srour M. Data-dependent cycle-accurate power modeling of RTL-level IPs using machine learning. [Internet] [Thesis]. University of Texas – Austin; 2018. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2152/65980.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srour M. Data-dependent cycle-accurate power modeling of RTL-level IPs using machine learning. [Thesis]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/65980

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

28. Nataraj, Gopal. Advances in Quantitative MRI: Acquisition, Estimation, and Application.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Michigan

 Quantitative magnetic resonance imaging (QMRI) produces images of potential MR biomarkers: measurable tissue properties related to physiological processes that characterize the onset and progression of… (more)

Subjects/Keywords: magnetic resonance imaging; optimal experiment design; parameter estimation; machine learning; kernel methods; myelin water imaging; Biomedical Engineering; Electrical Engineering; Radiology; Physics; Engineering; Health Sciences; Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nataraj, G. (2018). Advances in Quantitative MRI: Acquisition, Estimation, and Application. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/147486

Chicago Manual of Style (16th Edition):

Nataraj, Gopal. “Advances in Quantitative MRI: Acquisition, Estimation, and Application.” 2018. Doctoral Dissertation, University of Michigan. Accessed August 19, 2019. http://hdl.handle.net/2027.42/147486.

MLA Handbook (7th Edition):

Nataraj, Gopal. “Advances in Quantitative MRI: Acquisition, Estimation, and Application.” 2018. Web. 19 Aug 2019.

Vancouver:

Nataraj G. Advances in Quantitative MRI: Acquisition, Estimation, and Application. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/2027.42/147486.

Council of Science Editors:

Nataraj G. Advances in Quantitative MRI: Acquisition, Estimation, and Application. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/147486


Georgia Tech

29. Xuan, Xiangdong. Analysis and design of reliable mixed-signal CMOS circuits.

Degree: PhD, Electrical and Computer Engineering, 2004, Georgia Tech

 Facing the constantly increasing reliability challenges under technology scaling, the topics in IC reliability technique have been receiving serious attention during recent years. In this… (more)

Subjects/Keywords: Reliability simulation; Design-for-reliability; IC reliability; Metal oxide semiconductors, Complementary Reliability Computer simulation; Integrated circuits Reliability Computer simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xuan, X. (2004). Analysis and design of reliable mixed-signal CMOS circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/4776

Chicago Manual of Style (16th Edition):

Xuan, Xiangdong. “Analysis and design of reliable mixed-signal CMOS circuits.” 2004. Doctoral Dissertation, Georgia Tech. Accessed August 19, 2019. http://hdl.handle.net/1853/4776.

MLA Handbook (7th Edition):

Xuan, Xiangdong. “Analysis and design of reliable mixed-signal CMOS circuits.” 2004. Web. 19 Aug 2019.

Vancouver:

Xuan X. Analysis and design of reliable mixed-signal CMOS circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2004. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/1853/4776.

Council of Science Editors:

Xuan X. Analysis and design of reliable mixed-signal CMOS circuits. [Doctoral Dissertation]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/4776


Georgia Tech

30. Doppalapudi, Ranjeeth. Design-for-manufacturability (DFM) for system-in-package (SiP) applications.

Degree: MS, Electrical and Computer Engineering, 2008, Georgia Tech

 Microelectronic systems packaging involves layout dimensions of the order of microns. During manufacturing, process variations will cause parameters to deviate from their nominal values. As… (more)

Subjects/Keywords: DFM; SiP; Design for manufacturing; Tolerance (Engineering); Computer integrated manufacturing systems; Microelectronic packaging; Quality control

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Doppalapudi, R. (2008). Design-for-manufacturability (DFM) for system-in-package (SiP) applications. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26701

Chicago Manual of Style (16th Edition):

Doppalapudi, Ranjeeth. “Design-for-manufacturability (DFM) for system-in-package (SiP) applications.” 2008. Masters Thesis, Georgia Tech. Accessed August 19, 2019. http://hdl.handle.net/1853/26701.

MLA Handbook (7th Edition):

Doppalapudi, Ranjeeth. “Design-for-manufacturability (DFM) for system-in-package (SiP) applications.” 2008. Web. 19 Aug 2019.

Vancouver:

Doppalapudi R. Design-for-manufacturability (DFM) for system-in-package (SiP) applications. [Internet] [Masters thesis]. Georgia Tech; 2008. [cited 2019 Aug 19]. Available from: http://hdl.handle.net/1853/26701.

Council of Science Editors:

Doppalapudi R. Design-for-manufacturability (DFM) for system-in-package (SiP) applications. [Masters Thesis]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26701

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