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You searched for subject:(Timing analysis). Showing records 1 – 30 of 134 total matches.

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University of Illinois – Urbana-Champaign

1. Lai, Tin-Yin. An efficient and accurate timing macro-modeling algorithm for large hierarchical designs.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Ever-increasing circuit design complexity is driving the need for fast and accurate macro-modeling algorithms to accelerate hierarchical timing. We introduce LibAbs, an effective macro-modeling algorithm… (more)

Subjects/Keywords: Timing macro-modeling; Algorithm; Timing analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lai, T. (2017). An efficient and accurate timing macro-modeling algorithm for large hierarchical designs. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98236

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lai, Tin-Yin. “An efficient and accurate timing macro-modeling algorithm for large hierarchical designs.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed January 26, 2020. http://hdl.handle.net/2142/98236.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lai, Tin-Yin. “An efficient and accurate timing macro-modeling algorithm for large hierarchical designs.” 2017. Web. 26 Jan 2020.

Vancouver:

Lai T. An efficient and accurate timing macro-modeling algorithm for large hierarchical designs. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/2142/98236.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai T. An efficient and accurate timing macro-modeling algorithm for large hierarchical designs. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98236

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Ottawa

2. Fu, Jingyi J.Y. Delay Analysis of Digital Circuits Using Prony's Method .

Degree: 2011, University of Ottawa

 This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in… (more)

Subjects/Keywords: Prony's method; Timing Analysis; Obreshokov; numerical method; Dynamic Timing Analysis (DTA); Static Timing Analysis (STA)

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APA (6th Edition):

Fu, J. J. Y. (2011). Delay Analysis of Digital Circuits Using Prony's Method . (Thesis). University of Ottawa. Retrieved from http://hdl.handle.net/10393/20125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fu, Jingyi J Y. “Delay Analysis of Digital Circuits Using Prony's Method .” 2011. Thesis, University of Ottawa. Accessed January 26, 2020. http://hdl.handle.net/10393/20125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fu, Jingyi J Y. “Delay Analysis of Digital Circuits Using Prony's Method .” 2011. Web. 26 Jan 2020.

Vancouver:

Fu JJY. Delay Analysis of Digital Circuits Using Prony's Method . [Internet] [Thesis]. University of Ottawa; 2011. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/10393/20125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fu JJY. Delay Analysis of Digital Circuits Using Prony's Method . [Thesis]. University of Ottawa; 2011. Available from: http://hdl.handle.net/10393/20125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

3. Huang, Tsung-Wei. Distributed timing analysis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 As design complexities continue to grow larger, the need to efficiently analyze circuit timing with billions of transistors across multiple modes and corners is quickly… (more)

Subjects/Keywords: Distributed systems; Timing analysis

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APA (6th Edition):

Huang, T. (2017). Distributed timing analysis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99302

Chicago Manual of Style (16th Edition):

Huang, Tsung-Wei. “Distributed timing analysis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 26, 2020. http://hdl.handle.net/2142/99302.

MLA Handbook (7th Edition):

Huang, Tsung-Wei. “Distributed timing analysis.” 2017. Web. 26 Jan 2020.

Vancouver:

Huang T. Distributed timing analysis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/2142/99302.

Council of Science Editors:

Huang T. Distributed timing analysis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99302


North Carolina State University

4. Raghavendra, Raghuveer. Providing predictability for high end embedded systems.

Degree: MS, Computer Science, 2010, North Carolina State University

 Real-Time systems require logical and temporal correctness. Temporal correctness implies that each task running on the system has a deadline that needs to be met.… (more)

Subjects/Keywords: timing anomalies; worst case execution time; timing analysis

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APA (6th Edition):

Raghavendra, R. (2010). Providing predictability for high end embedded systems. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Raghavendra, Raghuveer. “Providing predictability for high end embedded systems.” 2010. Thesis, North Carolina State University. Accessed January 26, 2020. http://www.lib.ncsu.edu/resolver/1840.16/415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Raghavendra, Raghuveer. “Providing predictability for high end embedded systems.” 2010. Web. 26 Jan 2020.

Vancouver:

Raghavendra R. Providing predictability for high end embedded systems. [Internet] [Thesis]. North Carolina State University; 2010. [cited 2020 Jan 26]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Raghavendra R. Providing predictability for high end embedded systems. [Thesis]. North Carolina State University; 2010. Available from: http://www.lib.ncsu.edu/resolver/1840.16/415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Saskatchewan

5. Pelet, Eric R. Synchronization in all-digital QAM receivers.

Degree: 2009, University of Saskatchewan

 The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective… (more)

Subjects/Keywords: carrier frequency offset estimation; timing jitter analysis; timing recovery; digital communication

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pelet, E. R. (2009). Synchronization in all-digital QAM receivers. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/etd-04272009-155247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pelet, Eric R. “Synchronization in all-digital QAM receivers.” 2009. Thesis, University of Saskatchewan. Accessed January 26, 2020. http://hdl.handle.net/10388/etd-04272009-155247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pelet, Eric R. “Synchronization in all-digital QAM receivers.” 2009. Web. 26 Jan 2020.

Vancouver:

Pelet ER. Synchronization in all-digital QAM receivers. [Internet] [Thesis]. University of Saskatchewan; 2009. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/10388/etd-04272009-155247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pelet ER. Synchronization in all-digital QAM receivers. [Thesis]. University of Saskatchewan; 2009. Available from: http://hdl.handle.net/10388/etd-04272009-155247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

6. Kim, Hyun Sung. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.

Degree: 2009, Texas A&M University

 As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the… (more)

Subjects/Keywords: Statistical Static Timing Analysis; power supply noise

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, H. S. (2009). Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Hyun Sung. “Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.” 2009. Thesis, Texas A&M University. Accessed January 26, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Hyun Sung. “Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.” 2009. Web. 26 Jan 2020.

Vancouver:

Kim HS. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim HS. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

7. Fatemi, Hanif. Timing and power analysis of CMOS logic cells under noisy inputs.

Degree: PhD, Computer Engineering, 2009, University of Southern California

 This dissertation investigates the effect of capacitive crosstalk on the behavior of CMOS cells and presents a new cell modeling technique for the purpose of… (more)

Subjects/Keywords: timing analysis; crosstalk noise; cell modeling

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APA (6th Edition):

Fatemi, H. (2009). Timing and power analysis of CMOS logic cells under noisy inputs. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/486086/rec/7481

Chicago Manual of Style (16th Edition):

Fatemi, Hanif. “Timing and power analysis of CMOS logic cells under noisy inputs.” 2009. Doctoral Dissertation, University of Southern California. Accessed January 26, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/486086/rec/7481.

MLA Handbook (7th Edition):

Fatemi, Hanif. “Timing and power analysis of CMOS logic cells under noisy inputs.” 2009. Web. 26 Jan 2020.

Vancouver:

Fatemi H. Timing and power analysis of CMOS logic cells under noisy inputs. [Internet] [Doctoral dissertation]. University of Southern California; 2009. [cited 2020 Jan 26]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/486086/rec/7481.

Council of Science Editors:

Fatemi H. Timing and power analysis of CMOS logic cells under noisy inputs. [Doctoral Dissertation]. University of Southern California; 2009. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/486086/rec/7481


University of Minnesota

8. Shriram, Vignesh. Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits.

Degree: M.S.E.E., Electrical/Computer Engineering, 2019, University of Minnesota

 Coupling capacitance is becoming increasingly problematic at the more advanced technology nodes and affects the timing and sign-off timeline of integrated circuits (ICs). As the… (more)

Subjects/Keywords: coupling capacitance; static timing analysis; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shriram, V. (2019). Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/206136

Chicago Manual of Style (16th Edition):

Shriram, Vignesh. “Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits.” 2019. Masters Thesis, University of Minnesota. Accessed January 26, 2020. http://hdl.handle.net/11299/206136.

MLA Handbook (7th Edition):

Shriram, Vignesh. “Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits.” 2019. Web. 26 Jan 2020.

Vancouver:

Shriram V. Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits. [Internet] [Masters thesis]. University of Minnesota; 2019. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/11299/206136.

Council of Science Editors:

Shriram V. Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits. [Masters Thesis]. University of Minnesota; 2019. Available from: http://hdl.handle.net/11299/206136


NSYSU

9. Hsieh, Kai-Yang. Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 Small Delay Defect (SDD) is one kind of the signal transition delay faults. It could not be detected via traditional delay testing method because the… (more)

Subjects/Keywords: Commercial ATPG Tool; False Path; Statistical Static Timing Analysis; Timing-aware ATPG; Small Delay Defect

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsieh, K. (2013). Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsieh, Kai-Yang. “Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection.” 2013. Thesis, NSYSU. Accessed January 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsieh, Kai-Yang. “Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection.” 2013. Web. 26 Jan 2020.

Vancouver:

Hsieh K. Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Jan 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh K. Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

10. Wu, Meng. Analysis and Enforcement of Properties in Software Systems.

Degree: PhD, Computer Engineering, 2019, Virginia Tech

 It is important for everything around us to follow some rules to work correctly. That is the same for our software systems to follow the… (more)

Subjects/Keywords: Shield Synthesis; Program Analysis; Timing Side Channel; Cache Timing Leak; Speculative Execution; Abstract Interpretation

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APA (6th Edition):

Wu, M. (2019). Analysis and Enforcement of Properties in Software Systems. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/90887

Chicago Manual of Style (16th Edition):

Wu, Meng. “Analysis and Enforcement of Properties in Software Systems.” 2019. Doctoral Dissertation, Virginia Tech. Accessed January 26, 2020. http://hdl.handle.net/10919/90887.

MLA Handbook (7th Edition):

Wu, Meng. “Analysis and Enforcement of Properties in Software Systems.” 2019. Web. 26 Jan 2020.

Vancouver:

Wu M. Analysis and Enforcement of Properties in Software Systems. [Internet] [Doctoral dissertation]. Virginia Tech; 2019. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/10919/90887.

Council of Science Editors:

Wu M. Analysis and Enforcement of Properties in Software Systems. [Doctoral Dissertation]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/90887

11. Kahsu, Lidia. Evaluation of a method for identifying timing models.

Degree: Design and Engineering, 2012, Mälardalen University

  In today’s world, embedded systems which have very large and highly configurable software systems, consisting of hundreds of tasks with huge lines of code… (more)

Subjects/Keywords: Real-time systems; WCET analysis; simulation; Early timing analysis; SimpleScalar; SWEET; Linear timing models; Computer and Information Sciences; Data- och informationsvetenskap

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kahsu, L. (2012). Evaluation of a method for identifying timing models. (Thesis). Mälardalen University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-15093

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kahsu, Lidia. “Evaluation of a method for identifying timing models.” 2012. Thesis, Mälardalen University. Accessed January 26, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-15093.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kahsu, Lidia. “Evaluation of a method for identifying timing models.” 2012. Web. 26 Jan 2020.

Vancouver:

Kahsu L. Evaluation of a method for identifying timing models. [Internet] [Thesis]. Mälardalen University; 2012. [cited 2020 Jan 26]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-15093.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kahsu L. Evaluation of a method for identifying timing models. [Thesis]. Mälardalen University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-15093

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Pretoria

12. Yates, Marinus. Fundamental momentum as an investment timing indicator for value portfolios.

Degree: Gordon Institute of Business Science (GIBS), 2013, University of Pretoria

 The problem associated with value shares is that they may remain undervalued for an extended period of time. Therefore, determining when to buy value shares… (more)

Subjects/Keywords: UCTD; Value strategies; Momentum; Composite value measures; Investment timing; Fundamental analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yates, M. (2013). Fundamental momentum as an investment timing indicator for value portfolios. (Masters Thesis). University of Pretoria. Retrieved from http://hdl.handle.net/2263/23068

Chicago Manual of Style (16th Edition):

Yates, Marinus. “Fundamental momentum as an investment timing indicator for value portfolios.” 2013. Masters Thesis, University of Pretoria. Accessed January 26, 2020. http://hdl.handle.net/2263/23068.

MLA Handbook (7th Edition):

Yates, Marinus. “Fundamental momentum as an investment timing indicator for value portfolios.” 2013. Web. 26 Jan 2020.

Vancouver:

Yates M. Fundamental momentum as an investment timing indicator for value portfolios. [Internet] [Masters thesis]. University of Pretoria; 2013. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/2263/23068.

Council of Science Editors:

Yates M. Fundamental momentum as an investment timing indicator for value portfolios. [Masters Thesis]. University of Pretoria; 2013. Available from: http://hdl.handle.net/2263/23068


University of Minnesota

13. Kumar, Sanjay V. Reliability-aware and variation-aware CAD techniques.

Degree: PhD, Electrical Engineering, 2009, University of Minnesota

 Technology scaling into the sub-100nm domain implies that the effects of process, voltage, and temperature variations have a resounding effect on the performance of digital… (more)

Subjects/Keywords: Delay; Leakage; Reliability; Temperature; Timing Analysis; Variations; Electrical Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, S. V. (2009). Reliability-aware and variation-aware CAD techniques. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/57462

Chicago Manual of Style (16th Edition):

Kumar, Sanjay V. “Reliability-aware and variation-aware CAD techniques.” 2009. Doctoral Dissertation, University of Minnesota. Accessed January 26, 2020. http://purl.umn.edu/57462.

MLA Handbook (7th Edition):

Kumar, Sanjay V. “Reliability-aware and variation-aware CAD techniques.” 2009. Web. 26 Jan 2020.

Vancouver:

Kumar SV. Reliability-aware and variation-aware CAD techniques. [Internet] [Doctoral dissertation]. University of Minnesota; 2009. [cited 2020 Jan 26]. Available from: http://purl.umn.edu/57462.

Council of Science Editors:

Kumar SV. Reliability-aware and variation-aware CAD techniques. [Doctoral Dissertation]. University of Minnesota; 2009. Available from: http://purl.umn.edu/57462


NSYSU

14. Ko, Xue-Da. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 With the improvement of semiconductor manufacturing processes, the power consumption of the integrated circuit(IC) is growing rapidly. Therefore, the power consumption reduction of IC is… (more)

Subjects/Keywords: Static Timing Analysis; Level Converter; Critical Path; Multiple-Supply Voltage

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ko, X. (2013). Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Thesis, NSYSU. Accessed January 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Web. 26 Jan 2020.

Vancouver:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Jan 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Pretoria

15. [No author]. Fundamental momentum as an investment timing indicator for value portfolios .

Degree: 2013, University of Pretoria

 The problem associated with value shares is that they may remain undervalued for an extended period of time. Therefore, determining when to buy value shares… (more)

Subjects/Keywords: UCTD; Value strategies; Momentum; Composite value measures; Investment timing; Fundamental analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2013). Fundamental momentum as an investment timing indicator for value portfolios . (Masters Thesis). University of Pretoria. Retrieved from http://upetd.up.ac.za/thesis/available/etd-03092013-173201/

Chicago Manual of Style (16th Edition):

author], [No. “Fundamental momentum as an investment timing indicator for value portfolios .” 2013. Masters Thesis, University of Pretoria. Accessed January 26, 2020. http://upetd.up.ac.za/thesis/available/etd-03092013-173201/.

MLA Handbook (7th Edition):

author], [No. “Fundamental momentum as an investment timing indicator for value portfolios .” 2013. Web. 26 Jan 2020.

Vancouver:

author] [. Fundamental momentum as an investment timing indicator for value portfolios . [Internet] [Masters thesis]. University of Pretoria; 2013. [cited 2020 Jan 26]. Available from: http://upetd.up.ac.za/thesis/available/etd-03092013-173201/.

Council of Science Editors:

author] [. Fundamental momentum as an investment timing indicator for value portfolios . [Masters Thesis]. University of Pretoria; 2013. Available from: http://upetd.up.ac.za/thesis/available/etd-03092013-173201/


Case Western Reserve University

16. Krishnamurthy, Sivasubramaniam T. STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.

Degree: MSs (Engineering), Computer Engineering, 2008, Case Western Reserve University

 As designers build complex digital circuits with ever diminishing device sizes, there is a need to obtain fast circuits with low hardware overhead. Critical path… (more)

Subjects/Keywords: Static Timing Analysis; Partitioning; Heuristics; Microprocessors; Digital Logic; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Krishnamurthy, S. T. (2008). STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS. (Masters Thesis). Case Western Reserve University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462

Chicago Manual of Style (16th Edition):

Krishnamurthy, Sivasubramaniam T. “STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.” 2008. Masters Thesis, Case Western Reserve University. Accessed January 26, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

MLA Handbook (7th Edition):

Krishnamurthy, Sivasubramaniam T. “STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.” 2008. Web. 26 Jan 2020.

Vancouver:

Krishnamurthy ST. STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS. [Internet] [Masters thesis]. Case Western Reserve University; 2008. [cited 2020 Jan 26]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

Council of Science Editors:

Krishnamurthy ST. STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS. [Masters Thesis]. Case Western Reserve University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462


McMaster University

17. Qian, Zhizhao. High-Fidelity Simulation Model of a Dual FIFO CAN Stack.

Degree: MASc, 2018, McMaster University

 This thesis presents a simulation model for a Control Area Network (CAN) software stack, the Dual FIFO CAN (DFC) stack, and a method for identifying… (more)

Subjects/Keywords: Controller Area Network; simulation; timing analysis; CAN; modeling; SimEvents

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Qian, Z. (2018). High-Fidelity Simulation Model of a Dual FIFO CAN Stack. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/22847

Chicago Manual of Style (16th Edition):

Qian, Zhizhao. “High-Fidelity Simulation Model of a Dual FIFO CAN Stack.” 2018. Masters Thesis, McMaster University. Accessed January 26, 2020. http://hdl.handle.net/11375/22847.

MLA Handbook (7th Edition):

Qian, Zhizhao. “High-Fidelity Simulation Model of a Dual FIFO CAN Stack.” 2018. Web. 26 Jan 2020.

Vancouver:

Qian Z. High-Fidelity Simulation Model of a Dual FIFO CAN Stack. [Internet] [Masters thesis]. McMaster University; 2018. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/11375/22847.

Council of Science Editors:

Qian Z. High-Fidelity Simulation Model of a Dual FIFO CAN Stack. [Masters Thesis]. McMaster University; 2018. Available from: http://hdl.handle.net/11375/22847


Clemson University

18. Bhanu, Harikrishnan. Timing Side-Channel Attacks on SSH.

Degree: MS, Computer Engineering, 2010, Clemson University

 In most secure communication standards today, additional latency is kept to a minimum to preserve the Quality-of-Service. As a result, it is possible to mount… (more)

Subjects/Keywords: biometrics; hidden markov models; side-channel attack; timing analysis; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bhanu, H. (2010). Timing Side-Channel Attacks on SSH. (Masters Thesis). Clemson University. Retrieved from https://tigerprints.clemson.edu/all_theses/781

Chicago Manual of Style (16th Edition):

Bhanu, Harikrishnan. “Timing Side-Channel Attacks on SSH.” 2010. Masters Thesis, Clemson University. Accessed January 26, 2020. https://tigerprints.clemson.edu/all_theses/781.

MLA Handbook (7th Edition):

Bhanu, Harikrishnan. “Timing Side-Channel Attacks on SSH.” 2010. Web. 26 Jan 2020.

Vancouver:

Bhanu H. Timing Side-Channel Attacks on SSH. [Internet] [Masters thesis]. Clemson University; 2010. [cited 2020 Jan 26]. Available from: https://tigerprints.clemson.edu/all_theses/781.

Council of Science Editors:

Bhanu H. Timing Side-Channel Attacks on SSH. [Masters Thesis]. Clemson University; 2010. Available from: https://tigerprints.clemson.edu/all_theses/781

19. HEMENDRA SINGH NEGI. Two concrete problems in timing analysis of embedded software.

Degree: 2004, National University of Singapore

Subjects/Keywords: Timing Analysis of Embedded Software

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APA (6th Edition):

NEGI, H. S. (2004). Two concrete problems in timing analysis of embedded software. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/27710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

NEGI, HEMENDRA SINGH. “Two concrete problems in timing analysis of embedded software.” 2004. Thesis, National University of Singapore. Accessed January 26, 2020. http://scholarbank.nus.edu.sg/handle/10635/27710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

NEGI, HEMENDRA SINGH. “Two concrete problems in timing analysis of embedded software.” 2004. Web. 26 Jan 2020.

Vancouver:

NEGI HS. Two concrete problems in timing analysis of embedded software. [Internet] [Thesis]. National University of Singapore; 2004. [cited 2020 Jan 26]. Available from: http://scholarbank.nus.edu.sg/handle/10635/27710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

NEGI HS. Two concrete problems in timing analysis of embedded software. [Thesis]. National University of Singapore; 2004. Available from: http://scholarbank.nus.edu.sg/handle/10635/27710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

20. Hassan, Mohamed. Predictable Shared Memory Resources for Multi-Core Real-Time Systems.

Degree: 2017, University of Waterloo

 A major challenge in multi-core real-time systems is the interference problem on the shared hardware components amongst cores. Examples of these shared components include buses,… (more)

Subjects/Keywords: Real-time; Embedded Systems; Comptuer Hardware; Memory Systems; DRAM; Timing analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hassan, M. (2017). Predictable Shared Memory Resources for Multi-Core Real-Time Systems. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/11676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hassan, Mohamed. “Predictable Shared Memory Resources for Multi-Core Real-Time Systems.” 2017. Thesis, University of Waterloo. Accessed January 26, 2020. http://hdl.handle.net/10012/11676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hassan, Mohamed. “Predictable Shared Memory Resources for Multi-Core Real-Time Systems.” 2017. Web. 26 Jan 2020.

Vancouver:

Hassan M. Predictable Shared Memory Resources for Multi-Core Real-Time Systems. [Internet] [Thesis]. University of Waterloo; 2017. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/10012/11676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hassan M. Predictable Shared Memory Resources for Multi-Core Real-Time Systems. [Thesis]. University of Waterloo; 2017. Available from: http://hdl.handle.net/10012/11676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Bouchain, Antoine. Estimation spectrale parcimonieuse de signaux à échantillonnage irrégulier : application à l’analyse vibratoire d’aubes de turbomachines à partir de signaux tip-timing : Sparse spectral analysis of irregularly sampled signals : application to the vibrating analysis of turbomachine blades from tip-timing signals.

Degree: Docteur es, Traitement du signal et des images, 2019, Paris Saclay

Dans le cadre de la certification de ses moteurs d'hélicoptères, Safran Helicopter Engines réalise des essais en fonctionnement lors desquels les réponses vibratoires de turbomachines… (more)

Subjects/Keywords: Analyse spectrale; Echantillonnage non uniforme; Vibration de pales; Tip-Timing; Parcimonie; Spectral analysis; Non uniform sampling; Blade vibration; Tip-Timing; Sparsity

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bouchain, A. (2019). Estimation spectrale parcimonieuse de signaux à échantillonnage irrégulier : application à l’analyse vibratoire d’aubes de turbomachines à partir de signaux tip-timing : Sparse spectral analysis of irregularly sampled signals : application to the vibrating analysis of turbomachine blades from tip-timing signals. (Doctoral Dissertation). Paris Saclay. Retrieved from http://www.theses.fr/2019SACLC029

Chicago Manual of Style (16th Edition):

Bouchain, Antoine. “Estimation spectrale parcimonieuse de signaux à échantillonnage irrégulier : application à l’analyse vibratoire d’aubes de turbomachines à partir de signaux tip-timing : Sparse spectral analysis of irregularly sampled signals : application to the vibrating analysis of turbomachine blades from tip-timing signals.” 2019. Doctoral Dissertation, Paris Saclay. Accessed January 26, 2020. http://www.theses.fr/2019SACLC029.

MLA Handbook (7th Edition):

Bouchain, Antoine. “Estimation spectrale parcimonieuse de signaux à échantillonnage irrégulier : application à l’analyse vibratoire d’aubes de turbomachines à partir de signaux tip-timing : Sparse spectral analysis of irregularly sampled signals : application to the vibrating analysis of turbomachine blades from tip-timing signals.” 2019. Web. 26 Jan 2020.

Vancouver:

Bouchain A. Estimation spectrale parcimonieuse de signaux à échantillonnage irrégulier : application à l’analyse vibratoire d’aubes de turbomachines à partir de signaux tip-timing : Sparse spectral analysis of irregularly sampled signals : application to the vibrating analysis of turbomachine blades from tip-timing signals. [Internet] [Doctoral dissertation]. Paris Saclay; 2019. [cited 2020 Jan 26]. Available from: http://www.theses.fr/2019SACLC029.

Council of Science Editors:

Bouchain A. Estimation spectrale parcimonieuse de signaux à échantillonnage irrégulier : application à l’analyse vibratoire d’aubes de turbomachines à partir de signaux tip-timing : Sparse spectral analysis of irregularly sampled signals : application to the vibrating analysis of turbomachine blades from tip-timing signals. [Doctoral Dissertation]. Paris Saclay; 2019. Available from: http://www.theses.fr/2019SACLC029


University of Washington

22. WU, KEVIN. Detecting Streaming Wireless Cameras with Timing Analysis.

Degree: 2018, University of Washington

 The Internet of Things (IoT) is growing rapidly thanks to the convenience it provides to users, as sensors collect, communicate, and collaborate with each other… (more)

Subjects/Keywords: Cybersecurity; detection; IoT; machine learning; timing analysis; timing attack; Computer science; Computer engineering; Computing and software systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

WU, K. (2018). Detecting Streaming Wireless Cameras with Timing Analysis. (Thesis). University of Washington. Retrieved from http://hdl.handle.net/1773/42265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

WU, KEVIN. “Detecting Streaming Wireless Cameras with Timing Analysis.” 2018. Thesis, University of Washington. Accessed January 26, 2020. http://hdl.handle.net/1773/42265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

WU, KEVIN. “Detecting Streaming Wireless Cameras with Timing Analysis.” 2018. Web. 26 Jan 2020.

Vancouver:

WU K. Detecting Streaming Wireless Cameras with Timing Analysis. [Internet] [Thesis]. University of Washington; 2018. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/1773/42265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

WU K. Detecting Streaming Wireless Cameras with Timing Analysis. [Thesis]. University of Washington; 2018. Available from: http://hdl.handle.net/1773/42265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

23. Hatami, Safar. Gate delay modeling and static timing analysis in ASIC designs considering process variations.

Degree: PhD, Electrical Engineering, 2011, University of Southern California

 Static timing analysis (STA) is a key tool used for the design, optimization, and final sign-off of VLSI (Very Large Scale Integration) circuits. The down… (more)

Subjects/Keywords: VLSI; CSM; Statistical Timing Analysis; Current Source Modeling; Process Variation; Principal Component Analysis; PCA

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APA (6th Edition):

Hatami, S. (2011). Gate delay modeling and static timing analysis in ASIC designs considering process variations. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/658415/rec/2960

Chicago Manual of Style (16th Edition):

Hatami, Safar. “Gate delay modeling and static timing analysis in ASIC designs considering process variations.” 2011. Doctoral Dissertation, University of Southern California. Accessed January 26, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/658415/rec/2960.

MLA Handbook (7th Edition):

Hatami, Safar. “Gate delay modeling and static timing analysis in ASIC designs considering process variations.” 2011. Web. 26 Jan 2020.

Vancouver:

Hatami S. Gate delay modeling and static timing analysis in ASIC designs considering process variations. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2020 Jan 26]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/658415/rec/2960.

Council of Science Editors:

Hatami S. Gate delay modeling and static timing analysis in ASIC designs considering process variations. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/658415/rec/2960

24. Gaspar, Nuno Miguel Pires. Timing analysis: from predictions to certificates.

Degree: 2010, RCAAP

 In real-time systems timing properties must be satisfied in order to guarantee that deadlines will be met. In this context, the calculation of theworst-case execution… (more)

Subjects/Keywords: Timing analysis; Worst-case execution time; Static analysis; Fixpoint computation; Abstract interpretation; Abstraction-carrying code

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gaspar, N. M. P. (2010). Timing analysis: from predictions to certificates. (Thesis). RCAAP. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gaspar, Nuno Miguel Pires. “Timing analysis: from predictions to certificates.” 2010. Thesis, RCAAP. Accessed January 26, 2020. http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gaspar, Nuno Miguel Pires. “Timing analysis: from predictions to certificates.” 2010. Web. 26 Jan 2020.

Vancouver:

Gaspar NMP. Timing analysis: from predictions to certificates. [Internet] [Thesis]. RCAAP; 2010. [cited 2020 Jan 26]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gaspar NMP. Timing analysis: from predictions to certificates. [Thesis]. RCAAP; 2010. Available from: http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

25. Bartoň, Tomáš. Financování projektu z fondů EU .

Degree: 2011, Brno University of Technology

 Diplomová práce se zabývá problematikou projektového řízení a alternativními formami financování. Popisuje teoretické základy, které jsou následně realizovány v praxi. Obsahuje analytickou část problému, kde… (more)

Subjects/Keywords: Projektový management; projekt; časová analýza; analýza rizik.; Project management; project; timing analysis; risk analysis.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bartoň, T. (2011). Financování projektu z fondů EU . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/2552

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bartoň, Tomáš. “Financování projektu z fondů EU .” 2011. Thesis, Brno University of Technology. Accessed January 26, 2020. http://hdl.handle.net/11012/2552.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bartoň, Tomáš. “Financování projektu z fondů EU .” 2011. Web. 26 Jan 2020.

Vancouver:

Bartoň T. Financování projektu z fondů EU . [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/11012/2552.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bartoň T. Financování projektu z fondů EU . [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/2552

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

26. WANG, CHIH-KUAN. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

 This thesis presents an iterative, crosstalk aware timing analyzer. Parameters such as slew rate, voltage supply, coupling capacitance, and load capacitance are shown to affect… (more)

Subjects/Keywords: crosstalk; capacitive crosstalk; dual-vdd; timing analysis; static timing analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

WANG, C. (2006). AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235

Chicago Manual of Style (16th Edition):

WANG, CHIH-KUAN. “AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER.” 2006. Masters Thesis, University of Cincinnati. Accessed January 26, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235.

MLA Handbook (7th Edition):

WANG, CHIH-KUAN. “AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER.” 2006. Web. 26 Jan 2020.

Vancouver:

WANG C. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2020 Jan 26]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235.

Council of Science Editors:

WANG C. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235


Clemson University

27. Lu, Chen. Network Traffic Analysis Using Stochastic Grammars.

Degree: PhD, Electrical Engineering, 2012, Clemson University

 Network traffic analysis is widely used to infer information from Internet traffic. This is possible even if the traffic is encrypted. Previous work uses traffic… (more)

Subjects/Keywords: Botnet Detection; Hidden Markov Model; Network Traffic Analysis; Probabilistic Context-Free Grammar; Timing Analysis; Tor Analysis; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, C. (2012). Network Traffic Analysis Using Stochastic Grammars. (Doctoral Dissertation). Clemson University. Retrieved from https://tigerprints.clemson.edu/all_dissertations/1059

Chicago Manual of Style (16th Edition):

Lu, Chen. “Network Traffic Analysis Using Stochastic Grammars.” 2012. Doctoral Dissertation, Clemson University. Accessed January 26, 2020. https://tigerprints.clemson.edu/all_dissertations/1059.

MLA Handbook (7th Edition):

Lu, Chen. “Network Traffic Analysis Using Stochastic Grammars.” 2012. Web. 26 Jan 2020.

Vancouver:

Lu C. Network Traffic Analysis Using Stochastic Grammars. [Internet] [Doctoral dissertation]. Clemson University; 2012. [cited 2020 Jan 26]. Available from: https://tigerprints.clemson.edu/all_dissertations/1059.

Council of Science Editors:

Lu C. Network Traffic Analysis Using Stochastic Grammars. [Doctoral Dissertation]. Clemson University; 2012. Available from: https://tigerprints.clemson.edu/all_dissertations/1059


Texas A&M University

28. Singh, Karandeep. Maximum and minimum sensitizable timing analysis using data dependent delays.

Degree: 2007, Texas A&M University

 Modern digital designs require high performance and low cost. In this scenario, timing analysis is an essential step for each phase of the integrated circuit… (more)

Subjects/Keywords: sensitizable timing analysis; data dependent delay

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APA (6th Edition):

Singh, K. (2007). Maximum and minimum sensitizable timing analysis using data dependent delays. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/5948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Singh, Karandeep. “Maximum and minimum sensitizable timing analysis using data dependent delays.” 2007. Thesis, Texas A&M University. Accessed January 26, 2020. http://hdl.handle.net/1969.1/5948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Singh, Karandeep. “Maximum and minimum sensitizable timing analysis using data dependent delays.” 2007. Web. 26 Jan 2020.

Vancouver:

Singh K. Maximum and minimum sensitizable timing analysis using data dependent delays. [Internet] [Thesis]. Texas A&M University; 2007. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/1969.1/5948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Singh K. Maximum and minimum sensitizable timing analysis using data dependent delays. [Thesis]. Texas A&M University; 2007. Available from: http://hdl.handle.net/1969.1/5948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Veluswami, Senthilkumar. Statistical static timing analysis considering process variations and crosstalk.

Degree: 2005, Texas A&M University

 Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die… (more)

Subjects/Keywords: Timing analysis; Process variations; Crosstalk

…50 1 I. INTRODUCTION A. Timing Analysis Timing analysis is used to determine the… …clock frequency of the circuit. Static timing analysis is attractive to circuit designers as… …primary inputs. In Static Timing Analysis, the delays are treated as constants. As deep… …circuit timing behavior [1, 2, 3]. Most of the current Static Timing Analysis (… …simultaneously. An alternative approach to overcome this problem is Statistical Static Timing Analysis… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Veluswami, S. (2005). Statistical static timing analysis considering process variations and crosstalk. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/2545

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Veluswami, Senthilkumar. “Statistical static timing analysis considering process variations and crosstalk.” 2005. Thesis, Texas A&M University. Accessed January 26, 2020. http://hdl.handle.net/1969.1/2545.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Veluswami, Senthilkumar. “Statistical static timing analysis considering process variations and crosstalk.” 2005. Web. 26 Jan 2020.

Vancouver:

Veluswami S. Statistical static timing analysis considering process variations and crosstalk. [Internet] [Thesis]. Texas A&M University; 2005. [cited 2020 Jan 26]. Available from: http://hdl.handle.net/1969.1/2545.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Veluswami S. Statistical static timing analysis considering process variations and crosstalk. [Thesis]. Texas A&M University; 2005. Available from: http://hdl.handle.net/1969.1/2545

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Kang, Sang Yeol. Providing Static Timing Anlaysis Support for an ARM7 Processor Platform.

Degree: MS, Computer Engineering, 2008, North Carolina State University

 Scratchpad memory provides faster speed but smaller capacity than other memories do in embedded systems. It provides a visibly heterogeneous memory hierarchy rather than abstracting… (more)

Subjects/Keywords: Static Timing Analysis; WCET; BCET

…ABSTRACT KANG, SANG YEOL. Providing Static Timing Analysis Support for an ARM7 Processor… …program’s timing information. Based on the WCET and BCET estimated by static timing analysis, the… …timing analysis for an ARM processor platform (ARM7TDMI). Basic analysis is performed… …unstructured code are also identified, which make static timing analysis more difficult. A control… …In addition, the static timing analysis framework of this study is implemented by the tool… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kang, S. Y. (2008). Providing Static Timing Anlaysis Support for an ARM7 Processor Platform. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kang, Sang Yeol. “Providing Static Timing Anlaysis Support for an ARM7 Processor Platform.” 2008. Thesis, North Carolina State University. Accessed January 26, 2020. http://www.lib.ncsu.edu/resolver/1840.16/1546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kang, Sang Yeol. “Providing Static Timing Anlaysis Support for an ARM7 Processor Platform.” 2008. Web. 26 Jan 2020.

Vancouver:

Kang SY. Providing Static Timing Anlaysis Support for an ARM7 Processor Platform. [Internet] [Thesis]. North Carolina State University; 2008. [cited 2020 Jan 26]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kang SY. Providing Static Timing Anlaysis Support for an ARM7 Processor Platform. [Thesis]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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