Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Through silicon via). Showing records 1 – 30 of 42 total matches.

[1] [2]

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


NSYSU

1. Huang, Shu-Ting. Fabrication and characterization of high-speed through silicon via.

Degree: Master, Electro-Optical Engineering, 2012, NSYSU

 The target of this thesis is to fabricate through Silicon via (TSV) structures based on Si-bench technology for high-speed transmission interface. In this process, Si… (more)

Subjects/Keywords: s parameters; microwave loss; Through silicon via

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, S. (2012). Fabrication and characterization of high-speed through silicon via. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728112-031923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Shu-Ting. “Fabrication and characterization of high-speed through silicon via.” 2012. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728112-031923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Shu-Ting. “Fabrication and characterization of high-speed through silicon via.” 2012. Web. 23 Feb 2020.

Vancouver:

Huang S. Fabrication and characterization of high-speed through silicon via. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728112-031923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang S. Fabrication and characterization of high-speed through silicon via. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728112-031923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

2. Cho, Young Seek. Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

 Three dimensional packaging is considered as a promising packaging solution that can offer small form factor and high performance capability to high- speed electronics, for… (more)

Subjects/Keywords: 3D Packaging; embedded passive; flip-chip; silicon micromachining; through silicon via

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cho, Y. S. (2010). Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/191382

Chicago Manual of Style (16th Edition):

Cho, Young Seek. “Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems.” 2010. Doctoral Dissertation, University of Minnesota. Accessed February 23, 2020. http://hdl.handle.net/11299/191382.

MLA Handbook (7th Edition):

Cho, Young Seek. “Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems.” 2010. Web. 23 Feb 2020.

Vancouver:

Cho YS. Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/11299/191382.

Council of Science Editors:

Cho YS. Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://hdl.handle.net/11299/191382


NSYSU

3. Chen, You-Yi. Simulation and Analysis of 3D IC Through Silicon Vias (TSVs) Arrays under High-Frequency Electromagnetic Fields.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2014, NSYSU

 This study consists of two parts. First part is about the through via in printed circuit board (PCB). In the PCB, signal transmission between different… (more)

Subjects/Keywords: Decoupling Capacitor; , Through Via; Shorting Via; Finite Element Method; Through Silicon Via; S-parameter; Equivalent Circuit Model

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2014). Simulation and Analysis of 3D IC Through Silicon Vias (TSVs) Arrays under High-Frequency Electromagnetic Fields. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0406114-170143

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, You-Yi. “Simulation and Analysis of 3D IC Through Silicon Vias (TSVs) Arrays under High-Frequency Electromagnetic Fields.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0406114-170143.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, You-Yi. “Simulation and Analysis of 3D IC Through Silicon Vias (TSVs) Arrays under High-Frequency Electromagnetic Fields.” 2014. Web. 23 Feb 2020.

Vancouver:

Chen Y. Simulation and Analysis of 3D IC Through Silicon Vias (TSVs) Arrays under High-Frequency Electromagnetic Fields. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0406114-170143.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. Simulation and Analysis of 3D IC Through Silicon Vias (TSVs) Arrays under High-Frequency Electromagnetic Fields. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0406114-170143

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Viswanathan N. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.

Degree: Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters, 2015, Anna University

Three dimensional integration is one of the emerging techniques newlineto find solution for the global interconnect delay challenges faced in the newlineadvanced VLSI ULSI technology… (more)

Subjects/Keywords: Network on Chip; System on Chip; Through Silicon Via

Page 1

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

N, V. (2015). Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Thesis, Anna University. Accessed February 23, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Web. 23 Feb 2020.

Vancouver:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Feb 23]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New Mexico

5. Dou, Jingjing. Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry.

Degree: Mechanical Engineering, 2015, University of New Mexico

 Three-dimensional integration is a solution that vertically stacks multiple layers of silicon chips by Through-Silicon-Vias (TSVs) to enhance the performance of microelectronic devices. The tapered… (more)

Subjects/Keywords: tapered Through-Silicon-Via (TSV); wafer warpage; finite element analysis (FEA)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dou, J. (2015). Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/25737

Chicago Manual of Style (16th Edition):

Dou, Jingjing. “Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry.” 2015. Masters Thesis, University of New Mexico. Accessed February 23, 2020. http://hdl.handle.net/1928/25737.

MLA Handbook (7th Edition):

Dou, Jingjing. “Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry.” 2015. Web. 23 Feb 2020.

Vancouver:

Dou J. Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry. [Internet] [Masters thesis]. University of New Mexico; 2015. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/1928/25737.

Council of Science Editors:

Dou J. Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry. [Masters Thesis]. University of New Mexico; 2015. Available from: http://hdl.handle.net/1928/25737


NSYSU

6. Ho, Cheng-you. An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 This paper presents a set of novel scheme and corresponding methods for Test Interposer Interconnects. Testing interposer is difficult due to the large number of… (more)

Subjects/Keywords: 3D Stack; 3D Package; 2.5D; 3D IC; Interposer; Through-Silicon Via

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ho, C. (2014). An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ho, Cheng-you. “An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ho, Cheng-you. “An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.” 2014. Web. 23 Feb 2020.

Vancouver:

Ho C. An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho C. An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

7. Kumar, Vachan. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Modeling approaches are developed to optimize emerging on-chip and off-chip electrical interconnect technologies and benchmark them against conventional technologies. While transistor scaling results in an… (more)

Subjects/Keywords: Interconnect modeling; Graphene nanoribbons; Through silicon via, airgap interconnects

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, V. (2014). Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54280

Chicago Manual of Style (16th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 23, 2020. http://hdl.handle.net/1853/54280.

MLA Handbook (7th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Web. 23 Feb 2020.

Vancouver:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/1853/54280.

Council of Science Editors:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54280


University of Windsor

8. Basith, Iftekhar Ibne. Contactless Test Access Mechanism for 3D IC.

Degree: PhD, Electrical and Computer Engineering, 2016, University of Windsor

 3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size… (more)

Subjects/Keywords: 3D IC; Contactless; Coupling; Fabrication; Test; Through-Silicon Via

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Basith, I. I. (2016). Contactless Test Access Mechanism for 3D IC. (Doctoral Dissertation). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5799

Chicago Manual of Style (16th Edition):

Basith, Iftekhar Ibne. “Contactless Test Access Mechanism for 3D IC.” 2016. Doctoral Dissertation, University of Windsor. Accessed February 23, 2020. https://scholar.uwindsor.ca/etd/5799.

MLA Handbook (7th Edition):

Basith, Iftekhar Ibne. “Contactless Test Access Mechanism for 3D IC.” 2016. Web. 23 Feb 2020.

Vancouver:

Basith II. Contactless Test Access Mechanism for 3D IC. [Internet] [Doctoral dissertation]. University of Windsor; 2016. [cited 2020 Feb 23]. Available from: https://scholar.uwindsor.ca/etd/5799.

Council of Science Editors:

Basith II. Contactless Test Access Mechanism for 3D IC. [Doctoral Dissertation]. University of Windsor; 2016. Available from: https://scholar.uwindsor.ca/etd/5799


Université Montpellier II

9. Fkih, Yassine. Conception en vue du Test des Circuits Intégrés 3D à base de TSVs : Design for Test of TSV Based 3D Stacked Integrated Circuits.

Degree: Docteur es, Systèmes automatiques et microélectroniques, 2014, Université Montpellier II

Depuis plusieurs années, la complexité des circuits intégrés ne cesse d'augmenter : du SOC (System On Chip) vers le SIP (System In Package), et plus… (more)

Subjects/Keywords: Conception en vue de test; Circuit intégré 3D; TSVs (Through silicon via); Test; Design for Test; 3D stacked integrated circuit; Through silicon via; Test

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fkih, Y. (2014). Conception en vue du Test des Circuits Intégrés 3D à base de TSVs : Design for Test of TSV Based 3D Stacked Integrated Circuits. (Doctoral Dissertation). Université Montpellier II. Retrieved from http://www.theses.fr/2014MON20063

Chicago Manual of Style (16th Edition):

Fkih, Yassine. “Conception en vue du Test des Circuits Intégrés 3D à base de TSVs : Design for Test of TSV Based 3D Stacked Integrated Circuits.” 2014. Doctoral Dissertation, Université Montpellier II. Accessed February 23, 2020. http://www.theses.fr/2014MON20063.

MLA Handbook (7th Edition):

Fkih, Yassine. “Conception en vue du Test des Circuits Intégrés 3D à base de TSVs : Design for Test of TSV Based 3D Stacked Integrated Circuits.” 2014. Web. 23 Feb 2020.

Vancouver:

Fkih Y. Conception en vue du Test des Circuits Intégrés 3D à base de TSVs : Design for Test of TSV Based 3D Stacked Integrated Circuits. [Internet] [Doctoral dissertation]. Université Montpellier II; 2014. [cited 2020 Feb 23]. Available from: http://www.theses.fr/2014MON20063.

Council of Science Editors:

Fkih Y. Conception en vue du Test des Circuits Intégrés 3D à base de TSVs : Design for Test of TSV Based 3D Stacked Integrated Circuits. [Doctoral Dissertation]. Université Montpellier II; 2014. Available from: http://www.theses.fr/2014MON20063


University of Alabama

10. Jordan, Matthew Braxton. Fabrication of Carbon Nanotube filled blind vias and the investigation of Carbon Nanotubes embedded in a copper matrix for three-dimensional chip stacking applications.

Degree: 2013, University of Alabama

Through silicon vias (TSVs) have been studied extensively because of their ability to increase the performance of electronic systems. Ultimately the performance of the TSVs… (more)

Subjects/Keywords: Electronic Thesis or Dissertation;  – thesis; Electrical engineering; Carbon Nanotube; CNT; Copper; Through Silicon Via; TSV

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jordan, M. B. (2013). Fabrication of Carbon Nanotube filled blind vias and the investigation of Carbon Nanotubes embedded in a copper matrix for three-dimensional chip stacking applications. (Thesis). University of Alabama. Retrieved from http://purl.lib.ua.edu/84767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jordan, Matthew Braxton. “Fabrication of Carbon Nanotube filled blind vias and the investigation of Carbon Nanotubes embedded in a copper matrix for three-dimensional chip stacking applications.” 2013. Thesis, University of Alabama. Accessed February 23, 2020. http://purl.lib.ua.edu/84767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jordan, Matthew Braxton. “Fabrication of Carbon Nanotube filled blind vias and the investigation of Carbon Nanotubes embedded in a copper matrix for three-dimensional chip stacking applications.” 2013. Web. 23 Feb 2020.

Vancouver:

Jordan MB. Fabrication of Carbon Nanotube filled blind vias and the investigation of Carbon Nanotubes embedded in a copper matrix for three-dimensional chip stacking applications. [Internet] [Thesis]. University of Alabama; 2013. [cited 2020 Feb 23]. Available from: http://purl.lib.ua.edu/84767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jordan MB. Fabrication of Carbon Nanotube filled blind vias and the investigation of Carbon Nanotubes embedded in a copper matrix for three-dimensional chip stacking applications. [Thesis]. University of Alabama; 2013. Available from: http://purl.lib.ua.edu/84767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Cheng, Yu-Ting. Nickel electroforming combined UV laser processing applied to through silicon via high-frequency component packaging.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2016, NSYSU

 In this study, Nickel electroforming was integrated with 355 nm wavelength ultraviolet laser process to fabricate the through silicon via packaging. This technology was applied… (more)

Subjects/Keywords: nickel electroforming; ultraviolet laser; through silicon via; taper; current density; frequency analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cheng, Y. (2016). Nickel electroforming combined UV laser processing applied to through silicon via high-frequency component packaging. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705116-142733

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Yu-Ting. “Nickel electroforming combined UV laser processing applied to through silicon via high-frequency component packaging.” 2016. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705116-142733.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Yu-Ting. “Nickel electroforming combined UV laser processing applied to through silicon via high-frequency component packaging.” 2016. Web. 23 Feb 2020.

Vancouver:

Cheng Y. Nickel electroforming combined UV laser processing applied to through silicon via high-frequency component packaging. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705116-142733.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng Y. Nickel electroforming combined UV laser processing applied to through silicon via high-frequency component packaging. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705116-142733

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

12. Yao, Wei. Modeling and Optimization for High-speed Links and 3D IC.

Degree: Electrical Engineering, 2012, UCLA

 The advance of modern integrated circuit (IC) processes has supported increasing date rates on chip-to-chip communications in many consumer and professional applications, such as multimedia… (more)

Subjects/Keywords: Electrical engineering; 3D IC; circuit optimization; Interconnect modeling; signal integrity; through-silicon via

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yao, W. (2012). Modeling and Optimization for High-speed Links and 3D IC. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/5f2003tx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yao, Wei. “Modeling and Optimization for High-speed Links and 3D IC.” 2012. Thesis, UCLA. Accessed February 23, 2020. http://www.escholarship.org/uc/item/5f2003tx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yao, Wei. “Modeling and Optimization for High-speed Links and 3D IC.” 2012. Web. 23 Feb 2020.

Vancouver:

Yao W. Modeling and Optimization for High-speed Links and 3D IC. [Internet] [Thesis]. UCLA; 2012. [cited 2020 Feb 23]. Available from: http://www.escholarship.org/uc/item/5f2003tx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yao W. Modeling and Optimization for High-speed Links and 3D IC. [Thesis]. UCLA; 2012. Available from: http://www.escholarship.org/uc/item/5f2003tx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

13. Sadie, Jacob Alexander. Three-Dimensional Inkjet-Printed Metal Nanoparticles: Ink and Application Development.

Degree: Electrical Engineering & Computer Sciences, 2015, University of California – Berkeley

 The field of printed electronics is a rapidly-emerging area of research and development primarily concerned with low-cost fabrication materials and processes for electronic devices. As… (more)

Subjects/Keywords: Electrical engineering; Materials Science; inkjet; nanoparticle; pillar; three-dimensional; through-silicon via

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sadie, J. A. (2015). Three-Dimensional Inkjet-Printed Metal Nanoparticles: Ink and Application Development. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/9vw1m97m

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sadie, Jacob Alexander. “Three-Dimensional Inkjet-Printed Metal Nanoparticles: Ink and Application Development.” 2015. Thesis, University of California – Berkeley. Accessed February 23, 2020. http://www.escholarship.org/uc/item/9vw1m97m.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sadie, Jacob Alexander. “Three-Dimensional Inkjet-Printed Metal Nanoparticles: Ink and Application Development.” 2015. Web. 23 Feb 2020.

Vancouver:

Sadie JA. Three-Dimensional Inkjet-Printed Metal Nanoparticles: Ink and Application Development. [Internet] [Thesis]. University of California – Berkeley; 2015. [cited 2020 Feb 23]. Available from: http://www.escholarship.org/uc/item/9vw1m97m.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sadie JA. Three-Dimensional Inkjet-Printed Metal Nanoparticles: Ink and Application Development. [Thesis]. University of California – Berkeley; 2015. Available from: http://www.escholarship.org/uc/item/9vw1m97m

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

14. Wang, Chi-Chao. Predictive Modeling for Extremely Scaled CMOS and Post Silicon Devices.

Degree: PhD, Electrical Engineering, 2011, Arizona State University

 To extend the lifetime of complementary metal-oxide-semiconductors (CMOS), emerging process techniques are being proposed to conquer the manufacturing difficulties. New structures and materials are proposed… (more)

Subjects/Keywords: Electrical Engineering; Fe-FET; Layout dependent stress effect; nano CMOS; Predictive Modeling; Through Silicon Via

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, C. (2011). Predictive Modeling for Extremely Scaled CMOS and Post Silicon Devices. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/8849

Chicago Manual of Style (16th Edition):

Wang, Chi-Chao. “Predictive Modeling for Extremely Scaled CMOS and Post Silicon Devices.” 2011. Doctoral Dissertation, Arizona State University. Accessed February 23, 2020. http://repository.asu.edu/items/8849.

MLA Handbook (7th Edition):

Wang, Chi-Chao. “Predictive Modeling for Extremely Scaled CMOS and Post Silicon Devices.” 2011. Web. 23 Feb 2020.

Vancouver:

Wang C. Predictive Modeling for Extremely Scaled CMOS and Post Silicon Devices. [Internet] [Doctoral dissertation]. Arizona State University; 2011. [cited 2020 Feb 23]. Available from: http://repository.asu.edu/items/8849.

Council of Science Editors:

Wang C. Predictive Modeling for Extremely Scaled CMOS and Post Silicon Devices. [Doctoral Dissertation]. Arizona State University; 2011. Available from: http://repository.asu.edu/items/8849

15. Pangracious, Vinod. High Performance Three-Dimensional Tree-based FPGA Architecture using 3D Technology Process : Haute performance tridimensionnelle à base de FPGA Arborescents Architecture à l'aide de la technologie 3D processus.

Degree: Docteur es, Informatique, 2014, Université Pierre et Marie Curie – Paris VI

Les FPGAs (Field Programmable Gate Arrays) sont aujourd'hui des acteurs fondamen-taux dans le domaine des calculateurs qui etait auparavant domin par les microprocesseurs et les… (more)

Subjects/Keywords: FPGA arborescents; Integration 3D; TSV; Partionnement; Placement; Modèle thermique; FGPA architecture; Through Silicon Via; 004

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pangracious, V. (2014). High Performance Three-Dimensional Tree-based FPGA Architecture using 3D Technology Process : Haute performance tridimensionnelle à base de FPGA Arborescents Architecture à l'aide de la technologie 3D processus. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2014PA066480

Chicago Manual of Style (16th Edition):

Pangracious, Vinod. “High Performance Three-Dimensional Tree-based FPGA Architecture using 3D Technology Process : Haute performance tridimensionnelle à base de FPGA Arborescents Architecture à l'aide de la technologie 3D processus.” 2014. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed February 23, 2020. http://www.theses.fr/2014PA066480.

MLA Handbook (7th Edition):

Pangracious, Vinod. “High Performance Three-Dimensional Tree-based FPGA Architecture using 3D Technology Process : Haute performance tridimensionnelle à base de FPGA Arborescents Architecture à l'aide de la technologie 3D processus.” 2014. Web. 23 Feb 2020.

Vancouver:

Pangracious V. High Performance Three-Dimensional Tree-based FPGA Architecture using 3D Technology Process : Haute performance tridimensionnelle à base de FPGA Arborescents Architecture à l'aide de la technologie 3D processus. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. [cited 2020 Feb 23]. Available from: http://www.theses.fr/2014PA066480.

Council of Science Editors:

Pangracious V. High Performance Three-Dimensional Tree-based FPGA Architecture using 3D Technology Process : Haute performance tridimensionnelle à base de FPGA Arborescents Architecture à l'aide de la technologie 3D processus. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. Available from: http://www.theses.fr/2014PA066480


University College Cork

16. Hwang, How Yuan. Integrated silicon photonic packaging.

Degree: 2019, University College Cork

Silicon photonics has garnered plenty of interests from both the academia and industry due to its high-speed transmission potential as well as sensing capability to… (more)

Subjects/Keywords: MEMS optical switch; Pluggable; Silicon photonics; Packaging; Design rules; Evanescent; Through glass via

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hwang, H. Y. (2019). Integrated silicon photonic packaging. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/9524

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hwang, How Yuan. “Integrated silicon photonic packaging.” 2019. Thesis, University College Cork. Accessed February 23, 2020. http://hdl.handle.net/10468/9524.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hwang, How Yuan. “Integrated silicon photonic packaging.” 2019. Web. 23 Feb 2020.

Vancouver:

Hwang HY. Integrated silicon photonic packaging. [Internet] [Thesis]. University College Cork; 2019. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10468/9524.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hwang HY. Integrated silicon photonic packaging. [Thesis]. University College Cork; 2019. Available from: http://hdl.handle.net/10468/9524

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Defforge, Thomas. Optimisation de la gravure de macropores ordonnés dans le silicium et de leur remplissage de cuivre par voie électrochimique : application aux via traversants conducteurs : Optimization of ordered macropore etching in silicon and their filling copper by electrochemical way : application to through silicon via.

Degree: Docteur es, Electronique, 2012, Université François-Rabelais de Tours

Ces travaux de thèse portent sur la fabrication de via traversants conducteurs, brique technologique indispensable pour l’intégration des composants microélectroniques en 3 dimensions. Pour ce… (more)

Subjects/Keywords: Silicium poreux; Anodisation; Gravure électrochimique du silicium; Via traversants conducteurs; Dépôt électrochimique de cuivre; Porous silicon; Anodization; Silicon electrochemical etching; Through silicon via; Copper electrochemical deposition

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Defforge, T. (2012). Optimisation de la gravure de macropores ordonnés dans le silicium et de leur remplissage de cuivre par voie électrochimique : application aux via traversants conducteurs : Optimization of ordered macropore etching in silicon and their filling copper by electrochemical way : application to through silicon via. (Doctoral Dissertation). Université François-Rabelais de Tours. Retrieved from http://www.theses.fr/2012TOUR4033

Chicago Manual of Style (16th Edition):

Defforge, Thomas. “Optimisation de la gravure de macropores ordonnés dans le silicium et de leur remplissage de cuivre par voie électrochimique : application aux via traversants conducteurs : Optimization of ordered macropore etching in silicon and their filling copper by electrochemical way : application to through silicon via.” 2012. Doctoral Dissertation, Université François-Rabelais de Tours. Accessed February 23, 2020. http://www.theses.fr/2012TOUR4033.

MLA Handbook (7th Edition):

Defforge, Thomas. “Optimisation de la gravure de macropores ordonnés dans le silicium et de leur remplissage de cuivre par voie électrochimique : application aux via traversants conducteurs : Optimization of ordered macropore etching in silicon and their filling copper by electrochemical way : application to through silicon via.” 2012. Web. 23 Feb 2020.

Vancouver:

Defforge T. Optimisation de la gravure de macropores ordonnés dans le silicium et de leur remplissage de cuivre par voie électrochimique : application aux via traversants conducteurs : Optimization of ordered macropore etching in silicon and their filling copper by electrochemical way : application to through silicon via. [Internet] [Doctoral dissertation]. Université François-Rabelais de Tours; 2012. [cited 2020 Feb 23]. Available from: http://www.theses.fr/2012TOUR4033.

Council of Science Editors:

Defforge T. Optimisation de la gravure de macropores ordonnés dans le silicium et de leur remplissage de cuivre par voie électrochimique : application aux via traversants conducteurs : Optimization of ordered macropore etching in silicon and their filling copper by electrochemical way : application to through silicon via. [Doctoral Dissertation]. Université François-Rabelais de Tours; 2012. Available from: http://www.theses.fr/2012TOUR4033

18. Al attar, Sari. Conception et mise au point d'un procédé d'assemblage (Packaging) 3D ultra-compact de puces silicium amincies, empilées et interconnectées par des via électriques traversant latéralement les résines polymères d'enrobage : Design and development of three-dimensional assembly of integrated circuits embedded in a polymer.

Degree: Docteur es, Micro et Nanosystèmes, 2012, Toulouse, INSA

Ce travail de thèse vise la définition et la mise au point de technologies pour l'empilement depuces microélectroniques dans un polymère et connectées électriquement par… (more)

Subjects/Keywords: SiP; 3D-interconnect technology; Assemblage 3D; TPV-Through Silicon Via; Wafer-Level Packaging; SiP; 3D-interconnect technology; TPV-Through Silicon Vi; Wafer-Level Packaging; 621.381

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Al attar, S. (2012). Conception et mise au point d'un procédé d'assemblage (Packaging) 3D ultra-compact de puces silicium amincies, empilées et interconnectées par des via électriques traversant latéralement les résines polymères d'enrobage : Design and development of three-dimensional assembly of integrated circuits embedded in a polymer. (Doctoral Dissertation). Toulouse, INSA. Retrieved from http://www.theses.fr/2012ISAT0008

Chicago Manual of Style (16th Edition):

Al attar, Sari. “Conception et mise au point d'un procédé d'assemblage (Packaging) 3D ultra-compact de puces silicium amincies, empilées et interconnectées par des via électriques traversant latéralement les résines polymères d'enrobage : Design and development of three-dimensional assembly of integrated circuits embedded in a polymer.” 2012. Doctoral Dissertation, Toulouse, INSA. Accessed February 23, 2020. http://www.theses.fr/2012ISAT0008.

MLA Handbook (7th Edition):

Al attar, Sari. “Conception et mise au point d'un procédé d'assemblage (Packaging) 3D ultra-compact de puces silicium amincies, empilées et interconnectées par des via électriques traversant latéralement les résines polymères d'enrobage : Design and development of three-dimensional assembly of integrated circuits embedded in a polymer.” 2012. Web. 23 Feb 2020.

Vancouver:

Al attar S. Conception et mise au point d'un procédé d'assemblage (Packaging) 3D ultra-compact de puces silicium amincies, empilées et interconnectées par des via électriques traversant latéralement les résines polymères d'enrobage : Design and development of three-dimensional assembly of integrated circuits embedded in a polymer. [Internet] [Doctoral dissertation]. Toulouse, INSA; 2012. [cited 2020 Feb 23]. Available from: http://www.theses.fr/2012ISAT0008.

Council of Science Editors:

Al attar S. Conception et mise au point d'un procédé d'assemblage (Packaging) 3D ultra-compact de puces silicium amincies, empilées et interconnectées par des via électriques traversant latéralement les résines polymères d'enrobage : Design and development of three-dimensional assembly of integrated circuits embedded in a polymer. [Doctoral Dissertation]. Toulouse, INSA; 2012. Available from: http://www.theses.fr/2012ISAT0008


Université de Grenoble

19. Avertin, Sébastien. Développement et caractérisation de procédés de gravure plasma de T.S.V (Through Silicon Via) pour l'intégration tridimensionnelle de circuits intégrés : Development and characterization of plasma etch processes for TSV (Through Silicon Via) for Integration of Three-Dimensional Integrated Circuits.

Degree: Docteur es, Sciences et technologie industrielles, 2012, Université de Grenoble

Les dictats de la course à la miniaturisation et à l'accroissement des performances suivit par les industriels de la microélectronique, se heurte aujourd'hui aux limites… (more)

Subjects/Keywords: Gravure profonde; Plasma; Microélectronique; Interconnections 3D; TSV; Caractérisation de surface (XPS); Deep etching; Plasma; Microelectronics; 3D interconnection; TSV (Through Silicon Via)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Avertin, S. (2012). Développement et caractérisation de procédés de gravure plasma de T.S.V (Through Silicon Via) pour l'intégration tridimensionnelle de circuits intégrés : Development and characterization of plasma etch processes for TSV (Through Silicon Via) for Integration of Three-Dimensional Integrated Circuits. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2012GRENT029

Chicago Manual of Style (16th Edition):

Avertin, Sébastien. “Développement et caractérisation de procédés de gravure plasma de T.S.V (Through Silicon Via) pour l'intégration tridimensionnelle de circuits intégrés : Development and characterization of plasma etch processes for TSV (Through Silicon Via) for Integration of Three-Dimensional Integrated Circuits.” 2012. Doctoral Dissertation, Université de Grenoble. Accessed February 23, 2020. http://www.theses.fr/2012GRENT029.

MLA Handbook (7th Edition):

Avertin, Sébastien. “Développement et caractérisation de procédés de gravure plasma de T.S.V (Through Silicon Via) pour l'intégration tridimensionnelle de circuits intégrés : Development and characterization of plasma etch processes for TSV (Through Silicon Via) for Integration of Three-Dimensional Integrated Circuits.” 2012. Web. 23 Feb 2020.

Vancouver:

Avertin S. Développement et caractérisation de procédés de gravure plasma de T.S.V (Through Silicon Via) pour l'intégration tridimensionnelle de circuits intégrés : Development and characterization of plasma etch processes for TSV (Through Silicon Via) for Integration of Three-Dimensional Integrated Circuits. [Internet] [Doctoral dissertation]. Université de Grenoble; 2012. [cited 2020 Feb 23]. Available from: http://www.theses.fr/2012GRENT029.

Council of Science Editors:

Avertin S. Développement et caractérisation de procédés de gravure plasma de T.S.V (Through Silicon Via) pour l'intégration tridimensionnelle de circuits intégrés : Development and characterization of plasma etch processes for TSV (Through Silicon Via) for Integration of Three-Dimensional Integrated Circuits. [Doctoral Dissertation]. Université de Grenoble; 2012. Available from: http://www.theses.fr/2012GRENT029


University of Minnesota

20. Marella, Sravan. Performance variations due to layout-dependent stress in VLSI circuits.

Degree: PhD, Electrical Engineering, 2015, University of Minnesota

 Layout-dependent stress is a significant source of variability in advanced VLSI technologies that impacts circuit performance. Mechanical stress affects transistor electrical parameters mobility and threshold… (more)

Subjects/Keywords: 3D-IC; FinFET; Layout dependent mechanical stress; Shallow trench isolation; Static Timing Analysis; Through silicon via

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Marella, S. (2015). Performance variations due to layout-dependent stress in VLSI circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/175249

Chicago Manual of Style (16th Edition):

Marella, Sravan. “Performance variations due to layout-dependent stress in VLSI circuits.” 2015. Doctoral Dissertation, University of Minnesota. Accessed February 23, 2020. http://hdl.handle.net/11299/175249.

MLA Handbook (7th Edition):

Marella, Sravan. “Performance variations due to layout-dependent stress in VLSI circuits.” 2015. Web. 23 Feb 2020.

Vancouver:

Marella S. Performance variations due to layout-dependent stress in VLSI circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2015. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/11299/175249.

Council of Science Editors:

Marella S. Performance variations due to layout-dependent stress in VLSI circuits. [Doctoral Dissertation]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/175249


University of Rochester

21. Savidis, Ioannis (1982 - ). Characterization and modeling of TSV based 3-D integrated circuits.

Degree: PhD, 2013, University of Rochester

Through silicon via (TSV) based three-dimensional integrated circuits have rapidly progressed over the past decade. TSV based three-dimensional integration has the potential to significantly boost… (more)

Subjects/Keywords: 3-D integration; 3-D thermal coupling; Heterogeneous 3-D integration; Power delivery; Synchronization; Through silicon via; TSV

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Savidis, I. (. -. ). (2013). Characterization and modeling of TSV based 3-D integrated circuits. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/27881

Chicago Manual of Style (16th Edition):

Savidis, Ioannis (1982 - ). “Characterization and modeling of TSV based 3-D integrated circuits.” 2013. Doctoral Dissertation, University of Rochester. Accessed February 23, 2020. http://hdl.handle.net/1802/27881.

MLA Handbook (7th Edition):

Savidis, Ioannis (1982 - ). “Characterization and modeling of TSV based 3-D integrated circuits.” 2013. Web. 23 Feb 2020.

Vancouver:

Savidis I(-). Characterization and modeling of TSV based 3-D integrated circuits. [Internet] [Doctoral dissertation]. University of Rochester; 2013. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/1802/27881.

Council of Science Editors:

Savidis I(-). Characterization and modeling of TSV based 3-D integrated circuits. [Doctoral Dissertation]. University of Rochester; 2013. Available from: http://hdl.handle.net/1802/27881

22. Chillara, Krishna Chaitanya. Robust Signaling Techniques for Through Silicon Via Bundles.

Degree: MS, Electrical & Computer Engineering, 2011, University of Massachusetts

  3D circuit integration is becoming increasingly important as one of the remaining techniques for staying on Moore’s law trajectory. 3D Integrated Circuits (ICs) can… (more)

Subjects/Keywords: Through Silicon Via; 3D Integration; VLSI; Signaling techniques; Robustness; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chillara, K. C. (2011). Robust Signaling Techniques for Through Silicon Via Bundles. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/671

Chicago Manual of Style (16th Edition):

Chillara, Krishna Chaitanya. “Robust Signaling Techniques for Through Silicon Via Bundles.” 2011. Masters Thesis, University of Massachusetts. Accessed February 23, 2020. https://scholarworks.umass.edu/theses/671.

MLA Handbook (7th Edition):

Chillara, Krishna Chaitanya. “Robust Signaling Techniques for Through Silicon Via Bundles.” 2011. Web. 23 Feb 2020.

Vancouver:

Chillara KC. Robust Signaling Techniques for Through Silicon Via Bundles. [Internet] [Masters thesis]. University of Massachusetts; 2011. [cited 2020 Feb 23]. Available from: https://scholarworks.umass.edu/theses/671.

Council of Science Editors:

Chillara KC. Robust Signaling Techniques for Through Silicon Via Bundles. [Masters Thesis]. University of Massachusetts; 2011. Available from: https://scholarworks.umass.edu/theses/671

23. Oh, Hanju. Silicon microsystem platform with integrated microfluidic cooling and low-loss through-silicon vias.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 Microfluidic cooling technology is a promising thermal solution for high-performance three-dimensional (3-D) microsystems. However, the integration of microfluidic cooling into 3-D microsystems inevitably impacts tier-to-tier… (more)

Subjects/Keywords: 3D microsystem; Microfluidic cooling; Silicon interposer; Through-silicon via

…Capacitance, and Conductance SACVD Sub-Atomic Chemical Vapor Deposition TSV Through-Silicon Via… …b) a silicon interposer. 3 1.1.2 Through-Silicon Via Technology for Heterogeneous… …Integrated Microsystems A through-silicon via (TSV) is a vertical interconnect that… …stacked silicon dice using through-silicon vias (TSVs) for 3-D microsystem… …cooling into 3-D microsystems inevitably impacts tier-to-tier through-silicon vias (TSVs… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oh, H. (2017). Silicon microsystem platform with integrated microfluidic cooling and low-loss through-silicon vias. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58139

Chicago Manual of Style (16th Edition):

Oh, Hanju. “Silicon microsystem platform with integrated microfluidic cooling and low-loss through-silicon vias.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 23, 2020. http://hdl.handle.net/1853/58139.

MLA Handbook (7th Edition):

Oh, Hanju. “Silicon microsystem platform with integrated microfluidic cooling and low-loss through-silicon vias.” 2017. Web. 23 Feb 2020.

Vancouver:

Oh H. Silicon microsystem platform with integrated microfluidic cooling and low-loss through-silicon vias. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/1853/58139.

Council of Science Editors:

Oh H. Silicon microsystem platform with integrated microfluidic cooling and low-loss through-silicon vias. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58139


Université de Grenoble

24. Brocard, Mélanie. Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits.

Degree: Docteur es, Sciences et technologie industrielles, 2013, Université de Grenoble

Ces dernières années ont vu l'émergence d'un nouveaux concept dans le domaine de la microélectronique pour répondre aux besoins grandissant en termes de performances et… (more)

Subjects/Keywords: Vias traversant le silicium (TSV); Circuit intégrés 3D; Couplage substrat; Modélisation électrique; Simulation électriques; Transistors MOS; Through silicon via (TSV); 3D integrated circuits; Substrate coupling; Modeling; Electrical simulation; MOS transistors

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Brocard, M. (2013). Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2013GRENT049

Chicago Manual of Style (16th Edition):

Brocard, Mélanie. “Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits.” 2013. Doctoral Dissertation, Université de Grenoble. Accessed February 23, 2020. http://www.theses.fr/2013GRENT049.

MLA Handbook (7th Edition):

Brocard, Mélanie. “Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits.” 2013. Web. 23 Feb 2020.

Vancouver:

Brocard M. Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits. [Internet] [Doctoral dissertation]. Université de Grenoble; 2013. [cited 2020 Feb 23]. Available from: http://www.theses.fr/2013GRENT049.

Council of Science Editors:

Brocard M. Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits. [Doctoral Dissertation]. Université de Grenoble; 2013. Available from: http://www.theses.fr/2013GRENT049


NSYSU

25. Lu, Kuan-Chung. Physical Modeling of Broadband Vertical Interconnects with Measurement Verification.

Degree: PhD, Electrical Engineering, 2013, NSYSU

 Despite the shorter physical length and superior electrical properties of the vertical interconnects, the arrangement of corresponding grounding pins drastically affects the characteristic impedance, resulting… (more)

Subjects/Keywords: physical model; broadband scalable model; the method of multiple image-line charges; double-sided probe station; pogo pin; through-silicon via (TSV); Vertical interconnect

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, K. (2013). Physical Modeling of Broadband Vertical Interconnects with Measurement Verification. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1112113-230421

Chicago Manual of Style (16th Edition):

Lu, Kuan-Chung. “Physical Modeling of Broadband Vertical Interconnects with Measurement Verification.” 2013. Doctoral Dissertation, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1112113-230421.

MLA Handbook (7th Edition):

Lu, Kuan-Chung. “Physical Modeling of Broadband Vertical Interconnects with Measurement Verification.” 2013. Web. 23 Feb 2020.

Vancouver:

Lu K. Physical Modeling of Broadband Vertical Interconnects with Measurement Verification. [Internet] [Doctoral dissertation]. NSYSU; 2013. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1112113-230421.

Council of Science Editors:

Lu K. Physical Modeling of Broadband Vertical Interconnects with Measurement Verification. [Doctoral Dissertation]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1112113-230421


University of California – Irvine

26. Alqahtani, Ayed Saad A. Tackling the Effects of Elevated Temperature and Aging Phenomena in 3D Integrated Circuits.

Degree: Electrical and Computer Engineering, 2019, University of California – Irvine

 With technology advancement to the nanoscale level, 3D stacking of Integrated Circuits (ICs) provides significant advantages in saving device footprints, improving power management, and continuing… (more)

Subjects/Keywords: Computer engineering; Computer science; 3D ICs; 3D Network on Chips (3D NoCs); Adaptive Routing; Aging Phenomena; Thermal Management; Thermal Through Silicon Via (TTSV)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alqahtani, A. S. A. (2019). Tackling the Effects of Elevated Temperature and Aging Phenomena in 3D Integrated Circuits. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/95x5m06f

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alqahtani, Ayed Saad A. “Tackling the Effects of Elevated Temperature and Aging Phenomena in 3D Integrated Circuits.” 2019. Thesis, University of California – Irvine. Accessed February 23, 2020. http://www.escholarship.org/uc/item/95x5m06f.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alqahtani, Ayed Saad A. “Tackling the Effects of Elevated Temperature and Aging Phenomena in 3D Integrated Circuits.” 2019. Web. 23 Feb 2020.

Vancouver:

Alqahtani ASA. Tackling the Effects of Elevated Temperature and Aging Phenomena in 3D Integrated Circuits. [Internet] [Thesis]. University of California – Irvine; 2019. [cited 2020 Feb 23]. Available from: http://www.escholarship.org/uc/item/95x5m06f.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alqahtani ASA. Tackling the Effects of Elevated Temperature and Aging Phenomena in 3D Integrated Circuits. [Thesis]. University of California – Irvine; 2019. Available from: http://www.escholarship.org/uc/item/95x5m06f

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Liu, Meng-Hsiang. Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric.

Degree: Materials Science and Engineering, 2019, UCLA

 At UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), we have been developing a fine pitch heterogeneous wafer-scale platform with a single level of… (more)

Subjects/Keywords: Materials Science; copper electroplating; silicon etch; through wafer via

…wafer. 2 1.2 Three-Dimensional Integration and Through Silicon Via (TSV) The… …development of through-silicon vias (TSVs) originated from the evolution of three… …TiN/Ti/Cu layer sputtering Figure 11. TWV fabrication process. 21 3.1 Through Wafer Via… …500 μm of silicon. The via holes are formed by using dry reactive ion etch (DRIE)… …x28;b) zoomin on the 1 µm thermal oxide isolation layer between the silicon and the… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, M. (2019). Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/2cq350q6

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Meng-Hsiang. “Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric.” 2019. Thesis, UCLA. Accessed February 23, 2020. http://www.escholarship.org/uc/item/2cq350q6.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Meng-Hsiang. “Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric.” 2019. Web. 23 Feb 2020.

Vancouver:

Liu M. Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric. [Internet] [Thesis]. UCLA; 2019. [cited 2020 Feb 23]. Available from: http://www.escholarship.org/uc/item/2cq350q6.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu M. Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric. [Thesis]. UCLA; 2019. Available from: http://www.escholarship.org/uc/item/2cq350q6

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Yeleswarapu, Krishnamurthy. TCAD simulation framework for the study of TSV-device interaction.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of… (more)

Subjects/Keywords: Through silicon via; 3D IC; Three-dimensional integrated circuits

Through-Silicon Via (TSV) technology is critical to realizing 3D ICs, because of its… …connecting dies/wafers, through-silicon-via (TSV) technology has emerged as the 3D… …analyzed the through-oxide via (TOV) induced back-gate effect on the characteristics of… …effect of mechanical stress and electrical field coupling between through-silicon vias (… …CTE mismatch between the copper TSV and silicon substrate. This last cause of mechanical… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yeleswarapu, K. (2013). TCAD simulation framework for the study of TSV-device interaction. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51785

Chicago Manual of Style (16th Edition):

Yeleswarapu, Krishnamurthy. “TCAD simulation framework for the study of TSV-device interaction.” 2013. Masters Thesis, Georgia Tech. Accessed February 23, 2020. http://hdl.handle.net/1853/51785.

MLA Handbook (7th Edition):

Yeleswarapu, Krishnamurthy. “TCAD simulation framework for the study of TSV-device interaction.” 2013. Web. 23 Feb 2020.

Vancouver:

Yeleswarapu K. TCAD simulation framework for the study of TSV-device interaction. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/1853/51785.

Council of Science Editors:

Yeleswarapu K. TCAD simulation framework for the study of TSV-device interaction. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/51785


Georgia Tech

29. Natu, Nitish Umesh. Design and prototyping of temperature resilient clock distribution networks.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of… (more)

Subjects/Keywords: 3D IC; Through silicon via; Clock distribution network (CDN); Skew; Propagation delay; Adaptive voltage; Controllable delay; FPGA; Test vehicle; ASIC buffer design; Three-dimensional integrated circuits; Integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Natu, N. U. (2014). Design and prototyping of temperature resilient clock distribution networks. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51812

Chicago Manual of Style (16th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Masters Thesis, Georgia Tech. Accessed February 23, 2020. http://hdl.handle.net/1853/51812.

MLA Handbook (7th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Web. 23 Feb 2020.

Vancouver:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/1853/51812.

Council of Science Editors:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51812


Georgia Tech

30. Abbaspour, Reza. Three-Dimensional Microfabrication Technologies for Electronic and Lab-on-Chip Applications.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The density of heterogeneous three-dimensional integrated circuits (3D-ICs) is significantly limited by through-silicon-via (TSV) density and cooling challenges. To enable fine-grain 3D-ICs, high aspect-ratio sub-micron… (more)

Subjects/Keywords: 3D integrated circuits; through-silicon-via; microfluidics; power dissipation; Bosh process; lab on chip; soft lithography; copper 3D printing; red blood cells

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Abbaspour, R. (2018). Three-Dimensional Microfabrication Technologies for Electronic and Lab-on-Chip Applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62230

Chicago Manual of Style (16th Edition):

Abbaspour, Reza. “Three-Dimensional Microfabrication Technologies for Electronic and Lab-on-Chip Applications.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 23, 2020. http://hdl.handle.net/1853/62230.

MLA Handbook (7th Edition):

Abbaspour, Reza. “Three-Dimensional Microfabrication Technologies for Electronic and Lab-on-Chip Applications.” 2018. Web. 23 Feb 2020.

Vancouver:

Abbaspour R. Three-Dimensional Microfabrication Technologies for Electronic and Lab-on-Chip Applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/1853/62230.

Council of Science Editors:

Abbaspour R. Three-Dimensional Microfabrication Technologies for Electronic and Lab-on-Chip Applications. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/62230

[1] [2]

.