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You searched for subject:(TDDB). Showing records 1 – 21 of 21 total matches.

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University of Minnesota

1. Jain, Pulkit. Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes.

Degree: PhD, Electrical Engineering, 2012, University of Minnesota

 Rising electric fields and imperfections due to atomic level scaling create non-ideal and stochastic electrodynamics inside a transistor.These appear as reliability mechanisms such as Bias… (more)

Subjects/Keywords: 3D IC; BTI; Reliability; RTN; TDDB; TSV

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APA (6th Edition):

Jain, P. (2012). Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/165683

Chicago Manual of Style (16th Edition):

Jain, Pulkit. “Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes.” 2012. Doctoral Dissertation, University of Minnesota. Accessed September 26, 2020. http://hdl.handle.net/11299/165683.

MLA Handbook (7th Edition):

Jain, Pulkit. “Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes.” 2012. Web. 26 Sep 2020.

Vancouver:

Jain P. Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes. [Internet] [Doctoral dissertation]. University of Minnesota; 2012. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/11299/165683.

Council of Science Editors:

Jain P. Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes. [Doctoral Dissertation]. University of Minnesota; 2012. Available from: http://hdl.handle.net/11299/165683


North Carolina State University

2. Lee, Yi-Mu. Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD.

Degree: PhD, Electrical Engineering, 2003, North Carolina State University

 Remote-plasma-enhanced CVD (RPECVD) silicon nitride and silicon oxynitride alloys have been proposed to be the attractive alternatives to replace conventional oxides as the CMOS logic… (more)

Subjects/Keywords: reliability; TDDB breakdown; Gate dielectrics

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APA (6th Edition):

Lee, Y. (2003). Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3705

Chicago Manual of Style (16th Edition):

Lee, Yi-Mu. “Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD.” 2003. Doctoral Dissertation, North Carolina State University. Accessed September 26, 2020. http://www.lib.ncsu.edu/resolver/1840.16/3705.

MLA Handbook (7th Edition):

Lee, Yi-Mu. “Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD.” 2003. Web. 26 Sep 2020.

Vancouver:

Lee Y. Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD. [Internet] [Doctoral dissertation]. North Carolina State University; 2003. [cited 2020 Sep 26]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3705.

Council of Science Editors:

Lee Y. Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD. [Doctoral Dissertation]. North Carolina State University; 2003. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3705

3. Saliva, Marine. Circuits dédiés à l'étude des mécanismes de vieillissement dans les technologies CMOS avancées : conception et mesures : Dedicated circuits to aging mechanisms study in advanced CMOS technology nodes : design and mesurements.

Degree: Docteur es, Mécanique, physique, micro et nanoélectronique, 2015, Aix Marseille Université

Dans la chaine de développement des circuits, une attention particulière doit être portée sur le comportement en fiabilité des dispositifs MOS comme briques de base… (more)

Subjects/Keywords: Fdsoi; Bti; Hci; Tddb; Claquage soft; Moniteurs in-Situ; Abb; Circuits digitaux; Fdsoi; Bti; Hci; Tddb; Soft Breakdown; In situ monitors; Abb; Digital Circuits

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APA (6th Edition):

Saliva, M. (2015). Circuits dédiés à l'étude des mécanismes de vieillissement dans les technologies CMOS avancées : conception et mesures : Dedicated circuits to aging mechanisms study in advanced CMOS technology nodes : design and mesurements. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2015AIXM4337

Chicago Manual of Style (16th Edition):

Saliva, Marine. “Circuits dédiés à l'étude des mécanismes de vieillissement dans les technologies CMOS avancées : conception et mesures : Dedicated circuits to aging mechanisms study in advanced CMOS technology nodes : design and mesurements.” 2015. Doctoral Dissertation, Aix Marseille Université. Accessed September 26, 2020. http://www.theses.fr/2015AIXM4337.

MLA Handbook (7th Edition):

Saliva, Marine. “Circuits dédiés à l'étude des mécanismes de vieillissement dans les technologies CMOS avancées : conception et mesures : Dedicated circuits to aging mechanisms study in advanced CMOS technology nodes : design and mesurements.” 2015. Web. 26 Sep 2020.

Vancouver:

Saliva M. Circuits dédiés à l'étude des mécanismes de vieillissement dans les technologies CMOS avancées : conception et mesures : Dedicated circuits to aging mechanisms study in advanced CMOS technology nodes : design and mesurements. [Internet] [Doctoral dissertation]. Aix Marseille Université 2015. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2015AIXM4337.

Council of Science Editors:

Saliva M. Circuits dédiés à l'étude des mécanismes de vieillissement dans les technologies CMOS avancées : conception et mesures : Dedicated circuits to aging mechanisms study in advanced CMOS technology nodes : design and mesurements. [Doctoral Dissertation]. Aix Marseille Université 2015. Available from: http://www.theses.fr/2015AIXM4337


Virginia Tech

4. Ghosh, Gargi. Dependence of Set, Reset and Breakdown Voltages of a MIM Resistive Memory Device on the Input Voltage Waveform.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Owing to its excellent scaling potential, low power consumption, high switching speed, and good retention, and endurance properties, Resistive Random Access Memory (RRAM) is one… (more)

Subjects/Keywords: resistive switch; non-volatile memory; conductive filament; threshold distributions; interconnect; reliability study; TDDB

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APA (6th Edition):

Ghosh, G. (2015). Dependence of Set, Reset and Breakdown Voltages of a MIM Resistive Memory Device on the Input Voltage Waveform. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52704

Chicago Manual of Style (16th Edition):

Ghosh, Gargi. “Dependence of Set, Reset and Breakdown Voltages of a MIM Resistive Memory Device on the Input Voltage Waveform.” 2015. Masters Thesis, Virginia Tech. Accessed September 26, 2020. http://hdl.handle.net/10919/52704.

MLA Handbook (7th Edition):

Ghosh, Gargi. “Dependence of Set, Reset and Breakdown Voltages of a MIM Resistive Memory Device on the Input Voltage Waveform.” 2015. Web. 26 Sep 2020.

Vancouver:

Ghosh G. Dependence of Set, Reset and Breakdown Voltages of a MIM Resistive Memory Device on the Input Voltage Waveform. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/10919/52704.

Council of Science Editors:

Ghosh G. Dependence of Set, Reset and Breakdown Voltages of a MIM Resistive Memory Device on the Input Voltage Waveform. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/52704


Purdue University

5. Hassan, Khaled, MD. Statistical modeling and simulation of variability and reliability of CMOS technology.

Degree: PhD, Electrical and Computer Engineering, 2016, Purdue University

  The introduction of High-κ Metal Gate transistors led to higher integration density, low leakage current, and faster switching speed. However, this transition in technology… (more)

Subjects/Keywords: Applied sciences; BTI; High-k; RDF; Reliability; SILC; Tddb; Electrical and Computer Engineering

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APA (6th Edition):

Hassan, Khaled, M. (2016). Statistical modeling and simulation of variability and reliability of CMOS technology. (Doctoral Dissertation). Purdue University. Retrieved from https://docs.lib.purdue.edu/open_access_dissertations/932

Chicago Manual of Style (16th Edition):

Hassan, Khaled, MD. “Statistical modeling and simulation of variability and reliability of CMOS technology.” 2016. Doctoral Dissertation, Purdue University. Accessed September 26, 2020. https://docs.lib.purdue.edu/open_access_dissertations/932.

MLA Handbook (7th Edition):

Hassan, Khaled, MD. “Statistical modeling and simulation of variability and reliability of CMOS technology.” 2016. Web. 26 Sep 2020.

Vancouver:

Hassan, Khaled M. Statistical modeling and simulation of variability and reliability of CMOS technology. [Internet] [Doctoral dissertation]. Purdue University; 2016. [cited 2020 Sep 26]. Available from: https://docs.lib.purdue.edu/open_access_dissertations/932.

Council of Science Editors:

Hassan, Khaled M. Statistical modeling and simulation of variability and reliability of CMOS technology. [Doctoral Dissertation]. Purdue University; 2016. Available from: https://docs.lib.purdue.edu/open_access_dissertations/932


University College Cork

6. Hutchinson, Barry James. An investigation of high-k materials in metal-insulator-metal capacitor structures.

Degree: 2017, University College Cork

 Metal insulator metal (MIM) capacitors are vital components of many devices such as communication band beamformers, medical, automotive, RF IC’s and memory applications. Current MIM… (more)

Subjects/Keywords: High-k; Reliability; TDDB; Gamma irradiated; ALD; Conduction mechanisms; MIM capacitor; Dielectric; Atomic layer deposition

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APA (6th Edition):

Hutchinson, B. J. (2017). An investigation of high-k materials in metal-insulator-metal capacitor structures. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/5815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hutchinson, Barry James. “An investigation of high-k materials in metal-insulator-metal capacitor structures.” 2017. Thesis, University College Cork. Accessed September 26, 2020. http://hdl.handle.net/10468/5815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hutchinson, Barry James. “An investigation of high-k materials in metal-insulator-metal capacitor structures.” 2017. Web. 26 Sep 2020.

Vancouver:

Hutchinson BJ. An investigation of high-k materials in metal-insulator-metal capacitor structures. [Internet] [Thesis]. University College Cork; 2017. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/10468/5815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hutchinson BJ. An investigation of high-k materials in metal-insulator-metal capacitor structures. [Thesis]. University College Cork; 2017. Available from: http://hdl.handle.net/10468/5815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

7. Keane, John P. On-Chip circuits for characterizing transistor aging mechanisms in advanced CMOS technologies.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

 The parametric shifts or circuit failures caused by Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time Dependent Dielectric Breakdown (TDDB) in CMOS transistors… (more)

Subjects/Keywords: CMOS Reliability; Digital Circuits; HCI; NBTI; TDDB; Electrical Engineering

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APA (6th Edition):

Keane, J. P. (2010). On-Chip circuits for characterizing transistor aging mechanisms in advanced CMOS technologies. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/123382

Chicago Manual of Style (16th Edition):

Keane, John P. “On-Chip circuits for characterizing transistor aging mechanisms in advanced CMOS technologies.” 2010. Doctoral Dissertation, University of Minnesota. Accessed September 26, 2020. http://purl.umn.edu/123382.

MLA Handbook (7th Edition):

Keane, John P. “On-Chip circuits for characterizing transistor aging mechanisms in advanced CMOS technologies.” 2010. Web. 26 Sep 2020.

Vancouver:

Keane JP. On-Chip circuits for characterizing transistor aging mechanisms in advanced CMOS technologies. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2020 Sep 26]. Available from: http://purl.umn.edu/123382.

Council of Science Editors:

Keane JP. On-Chip circuits for characterizing transistor aging mechanisms in advanced CMOS technologies. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://purl.umn.edu/123382


Université de Bordeaux I

8. El Moukhtari, Issam. Élaboration de nouvelles méthodologies d’évaluation de la fiabilité de circuits nanoélectroniques : Systems and methods for adaptive and real-time detection of biological activity.

Degree: Docteur es, Electronique, 2012, Université de Bordeaux I

Ce travail constitue une contribution à l’étude de la synergie entre le vieillissement accéléré et l’évolution de la robustesse aux évènements singuliers pour les technologies… (more)

Subjects/Keywords: Nbti; Porteurs chaud; Tddb; Électromigration; Effets singuliers; Test par faisceau Laser pulsé; CMOS 65 nm basse puissance; Robustesse; Nbti; Hci; Tddb; Electromigration; Single Event Effects; Pulsed laser testing; CMOS 65 nm Low Power; Robustness

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APA (6th Edition):

El Moukhtari, I. (2012). Élaboration de nouvelles méthodologies d’évaluation de la fiabilité de circuits nanoélectroniques : Systems and methods for adaptive and real-time detection of biological activity. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2012BOR14650

Chicago Manual of Style (16th Edition):

El Moukhtari, Issam. “Élaboration de nouvelles méthodologies d’évaluation de la fiabilité de circuits nanoélectroniques : Systems and methods for adaptive and real-time detection of biological activity.” 2012. Doctoral Dissertation, Université de Bordeaux I. Accessed September 26, 2020. http://www.theses.fr/2012BOR14650.

MLA Handbook (7th Edition):

El Moukhtari, Issam. “Élaboration de nouvelles méthodologies d’évaluation de la fiabilité de circuits nanoélectroniques : Systems and methods for adaptive and real-time detection of biological activity.” 2012. Web. 26 Sep 2020.

Vancouver:

El Moukhtari I. Élaboration de nouvelles méthodologies d’évaluation de la fiabilité de circuits nanoélectroniques : Systems and methods for adaptive and real-time detection of biological activity. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2012. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2012BOR14650.

Council of Science Editors:

El Moukhtari I. Élaboration de nouvelles méthodologies d’évaluation de la fiabilité de circuits nanoélectroniques : Systems and methods for adaptive and real-time detection of biological activity. [Doctoral Dissertation]. Université de Bordeaux I; 2012. Available from: http://www.theses.fr/2012BOR14650

9. Benoist, Antoine. Pre and post breakdwon modeling of high-k dielectrics regarding antifuse and OxRAM non-volatile memories : Modélisation pre et post claquage de diélectriques à haute permittivité dans le cadres des mémoires non volatiles antifuse et OxRAM.

Degree: Docteur es, Génie électrique, 2017, Lyon

Les mémoires non volatiles intégrées représentent une part importante du marché des semi-conducteurs. Bien qu'il s'adresse à de nombreuses applications différentes, ce type de mémoire… (more)

Subjects/Keywords: Electronique de puissance; Haute tension; TDDB - time-Dependent dielectric breakdown; OxRAM - oxide-Based resistive memory; Haute permittivité; Post-Claquage; CMOS avancé; Distribution de courant; Power Electronics; High Voltage; Time-Dependent dielectric breakdown (TDDB); OxRAM - oxide-Based resistive memory; Post breakdown; Advanced CMOS; Read Current Yield; 621.317 072

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APA (6th Edition):

Benoist, A. (2017). Pre and post breakdwon modeling of high-k dielectrics regarding antifuse and OxRAM non-volatile memories : Modélisation pre et post claquage de diélectriques à haute permittivité dans le cadres des mémoires non volatiles antifuse et OxRAM. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2017LYSEI007

Chicago Manual of Style (16th Edition):

Benoist, Antoine. “Pre and post breakdwon modeling of high-k dielectrics regarding antifuse and OxRAM non-volatile memories : Modélisation pre et post claquage de diélectriques à haute permittivité dans le cadres des mémoires non volatiles antifuse et OxRAM.” 2017. Doctoral Dissertation, Lyon. Accessed September 26, 2020. http://www.theses.fr/2017LYSEI007.

MLA Handbook (7th Edition):

Benoist, Antoine. “Pre and post breakdwon modeling of high-k dielectrics regarding antifuse and OxRAM non-volatile memories : Modélisation pre et post claquage de diélectriques à haute permittivité dans le cadres des mémoires non volatiles antifuse et OxRAM.” 2017. Web. 26 Sep 2020.

Vancouver:

Benoist A. Pre and post breakdwon modeling of high-k dielectrics regarding antifuse and OxRAM non-volatile memories : Modélisation pre et post claquage de diélectriques à haute permittivité dans le cadres des mémoires non volatiles antifuse et OxRAM. [Internet] [Doctoral dissertation]. Lyon; 2017. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2017LYSEI007.

Council of Science Editors:

Benoist A. Pre and post breakdwon modeling of high-k dielectrics regarding antifuse and OxRAM non-volatile memories : Modélisation pre et post claquage de diélectriques à haute permittivité dans le cadres des mémoires non volatiles antifuse et OxRAM. [Doctoral Dissertation]. Lyon; 2017. Available from: http://www.theses.fr/2017LYSEI007


Université de Grenoble

10. Delcroix, Pierre. Etude à l'échelle nanométrique par sonde locale de la fiabilité de diélectriques minces pour l'intégration dans les composants microélectroniques du futur : Study at nanoscale, using scanning probe microscopy, of thin dielectric fialibilty for futur integrated devices in microelectronic field.

Degree: Docteur es, Sciences et technologie industrielles, 2012, Université de Grenoble

Afin de pouvoir continuer la miniaturisation de la brique de base des circuits électroniques, le transistor MOS, l’introduction d’oxyde de grille à haute permittivité était… (more)

Subjects/Keywords: Fiabilité; Microscopie à Force Atomique en mode Conduction; TDDB; Métal-Oxyde-Semi-conducteur,; Oxyde bicouche; Filament; Résistance Différentielle Négative; Caractérisation électrique; Microélectronique; Nanoélectronique; Ultravide; Reliability; Atomic Force Microscopy; TDDB; Metal-Oxide-Semiconductor; Bi-layer Oxide; Filament; Negative differential resistance; Electrical characterization; Microelectronics; Nanoelectronics; Ultra high vacuum

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APA (6th Edition):

Delcroix, P. (2012). Etude à l'échelle nanométrique par sonde locale de la fiabilité de diélectriques minces pour l'intégration dans les composants microélectroniques du futur : Study at nanoscale, using scanning probe microscopy, of thin dielectric fialibilty for futur integrated devices in microelectronic field. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2012GRENT080

Chicago Manual of Style (16th Edition):

Delcroix, Pierre. “Etude à l'échelle nanométrique par sonde locale de la fiabilité de diélectriques minces pour l'intégration dans les composants microélectroniques du futur : Study at nanoscale, using scanning probe microscopy, of thin dielectric fialibilty for futur integrated devices in microelectronic field.” 2012. Doctoral Dissertation, Université de Grenoble. Accessed September 26, 2020. http://www.theses.fr/2012GRENT080.

MLA Handbook (7th Edition):

Delcroix, Pierre. “Etude à l'échelle nanométrique par sonde locale de la fiabilité de diélectriques minces pour l'intégration dans les composants microélectroniques du futur : Study at nanoscale, using scanning probe microscopy, of thin dielectric fialibilty for futur integrated devices in microelectronic field.” 2012. Web. 26 Sep 2020.

Vancouver:

Delcroix P. Etude à l'échelle nanométrique par sonde locale de la fiabilité de diélectriques minces pour l'intégration dans les composants microélectroniques du futur : Study at nanoscale, using scanning probe microscopy, of thin dielectric fialibilty for futur integrated devices in microelectronic field. [Internet] [Doctoral dissertation]. Université de Grenoble; 2012. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2012GRENT080.

Council of Science Editors:

Delcroix P. Etude à l'échelle nanométrique par sonde locale de la fiabilité de diélectriques minces pour l'intégration dans les composants microélectroniques du futur : Study at nanoscale, using scanning probe microscopy, of thin dielectric fialibilty for futur integrated devices in microelectronic field. [Doctoral Dissertation]. Université de Grenoble; 2012. Available from: http://www.theses.fr/2012GRENT080


Penn State University

11. Mangalagiri, Prasanth. A Reliable Design Flow for Platform FPGAs.

Degree: 2010, Penn State University

 Aggressive technology scaling over the years has led to increased levels of integration and heterogeneity in the design fabric of Field Programmable Gate Arrays (FPGAs).… (more)

Subjects/Keywords: FPGA; TDDB; HCI; NBTI; CMOS; Dual Vdd; Thermal Estimation; Electromigration

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APA (6th Edition):

Mangalagiri, P. (2010). A Reliable Design Flow for Platform FPGAs. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/10497

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mangalagiri, Prasanth. “A Reliable Design Flow for Platform FPGAs.” 2010. Thesis, Penn State University. Accessed September 26, 2020. https://submit-etda.libraries.psu.edu/catalog/10497.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mangalagiri, Prasanth. “A Reliable Design Flow for Platform FPGAs.” 2010. Web. 26 Sep 2020.

Vancouver:

Mangalagiri P. A Reliable Design Flow for Platform FPGAs. [Internet] [Thesis]. Penn State University; 2010. [cited 2020 Sep 26]. Available from: https://submit-etda.libraries.psu.edu/catalog/10497.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mangalagiri P. A Reliable Design Flow for Platform FPGAs. [Thesis]. Penn State University; 2010. Available from: https://submit-etda.libraries.psu.edu/catalog/10497

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. YIANG KOK YONG. Dielectric reliability of copper/low-k interconnects.

Degree: 2006, National University of Singapore

Subjects/Keywords: Reliability; Low-k; Buried Capping Layer; BCL; TDDB; in-situ FTIRS

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APA (6th Edition):

YONG, Y. K. (2006). Dielectric reliability of copper/low-k interconnects. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/15133

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

YONG, YIANG KOK. “Dielectric reliability of copper/low-k interconnects.” 2006. Thesis, National University of Singapore. Accessed September 26, 2020. http://scholarbank.nus.edu.sg/handle/10635/15133.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

YONG, YIANG KOK. “Dielectric reliability of copper/low-k interconnects.” 2006. Web. 26 Sep 2020.

Vancouver:

YONG YK. Dielectric reliability of copper/low-k interconnects. [Internet] [Thesis]. National University of Singapore; 2006. [cited 2020 Sep 26]. Available from: http://scholarbank.nus.edu.sg/handle/10635/15133.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

YONG YK. Dielectric reliability of copper/low-k interconnects. [Thesis]. National University of Singapore; 2006. Available from: http://scholarbank.nus.edu.sg/handle/10635/15133

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

13. Fang, Runchen. Defect Induced Aging and Breakdown in High-k Dielectrics.

Degree: Electrical Engineering, 2018, Arizona State University

Subjects/Keywords: Electrical engineering; BTI; CMOS Reliability; Emerging Memory; High-k Dielectrics; Resistive Memory; TDDB

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APA (6th Edition):

Fang, R. (2018). Defect Induced Aging and Breakdown in High-k Dielectrics. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/49036

Chicago Manual of Style (16th Edition):

Fang, Runchen. “Defect Induced Aging and Breakdown in High-k Dielectrics.” 2018. Doctoral Dissertation, Arizona State University. Accessed September 26, 2020. http://repository.asu.edu/items/49036.

MLA Handbook (7th Edition):

Fang, Runchen. “Defect Induced Aging and Breakdown in High-k Dielectrics.” 2018. Web. 26 Sep 2020.

Vancouver:

Fang R. Defect Induced Aging and Breakdown in High-k Dielectrics. [Internet] [Doctoral dissertation]. Arizona State University; 2018. [cited 2020 Sep 26]. Available from: http://repository.asu.edu/items/49036.

Council of Science Editors:

Fang R. Defect Induced Aging and Breakdown in High-k Dielectrics. [Doctoral Dissertation]. Arizona State University; 2018. Available from: http://repository.asu.edu/items/49036

14. Aviñó Salvadó, Oriol. Contribution to the study of the SiC MOSFETs gate oxide : Contribution à l'étude de la robustesse de l'oxyde de grille des MOSFET en SiC.

Degree: Docteur es, Génie électrique, 2018, Lyon

Les MOSFET en SiC sont appelées à remplacer les IGBT en Silicium pour des applications de demandant une plus forte vitesse de commutation. Cependant, les… (more)

Subjects/Keywords: Transistor bipolaire à grille isolée - IGBT; MOSFET en SiC; SiO2; Time-Dependent dielectric breakdown - TDDB; High Temperature Gate Bias - HTGB; Oxyde; Diode intrinsèque; Electronique de puissance; Insulated Gate Bipolar Transistor - IGBT; SiC MOSFET; SiO2; Time-Dependent dielectric breakdown - TDDB; High Temperature Gate Bias - HTGB; Intrinsic diode; Power Electronics; 621.317 072

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APA (6th Edition):

Aviñó Salvadó, O. (2018). Contribution to the study of the SiC MOSFETs gate oxide : Contribution à l'étude de la robustesse de l'oxyde de grille des MOSFET en SiC. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2018LYSEI110

Chicago Manual of Style (16th Edition):

Aviñó Salvadó, Oriol. “Contribution to the study of the SiC MOSFETs gate oxide : Contribution à l'étude de la robustesse de l'oxyde de grille des MOSFET en SiC.” 2018. Doctoral Dissertation, Lyon. Accessed September 26, 2020. http://www.theses.fr/2018LYSEI110.

MLA Handbook (7th Edition):

Aviñó Salvadó, Oriol. “Contribution to the study of the SiC MOSFETs gate oxide : Contribution à l'étude de la robustesse de l'oxyde de grille des MOSFET en SiC.” 2018. Web. 26 Sep 2020.

Vancouver:

Aviñó Salvadó O. Contribution to the study of the SiC MOSFETs gate oxide : Contribution à l'étude de la robustesse de l'oxyde de grille des MOSFET en SiC. [Internet] [Doctoral dissertation]. Lyon; 2018. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2018LYSEI110.

Council of Science Editors:

Aviñó Salvadó O. Contribution to the study of the SiC MOSFETs gate oxide : Contribution à l'étude de la robustesse de l'oxyde de grille des MOSFET en SiC. [Doctoral Dissertation]. Lyon; 2018. Available from: http://www.theses.fr/2018LYSEI110

15. Foissac, Romain. Etude à l'échelle nanométrique par sonde locale de la fiabilité et de la dégradation de films minces d'oxyde pour applications MOS et MIM : Study of the reliability and degradation of ultra-thin oxide layers at nanometric scale by scanning probe microscopy for MOS and MIM applications.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2015, Université Grenoble Alpes (ComUE)

L'intégration de diélectriques High-k dans les empilements de grille des dispositifs MOS a fait naître de nouvelles interrogations concernant la fiabilité des futurs nœuds technologiques.… (more)

Subjects/Keywords: Fiabilité; Microscopie à force atomique en mode conduction; TDDB; Métaloxyde semi conducteur; Oxyde bicouche; Filament; Résistance différentielle négative; Caractérisation électrique; Microélectronique; Nanoélectronique; Ultravide; Pulse; ESD; MIM; Mémoires résistives; Reliability; Atomic force microscopy in conductive mode; TDDB; Métal oxyde semi conductor; Bilayer oxide stack; Filament; Negative differential resistance; Electrical caracterisation; Microelectronics; Nanoelectronics; Ultra high vacuum; Pulse; ESD; MIM; Oxide resistive memories; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Foissac, R. (2015). Etude à l'échelle nanométrique par sonde locale de la fiabilité et de la dégradation de films minces d'oxyde pour applications MOS et MIM : Study of the reliability and degradation of ultra-thin oxide layers at nanometric scale by scanning probe microscopy for MOS and MIM applications. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2015GREAT047

Chicago Manual of Style (16th Edition):

Foissac, Romain. “Etude à l'échelle nanométrique par sonde locale de la fiabilité et de la dégradation de films minces d'oxyde pour applications MOS et MIM : Study of the reliability and degradation of ultra-thin oxide layers at nanometric scale by scanning probe microscopy for MOS and MIM applications.” 2015. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed September 26, 2020. http://www.theses.fr/2015GREAT047.

MLA Handbook (7th Edition):

Foissac, Romain. “Etude à l'échelle nanométrique par sonde locale de la fiabilité et de la dégradation de films minces d'oxyde pour applications MOS et MIM : Study of the reliability and degradation of ultra-thin oxide layers at nanometric scale by scanning probe microscopy for MOS and MIM applications.” 2015. Web. 26 Sep 2020.

Vancouver:

Foissac R. Etude à l'échelle nanométrique par sonde locale de la fiabilité et de la dégradation de films minces d'oxyde pour applications MOS et MIM : Study of the reliability and degradation of ultra-thin oxide layers at nanometric scale by scanning probe microscopy for MOS and MIM applications. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2015. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2015GREAT047.

Council of Science Editors:

Foissac R. Etude à l'échelle nanométrique par sonde locale de la fiabilité et de la dégradation de films minces d'oxyde pour applications MOS et MIM : Study of the reliability and degradation of ultra-thin oxide layers at nanometric scale by scanning probe microscopy for MOS and MIM applications. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2015. Available from: http://www.theses.fr/2015GREAT047

16. HANDRA. IMD TDDB (TIME DEPENDENCE DIELECTRIC BREAKDOWN) ON LOW-k DIELETRICS.

Degree: 2008, National University of Singapore

Subjects/Keywords: Low-k dielectrics; TDDB; Process variation (Wafer's Center and Edge); Spacing adjusted voltage stress; Equal e-field

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APA (6th Edition):

HANDRA. (2008). IMD TDDB (TIME DEPENDENCE DIELECTRIC BREAKDOWN) ON LOW-k DIELETRICS. (Thesis). National University of Singapore. Retrieved from https://scholarbank.nus.edu.sg/handle/10635/153914

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

HANDRA. “IMD TDDB (TIME DEPENDENCE DIELECTRIC BREAKDOWN) ON LOW-k DIELETRICS.” 2008. Thesis, National University of Singapore. Accessed September 26, 2020. https://scholarbank.nus.edu.sg/handle/10635/153914.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

HANDRA. “IMD TDDB (TIME DEPENDENCE DIELECTRIC BREAKDOWN) ON LOW-k DIELETRICS.” 2008. Web. 26 Sep 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

HANDRA. IMD TDDB (TIME DEPENDENCE DIELECTRIC BREAKDOWN) ON LOW-k DIELETRICS. [Internet] [Thesis]. National University of Singapore; 2008. [cited 2020 Sep 26]. Available from: https://scholarbank.nus.edu.sg/handle/10635/153914.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

HANDRA. IMD TDDB (TIME DEPENDENCE DIELECTRIC BREAKDOWN) ON LOW-k DIELETRICS. [Thesis]. National University of Singapore; 2008. Available from: https://scholarbank.nus.edu.sg/handle/10635/153914

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

17. LEE YUN. PROCESS IMPROVEMENT IN 0.152 CMOS FOR PLASMA INDUCED DAMAGE IN GATE CURRENT PERFORMANCE.

Degree: 2010, National University of Singapore

Subjects/Keywords: Plasma induced damage; trap charge; interface trapped charge; gate leakage; plasma charging; TDDB; ILD; reliability; C-V measurement; electron shading effect

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APA (6th Edition):

YUN, L. (2010). PROCESS IMPROVEMENT IN 0.152 CMOS FOR PLASMA INDUCED DAMAGE IN GATE CURRENT PERFORMANCE. (Thesis). National University of Singapore. Retrieved from https://scholarbank.nus.edu.sg/handle/10635/153949

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

YUN, LEE. “PROCESS IMPROVEMENT IN 0.152 CMOS FOR PLASMA INDUCED DAMAGE IN GATE CURRENT PERFORMANCE.” 2010. Thesis, National University of Singapore. Accessed September 26, 2020. https://scholarbank.nus.edu.sg/handle/10635/153949.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

YUN, LEE. “PROCESS IMPROVEMENT IN 0.152 CMOS FOR PLASMA INDUCED DAMAGE IN GATE CURRENT PERFORMANCE.” 2010. Web. 26 Sep 2020.

Vancouver:

YUN L. PROCESS IMPROVEMENT IN 0.152 CMOS FOR PLASMA INDUCED DAMAGE IN GATE CURRENT PERFORMANCE. [Internet] [Thesis]. National University of Singapore; 2010. [cited 2020 Sep 26]. Available from: https://scholarbank.nus.edu.sg/handle/10635/153949.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

YUN L. PROCESS IMPROVEMENT IN 0.152 CMOS FOR PLASMA INDUCED DAMAGE IN GATE CURRENT PERFORMANCE. [Thesis]. National University of Singapore; 2010. Available from: https://scholarbank.nus.edu.sg/handle/10635/153949

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Fan, Ye. Resistive Switching Behavior in Low-K Dielectric Compatible with CMOS Back End Process.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 In an effort to lower interconnect time delays and power dissipation in highly integrated logic and memory nanoelectronic products, numerous changes in the materials and… (more)

Subjects/Keywords: resistive switch; non-volatile memory; conductive filament; interconnect; low-k; TDDB

…Density vs Electric Field at 100 C for sample 26, 295 and 307. …...80 Figure 4.10 TDDB… …measurements on sample 26 and sample 295. …81 Figure 4.11 TDDB measurements on sample 307… …of Cu/TaOx/Ru devices. ...….64 Table 4.1 Intel TDDB samples… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fan, Y. (2016). Resistive Switching Behavior in Low-K Dielectric Compatible with CMOS Back End Process. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78172

Chicago Manual of Style (16th Edition):

Fan, Ye. “Resistive Switching Behavior in Low-K Dielectric Compatible with CMOS Back End Process.” 2016. Masters Thesis, Virginia Tech. Accessed September 26, 2020. http://hdl.handle.net/10919/78172.

MLA Handbook (7th Edition):

Fan, Ye. “Resistive Switching Behavior in Low-K Dielectric Compatible with CMOS Back End Process.” 2016. Web. 26 Sep 2020.

Vancouver:

Fan Y. Resistive Switching Behavior in Low-K Dielectric Compatible with CMOS Back End Process. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/10919/78172.

Council of Science Editors:

Fan Y. Resistive Switching Behavior in Low-K Dielectric Compatible with CMOS Back End Process. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/78172


Texas Tech University

19. Williamson, Adam J. Investigation in gate oxide integrity.

Degree: Electrical and Computer Engineering, 2006, Texas Tech University

 Consistent and dependable transistors are necessary for all integrated circuit applications. Of particular interest is the gate silicon oxide (SiO2) region of the transistor. Ramped… (more)

Subjects/Keywords: Gate; Time-dependent dielectric breakdown (TDDB); Capacitance-voltage (CV) Plot; Reliability; Oxide; Gate oxide integrity (GOI)

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APA (6th Edition):

Williamson, A. J. (2006). Investigation in gate oxide integrity. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/10301

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Williamson, Adam J. “Investigation in gate oxide integrity.” 2006. Thesis, Texas Tech University. Accessed September 26, 2020. http://hdl.handle.net/2346/10301.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Williamson, Adam J. “Investigation in gate oxide integrity.” 2006. Web. 26 Sep 2020.

Vancouver:

Williamson AJ. Investigation in gate oxide integrity. [Internet] [Thesis]. Texas Tech University; 2006. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/2346/10301.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Williamson AJ. Investigation in gate oxide integrity. [Thesis]. Texas Tech University; 2006. Available from: http://hdl.handle.net/2346/10301

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

20. Rezaee, Leila. Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology.

Degree: 2008, University of Waterloo

 In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling)… (more)

Subjects/Keywords: Oxide Breakdown; Percolation; CMOS; TDDB; CVS; CCS; SILC; Stress Induced Leakage Current; Markov Chain; Noise; Post-breakdown Current; Soft Breakdown; Hard Breakdown; Weibull; Critical Phenomenon; Quasi-critical Phenomenon; Analytical; Percolation Probability; Reliability; Monte-Carlo

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APA (6th Edition):

Rezaee, L. (2008). Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/4155

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rezaee, Leila. “Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology.” 2008. Thesis, University of Waterloo. Accessed September 26, 2020. http://hdl.handle.net/10012/4155.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rezaee, Leila. “Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology.” 2008. Web. 26 Sep 2020.

Vancouver:

Rezaee L. Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology. [Internet] [Thesis]. University of Waterloo; 2008. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/10012/4155.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rezaee L. Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology. [Thesis]. University of Waterloo; 2008. Available from: http://hdl.handle.net/10012/4155

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Bashir, Muhammad Muqarrab. Modeling reliability in copper/low-k interconnects and variability in cmos.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown… (more)

Subjects/Keywords: Weibull; Copper interconnects; Low-k TDDB; Dielectric breakdown; Interconnect reliability; Low-k dielectrics; CMOS variation; Systematic variation; Random variation; With-die variation; System reliability; Chip reliability; Weibull distribution; Breakdown (Electricity); Integrated circuits

…Tantalum Nitride TDDB Time-Dependent Dielectric Breakdown TEM Transmission Electron… …breakdown of a dielectric’s insulation property. Time-dependent dielectric breakdown (TDDB… …field (E), lower than the breakdown field, to the dielectric. TDDB results in the… …In device operation, TDDB of the gate oxide renders the device useless because of the… …change in current properties. In interconnects, TDDB of the low-k dielectric leads to a… 

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APA (6th Edition):

Bashir, M. M. (2011). Modeling reliability in copper/low-k interconnects and variability in cmos. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41092

Chicago Manual of Style (16th Edition):

Bashir, Muhammad Muqarrab. “Modeling reliability in copper/low-k interconnects and variability in cmos.” 2011. Doctoral Dissertation, Georgia Tech. Accessed September 26, 2020. http://hdl.handle.net/1853/41092.

MLA Handbook (7th Edition):

Bashir, Muhammad Muqarrab. “Modeling reliability in copper/low-k interconnects and variability in cmos.” 2011. Web. 26 Sep 2020.

Vancouver:

Bashir MM. Modeling reliability in copper/low-k interconnects and variability in cmos. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/1853/41092.

Council of Science Editors:

Bashir MM. Modeling reliability in copper/low-k interconnects and variability in cmos. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/41092

.