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You searched for subject:(Systems on chip design). Showing records 1 – 30 of 120689 total matches.

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Ryerson University

1. Tino, Anita. Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures.

Degree: 2011, Ryerson University

 Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works… (more)

Subjects/Keywords: Networks on a chip  – Design; Networks on a chip  – Mathematical models; Networks on a chip; Systems on a chip  – Design; Systems on a chip  – Mathematical models; Systems on a chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tino, A. (2011). Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tino, Anita. “Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures.” 2011. Thesis, Ryerson University. Accessed July 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A1213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tino, Anita. “Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures.” 2011. Web. 18 Jul 2019.

Vancouver:

Tino A. Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures. [Internet] [Thesis]. Ryerson University; 2011. [cited 2019 Jul 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tino A. Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures. [Thesis]. Ryerson University; 2011. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

2. Qian, Zhiliang. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.

Degree: 2014, Hong Kong University of Science and Technology

 With technology scaling down, hundreds and thousands processing elements (PEs) can be integrated on a single chip. Consequently, the embedded systems have led to the… (more)

Subjects/Keywords: Systems on a chip; Design and construction; Networks on a chip

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APA (6th Edition):

Qian, Z. (2014). High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Qian, Zhiliang. “High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed July 18, 2019. https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Qian, Zhiliang. “High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.” 2014. Web. 18 Jul 2019.

Vancouver:

Qian Z. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2019 Jul 18]. Available from: https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Qian Z. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Portland State University

3. Chung, Haera. Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip.

Degree: PhD, Electrical and Computer Engineering, 2013, Portland State University

  Communication has become a bottleneck for modern microprocessors and multi-core chips because metal wires don't scale. The problem becomes worse as the number of… (more)

Subjects/Keywords: Networks on a chip; Systems on a chip  – Design and construction; Heterogeneous computing; Computer and Systems Architecture; Systems and Communications

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APA (6th Edition):

Chung, H. (2013). Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/997

Chicago Manual of Style (16th Edition):

Chung, Haera. “Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip.” 2013. Doctoral Dissertation, Portland State University. Accessed July 18, 2019. https://pdxscholar.library.pdx.edu/open_access_etds/997.

MLA Handbook (7th Edition):

Chung, Haera. “Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip.” 2013. Web. 18 Jul 2019.

Vancouver:

Chung H. Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip. [Internet] [Doctoral dissertation]. Portland State University; 2013. [cited 2019 Jul 18]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/997.

Council of Science Editors:

Chung H. Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip. [Doctoral Dissertation]. Portland State University; 2013. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/997

4. Nitin. A New Approach to Stable Matching and Networks on Chip Problem;.

Degree: 2013, Jaypee University of Information Technology, Solan

This thesis emphasizes that the Stable Matching problems are the same as the problems of stable configurations of Multi stage Interconnection Networks (MIN). Author has… (more)

Subjects/Keywords: Networks on Chip; Systems on Chip

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APA (6th Edition):

Nitin. (2013). A New Approach to Stable Matching and Networks on Chip Problem;. (Thesis). Jaypee University of Information Technology, Solan. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/11151

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nitin. “A New Approach to Stable Matching and Networks on Chip Problem;.” 2013. Thesis, Jaypee University of Information Technology, Solan. Accessed July 18, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/11151.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nitin. “A New Approach to Stable Matching and Networks on Chip Problem;.” 2013. Web. 18 Jul 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Nitin. A New Approach to Stable Matching and Networks on Chip Problem;. [Internet] [Thesis]. Jaypee University of Information Technology, Solan; 2013. [cited 2019 Jul 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11151.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nitin. A New Approach to Stable Matching and Networks on Chip Problem;. [Thesis]. Jaypee University of Information Technology, Solan; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11151

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

5. Briao, Eduardo Wenzel. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.

Degree: 2008, Universidade do Rio Grande do Sul

A complexidade no projeto de sistemas eletrônicos tem aumentado devido à evolução tecnológica e permite a concepção de sistemas inteiros em um único chip (SoCs… (more)

Subjects/Keywords: Embedded systems; Microeletrônica; Design space exploration; Network-on-chip; Systemon- chip; Distributed system

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APA (6th Edition):

Briao, E. W. (2008). Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/13157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Briao, Eduardo Wenzel. “Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed July 18, 2019. http://hdl.handle.net/10183/13157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Briao, Eduardo Wenzel. “Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.” 2008. Web. 18 Jul 2019.

Vancouver:

Briao EW. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2019 Jul 18]. Available from: http://hdl.handle.net/10183/13157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Briao EW. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/13157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

6. Liu, Weichen. Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip.

Degree: 2011, Hong Kong University of Science and Technology

 As feature sizes continue to shrink with the advancement of nanotechnology, multiprocessor system-on-chip (MPSoC) becomes a promising solution to satisfy the growing demands of future… (more)

Subjects/Keywords: Digital light processing; Networks on a chip  – Design and construction; Multiprocessors; Systems on a chip  – Design and construction; Integrated circuits

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APA (6th Edition):

Liu, W. (2011). Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1155165 ; http://lbsearch.ust.hk:3210/sfx?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rfr_id=info:sid/HKUST:SPI&rft.genre=article&rft.issn=0258-7025&rft.volume=39&rft.issue=SUPPL.2&rft.date=2011&rft.spage=&rft.aulast=Liu&rft.aufirst=Weichen&rft.atitle=Design+and+optimization+of+high-performance+resilient+network-on-chip+based+multiprocessor+system-on-chip&rft.title=%E4%B8%AD%E5%9B%BD%E6%BF%80%E5%85%89 ; http://www.scopus.com/record/display.url?eid=2-s2.0-84874457971&origin=inward ; http://repository.ust.hk/ir/bitstream/1783.1-7321/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Weichen. “Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip.” 2011. Thesis, Hong Kong University of Science and Technology. Accessed July 18, 2019. https://doi.org/10.14711/thesis-b1155165 ; http://lbsearch.ust.hk:3210/sfx?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rfr_id=info:sid/HKUST:SPI&rft.genre=article&rft.issn=0258-7025&rft.volume=39&rft.issue=SUPPL.2&rft.date=2011&rft.spage=&rft.aulast=Liu&rft.aufirst=Weichen&rft.atitle=Design+and+optimization+of+high-performance+resilient+network-on-chip+based+multiprocessor+system-on-chip&rft.title=%E4%B8%AD%E5%9B%BD%E6%BF%80%E5%85%89 ; http://www.scopus.com/record/display.url?eid=2-s2.0-84874457971&origin=inward ; http://repository.ust.hk/ir/bitstream/1783.1-7321/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Weichen. “Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip.” 2011. Web. 18 Jul 2019.

Vancouver:

Liu W. Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2011. [cited 2019 Jul 18]. Available from: https://doi.org/10.14711/thesis-b1155165 ; http://lbsearch.ust.hk:3210/sfx?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rfr_id=info:sid/HKUST:SPI&rft.genre=article&rft.issn=0258-7025&rft.volume=39&rft.issue=SUPPL.2&rft.date=2011&rft.spage=&rft.aulast=Liu&rft.aufirst=Weichen&rft.atitle=Design+and+optimization+of+high-performance+resilient+network-on-chip+based+multiprocessor+system-on-chip&rft.title=%E4%B8%AD%E5%9B%BD%E6%BF%80%E5%85%89 ; http://www.scopus.com/record/display.url?eid=2-s2.0-84874457971&origin=inward ; http://repository.ust.hk/ir/bitstream/1783.1-7321/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu W. Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip. [Thesis]. Hong Kong University of Science and Technology; 2011. Available from: https://doi.org/10.14711/thesis-b1155165 ; http://lbsearch.ust.hk:3210/sfx?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rfr_id=info:sid/HKUST:SPI&rft.genre=article&rft.issn=0258-7025&rft.volume=39&rft.issue=SUPPL.2&rft.date=2011&rft.spage=&rft.aulast=Liu&rft.aufirst=Weichen&rft.atitle=Design+and+optimization+of+high-performance+resilient+network-on-chip+based+multiprocessor+system-on-chip&rft.title=%E4%B8%AD%E5%9B%BD%E6%BF%80%E5%85%89 ; http://www.scopus.com/record/display.url?eid=2-s2.0-84874457971&origin=inward ; http://repository.ust.hk/ir/bitstream/1783.1-7321/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

7. Wu, Xiang. Scheduling on-chip networks.

Degree: Electrical and Computer Engineering, 2009, University of Texas – Austin

 Networks-on-Chip (NoC) have been proposed to meet many challenges of modern Systems-on-Chip (SoC) design and manufacturing. At the architectural level, a clean separation of computation… (more)

Subjects/Keywords: Networks-on-chip design; Systems-on-chip design; Network scheduling; Interconnects; Parallel shared memories; Network traffic matrix scheduling; NoC design; Scheduling networks-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, X. (2009). Scheduling on-chip networks. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/6633

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Xiang. “Scheduling on-chip networks.” 2009. Thesis, University of Texas – Austin. Accessed July 18, 2019. http://hdl.handle.net/2152/6633.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Xiang. “Scheduling on-chip networks.” 2009. Web. 18 Jul 2019.

Vancouver:

Wu X. Scheduling on-chip networks. [Internet] [Thesis]. University of Texas – Austin; 2009. [cited 2019 Jul 18]. Available from: http://hdl.handle.net/2152/6633.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu X. Scheduling on-chip networks. [Thesis]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/6633

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

8. Kini, Kuntadi Nitin. System-on-chip (SoC) design challenges - managing non-technical issues.

Degree: Engineering Management, 2009, University of Texas – Austin

 Efforts to increase productivity, reduce time to market, reduce costs and desire for increased functionality on a chip are driving semiconductor companies to consider SoC… (more)

Subjects/Keywords: System-on-chip design; Semiconductors

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APA (6th Edition):

Kini, K. N. (2009). System-on-chip (SoC) design challenges - managing non-technical issues. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2009-08-211

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kini, Kuntadi Nitin. “System-on-chip (SoC) design challenges - managing non-technical issues.” 2009. Thesis, University of Texas – Austin. Accessed July 18, 2019. http://hdl.handle.net/2152/ETD-UT-2009-08-211.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kini, Kuntadi Nitin. “System-on-chip (SoC) design challenges - managing non-technical issues.” 2009. Web. 18 Jul 2019.

Vancouver:

Kini KN. System-on-chip (SoC) design challenges - managing non-technical issues. [Internet] [Thesis]. University of Texas – Austin; 2009. [cited 2019 Jul 18]. Available from: http://hdl.handle.net/2152/ETD-UT-2009-08-211.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kini KN. System-on-chip (SoC) design challenges - managing non-technical issues. [Thesis]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/ETD-UT-2009-08-211

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Mittal, Shaily. Memory customization in multiprocessor Systems-On-Chip.

Degree: Computer Science Engineering, 2014, Jaypee University of Information Technology, Solan

With the change in time, there is increase in the demand of embedded system applications with advanced technologies. Multiprocessor Systems-on-Chip (MPSoC s) become usual in… (more)

Subjects/Keywords: Embedded Systems; Multiprocessor; Systems-On-Chip

Page 1

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mittal, S. (2014). Memory customization in multiprocessor Systems-On-Chip. (Thesis). Jaypee University of Information Technology, Solan. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/18806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mittal, Shaily. “Memory customization in multiprocessor Systems-On-Chip.” 2014. Thesis, Jaypee University of Information Technology, Solan. Accessed July 18, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/18806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mittal, Shaily. “Memory customization in multiprocessor Systems-On-Chip.” 2014. Web. 18 Jul 2019.

Vancouver:

Mittal S. Memory customization in multiprocessor Systems-On-Chip. [Internet] [Thesis]. Jaypee University of Information Technology, Solan; 2014. [cited 2019 Jul 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/18806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mittal S. Memory customization in multiprocessor Systems-On-Chip. [Thesis]. Jaypee University of Information Technology, Solan; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/18806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de València

10. Gilabert Villamón, Francisco. Design Space Exploration for Networks On-chip .

Degree: 2011, Universitat Politècnica de València

 Los diseños multi-núcleo se están convirtiendo en la solución más popular a la mayoría de las limitaciones de los diseños mono-núcleo. Un diseño multi-núcleo sigue… (more)

Subjects/Keywords: Design space exploration; Networks on-chip; On-chip interconnects

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APA (6th Edition):

Gilabert Villamón, F. (2011). Design Space Exploration for Networks On-chip . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/11521

Chicago Manual of Style (16th Edition):

Gilabert Villamón, Francisco. “Design Space Exploration for Networks On-chip .” 2011. Doctoral Dissertation, Universitat Politècnica de València. Accessed July 18, 2019. http://hdl.handle.net/10251/11521.

MLA Handbook (7th Edition):

Gilabert Villamón, Francisco. “Design Space Exploration for Networks On-chip .” 2011. Web. 18 Jul 2019.

Vancouver:

Gilabert Villamón F. Design Space Exploration for Networks On-chip . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2011. [cited 2019 Jul 18]. Available from: http://hdl.handle.net/10251/11521.

Council of Science Editors:

Gilabert Villamón F. Design Space Exploration for Networks On-chip . [Doctoral Dissertation]. Universitat Politècnica de València; 2011. Available from: http://hdl.handle.net/10251/11521


Ryerson University

11. Gharan, Masoud Oveis. Virtual channel organization and arbitration for network on chip router architecure.

Degree: 2016, Ryerson University

 The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the… (more)

Subjects/Keywords: Systems on a chip; Networks on a chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gharan, M. O. (2016). Virtual channel organization and arbitration for network on chip router architecure. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gharan, Masoud Oveis. “Virtual channel organization and arbitration for network on chip router architecure.” 2016. Thesis, Ryerson University. Accessed July 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A5048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gharan, Masoud Oveis. “Virtual channel organization and arbitration for network on chip router architecure.” 2016. Web. 18 Jul 2019.

Vancouver:

Gharan MO. Virtual channel organization and arbitration for network on chip router architecure. [Internet] [Thesis]. Ryerson University; 2016. [cited 2019 Jul 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gharan MO. Virtual channel organization and arbitration for network on chip router architecure. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

12. Raducu, Rares. SoC for real - time object tracking in 3D space.

Degree: 2014, Ryerson University

 With the rapid growth of workplaces, there is also an increase of the risk employees are exposed to. A high percentage of the injuries suffered… (more)

Subjects/Keywords: Systems on a chip  – Design and construction; Image processing  – Digital techniques; Three-dimensional display systems; Accidents  – Prevention

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Raducu, R. (2014). SoC for real - time object tracking in 3D space. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A3469

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Raducu, Rares. “SoC for real - time object tracking in 3D space.” 2014. Thesis, Ryerson University. Accessed July 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A3469.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Raducu, Rares. “SoC for real - time object tracking in 3D space.” 2014. Web. 18 Jul 2019.

Vancouver:

Raducu R. SoC for real - time object tracking in 3D space. [Internet] [Thesis]. Ryerson University; 2014. [cited 2019 Jul 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3469.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Raducu R. SoC for real - time object tracking in 3D space. [Thesis]. Ryerson University; 2014. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3469

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de València

13. Roca Pérez, Antoni. Floorplan-Aware High Performance NoC Design .

Degree: 2012, Universitat Politècnica de València

 Las actuales arquitecturas de m�ltiples n�cleos como los chip multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) han adoptado a las redes… (more)

Subjects/Keywords: Noc; Switch design; On-chip networks; Vlsi

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roca Pérez, A. (2012). Floorplan-Aware High Performance NoC Design . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/17844

Chicago Manual of Style (16th Edition):

Roca Pérez, Antoni. “Floorplan-Aware High Performance NoC Design .” 2012. Doctoral Dissertation, Universitat Politècnica de València. Accessed July 18, 2019. http://hdl.handle.net/10251/17844.

MLA Handbook (7th Edition):

Roca Pérez, Antoni. “Floorplan-Aware High Performance NoC Design .” 2012. Web. 18 Jul 2019.

Vancouver:

Roca Pérez A. Floorplan-Aware High Performance NoC Design . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2012. [cited 2019 Jul 18]. Available from: http://hdl.handle.net/10251/17844.

Council of Science Editors:

Roca Pérez A. Floorplan-Aware High Performance NoC Design . [Doctoral Dissertation]. Universitat Politècnica de València; 2012. Available from: http://hdl.handle.net/10251/17844


University of Utah

14. You, Junbok. Design and optimization of asynchronous network-on-chip.

Degree: PhD, Electrical & Computer Engineering, 2011, University of Utah

 The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on… (more)

Subjects/Keywords: Asynchronous circuit design; Digital VLSI design; Interconnect system; Network-on-chip; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

You, J. (2011). Design and optimization of asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633

Chicago Manual of Style (16th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed July 18, 2019. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

MLA Handbook (7th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Web. 18 Jul 2019.

Vancouver:

You J. Design and optimization of asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2019 Jul 18]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

Council of Science Editors:

You J. Design and optimization of asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633


Universidade do Porto

15. Calado, José Henrique de Magalhães Simões. Synchronization of tasks in multiprocessor systems-on-chip.

Degree: 2010, Universidade do Porto

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 2010 Advisors/Committee Members: Alves, José Carlos dos Santos, Universidade do Porto. Faculdade de Engenharia.

Subjects/Keywords: Systems-on-chip; Multiprocessadores; Sincronização; Microelectrónica

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Calado, J. H. d. M. S. (2010). Synchronization of tasks in multiprocessor systems-on-chip. (Thesis). Universidade do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/57633

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Calado, José Henrique de Magalhães Simões. “Synchronization of tasks in multiprocessor systems-on-chip.” 2010. Thesis, Universidade do Porto. Accessed July 18, 2019. http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/57633.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Calado, José Henrique de Magalhães Simões. “Synchronization of tasks in multiprocessor systems-on-chip.” 2010. Web. 18 Jul 2019.

Vancouver:

Calado JHdMS. Synchronization of tasks in multiprocessor systems-on-chip. [Internet] [Thesis]. Universidade do Porto; 2010. [cited 2019 Jul 18]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/57633.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Calado JHdMS. Synchronization of tasks in multiprocessor systems-on-chip. [Thesis]. Universidade do Porto; 2010. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/57633

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

16. Mo, Morton Kwai Hung. A hierarchical hybrid optical-electronic network-on-chip.

Degree: 2009, Hong Kong University of Science and Technology

 Network-on-chip (NoC) can improve the performance, power efficiency and scalability of multiprocessor system-on-chip (MPSoC). However, traditional NoCs using metallic interconnects consume significant amount of power… (more)

Subjects/Keywords: Systems on a chip; Optical communications

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mo, M. K. H. (2009). A hierarchical hybrid optical-electronic network-on-chip. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1071141 ; http://repository.ust.hk/ir/bitstream/1783.1-7592/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mo, Morton Kwai Hung. “A hierarchical hybrid optical-electronic network-on-chip.” 2009. Thesis, Hong Kong University of Science and Technology. Accessed July 18, 2019. https://doi.org/10.14711/thesis-b1071141 ; http://repository.ust.hk/ir/bitstream/1783.1-7592/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mo, Morton Kwai Hung. “A hierarchical hybrid optical-electronic network-on-chip.” 2009. Web. 18 Jul 2019.

Vancouver:

Mo MKH. A hierarchical hybrid optical-electronic network-on-chip. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2009. [cited 2019 Jul 18]. Available from: https://doi.org/10.14711/thesis-b1071141 ; http://repository.ust.hk/ir/bitstream/1783.1-7592/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mo MKH. A hierarchical hybrid optical-electronic network-on-chip. [Thesis]. Hong Kong University of Science and Technology; 2009. Available from: https://doi.org/10.14711/thesis-b1071141 ; http://repository.ust.hk/ir/bitstream/1783.1-7592/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Sydney

17. Soh, Jeremy. A scalable, portable, FPGA-based implementation of the Unscented Kalman Filter .

Degree: 2017, University of Sydney

 Sustained technological progress has come to a point where robotic/autonomous systems may well soon become ubiquitous. In order for these systems to actually be useful,… (more)

Subjects/Keywords: Field Programmable Gate Array (FPGA); Unscented Kalman Filter (UKF); System-on-chip; state estimation; co-design; control systems

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APA (6th Edition):

Soh, J. (2017). A scalable, portable, FPGA-based implementation of the Unscented Kalman Filter . (Thesis). University of Sydney. Retrieved from http://hdl.handle.net/2123/17286

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Soh, Jeremy. “A scalable, portable, FPGA-based implementation of the Unscented Kalman Filter .” 2017. Thesis, University of Sydney. Accessed July 18, 2019. http://hdl.handle.net/2123/17286.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Soh, Jeremy. “A scalable, portable, FPGA-based implementation of the Unscented Kalman Filter .” 2017. Web. 18 Jul 2019.

Vancouver:

Soh J. A scalable, portable, FPGA-based implementation of the Unscented Kalman Filter . [Internet] [Thesis]. University of Sydney; 2017. [cited 2019 Jul 18]. Available from: http://hdl.handle.net/2123/17286.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Soh J. A scalable, portable, FPGA-based implementation of the Unscented Kalman Filter . [Thesis]. University of Sydney; 2017. Available from: http://hdl.handle.net/2123/17286

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

18. Lau, Sai Kit ECE. Low-voltage low-dropout regulator for system-on-chip applications.

Degree: 2004, Hong Kong University of Science and Technology

 With the rapid development of system-on-chip (SoC) designs, there is a growing trend towards the integration of IC systems and power-management circuits. Local, on-chip and… (more)

Subjects/Keywords: Voltage regulators; Design and construction; Systems on a chip

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APA (6th Edition):

Lau, S. K. E. (2004). Low-voltage low-dropout regulator for system-on-chip applications. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b838713 ; http://repository.ust.hk/ir/bitstream/1783.1-97223/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lau, Sai Kit ECE. “Low-voltage low-dropout regulator for system-on-chip applications.” 2004. Thesis, Hong Kong University of Science and Technology. Accessed July 18, 2019. https://doi.org/10.14711/thesis-b838713 ; http://repository.ust.hk/ir/bitstream/1783.1-97223/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lau, Sai Kit ECE. “Low-voltage low-dropout regulator for system-on-chip applications.” 2004. Web. 18 Jul 2019.

Vancouver:

Lau SKE. Low-voltage low-dropout regulator for system-on-chip applications. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2004. [cited 2019 Jul 18]. Available from: https://doi.org/10.14711/thesis-b838713 ; http://repository.ust.hk/ir/bitstream/1783.1-97223/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lau SKE. Low-voltage low-dropout regulator for system-on-chip applications. [Thesis]. Hong Kong University of Science and Technology; 2004. Available from: https://doi.org/10.14711/thesis-b838713 ; http://repository.ust.hk/ir/bitstream/1783.1-97223/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

19. Burke, Patrick William. A New Look at Retargetable Compilers.

Degree: 2014, University of North Texas

 Consumers demand new and innovative personal computing devices every 2 years when their cellular phone service contracts are renewed. Yet, a 2 year development cycle… (more)

Subjects/Keywords: Retargetable compiler; architecture description; software process; Compilers (Computer programs); Systems on a chip  – Design and construction.; Software failures  – Prevention.

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APA (6th Edition):

Burke, P. W. (2014). A New Look at Retargetable Compilers. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc699988/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Burke, Patrick William. “A New Look at Retargetable Compilers.” 2014. Thesis, University of North Texas. Accessed July 18, 2019. https://digital.library.unt.edu/ark:/67531/metadc699988/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Burke, Patrick William. “A New Look at Retargetable Compilers.” 2014. Web. 18 Jul 2019.

Vancouver:

Burke PW. A New Look at Retargetable Compilers. [Internet] [Thesis]. University of North Texas; 2014. [cited 2019 Jul 18]. Available from: https://digital.library.unt.edu/ark:/67531/metadc699988/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Burke PW. A New Look at Retargetable Compilers. [Thesis]. University of North Texas; 2014. Available from: https://digital.library.unt.edu/ark:/67531/metadc699988/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

20. Gharan, Masoud Oveis. Power and chip-area aware network-on-chip simulation.

Degree: 2011, Ryerson University

 Among different communication architectures employed in Multi-Processor Systems-on-Chip (MPSoC), Network-on-Chip (NoC) is recognized as a state of the art paradigm that can overcome on-chip communication… (more)

Subjects/Keywords: Networks on a chip  – Simulation methods; Systems on a chip  – Simulation methods

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gharan, M. O. (2011). Power and chip-area aware network-on-chip simulation. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gharan, Masoud Oveis. “Power and chip-area aware network-on-chip simulation.” 2011. Thesis, Ryerson University. Accessed July 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A1816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gharan, Masoud Oveis. “Power and chip-area aware network-on-chip simulation.” 2011. Web. 18 Jul 2019.

Vancouver:

Gharan MO. Power and chip-area aware network-on-chip simulation. [Internet] [Thesis]. Ryerson University; 2011. [cited 2019 Jul 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gharan MO. Power and chip-area aware network-on-chip simulation. [Thesis]. Ryerson University; 2011. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Columbia University

21. Yoon, Young Jin. Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip.

Degree: 2017, Columbia University

 Due to the tight power budget and reduced time-to-market, Systems-on-Chip (SoC) have emerged as a power-efficient solution that provides the functionality required by target applications… (more)

Subjects/Keywords: Signal processing; Networks on a chip; Systems on a chip; Computer science; Computer engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yoon, Y. J. (2017). Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8VM4J04

Chicago Manual of Style (16th Edition):

Yoon, Young Jin. “Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip.” 2017. Doctoral Dissertation, Columbia University. Accessed July 18, 2019. https://doi.org/10.7916/D8VM4J04.

MLA Handbook (7th Edition):

Yoon, Young Jin. “Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip.” 2017. Web. 18 Jul 2019.

Vancouver:

Yoon YJ. Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip. [Internet] [Doctoral dissertation]. Columbia University; 2017. [cited 2019 Jul 18]. Available from: https://doi.org/10.7916/D8VM4J04.

Council of Science Editors:

Yoon YJ. Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip. [Doctoral Dissertation]. Columbia University; 2017. Available from: https://doi.org/10.7916/D8VM4J04


Portland State University

22. Amarnath, Avinash. A Self-Configurable Architecture on an Irregular Reconfigurable Fabric.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2011, Portland State University

  Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level.… (more)

Subjects/Keywords: Reconfigurable computing; Self-configuration; Unstructured fabric; Adaptive computing systems; Systems on a chip  – Design and construction; Nanoelectronics; Complementary Metal oxide semiconductors  – Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Amarnath, A. (2011). A Self-Configurable Architecture on an Irregular Reconfigurable Fabric. (Masters Thesis). Portland State University. Retrieved from http://pdxscholar.library.pdx.edu/open_access_etds/634

Chicago Manual of Style (16th Edition):

Amarnath, Avinash. “A Self-Configurable Architecture on an Irregular Reconfigurable Fabric.” 2011. Masters Thesis, Portland State University. Accessed July 18, 2019. http://pdxscholar.library.pdx.edu/open_access_etds/634.

MLA Handbook (7th Edition):

Amarnath, Avinash. “A Self-Configurable Architecture on an Irregular Reconfigurable Fabric.” 2011. Web. 18 Jul 2019.

Vancouver:

Amarnath A. A Self-Configurable Architecture on an Irregular Reconfigurable Fabric. [Internet] [Masters thesis]. Portland State University; 2011. [cited 2019 Jul 18]. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/634.

Council of Science Editors:

Amarnath A. A Self-Configurable Architecture on an Irregular Reconfigurable Fabric. [Masters Thesis]. Portland State University; 2011. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/634


Indian Institute of Science

23. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: 2010, Indian Institute of Science

 A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed July 18, 2019. http://hdl.handle.net/2005/1408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 18 Jul 2019.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2019 Jul 18]. Available from: http://hdl.handle.net/2005/1408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://hdl.handle.net/2005/1408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

24. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: 2010, Indian Institute of Science

 A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed July 18, 2019. http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 18 Jul 2019.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2019 Jul 18]. Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

25. Goldenberg, Dina. Embedded e-maintenance for an FPGA-based reconfigurable system.

Degree: 2007, Ryerson University

 In recent years with the use of Internet Technologies e-Maintenance systems for remote connectivity, performance monitoring and diagnostics were introduced. As reconfigurable system based on… (more)

Subjects/Keywords: Embedded computer systems; Computer-aided design; Programmable logic devices; Systems on a chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Goldenberg, D. (2007). Embedded e-maintenance for an FPGA-based reconfigurable system. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A897

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Goldenberg, Dina. “Embedded e-maintenance for an FPGA-based reconfigurable system.” 2007. Thesis, Ryerson University. Accessed July 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A897.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Goldenberg, Dina. “Embedded e-maintenance for an FPGA-based reconfigurable system.” 2007. Web. 18 Jul 2019.

Vancouver:

Goldenberg D. Embedded e-maintenance for an FPGA-based reconfigurable system. [Internet] [Thesis]. Ryerson University; 2007. [cited 2019 Jul 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A897.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Goldenberg D. Embedded e-maintenance for an FPGA-based reconfigurable system. [Thesis]. Ryerson University; 2007. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A897

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. LIU YANHONG. System-level modeling and analysis of multimedia-soc platforms.

Degree: 2007, National University of Singapore

Subjects/Keywords: embedded systems; multimedia systems; system-on-chip; modeling; performance analysis; system-level design

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APA (6th Edition):

YANHONG, L. (2007). System-level modeling and analysis of multimedia-soc platforms. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/16485

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

YANHONG, LIU. “System-level modeling and analysis of multimedia-soc platforms.” 2007. Thesis, National University of Singapore. Accessed July 18, 2019. http://scholarbank.nus.edu.sg/handle/10635/16485.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

YANHONG, LIU. “System-level modeling and analysis of multimedia-soc platforms.” 2007. Web. 18 Jul 2019.

Vancouver:

YANHONG L. System-level modeling and analysis of multimedia-soc platforms. [Internet] [Thesis]. National University of Singapore; 2007. [cited 2019 Jul 18]. Available from: http://scholarbank.nus.edu.sg/handle/10635/16485.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

YANHONG L. System-level modeling and analysis of multimedia-soc platforms. [Thesis]. National University of Singapore; 2007. Available from: http://scholarbank.nus.edu.sg/handle/10635/16485

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Washington State University

27. [No author]. Evaluating hardware .

Degree: 2006, Washington State University

Subjects/Keywords: Embedded computer systems  – Design and construction.; Systems on a chip.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2006). Evaluating hardware . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “Evaluating hardware .” 2006. Thesis, Washington State University. Accessed July 18, 2019. http://hdl.handle.net/2376/510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “Evaluating hardware .” 2006. Web. 18 Jul 2019.

Vancouver:

author] [. Evaluating hardware . [Internet] [Thesis]. Washington State University; 2006. [cited 2019 Jul 18]. Available from: http://hdl.handle.net/2376/510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Evaluating hardware . [Thesis]. Washington State University; 2006. Available from: http://hdl.handle.net/2376/510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

28. Basavaraj, T. NoC Design & Optimization of Multicore Media Processors.

Degree: 2013, Indian Institute of Science

 Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of… (more)

Subjects/Keywords: Network-On-Chip (NOC); Quality of Service (QOS); Label Switched Network On Chip (LS-NoC); Chip Multiprocessor Designs; Multicore Media Processors; Network-On-Chip (NOC) - Design and Construction; System on Chip (SoC); Link Microarchitectural Exploration, Network-on-Chip (NOC); Tile Exploration - Chip Multiprocessors (CMP); Ford-Fulkerson’s MaxFlow Algorithm; Flow Algorithm; Network-on-Chips; On-Chip Interconnection Networks; Microarchitecture Exploration; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Basavaraj, T. (2013). NoC Design & Optimization of Multicore Media Processors. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Thesis, Indian Institute of Science. Accessed July 18, 2019. http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Web. 18 Jul 2019.

Vancouver:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2019 Jul 18]. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

29. Dwarakanath, Nagendra Gulur. Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements.

Degree: 2015, Indian Institute of Science

 Memory system design is increasingly influencing modern multi-core architectures from both performance and power perspectives. Both main memory latency and bandwidth have im-proved at a… (more)

Subjects/Keywords: Multi Core Architecture; ANATOMY-Cache; DRAM; Off-chip Memory; Off-chip Bandwidth; On-chip Memory Systems; ANATOMY; Multi-Core Memory System; DRAM Cache; Computer System-performance Evaluation; Memory System Design; Computer Science

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APA (6th Edition):

Dwarakanath, N. G. (2015). Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3935 ; http://etd.iisc.ernet.in/abstracts/4812/G27186-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dwarakanath, Nagendra Gulur. “Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements.” 2015. Thesis, Indian Institute of Science. Accessed July 18, 2019. http://etd.iisc.ernet.in/2005/3935 ; http://etd.iisc.ernet.in/abstracts/4812/G27186-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dwarakanath, Nagendra Gulur. “Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements.” 2015. Web. 18 Jul 2019.

Vancouver:

Dwarakanath NG. Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2019 Jul 18]. Available from: http://etd.iisc.ernet.in/2005/3935 ; http://etd.iisc.ernet.in/abstracts/4812/G27186-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dwarakanath NG. Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/2005/3935 ; http://etd.iisc.ernet.in/abstracts/4812/G27186-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Diamantopoulos, Dionysios. Πολυεπίπεδη ταχεία προτυποποίηση και σύνθεση εξειδικευμένων και επαναδιαμορφούμενων συστημάτων πολλαπλών επιταχυντών υλικού.

Degree: 2015, National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ)

 Technological advances of recent years laid the foundation consolidation of informatisationof society, impacting on economic, political, cultural and socialdimensions. At the peak of this realization,… (more)

Subjects/Keywords: Επαναδιαμορφούμενες αρχιτεκτονικές,; Συστήματα σε ψηφίδα; Συστήματα πολλαπλών επιταχυντών υλικού; Ταχεία εικονική προτυποποίηση; Υψηλού επιπέδου σύνθεσης; Συν-σχεδιασμός υλικού/λογισμικού; Συστήματα χαμηλής κατανάλωσης ισχύος; Συστήματα σε δίκτυο; Εργαλεία σχεδιασμού υπολογιστικών συστημάτων; Reconfigurable Architectures; Systems on chip; Network on chip; Many-Accelerator Systems; Rapid virtyal prototypinh; High level synthesis; Hardware/software co-design; Low power systems; VLSI; FPGA; ASIC; Computer aided design

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APA (6th Edition):

Diamantopoulos, D. (2015). Πολυεπίπεδη ταχεία προτυποποίηση και σύνθεση εξειδικευμένων και επαναδιαμορφούμενων συστημάτων πολλαπλών επιταχυντών υλικού. (Thesis). National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ). Retrieved from http://hdl.handle.net/10442/hedi/43011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Diamantopoulos, Dionysios. “Πολυεπίπεδη ταχεία προτυποποίηση και σύνθεση εξειδικευμένων και επαναδιαμορφούμενων συστημάτων πολλαπλών επιταχυντών υλικού.” 2015. Thesis, National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ). Accessed July 18, 2019. http://hdl.handle.net/10442/hedi/43011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Diamantopoulos, Dionysios. “Πολυεπίπεδη ταχεία προτυποποίηση και σύνθεση εξειδικευμένων και επαναδιαμορφούμενων συστημάτων πολλαπλών επιταχυντών υλικού.” 2015. Web. 18 Jul 2019.

Vancouver:

Diamantopoulos D. Πολυεπίπεδη ταχεία προτυποποίηση και σύνθεση εξειδικευμένων και επαναδιαμορφούμενων συστημάτων πολλαπλών επιταχυντών υλικού. [Internet] [Thesis]. National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ); 2015. [cited 2019 Jul 18]. Available from: http://hdl.handle.net/10442/hedi/43011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Diamantopoulos D. Πολυεπίπεδη ταχεία προτυποποίηση και σύνθεση εξειδικευμένων και επαναδιαμορφούμενων συστημάτων πολλαπλών επιταχυντών υλικού. [Thesis]. National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ); 2015. Available from: http://hdl.handle.net/10442/hedi/43011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [4023]

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