You searched for subject:(System on chip).
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Penn State University
1.
Vaidyanathan, Balaji.
RELIABILITY ANALYSIS AND OPTIMIZATION FOR.
Degree: PhD, Computer Science and Engineering, 2009, Penn State University
URL: https://etda.libraries.psu.edu/catalog/10443 
► System-on-Chip occupies a major share of electronic market with products ranging from consumer electronics like cellphone, iPod, gaming machines, PDA, netbooks, smartbooks, and safety critical…
(more)
▼ System-on-Chip occupies a major share of electronic
market with products ranging from consumer electronics like
cellphone, iPod, gaming machines, PDA, netbooks, smartbooks, and
safety critical applications like medical and military electronics.
Technology scaling is an important driver in obtaining a highly
integrable and compact version of these commodity products.
However, the scaling beyond 45nm has brought with it plethora of
issues like process variation, progressive aging, di-electric
breakdown mechanisms, radiation sensitivity, crosstalk, among many
others. From the functionality perspective SoC can be sub-divided
into logic, memory, analog/RF and system bus. Each of the
sub-component have distinct functions and different reliability
metrics that guide their qualification. In this thesis we model the
reliability mechanisms covering NBTI, HCE, SER, crosstalk; analyze
and predict their impact on the SoC sub-components. Using the
gained insight, we propose solutions at circuit level to overcome
them. Specifically in Chapter 2 we outline a silicon verified
statistical aging prediction tool that helps in tracking two
important phenomenons namely, aging and process variation. In
Chapter 3, we analyze pipeline logic statistical aging and propose
solutions to buy back the lost yield during its operational
lifetime. Subsequently we also analyze hardening techniques for
asynchronous control circuitry comprising of C-elements against
radiation induced soft errors. In chapter 4 we propose a novel
heterogeneous 3D architecture for on-chip caches to collectively
reduce statistical aging induced lifetime yield effects and also
the manufacturing cost. A silicon verified compact analytical model
for alpha and neutron SER prediction is proposed that is used to
predict the eDRAM versus SRAM SER trend for the next generation
technology. In Chapter 5 we analyze aging in on-chip bus and
propose a novel hardware based runtime adaptive technique to allow
system bus functionality to gracefully degrade with aging.
Additionally we analyze crosstalk induced power consumption in
on-chip buses and propose an add-on algorithm to the existent code
compression scheme to reduce the same without any power,
performance, or area overhead.
Subjects/Keywords: circuit reliability; system-on-chip
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APA (6th Edition):
Vaidyanathan, B. (2009). RELIABILITY ANALYSIS AND OPTIMIZATION FOR. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/10443
Chicago Manual of Style (16th Edition):
Vaidyanathan, Balaji. “RELIABILITY ANALYSIS AND OPTIMIZATION FOR.” 2009. Doctoral Dissertation, Penn State University. Accessed October 14, 2019.
https://etda.libraries.psu.edu/catalog/10443.
MLA Handbook (7th Edition):
Vaidyanathan, Balaji. “RELIABILITY ANALYSIS AND OPTIMIZATION FOR.” 2009. Web. 14 Oct 2019.
Vancouver:
Vaidyanathan B. RELIABILITY ANALYSIS AND OPTIMIZATION FOR. [Internet] [Doctoral dissertation]. Penn State University; 2009. [cited 2019 Oct 14].
Available from: https://etda.libraries.psu.edu/catalog/10443.
Council of Science Editors:
Vaidyanathan B. RELIABILITY ANALYSIS AND OPTIMIZATION FOR. [Doctoral Dissertation]. Penn State University; 2009. Available from: https://etda.libraries.psu.edu/catalog/10443
Brunel University
2.
Tulasidas, Sivanesan.
Secure expandable communication framework for POCT system development and deployment.
Degree: PhD, 2018, Brunel University
URL: http://bura.brunel.ac.uk/handle/2438/17132
;
https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056
► Health-care delivery in developing countries has many challenges because they do not have enough resources for meeting the healthcare needs and they lack testing lab…
(more)
▼ Health-care delivery in developing countries has many challenges because they do not have enough resources for meeting the healthcare needs and they lack testing lab infras- tructures in communities. It has been proven that Point-Of-Care (POC) testing can be considered as one of the ways to resolve the crisis in healthcare delivery in these com- munities. The POC testing is a mission critical processes in which the patient conduct tests outside of laboratory environment and it needs a secure communication system of architecture support which the research refers as POCT system Almost every ten years there will be a new radio access technology (RAT) is released in the wireless communication system evolution which is primarily driven by the 3GPP standards organisation. It is challenging to develop a predictable communication sys- tem in an environment of frequent changes originated by the 3GPP and the wireless operators. The scalable and expandable network architecture is needed for cost-effective network management, deployment and operation of the POC devices. Security mecha- nisms are necessary to address the specific threats associated with POCT system. Se- curity mechanisms are necessary to address the specific threats associated with POCT system. The POCT system communication must provide secure storage and secure com- munication to maintain patient data privacy and security. The Federal Drug Admin- istration (FDA) reports the leading causes of defects and system failures in medical devices are caused by gaps between the requirements, implementation and testing. The research was conducted, and technical research contributions are made to resolve the issues and challenges related to the POCT system. A communication protocol implemented at the application level, independent of radio access technologies. A new methodology was created by combining Easy Approach to Requirement Specifications (EARS) methodology and Use Case Maps (UCM) model which is a new approach and it addresses the concerns raised by the FDA. Secure cloud architecture was created which is a new way of data storage and security algorithms models were designed to address the security threats in the POCT system. The security algorithms, secure cloud architecture and the communication protocol coexist together to provide Radio access technology Independent Secure and Expandable (RISE) POCT system. These are the contributions to new knowledge that came out of the research. The research was conducted with a team of experts who are the subject matter experts in the areas such as microfluidics, bio-medical, mechanical engineering and medicine.
Subjects/Keywords: Lab on chip system development
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APA (6th Edition):
Tulasidas, S. (2018). Secure expandable communication framework for POCT system development and deployment. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056
Chicago Manual of Style (16th Edition):
Tulasidas, Sivanesan. “Secure expandable communication framework for POCT system development and deployment.” 2018. Doctoral Dissertation, Brunel University. Accessed October 14, 2019.
http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056.
MLA Handbook (7th Edition):
Tulasidas, Sivanesan. “Secure expandable communication framework for POCT system development and deployment.” 2018. Web. 14 Oct 2019.
Vancouver:
Tulasidas S. Secure expandable communication framework for POCT system development and deployment. [Internet] [Doctoral dissertation]. Brunel University; 2018. [cited 2019 Oct 14].
Available from: http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056.
Council of Science Editors:
Tulasidas S. Secure expandable communication framework for POCT system development and deployment. [Doctoral Dissertation]. Brunel University; 2018. Available from: http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056
University of Florida
3.
Sadi, Mehdi Zahid.
On-Chip Structures for Reliability Management of System-On-Chips.
Degree: PhD, Electrical and Computer Engineering, 2017, University of Florida
URL: http://ufdc.ufl.edu/UFE0051010
► With aggressive technology scaling in the finfet era the transistor density per unit chip area has increased significantly over the past decade. As a result…
(more)
▼ With aggressive technology scaling in the finfet era the transistor density per unit
chip area has increased significantly over the past decade. As a result billion transistor complex
System on Chips (SoC) that integrate multicore processors, memory, ASIC on the same die are becoming the trend. The semiconductor design houses actively conform to this trend to remain competitive in the global market. Although the complex design of emerging SoCs offer significant performance boost with innovative features, maintaining lifetime reliable operation of these SoCs are becoming a challenge. To develop an integrated framework for continuous monitoring of key hardware reliability parameters, we explore the design of novel embedded on-
chip structures that can collect key reliability data from critical components of the SoC in-field. Moreover, we explore the use of software level machine learning techniques to process the data collected by these on-
chip macros for the reliability and integrity management of SoCs. In this presentation the primary focus will be on the reliability challenges stemming from power supply noise, timing delay of critical paths, and in-field aging degradation.
Advisors/Committee Members: TEHRANIPOOR,MARK M (committee chair), BHUNIA,SWARUP (committee member), BUTLER,KEVIN (committee member).
Subjects/Keywords: reliability – system-on-chip – vlsi
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APA (6th Edition):
Sadi, M. Z. (2017). On-Chip Structures for Reliability Management of System-On-Chips. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0051010
Chicago Manual of Style (16th Edition):
Sadi, Mehdi Zahid. “On-Chip Structures for Reliability Management of System-On-Chips.” 2017. Doctoral Dissertation, University of Florida. Accessed October 14, 2019.
http://ufdc.ufl.edu/UFE0051010.
MLA Handbook (7th Edition):
Sadi, Mehdi Zahid. “On-Chip Structures for Reliability Management of System-On-Chips.” 2017. Web. 14 Oct 2019.
Vancouver:
Sadi MZ. On-Chip Structures for Reliability Management of System-On-Chips. [Internet] [Doctoral dissertation]. University of Florida; 2017. [cited 2019 Oct 14].
Available from: http://ufdc.ufl.edu/UFE0051010.
Council of Science Editors:
Sadi MZ. On-Chip Structures for Reliability Management of System-On-Chips. [Doctoral Dissertation]. University of Florida; 2017. Available from: http://ufdc.ufl.edu/UFE0051010
University of Manitoba
4.
Cook, Darcy Philip.
A multiprocessng system-on-chip framework targeting stream-oriented applications.
Degree: Electrical and Computer Engineering, 2011, University of Manitoba
URL: http://hdl.handle.net/1993/4383
► Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be…
(more)
▼ Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be considered to increase the processing speed of the
system (due to overheating and other constraints), the development of multiprocessors on a single
chip has stepped up to meet the demand. One approach has been to design and develop a multiprocessing platform to handle a large set of homogeneous applications. However, this development has been slow due to the intractable design space, which results when both the hardware and software are required to be adjustable to meet the needs of the dissimilar applications. A different approach has been to limit the number of targeted applications to be similar in some sense. By limiting the number of targeted applications to a cohesive set, the design space can become manageable. This thesis proposes a framework for a multiprocessing
system-on-
chip (MPSoC), consisting of a cohesive hardware and software architecture intended specifically for problems that are stream-oriented (e.g., video streaming). The framework allows the hardware and software to be customized to fit a specific application within the cohesive set, while narrowing the design space to a manageable set of design parameters. In addition, this thesis designs and develops an analytic model, using a discrete-time Markov chain, to measure the performance of an MPSoC framework implementation when the number of concurrent processing elements is varied. Finally, a chaotic simulated annealing algorithm was developed to determine an optimal mapping and scheduling of tasks to processing elements within the MPSoC.
Advisors/Committee Members: Ferens, Ken (Electrical and Computer Engineering) (supervisor), Kinsner, Witold (Electrical and Computer Engineering).
Subjects/Keywords: system-on-chip; multiprocessing
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APA (6th Edition):
Cook, D. P. (2011). A multiprocessng system-on-chip framework targeting stream-oriented applications. (Masters Thesis). University of Manitoba. Retrieved from http://hdl.handle.net/1993/4383
Chicago Manual of Style (16th Edition):
Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Masters Thesis, University of Manitoba. Accessed October 14, 2019.
http://hdl.handle.net/1993/4383.
MLA Handbook (7th Edition):
Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Web. 14 Oct 2019.
Vancouver:
Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Internet] [Masters thesis]. University of Manitoba; 2011. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/1993/4383.
Council of Science Editors:
Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Masters Thesis]. University of Manitoba; 2011. Available from: http://hdl.handle.net/1993/4383
Texas A&M University
5.
Malave-Bonet, Javier.
A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.
Degree: 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662
► Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused…
(more)
▼ Network-on-
Chip (NOC) based designs have garnered significant attention from both
researchers and industry over the past several years. The analysis of these designs has
focused on broad topics such as NOC component micro-architecture, fault-tolerant
communication, and
system memory architecture. Nonetheless, the design of lowlatency,
high-bandwidth, low-power and area-efficient NOC is extremely complex due
to the conflicting nature of these design objectives. Benchmarks are an indispensable
tool in the design process; providing thorough measurement and fair comparison
between designs in order to achieve optimal results (i.e performance, cost, quality of
service).
This research proposes a benchmarking platform called NoCBench for evaluating
the performance of Network-on-
chip. Although previous research has proposed standard
guidelines to develop benchmarks for Network-on-
Chip, this work moves forward and
proposes a
System-C based simulation platform for
system-level design exploration. It
will provide an initial set of synthetic benchmarks for on-
chip network interconnection
validation along with an initial set of standardized processing cores, NOC components,
and
system-wide services.
The benchmarks were constructed using synthetic applications described by Task
Graphs For Free (TGFF) task graphs extracted from the E3S benchmark suite. Two
benchmarks were used for characterization: Consumer and Networking. They are
characterized based on throughput and latency. Case studies show how they can be used
to evaluate metrics beyond throughput and latency (i.e. traffic distribution).
The contribution of this work is two-fold: 1) This study provides a methodology
for benchmark creation and characterization using NoCBench that evaluates important
metrics in NOC design (i.e. end-to-end packet delay, throughput). 2) The developed
full-
system simulation platform provides a complete environment for further benchmark
characterization on NOC based MpSoC as well as
system-level design space
exploration.
Advisors/Committee Members: Mahapatra, Rabi N. (advisor), Bettati, Riccardo (committee member), Gratz, Paul (committee member).
Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C
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APA ·
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APA (6th Edition):
Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Thesis, Texas A&M University. Accessed October 14, 2019.
http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 14 Oct 2019.
Vancouver:
Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
6.
Magnos Roberto Pizzoni.
PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.
Degree: 2010, Universidade do Vale do Itajaí
URL: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947
► Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos…
(more)
▼ Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos utilizando-se blocos de silício reutilizáveis (núcleos). Com as novas tecnologias de integração, será possível construir sistema com várias dezenas a centenas de núcleos em um mesmo chip. Tais sistemas terão alto poder de processamento, mas irá requerer estruturas de comunicação reutilizáveis com desempenho escalável, o que não é possível de ser obtido com as arquiteturas usadas atualmente, baseadas no barramento. É consenso na comunidade acadêmica e na indústria que a melhor solução para esse problema é baseada em estruturas de interconexão com canais chaveados por roteadores as chamadas Redes-em-Chip ou NoCs (Networks-on-Chip). Atualmente, diversos grupos de pesquisa trabalham investigando diferentes aspectos sobre NoCs e a grande maioria desses trabalhos utiliza ambientes de simulação para exploração arquitetural e avaliação de desempenho. No entanto, em modelos detalhados e com precisão de ciclo, o tempo de simulação é bastante alto, o que limita a quantidade de ciclos a serem simulados. Após a validação e a avaliação baseada em simulação, usualmente, realiza-se a síntese da NoC em FPGA (Field Programmable Gate Array) para realizar a sua validação física. Para tal, é necessário construir um sistema com núcleos conectados à rede e que produzam o tráfego que permitam validar a arquitetura implementada. Este projeto insere-se nesse contexto e busca desenvolver uma infra-estrutura de apoio à pesquisa sobre NoCs por meio da disponibilização de geradores de tráfego sintetizáveis para validação física e para a avaliação de desempenho de NoCs em dispositivos do tipo FPGA. A idéia é que essa infra-instrutora facilite a validação da rede e a realização de experimentos de análise de desempenho mais rapidamente e com maior precisão do que aqueles realizados em ambientes de simulação. Neste trabalho, foram desenvolvidos componentes de hardware e de software para a construção da plataforma proposta
With the evolution of the circuit manufacturer processes is becoming possible to integrate complete systems in a single chip, which are built of reusable silicon-based blocks (cores). With the advent of new integration technologies, it will be possible to build a system with several tens to hundreds of cores in the same chip. Such systems will have a higher processing power, but will require reusable communication structures with scalable performance, which is not possible to be obtained with the current bus-based architectures. The consensus in the academic community and industry is that the best solution for this problem is based on interconnection architectures with switching channels by routers the so called chip-networks or NoCs (Networks-on-Chip). Nowadays, several groups of research investigate different aspects of NoCs and the majority of the work being done uses simulation environments for architectural exploration and performance evaluation. However, in detailed models…
Advisors/Committee Members: Cesar Augusto Tischer, Alejandro Rafael Garcia Ramirez, Michelle Silva Wangham.
Subjects/Keywords: System-on-Chip; Network-on-Chip; Avaliação de desempenho; CIENCIA DA COMPUTACAO; Circuitos integrados; System-on-Chip; Network-on-Chip; Performance
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APA (6th Edition):
Pizzoni, M. R. (2010). PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Thesis, Universidade do Vale do Itajaí. Accessed October 14, 2019.
http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Web. 14 Oct 2019.
Vancouver:
Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2010. [cited 2019 Oct 14].
Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Thesis]. Universidade do Vale do Itajaí; 2010. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Anna University
7.
Saravanakumar U.
An investigation on macro and micro Architectures for
network on chip;.
Degree: An investigation on macro and micro Architectures for
network on chip, 2015, Anna University
URL: http://shodhganga.inflibnet.ac.in/handle/10603/40748
► As the technology scales down more processors or Processing newlineElements PEs are integrated in the same die and such technology is called as newlineMultiprocessor System…
(more)
▼ As the technology scales down more processors or
Processing newlineElements PEs are integrated in the same die and
such technology is called as newlineMultiprocessor System on Chip
MPSoC In the earlier MPSoCs bus newlinecommunication architecture
is used for communication of processors or PEs newlinewith each
other However this traditional bus communication architecture is
newlinenot suitable for more complex MPSoCs because of its limited
scalability and newlinereliability To provide better communication
architecture for complex newlineMPSoCs new communication
architecture Network on Chip NoC emerged newlineas alternate for
bus NoC uses the concepts and design methodologies adopted
newlinefrom computer network Silicon implementation of networks
requires newlinedifferent perspectives because network
architectures and protocols have to newlinedeal with the advantages
and limitations of the silicon fabric These newlinecharacteristics
require new methodologies for both on chip router designs as
newlinewell as routing algorithm designs The research works on NoCs
have multi newlinedimension to solve different issues and they are
arranged in two groups newlinenamed as Macro and Micro
architectures Macro architectural choices aim to newlinemerge
interconnection architecture with remaining systems and
Microarchitectural newlineaims at innovations within NoC components
newline
reference p177-193.
Advisors/Committee Members: Rangarajan R.
Subjects/Keywords: Microarchitectural aims; Multiprocessor System on Chip; Network on Chip
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APA (6th Edition):
U, S. (2015). An investigation on macro and micro Architectures for
network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40748
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
U, Saravanakumar. “An investigation on macro and micro Architectures for
network on chip;.” 2015. Thesis, Anna University. Accessed October 14, 2019.
http://shodhganga.inflibnet.ac.in/handle/10603/40748.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
U, Saravanakumar. “An investigation on macro and micro Architectures for
network on chip;.” 2015. Web. 14 Oct 2019.
Vancouver:
U S. An investigation on macro and micro Architectures for
network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2019 Oct 14].
Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
U S. An investigation on macro and micro Architectures for
network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
8.
Mandal, Suman Kalyan.
Dynamic Power Management of High Performance Network on Chip.
Degree: 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526
► With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication…
(more)
▼ With increased density of modern
System on
Chip(SoC) communication between nodes has become a major problem. Network on
Chip is a novel on
chip communication paradigm to solve this by using highly scalable and efficient packet switched network. The addition of intelligent networking on the
chip adds to the
chip?s power consumption thus making management of communication power an interesting and challenging research problem. While VLSI techniques have evolved over time to enable power reduction in the circuit level, the highly dynamic nature of modern large SoC demand more than that. This dissertation explores some innovative dynamic solutions to manage the ever increasing communication power in the post sub-micron era.
Today?s highly integrated SoCs require great level of cross layer optimizations to provide maximum efficiency. This dissertation aims at the dynamic power management problem from top. Starting with a
system level distribution and management down to microarchitecture enhancements were found necessary to deliver maximum power efficiency. A distributed power budget sharing technique is proposed. To efficiently satisfy the established power budget, a novel flow control and throttling technique is proposed. Finally power efficiency of underlying microarchitecture is explored and novel buffer and link management techniques are developed.
All of the proposed techniques yield improvement in power-performance efficiency of the NoC infrastructure.
Advisors/Committee Members: Mahapatra, Rabi N. (advisor), Walker, Duncan M. (committee member), Stoleru, Radu (committee member), Choi, Gwan S. (committee member).
Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC
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APA (6th Edition):
Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Thesis, Texas A&M University. Accessed October 14, 2019.
http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 14 Oct 2019.
Vancouver:
Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
9.
Viswanathan N.
Certain investigations on vertically Partially connected
3d network On chip topology and arbiter design With optimized
parameters;.
Degree: Certain investigations on vertically Partially
connected 3d network On chip topology and arbiter design With
optimized parameters, 2015, Anna University
URL: http://shodhganga.inflibnet.ac.in/handle/10603/33543
► Three dimensional integration is one of the emerging techniques newlineto find solution for the global interconnect delay challenges faced in the newlineadvanced VLSI ULSI technology…
(more)
▼ Three dimensional integration is one of the
emerging techniques newlineto find solution for the global
interconnect delay challenges faced in the newlineadvanced VLSI
ULSI technology Network on Chip NOC is a novel newlinedesign
paradigm in which the 3D integration can be realized for
newlineincreasingly complex System on Chip SOC In a three
dimensional newlineNetwork on Chip 3D NoC topology the adjacent
layers are newlineinterconnected with each other by using vertical
links In the fabrication newlineprocess the right candidate to
realize the vertical links is Through Silicon newlineVia TSV which
has several problems such as misalignment thermal newlineissues and
consuming considerable chip area etc Hence the number of
newlinevertical links used in a 3D NoC architecture must be
minimized Design of newlinea priority based programmable arbiter is
of paramount importance as its newlineperformance influences more
on the operating speed of the router scheduler newlineThe
objectives of this research work are to i exhibit that 3D
newlineNoC minimizes chip area wire length and energy consumption
compared to newlinethat of 2D NoC architecture ii evolve a
vertically partially and newlineHamiltonian connected 3D NoC
topology with minimum vertical links and newlineto develop a
deadlock free 3D routing algorithm iii evaluate the
newlineperformance of the 3D NoC topology using an analytical model
and newline design a programmable prefix router arbiter and
implement it in newlineFPGA for effective implementation of System
on Chip SoC newline newline
reference p183-194.
Advisors/Committee Members: Paramasivam K.
Subjects/Keywords: Network on Chip; System on Chip; Through Silicon Via
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
N, V. (2015). Certain investigations on vertically Partially connected
3d network On chip topology and arbiter design With optimized
parameters;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33543
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
N, Viswanathan. “Certain investigations on vertically Partially connected
3d network On chip topology and arbiter design With optimized
parameters;.” 2015. Thesis, Anna University. Accessed October 14, 2019.
http://shodhganga.inflibnet.ac.in/handle/10603/33543.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
N, Viswanathan. “Certain investigations on vertically Partially connected
3d network On chip topology and arbiter design With optimized
parameters;.” 2015. Web. 14 Oct 2019.
Vancouver:
N V. Certain investigations on vertically Partially connected
3d network On chip topology and arbiter design With optimized
parameters;. [Internet] [Thesis]. Anna University; 2015. [cited 2019 Oct 14].
Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
N V. Certain investigations on vertically Partially connected
3d network On chip topology and arbiter design With optimized
parameters;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Anna University
10.
Maheswari M.
Novel approaches in the design of Reliable custom
topology for Application specific network on chip;.
Degree: Novel approaches in the design of Reliable custom
topology for Application specific network on chip, 2015, Anna University
URL: http://shodhganga.inflibnet.ac.in/handle/10603/39199
► Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed…
(more)
▼ Continued Technology scaling helps the designer to
interconnect newlinelarge number of Intellectual Property IP blocks
like Digital Signal Processor newline DSP hardware accelerator high
speed memory and I O interfaces in a newlinesingle System on Chip
SoC In SoC shared bus based communication newlinearchitecture is
used to interconnect the IP blocks However the performance
newlineof the bus based communication architecture deteriorates
with increased newlinenumber of IP blocks newlineNetworks on Chip
NoC has emerged as a feasible solution to newlineovercome the
communication problem in the SoC NoC brings the concept of
newlinepacket switched network on to the chip In NoC I O blocks are
connected newlinethrough routers Standard topologies like Mesh Ring
Star and Binary tree are newlinemainly used to interconnect routers
and IP blocks Standard topologies are newlinesuitable for NoCs that
are reusable for many applications But for newlineApplication
Specific NoC ASNoC such standard topologies would lead to
newlinepoor performance such as increased area power consumption
and latency newlinethereby limiting the use of standard topologies
for ASNoC Hence for newlineASNoC tailor made custom topology has to
be designed to increase the newlinePerformance The custom topology
utilizes fewer resources like routers and newlineinterconnection
links that lead to less area and power consumption newline
newline
reference p158-170.
Advisors/Committee Members: Seetharaman G.
Subjects/Keywords: Digital Signal Processor; Intellectual Property; Networks on Chip; System on Chip
Record Details
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Record Details
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❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
M, M. (2015). Novel approaches in the design of Reliable custom
topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/39199
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
M, Maheswari. “Novel approaches in the design of Reliable custom
topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed October 14, 2019.
http://shodhganga.inflibnet.ac.in/handle/10603/39199.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
M, Maheswari. “Novel approaches in the design of Reliable custom
topology for Application specific network on chip;.” 2015. Web. 14 Oct 2019.
Vancouver:
M M. Novel approaches in the design of Reliable custom
topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2019 Oct 14].
Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
M M. Novel approaches in the design of Reliable custom
topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Anna University
11.
Maheswari M.
Novel approaches in the design of Reliable custom
topology for Application specific network on chip;.
Degree: Novel approaches in the design of Reliable custom
topology for Application specific network on chip, 2015, Anna University
URL: http://shodhganga.inflibnet.ac.in/handle/10603/41574
► Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed…
(more)
▼ Continued Technology scaling helps the designer to
interconnect newlinelarge number of Intellectual Property IP blocks
like Digital Signal Processor newline DSP hardware accelerator high
speed memory and I O interfaces in a newlinesingle System on Chip
SoC In SoC shared bus based communication newlinearchitecture is
used to interconnect the IP blocks However the performance
newlineof the bus based communication architecture deteriorates
with increased newlinenumber of IP blocks newlineNetworks on Chip
NoC has emerged as a feasible solution to newlineovercome the
communication problem in the SoC NoC brings the concept of
newlinepacket switched network on to the chip In NoC I O blocks are
connected newlinethrough routers Standard topologies like Mesh Ring
Star and Binary tree are newlinemainly used to interconnect routers
and IP blocks Standard topologies are newlinesuitable for NoCs that
are reusable for many applications But for newlineApplication
Specific NoC ASNoC such standard topologies would lead to
newlinepoor performance such as increased area power consumption
and latency newlinethereby limiting the use of standard topologies
for ASNoC Hence for newlineASNoC tailor made custom topology has to
be designed to increase the newlinePerformance The custom topology
utilizes fewer resources like routers and newlineinterconnection
links that lead to less area and power consumption newline
newline
reference p158-170.
Advisors/Committee Members: Seetharaman G.
Subjects/Keywords: Digital Signal Processor; Networks on Chip; System on Chip
Record Details
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Record Details
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❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
M, M. (2015). Novel approaches in the design of Reliable custom
topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/41574
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
M, Maheswari. “Novel approaches in the design of Reliable custom
topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed October 14, 2019.
http://shodhganga.inflibnet.ac.in/handle/10603/41574.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
M, Maheswari. “Novel approaches in the design of Reliable custom
topology for Application specific network on chip;.” 2015. Web. 14 Oct 2019.
Vancouver:
M M. Novel approaches in the design of Reliable custom
topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2019 Oct 14].
Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
M M. Novel approaches in the design of Reliable custom
topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Delft University of Technology
12.
Escudero Martínez, M.
An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.
Degree: 2010, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847
► Prototyping Systems on Chip (SoC) on FPGA technology improves the time that the de- signer needs to spend in the verification stage when developing new…
(more)
▼ Prototyping Systems on
Chip (SoC) on FPGA technology improves the time that the de- signer needs to spend in the verification stage when developing new systems or upgrading the existing ones. However, FPGA prototyping is very challenging due to the few resources available in this chips, and often the large designs do not fit into one single FPGA. Since Net- works on
Chip (NoC) are used as SoC interconnects, extending them for offering communication services between two different chips will solve the problem. This work explores how a bridge can extend the NoC while providing Quality of Service (QoS) to the applications. After a detailed investigation of the NoC protocol stack, we found that the best layer for placing the bridge was at the transport layer. Here, the bridge multiplexes several NoC connections on an off-
chip link, with data granularity of words. The bridge offers QoS by means of TDM scheduling and a credit-based mechanism preserves the end-to-end flow-control offered by the NoC. Software and hardware implementations of this bridge are tested and verified showing that they are fully func- tional. Moreover, two different NoC configuration procedures are developed, so the SoC resources can be monitored from an external host. Finally, this work concludes that it is possible to extend a NoC over more than one single
chip without loosing the QoS and hiding the complexity of the off-
chip link to the applications.
Advisors/Committee Members: Goossens, K..
Subjects/Keywords: network on chip; NoC; system on chip; SoC; bridge; FPGA; prototyping
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Escudero Martínez, M. (2010). An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847
Chicago Manual of Style (16th Edition):
Escudero Martínez, M. “An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.” 2010. Masters Thesis, Delft University of Technology. Accessed October 14, 2019.
http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847.
MLA Handbook (7th Edition):
Escudero Martínez, M. “An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.” 2010. Web. 14 Oct 2019.
Vancouver:
Escudero Martínez M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2019 Oct 14].
Available from: http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847.
Council of Science Editors:
Escudero Martínez M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847
University of New South Wales
13.
Hussain, Mubashir.
Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.
Degree: Computer Science & Engineering, 2018, University of New South Wales
URL: http://handle.unsw.edu.au/1959.4/60304
;
https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true
► Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system…
(more)
▼ Traditionally, the computing
system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a
system may involve different parties, especially for the design of
system-on-
chip (SoC) where the high complexity of the design has pushed designers towards using the third-party components that may have been modified with malicious additions without notice of the designer.Such a malicious modification (known as hardware Trojan) may be very small and can escape the scrutiny of the offline circuit-level testing and appear in the final product, which creates a new class of threats that have to be addressed at the hardware level and at the runtime.For SoCs, one of the most vulnerable components is the communication sub-
system, called network-on-
chip (NoC). NoC is able to access all components in the
system and can be an easy target for varied attacks.This thesis aims at the hardware Trojan inside the router of a NoC. When activated, the Trojan can modify passing packets for two different purposes: 1) hijacking packets to harvest information carried by the packet; 2) manipulating the packet to alter the packet data. Both attacks can be tackled by the authentication.But unlike the software level authentication designs in the traditional networking
system, the authentication in NoC has on-
chip overhead issues.The thesis investigates three designs: one for packet hijacking attack detection, one for packet integrity attack detection, and one for Trojan location detection. Each design has a different dominant overhead issue. We, therefore, have a different optimization objective in the design.For the packet hijacking attack detection, we target the overhead on the
chip cost and we present a customization design. For the packet data integrity authentication, the main concern is the bandwidth consumption caused by the large tag size and we introduce a progressive authentication scheme to reduce the bandwidth overhead. For the Trojan location detection, we propose a dynamic search algorithm to minimize the energy consumption.We have conducted a range of extensive experiments on each design, which demonstrate the effectiveness of our design approaches.
Advisors/Committee Members: Guo, Hui, UNSW.
Subjects/Keywords: System-on-Chip; Hardware Trojan; Network-on-Chip; Hardware Security
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APA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Hussain, M. (2018). Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true
Chicago Manual of Style (16th Edition):
Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Doctoral Dissertation, University of New South Wales. Accessed October 14, 2019.
http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.
MLA Handbook (7th Edition):
Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Web. 14 Oct 2019.
Vancouver:
Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2019 Oct 14].
Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.
Council of Science Editors:
Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true
University of New South Wales
14.
Avnit, Karin.
Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters.
Degree: Computer Science & Engineering, 2010, University of New South Wales
URL: http://handle.unsw.edu.au/1959.4/44701
;
https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8001/SOURCE01?view=true
► The field of chip design is characterized by contradictory pressures to reduce time-to-market and maintain a high level of reliability. As a result, module reuse…
(more)
▼ The field of
chip design is characterized by contradictory pressures to reduce time-to-market and maintain a high level of reliability. As a result, module reuse has become common practice in
chip design. To save time on both design and verification, Systems-on-Chips (SoCs) are composed using pre-designed and pre-verified modules. The integrated modules are often designed by different groups and for different purposes, and are later integrated into a single
chip. In the absence of a single interface standard for such modules, "plug-n-play" style integration is not likely, as the
subject modules are often designed to comply with different interface protocols. For such modules to communicate correctly there is a need for some glue logic, also called a protocol converter that mediates between them.Though much research has been dedicated to the protocol converter synthesis problem of SoC communication, converter synthesis is still performed manually, consuming development and verification time and risking human error. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the Hardware Description Language (HDL) implementation level or grossly simplify the structure of the protocols considered.This thesis develops and presents techniques for automatic synthesis of provably correct on-
chip protocol converters. Basing the solution on a formal approach, a novel state-machine based formalism is presented for modelling bus-based protocols and formalizing the notions of protocol compatibility and correct protocol conversion. Algorithms for automatic compatibility checking and provably-correct converter synthesis are derived from the formalism, including a systematic exploration of the design space of the protocol converter, the first in the field, which enables generation of various alternative deterministic converters. The work presented is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modelling of protocol characteristics and automatic translation of the constructed converter to HDL.
Advisors/Committee Members: Sowmya, Arcot, Computer Science & Engineering, Faculty of Engineering, UNSW, Parameswaran, Sri, Computer Science & Engineering, Faculty of Engineering, UNSW.
Subjects/Keywords: System-on-Chip; Formal Methods; Protocol converter
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APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Avnit, K. (2010). Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/44701 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8001/SOURCE01?view=true
Chicago Manual of Style (16th Edition):
Avnit, Karin. “Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters.” 2010. Doctoral Dissertation, University of New South Wales. Accessed October 14, 2019.
http://handle.unsw.edu.au/1959.4/44701 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8001/SOURCE01?view=true.
MLA Handbook (7th Edition):
Avnit, Karin. “Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters.” 2010. Web. 14 Oct 2019.
Vancouver:
Avnit K. Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters. [Internet] [Doctoral dissertation]. University of New South Wales; 2010. [cited 2019 Oct 14].
Available from: http://handle.unsw.edu.au/1959.4/44701 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8001/SOURCE01?view=true.
Council of Science Editors:
Avnit K. Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters. [Doctoral Dissertation]. University of New South Wales; 2010. Available from: http://handle.unsw.edu.au/1959.4/44701 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8001/SOURCE01?view=true
University of Utah
15.
You, Junbok.
Design and optimization of asynchronous network-on-chip.
Degree: PhD, Electrical & Computer Engineering, 2011, University of Utah
URL: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633
► The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on…
(more)
▼ The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on an asynchronous NoC link will also vary depending on the wire length between sender and receiver. This work explores the benefit to NoC performance, area, and energy when this property is used to optimize bandwidth on specific links based on its bandwidth required by a target SoC design. Three asynchronous routers were designed for implementing of asynchronous NoCs. Simple routing scheme and single-flit packet format lead to performance- and area-efficient router designs. Their performance was evaluated in consideration of link wire delay. Comprehensive analysis of pipeline latch insertion in asynchronous communication links is performed in regard to link bandwidth. Optimal placement of pipeline latch for maximizing benefit to increase of bandwidth is described. Specific methods are proposed for performance, area and energy optimization, respectively. Performance optimization is achieved by increasing bandwidth of high trafficked and high utilized links in an NoC, as inserting pipeline latches in those links. Through decrease of bandwidth of links with low traffic and low utilization by halving data-path width, reduction of wire area of an NoC is accomplished. Energy optimization is performed using wide spacing between wires in links with high energy consumption. An analytical model for asynchronous link bandwidth estimation is presented. It is utilized to deploy NoC optimization methods as identifying adequate links for each optimization method. Energy and latency characteristics of an asynchronous NoC are compared to a similarly-designed synchronous NoC. The results indicate that the asynchronous network has lower energy, and link-specific bandwidth optimization has improved NoC performance. Evaluation of proposed optimization methods by employing to an asynchronous NoC shows achievements of performance enhancement, wire area reduction and wire energy saving.
Subjects/Keywords: Asynchronous circuit design; Digital VLSI design; Interconnect system; Network-on-chip; System-on-chip
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APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
You, J. (2011). Design and optimization of asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633
Chicago Manual of Style (16th Edition):
You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed October 14, 2019.
http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.
MLA Handbook (7th Edition):
You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Web. 14 Oct 2019.
Vancouver:
You J. Design and optimization of asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2019 Oct 14].
Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.
Council of Science Editors:
You J. Design and optimization of asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633
16.
Papastefanakis, Ermis.
Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC).
Degree: Docteur es, Informatique, 2017, Université Paris-Est
URL: http://www.theses.fr/2017PESC1137
► L'évolution de Systems-on-Chip (SoCs) est rapide et le nombre des processeurs augmente conduisant à la transition des les plates-formes Multi-core vers les Manycore. Dans telles…
(more)
▼ L'évolution de Systems-on-
Chip (SoCs) est rapide et le nombre des processeurs augmente conduisant à la transition des les plates-formes Multi-core vers les Manycore. Dans telles plates-formes, l'architecture d'interconnexion a également décalé des bus traditionnels vers les Réseaux sur puce (NoC) afin de faire face à la mise en échelle. Les NoC permettent aux processeurs d'échanger des informations avec la mémoire et les périphériques lors de l'exécution d'une tâche et d'effectuer plusieurs communications en parallèle. Les plates-formes basées sur un NoC sont aussi présentes dans des systèmes embarqués, caractérisés par des exigences comme la prédictibilité, la sécurité et la criticité mixte. Afin de fournir telles fonctionnalités dans les plates-formes commerciales existantes, il faut prendre en considération le NoC qui est un élément clé ayant un impact important sur les performances d'un SoC. Une tâche échange des informations à travers du NoC et par conséquent, son temps d'exécution dépend du temps de transmission des flux qu'elle génère. En calculant le temps de transmission de pire cas (WCTT) des flux dans le NoC, une étape est faite vers le calcul du temps d'exécution de pire cas (WCET) d'une tâche. Ceci contribue à la prédictibilité globale du système. De plus, en prenant en compte les politiques d'arbitrage dans le NoC, il est possible de fournir des garanties de sécurité contre des tâches compromises qui pourraient essayer de saturer les ressources du système (attaque DoS). Dans les systèmes critiques de sécurité, une distinction des tâches par rapport à leur niveau de criticité, permet aux tâches de criticité mixte de coexister et d'exécuter en harmonie. De plus, ça permet aux tâches critiques de maintenir leurs temps d'exécution au prix de tâches de faible criticité qui seront ralenties ou arrêtées. Cette thèse vise à fournir des méthodes et des mécanismes dans le but de contribuer aux axes de prédictibilité, de sécurité et de criticité mixte dans les architectures Manycore basées sur Noc. En outre, l'incitation consiste à relever conjointement les défis dans ces trois axes en tenant compte de leur impact mutuel. Chaque axe a été étudié individuellement, mais très peu de recherche prend en compte leur interdépendance. Cette fusion des aspects est de plus en plus intrinsèque dans des domaines tels que Internet-of-Things, Cyber-Physical Systems (CPS), véhicules connectés et autonomes qui gagnent de l'élan. La raison en est leur haut degré de connectivité qui crée une grande surface d'exposition ainsi que leur présence croissante qui rend l'impact des attaques sévère et visible. Les contributions de cette thèse consistent en une méthode pour fournir une prédictibilité aux flux dans le NoC, un mécanisme pour la sécurité du NoC et une boîte à outils pour la génération de trafic utilisée pour l'analyse comparative. La première contribution est une adaptation de l'approche de la trajectoire traditionnellement utilisée dans les réseaux avioniques (AFDX) pour calculer le WCET. Dans cette thèse, nous identifions…
Advisors/Committee Members: George, Laurent (thesis director).
Subjects/Keywords: Network on Chip; System on Chip; Architectures embarquées; Qualité de service; Criticalité mixte; Network on Chip; System on Chip; Embedded architectures; Quality of service; Mixed criticality
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APA (6th Edition):
Papastefanakis, E. (2017). Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC). (Doctoral Dissertation). Université Paris-Est. Retrieved from http://www.theses.fr/2017PESC1137
Chicago Manual of Style (16th Edition):
Papastefanakis, Ermis. “Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC).” 2017. Doctoral Dissertation, Université Paris-Est. Accessed October 14, 2019.
http://www.theses.fr/2017PESC1137.
MLA Handbook (7th Edition):
Papastefanakis, Ermis. “Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC).” 2017. Web. 14 Oct 2019.
Vancouver:
Papastefanakis E. Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC). [Internet] [Doctoral dissertation]. Université Paris-Est; 2017. [cited 2019 Oct 14].
Available from: http://www.theses.fr/2017PESC1137.
Council of Science Editors:
Papastefanakis E. Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC). [Doctoral Dissertation]. Université Paris-Est; 2017. Available from: http://www.theses.fr/2017PESC1137
University of Utah
17.
Gebhardt, Daniel J.
Energy-efficient design of an asynchronous network-on-chip.
Degree: PhD, Computer Science, 2011, University of Utah
URL: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871
► Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are…
(more)
▼ Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are under a demand to offer more functionality and increased battery life. A difficult problem in SoC design is providing energy-efficient communication between its components while maintaining the required performance. This dissertation introduces a novel energy-efficient network-on-chip (NoC) communication architecture. A NoC is used within complex SoCs due it its superior performance, energy usage, modularity, and scalability over traditional bus and point-to-point methods of connecting SoC components. This is the first academic research that combines asynchronous NoC circuits, a focus on energy-efficient design, and a software framework to customize a NoC for a particular SoC. Its key contribution is demonstrating that a simple, asynchronous NoC concept is a good match for low-power devices, and is a fruitful area for additional investigation. The proposed NoC is energy-efficient in several ways: simple switch and arbitration logic, low port radix, latch-based router buffering, a topology with the minimum number of 3-port routers, and the asynchronous advantages of zero dynamic power consumption while idle and the lack of a clock tree. The tool framework developed for this work uses novel methods to optimize the topology and router oorplan based on simulated annealing and force-directed movement. It studies link pipelining techniques that yield improved throughput in an energy-efficient manner. A simulator is automatically generated for each customized NoC, and its traffic generators use a self-similar message distribution, as opposed to Poisson, to better match application behavior. Compared to a conventional synchronous NoC, this design is superior by achieving comparable message latency with half the energy.
Subjects/Keywords: Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
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APA (6th Edition):
Gebhardt, D. J. (2011). Energy-efficient design of an asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871
Chicago Manual of Style (16th Edition):
Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed October 14, 2019.
http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.
MLA Handbook (7th Edition):
Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Web. 14 Oct 2019.
Vancouver:
Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2019 Oct 14].
Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.
Council of Science Editors:
Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871
Universidade do Rio Grande do Sul
18.
Reinbrecht, Cezar Rodolfo Wedig.
Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.
Degree: 2012, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/67148
► Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas…
(more)
▼ Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas com múltiplos processadores num chip (MPSoCs, do inglês MultiProcessor System-on-Chip). Essa possibilidade de integração permite inserir dezenas de Elementos de Processamento (EPs) nos circuitos integrados atuais, e já se projeta centenas de EPs para os sistemas da próxima década (ITRS, 2011). Nesse cenário, um dos principais desafios se refere ao serviço de interconexão dos EPs, que deve apresentar um desempenho de comunicação necessário para as aplicações em execução sem comprometer as limitações de consumo de área e energia do circuito. Nos primeiros sistemas multiprocessados, com poucos nodos, arquiteturas baseadas em barramento foram suficientes para cumprir esses requisitos. Porém, o número de elementos nos sistemas recentes aumentou rapidamente, tornando as redes-em-chip a solução mais apropriada, por aliar escalabilidade e reuso na mesma estrutura. Contudo, diante da previsão de que essa tendência de aumento se manterá retorna a discussão se as redes-em-chip atuais continuarão adequadas para os futuros sistemas. De fato, o custo das redes-em-chip convencionais pode se tornar proibitivo para as escalas dos circuitos em um futuro próximo. Novas propostas têm sido apresentadas na literatura científica onde se podem destacar duas principais estratégias de projeto às redes de interconexão: reconfiguração arquitetural e organização hierárquica da topologia. A reconfiguração arquitetural permite obter uma grande eficiência, independente do tipo de aplicação em execução, pois uma das alternativas é projetar o circuito para que ele se auto adapte conforme os requisitos de desempenho para cada aplicação. Por outro lado, arquiteturas organizadas em topologias hierárquicas são desenvolvidas para uma estrutura computacional definida em tempo de projeto, sendo mais eficazes para uma classe de aplicações. O presente trabalho explora a sinergia da combinação das potencialidades das duas soluções e propõe uma nova estrutura que oferece melhor desempenho para uma classe maior de aplicações apropriada para os futuros sistemas. Como resultado foi implementada uma arquitetura adaptativa chamada MINoC (Multiple Interconnections Networks-on-Chip), uma arquitetura organizada em hierarquia, chamada HiCIT (Hierarchical Crossbar-based Interconnection Topology) e uma simbiose de ambas culminando na arquitetura hierárquica adaptativa HASIN (Hierarchical Adaptive Switching Interconnection Network). São apresentados resultados que mostram a eficiência desses conceitos validando a proposta hierárquica adaptativa.
With the advent of submicron processes, the number of transistors integrated on a single chip has reached levels that allowed the design of Multiprocessor Systems-on-Chip (MPSoCs). This capability allows the integration of several processing elements (PEs) in integrated circuits designed nowadays. In the next decade it is expected that hundreds of PEs…
Advisors/Committee Members: Susin, Altamiro Amadeu.
Subjects/Keywords: Microeletrônica; MPSoCs; Network-on-chip; Sistemas embarcados; MPSoC; Interconnections; Adaptive architecture; System-on-chip
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APA ·
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APA (6th Edition):
Reinbrecht, C. R. W. (2012). Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/67148
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Reinbrecht, Cezar Rodolfo Wedig. “Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed October 14, 2019.
http://hdl.handle.net/10183/67148.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Reinbrecht, Cezar Rodolfo Wedig. “Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.” 2012. Web. 14 Oct 2019.
Vancouver:
Reinbrecht CRW. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/10183/67148.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Reinbrecht CRW. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/67148
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Delft University of Technology
19.
De Windt, J.
Protocol conversions for the Aethereal Networks-on-Chip:.
Degree: 2009, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:2287ef2c-248f-409b-959a-eb1f6236e4a4
► Bus based interconnects are commonly used to connect Intellectual Properties (IPs) on System-on-Chip (SoC). However, as the number of high performance IPs with large communication…
(more)
▼ Bus based interconnects are commonly used to connect Intellectual Properties (IPs) on
System-on-
Chip (SoC). However, as the number of high performance IPs with large communication requirements in a Multi Processor SoC (MPSoC) increases, the bus interconnects become a communication bottleneck. To overcome this limitation, the bus based interconnects are replaced by Networks-on-
Chip (NoC) as the interconnect for IPs in an MPSoC. The ability to support multiple protocols, both legacy and newer, is essential for leveraging the advantages of the NoC. This thesis describes the protocol conversions, or shells, we design for the aethereal NoC, to provide a unified message format for the PLB, OPB and FSL protocols. Furthermore, to tolerate the latencies when accessing memory and to increase the throughput when possible, we add support for posted write and prefetch read in the shells and we design a mechanism to coalesce multiple single transactions into burst transaction when possible.
To validate our design, we prototype it on a Virtex-II PRO FPGA. We use both synthetic applications as well as real life applications to benchmark and analyze the effect of factors, like computation-to-communication ratio, various link bandwidths and compiler loop unrolling on the performance of the
system. The results show that reducing the link bandwidth up to a certain point does not affect the performance anymore, as the latency associated with NoC internals becomes dominant. Also the burst transaction can sustain the performance of the
system up to a certain point, when the link bandwidth is reduced. The best result is obtained using a shell with posted write and prefetch read.
Advisors/Committee Members: Goossens, K..
Subjects/Keywords: Networks-on-Chip; FPGA; protocol conversion; System-on-Chip; IBM CoreConnect; Xilinx
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APA (6th Edition):
De Windt, J. (2009). Protocol conversions for the Aethereal Networks-on-Chip:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:2287ef2c-248f-409b-959a-eb1f6236e4a4
Chicago Manual of Style (16th Edition):
De Windt, J. “Protocol conversions for the Aethereal Networks-on-Chip:.” 2009. Masters Thesis, Delft University of Technology. Accessed October 14, 2019.
http://resolver.tudelft.nl/uuid:2287ef2c-248f-409b-959a-eb1f6236e4a4.
MLA Handbook (7th Edition):
De Windt, J. “Protocol conversions for the Aethereal Networks-on-Chip:.” 2009. Web. 14 Oct 2019.
Vancouver:
De Windt J. Protocol conversions for the Aethereal Networks-on-Chip:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2019 Oct 14].
Available from: http://resolver.tudelft.nl/uuid:2287ef2c-248f-409b-959a-eb1f6236e4a4.
Council of Science Editors:
De Windt J. Protocol conversions for the Aethereal Networks-on-Chip:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:2287ef2c-248f-409b-959a-eb1f6236e4a4
Iowa State University
20.
Keung, Ka-ming.
A study of on-chip FPGA system with 2D mesh network.
Degree: 2010, Iowa State University
URL: https://lib.dr.iastate.edu/etd/11251
► The advance in fabrication technology hugely increases the number of available transistors on a single chip. It allows the industry to build the entire system…
(more)
▼ The advance in fabrication technology hugely increases the number of available transistors
on a single chip. It allows the industry to build the entire system on a single chip which was
only realizable on a board in the past. On-chip System not only reduces the computer physical
size, but also increases the computation performance because modules/cores/intellectual properties (IPs) are packed closely together. When simply increasing the clock frequency to increase
the computer performance becomes harder because of the wire delay, putting more computation units on a single chip becomes a good alternative for improving computer performance.
Building more cores on a chip in the future is expected.
With many IPs on a chip, traditional bus is no longer able to provide enough bandwidth to
support the communication between IPs. Providing a high performance on-chip network infrastructure for the IP communication becomes a key to high performance on-chip computation.
This thesis focuses on an on-chip network supporting on-chip system.
This thesis is composed of two main parts. In the first part, a high performance deadlock
free dual-coded on-chip router using adaptive multicast routing is built. Compared with the
traditional deterministic XY unicast router, this router can reduce both packet latency and
energy consumption.
In the second part, a co-processor placement algorithm for an on-chip system built from
FPGAs with an on-chip network is proposed. The algorithm aims to place the communicating
modules as close as possible. In addition, an algorithm for sharing a FPGA by multiple co-processors and an algorithm for supporting polymorphic co-processor are proposed to increase
on-chip FPGA system throughput.
Subjects/Keywords: Adaptive Routing; FPGA; Multicast; On-chip network; On-chip system; Placement; Electrical and Computer Engineering
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Export
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APA (6th Edition):
Keung, K. (2010). A study of on-chip FPGA system with 2D mesh network. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/11251
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Keung, Ka-ming. “A study of on-chip FPGA system with 2D mesh network.” 2010. Thesis, Iowa State University. Accessed October 14, 2019.
https://lib.dr.iastate.edu/etd/11251.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Keung, Ka-ming. “A study of on-chip FPGA system with 2D mesh network.” 2010. Web. 14 Oct 2019.
Vancouver:
Keung K. A study of on-chip FPGA system with 2D mesh network. [Internet] [Thesis]. Iowa State University; 2010. [cited 2019 Oct 14].
Available from: https://lib.dr.iastate.edu/etd/11251.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Keung K. A study of on-chip FPGA system with 2D mesh network. [Thesis]. Iowa State University; 2010. Available from: https://lib.dr.iastate.edu/etd/11251
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Washington State University
21.
[No author].
COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING
.
Degree: 2017, Washington State University
URL: http://hdl.handle.net/2376/13038
► In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and…
(more)
▼ In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and highly scalable platform suitable for both data- and compute-intensive applications. The performance of a manycore architecture is highly dependent on the capabilities of its communication backbone, namely the Network on-
chip (NoC). An efficient NoC designed for a manycore platform must align the connectivity of the NoC with the application’s on-
chip traffic patterns.
Analysis on the inter-core traffic patterns exhibited by various Big Data applications reveal irregular memory access behaviors that give rise to long-range on-
chip communication requirements. In addition to the irregular memory access patterns, many of the modern applications also necessitate dense collective communication capabilities among the on-
chip nodes. Under collective communication, either a single source node transmits data to all the other nodes in the
system (one-to-all) or all the nodes in the
system communicate with a single destination node (all-to-one).
Wireless NoC is an emerging paradigm to design high bandwidth and energy efficient communication backbone for manycore chips. Previous works show that the wireless links can establish low-latency data-transfers even between physically distant on-
chip nodes. In addition, with its inherent broadcast capability, the on-
chip wireless links are highly suited to perform efficient collective-communication. Thus, employing on-
chip wireless links one can design efficient communication infrastructures for manycore platforms running high performance Big Data processing.
This dissertation focuses on designing a hybrid (wireline + wireless) network-on-
chip architecture (called WiNoC) capable of low-latency collective communication. First, we leverage the knowledge gained from studying small-world graphs to design low hop count WiNoC topologies. Next, we augment the WiNoC with suitable data-transfer mechanisms to ensure a congestion-free high performance NoC.
On overall, this work indicates on-
chip communication challenges arise from manycore Big Data processing and proposes a wireless-enabled high performance and energy efficient NoC capable of addressing these challenges.
Advisors/Committee Members: Pande, Partha Pratim (advisor).
Subjects/Keywords: Computer engineering;
Big Data;
Graph Analytics;
MapReduce;
Network-on-Chip;
System-on-Chip;
Wireless NoC
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APA ·
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Manager
APA (6th Edition):
author], [. (2017). COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING
. (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/13038
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING
.” 2017. Thesis, Washington State University. Accessed October 14, 2019.
http://hdl.handle.net/2376/13038.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING
.” 2017. Web. 14 Oct 2019.
Vancouver:
author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING
. [Internet] [Thesis]. Washington State University; 2017. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/2376/13038.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING
. [Thesis]. Washington State University; 2017. Available from: http://hdl.handle.net/2376/13038
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Oklahoma State University
22.
Williams, Seth Adam.
Benchmarking ARM-based Application Integrated Systems.
Degree: School of Electrical & Computer Engineering, 2011, Oklahoma State University
URL: http://hdl.handle.net/11244/10295
► ARM Holding Ltd. is in a very good position; by owning a very prolific instruction set architecture (named ARM) and licensing it to other companies…
(more)
▼ ARM Holding Ltd. is in a very good position; by owning a very prolific instruction set architecture (named ARM) and licensing it to other companies that compete with one another, they are always winners. Though ARM is used throughout the domain covered by embedded systems; one particular market that they have cornered is in the application cores used in mobile handset devices. Licensees oftentimes make their own alterations to the core, add other system components, and print or package them together into devices that this thesis will refer to as integrated systems. Though finding very specific architectural details between the cores themselves is as simple as going onto the website, true performance comparisons stemming from credible benchmarks of the integrated systems that contain them are not as forthcoming. This thesis aims to explore the realities of benchmarking ARM-based application integrated systems. By looking at what kind of benchmarks are available and what kind of tests have been done in the past it should become apparent what, if anything, needs to be developed to provide thorough comparisons between these devices. During the course of this investigation, topics such as the ambiguity in integrated system methods, the future of application integrated systems, and the process in actually selecting and running a benchmark on a sample system shall be explored.
Subjects/Keywords: arm; embedded benchmarks; package-on-package; system-on-chip
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APA ·
Chicago ·
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Export
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APA (6th Edition):
Williams, S. A. (2011). Benchmarking ARM-based Application Integrated Systems. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/10295
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Thesis, Oklahoma State University. Accessed October 14, 2019.
http://hdl.handle.net/11244/10295.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Web. 14 Oct 2019.
Vancouver:
Williams SA. Benchmarking ARM-based Application Integrated Systems. [Internet] [Thesis]. Oklahoma State University; 2011. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/11244/10295.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Williams SA. Benchmarking ARM-based Application Integrated Systems. [Thesis]. Oklahoma State University; 2011. Available from: http://hdl.handle.net/11244/10295
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Indian Institute of Science
23.
Vikas, G.
Power Optimal Network-On-Chip Interconnect Design.
Degree: 2010, Indian Institute of Science
URL: http://hdl.handle.net/2005/1408
► A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power…
(more)
▼ A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on
Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on
Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values.
To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific
System on
Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for
Chip Multi Processor (CMP) case that can solve the ASSoC scenario also.
Advisors/Committee Members: Varghese, Kuruvilla, Kuri, Joy.
Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering
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❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1408
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed October 14, 2019.
http://hdl.handle.net/2005/1408.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 14 Oct 2019.
Vancouver:
Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/2005/1408.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://hdl.handle.net/2005/1408
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Indian Institute of Science
24.
Vikas, G.
Power Optimal Network-On-Chip Interconnect Design.
Degree: 2010, Indian Institute of Science
URL: http://etd.iisc.ernet.in/handle/2005/1408
;
http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf
► A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power…
(more)
▼ A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on
Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on
Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values.
To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific
System on
Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for
Chip Multi Processor (CMP) case that can solve the ASSoC scenario also.
Advisors/Committee Members: Varghese, Kuruvilla, Kuri, Joy.
Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering
Record Details
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Record Details
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« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed October 14, 2019.
http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 14 Oct 2019.
Vancouver:
Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2019 Oct 14].
Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
25.
Psarras, Anastasios.
High-performance networks-on-chip.
Degree: 2017, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ)
URL: http://hdl.handle.net/10442/hedi/41266
► Over the last two decades, we have witnessed a fundamental paradigm shift in digital system design: the transition to the multi-core realm. Naturally, the multi-core…
(more)
▼ Over the last two decades, we have witnessed a fundamental paradigm shift in digital system design: the transition to the multi-core realm. Naturally, the multi-core domain has elevated the criticality of the on-chip interconnection fabric, which is now tasked with satisfying amplified communication demands. Owing to their scalability attributes, Networks-on-Chip (NoC) have established their position as the de facto communication medium in multi-core systems. To sustain system scalability into the many-core domain (with potentially hundreds of cores), it is imperative that the NoC's hardware cost is minimized, while not sacrificing network performance.To this end, we propose three alternative architectures that can significantly improve the performance of NoCs, or lead to an overall lower power consumption.The first one is a pipelined router architecture, called ShortPath, that parallelizes - for the first time - the allocation steps involved in the operation of a VC-based router without resorting to speculation. Most importantly, ShortPath is augmented with an always-productive pipeline bypassing mechanism, which skips all stages without contention, and "fast-forwards" the flits to the first encountered point of contention.The other two approaches exploit fast link traversal, after appropriate wire engineering, to rapidly transfer flits between adjacent routers (connected with links of reasonable, short-to-medium length of up to a few millimeters) in half a clock cycle. Under this clocking principle, two design alternatives are explored, which allow for half-cycle and Double-Data-Rate (DDR) link traversal. The proposed approaches can markedly increase network performance, or decrease the area/power cost of the NoC. Although not obvious at first glance, half-cycle link traversal opens up new possibilities for reducing wire capacitance. By harnessing these opportunities, the half-cycle-delay requirement becomes easier to achieve and potentially extends half-cycle traversal capabilities to longer links. To tackle longer links, novel DDR dual-stream elastic buffers are proposed for pipelining the links while still following DDR flow control.As multi/many-core architectures evolve, the demands on the NoC are amplified. In addition to high performance and physical scalability, the NoC is increasingly required to also provide specialized functionality, such as network virtualization, flow isolation, and quality-of-service guarantees. Although traditional architectures supporting Virtual Channels (VCs) offer the resources for flow partitioning and isolation, an adversarial workload can still interfere and degrade the performance of other workloads that are active in a different set of VCs. Motivated by this aspect, we present PhaseNoC, a truly non interfering VC-based architecture that adopts time-division multiplexing at the VC level. Distinct flows, or application domains, mapped to disjoint sets of VCs are isolated, both inside the router's pipeline, and at the network level. Any latency overhead is minimized by…
Subjects/Keywords: Δίκτυα σε Ολοκληρωμένα Κυκλώματα; Ολοκληρωμένα κυκλώματα; Πολυπύρηνοι επεξεργαστές; Συστήματα σε Ολοκληρωμένα Κυκλώματα; Networks-on-Chip; VLSI; Multi-core architectures; Chip Multi-Processors; System-on-chip; On-chip Interconnection Networks
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Psarras, A. (2017). High-performance networks-on-chip. (Thesis). Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Retrieved from http://hdl.handle.net/10442/hedi/41266
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Psarras, Anastasios. “High-performance networks-on-chip.” 2017. Thesis, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Accessed October 14, 2019.
http://hdl.handle.net/10442/hedi/41266.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Psarras, Anastasios. “High-performance networks-on-chip.” 2017. Web. 14 Oct 2019.
Vancouver:
Psarras A. High-performance networks-on-chip. [Internet] [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2017. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/10442/hedi/41266.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Psarras A. High-performance networks-on-chip. [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2017. Available from: http://hdl.handle.net/10442/hedi/41266
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
26.
Sílvio Roberto Fernandes de Araújo.
Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.
Degree: 2008, Universidade Federal do Rio Grande do Norte
URL: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541
► O aumento na capacidade de integração de transistores permitiu o desenvolvimento de sistemas completos, com inúmeros componentes, dentro de um único chip, são os chamados…
(more)
▼ O aumento na capacidade de integração de transistores permitiu o desenvolvimento de sistemas completos, com inúmeros componentes, dentro de um único chip, são os chamados SoCs (System-on-Chip). No entanto, o subsistema de interconexão utilizado pode limitar a escalabilidade dos SoCs, como os barramentos, ou ser uma solução ad hoc, como a hierarquia de barramentos. Desse modo, a solução ideal para interconexão no SoCs são as redes em chip ou NoCs (Network-on-Chip). As NoCs permitem múltiplas conexão ponto-a-ponto entre os componente e podem ser reusadas em projetos diversos. Entretanto, o uso de NoCs pode representar o aumento na complexidade do projeto do sistema, da área em chip e/ou potência dissipada. Dessa forma, é necessário ampliar o horizonte de utilização dos sistemas ou quebrar o paradigma do seu desenvolvimento. Assim, é proposto um sistema baseado em uma NoC, onde as aplicações são descritas em forma de pacotes e executadas de roteador em roteador durante o percurso entre origem e destino dos pacotes, sem a necessidade do uso de processadores convencionais. Para permitir a execução de aplicações, independente do número de instruções e das dimensões da rede, foi desenvolvido o algoritmo spiral complement, que permite re-rotear pacotes até que todas as instruções contidas nele sejam executadas. Portanto, o objetivo desse trabalho foi estudar a viabilidade do desenvolvimento de tal sistema, denominado sistema IPNoSys. Nesse estudo, foi desenvolvida em SystemC, com precisão de ciclo, uma ferramenta para simulação do sistema, a qual permite executar aplicações implementadas na linguagem de descrição de pacotes, também desenvolvida para esse fim. Através da ferramenta podem ser obtidos diversos resultados que permitem avaliar o funcionamento e desempenho do sistema. A metodologia empregada para descrição das aplicações corresponde, a priori, em obter o grafo de fluxo de dados da aplicação em alto nível, e desse grafo descrevê-la em um ou mais pacotes. Utilizando essa metodologia, foram realizados três estudos de casos: contador, DCT-2D e adição de ponto flutuante. O contador foi usado para avaliar a capacidade do sistema em tratar situações de deadlock e executar aplicações em paralelo. A DCT-2D foi utilizada para realizar comparações com a plataforma STORM. E, finalmente, a adição de ponto flutuante teve como objetivo ser usada como rotina de tratamento de uma instrução não implementada em hardware. Os resultados de simulação apontam favoravelmente com relação à viabilidade do desenvolvimento do sistema IPNoSys. Mostrando que é possível executar aplicações em forma de pacotes, inclusive paralelamente, sem interrupções provocadas por eventuais deadlocks, e ainda indicam maior eficiência do sistema IPNoSys a respeito do tempo de execução comparada a plataforma STORM
The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs,…
Advisors/Committee Members: Eduardo Bráulio Wanderley Netto, Fernando Rangel de Sousa, Ivan Saraiva Silva, Sérgio Bampi.
Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; SISTEMAS DE COMPUTACAO; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system
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Record Details
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Cite
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❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. (Thesis). Universidade Federal do Rio Grande do Norte. Retrieved from http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.” 2008. Thesis, Universidade Federal do Rio Grande do Norte. Accessed October 14, 2019.
http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.” 2008. Web. 14 Oct 2019.
Vancouver:
Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. [Internet] [Thesis]. Universidade Federal do Rio Grande do Norte; 2008. [cited 2019 Oct 14].
Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. [Thesis]. Universidade Federal do Rio Grande do Norte; 2008. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Norte
27.
Araújo, Sílvio Roberto Fernandes de.
Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
.
Degree: 2008, Universidade do Rio Grande do Norte
URL: http://repositorio.ufrn.br/handle/123456789/17969
► The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the…
(more)
▼ The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single
chip, they are called SoC (
System-on-
Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-
Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in
chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a
system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed.
Therefore, the objective is to study the viability of development that
system, denominated IPNoSys
system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the
system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the
system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys
system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform
Advisors/Committee Members: Silva, Ivan Saraiva (advisor), CPF:43728090425 (advisor), http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2 (advisor).
Subjects/Keywords: Sistema em chip (SoC);
Redes em chip (NoC);
Algoritmo spiral complement;
Sistema IPNoSys;
System-on-chip (SoC);
Network-on-chip (NoC);
Spiral complement algorithm;
IPNoSys system
Record Details
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Cite
Share »
Record Details
Similar Records
Cite
« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
. (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17969
Chicago Manual of Style (16th Edition):
Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
.” 2008. Masters Thesis, Universidade do Rio Grande do Norte. Accessed October 14, 2019.
http://repositorio.ufrn.br/handle/123456789/17969.
MLA Handbook (7th Edition):
Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
.” 2008. Web. 14 Oct 2019.
Vancouver:
Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
. [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2008. [cited 2019 Oct 14].
Available from: http://repositorio.ufrn.br/handle/123456789/17969.
Council of Science Editors:
Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
. [Masters Thesis]. Universidade do Rio Grande do Norte; 2008. Available from: http://repositorio.ufrn.br/handle/123456789/17969
Universidade do Rio Grande do Norte
28.
Araújo, Sílvio Roberto Fernandes de.
Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
.
Degree: 2008, Universidade do Rio Grande do Norte
URL: http://repositorio.ufrn.br/handle/123456789/17969
► The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the…
(more)
▼ The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single
chip, they are called SoC (
System-on-
Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-
Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in
chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a
system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed.
Therefore, the objective is to study the viability of development that
system, denominated IPNoSys
system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the
system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the
system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys
system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform
Advisors/Committee Members: Silva, Ivan Saraiva (advisor), CPF:43728090425 (advisor), http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2 (advisor).
Subjects/Keywords: Sistema em chip (SoC);
Redes em chip (NoC);
Algoritmo spiral complement;
Sistema IPNoSys;
System-on-chip (SoC);
Network-on-chip (NoC);
Spiral complement algorithm;
IPNoSys system
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APA (6th Edition):
Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
. (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17969
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
.” 2008. Thesis, Universidade do Rio Grande do Norte. Accessed October 14, 2019.
http://repositorio.ufrn.br/handle/123456789/17969.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
.” 2008. Web. 14 Oct 2019.
Vancouver:
Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
. [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2008. [cited 2019 Oct 14].
Available from: http://repositorio.ufrn.br/handle/123456789/17969.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
. [Thesis]. Universidade do Rio Grande do Norte; 2008. Available from: http://repositorio.ufrn.br/handle/123456789/17969
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
29.
Briao, Eduardo Wenzel.
Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.
Degree: 2008, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/13157
► A complexidade no projeto de sistemas eletrônicos tem aumentado devido à evolução tecnológica e permite a concepção de sistemas inteiros em um único chip (SoCs…
(more)
▼ A complexidade no projeto de sistemas eletrônicos tem aumentado devido à evolução tecnológica e permite a concepção de sistemas inteiros em um único chip (SoCs – do inglês, Systems-on-Chip). Com o objetivo de reduzir a alta complexidade de projeto, custos de projeto e o tempo de lançamento do produto no mercado, os sistemas são desenvolvidos em módulos funcionais, pré-verificados e pré-projetados, denominados de núcleos de propriedade intelectual (IP – do inglês, Intellectual Property). Esses núcleos IP podem ser reutilizados de outros projetos ou adquiridos de terceiros. Entretanto, é necessário prover uma estrutura de comunicação para interligar esses núcleos e as estruturas atuais (barramentos) são inadequadas para atender as necessidades dos futuros SoCs (compartilhamento de banda, falta de escalabilidade). As redes-em-chip (NoCs{ XE "NoCs" } – do inglês, Networks-on-Chip) vêm sendo apresentadas como uma solução para atender essas restrições. No desenvolvimento de sistemas embarcados baseados em redes-em-chip, deve-se personalizar a rede para atendimento de restrições. Essa exploração de espaço de projeto (EEP), segundo uma infinidade de trabalhos, é realizada em tempo de projeto, supondo-se que é conhecido o perfil das aplicações que devem ser executadas pelo sistema. No entanto, cada vez mais sistemas embarcados aproximam-se de dispositivos genéricos de processamento (como palmtops), onde as tarefas a serem executadas não são inteiramente conhecidas a priori. Com a mudança dinâmica da carga de trabalho de um sistema embarcado, a busca pelo atendimento de requisitos pode então ser enfrentada por mecanismos adaptativos, que implementam dinamicamente a EEP. No âmbito deste trabalho, a EEP em tempo de execução provê mecanismos adaptativos que deverão realizar suas funções para atendimento de restrições de projeto. Consequentemente, EEP em tempo de execução pode permitir resultados ainda melhores, no que diz respeito a sistemas embarcados com restrições de projetos rígidas. É possível maximizar o tempo de duração da energia da bateria que alimenta um sistema embarcado ou, até mesmo, diminuir a taxa de perda de deadlines em um sistema de tempo real soft, realocando em tempo de execução tarefas de modo a gerar menor taxa de comunicação entre os processadores, desde que o sistema seja executado em um tempo suficiente para amortizar os custos de migração. Neste trabalho, foi utilizada a combinação de heurísticas de alocação da área dos Sistemas Computacionais Distribuídos como, por exemplo, algoritmos bin-packing e linear clustering. Resultados mostraram que a realocação de tarefas, utilizando uma combinação Worst-Fit e Linear Clustering, reduziu o consumo de energia e a taxa de perda de deadlines em 17% e 37%, respectivamente, utilizando o modelo de migração por cópia.
The complexity of electronic systems design has been increasing due to the technological evolution, which now allows the inclusion of a complete system on a single chip (SoC – System-on-Chip). In order to cope with the corresponding design complexity…
Advisors/Committee Members: Wagner, Flavio Rech.
Subjects/Keywords: Embedded systems; Microeletrônica; Design space exploration; Network-on-chip; Systemon- chip; Distributed system
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Record Details
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❌
APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Briao, E. W. (2008). Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/13157
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Briao, Eduardo Wenzel. “Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed October 14, 2019.
http://hdl.handle.net/10183/13157.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Briao, Eduardo Wenzel. “Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.” 2008. Web. 14 Oct 2019.
Vancouver:
Briao EW. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/10183/13157.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Briao EW. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/13157
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
King Abdullah University of Science and Technology
30.
Nafe, Mahmoud.
Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz.
Degree: 2015, King Abdullah University of Science and Technology
URL: http://hdl.handle.net/10754/565638
► Nowadays, there is a growing demand for high frequency-bandwidth mm-wave (30-300 GHz) electronic wireless transceiver systems to support applications such as high data-rate wireless communication…
(more)
▼ Nowadays, there is a growing demand for high frequency-bandwidth mm-wave (30-300 GHz) electronic wireless transceiver systems to support applications such as high data-rate wireless communication and high resolution imaging. Such mm-wave systems are becoming more feasible due to the extreme transistor downscaling in silicon-based integrated circuits, which enabled densely-integrated high-speed elec- tronics operating up to more than 100 GHz with low fabrication cost. To further enhance system integrability, it is required to implement all wireless system compo- nents on the chip. Presently, the last major barrier to true System-on-Chip (SoC) realization is the antenna implementation on the silicon chip.
Although at mm-wave frequencies the antenna size becomes small enough to fit on chip, the antenna performance is greatly deteriorated due the high conductivity and high relative permittivity of the silicon substrate. The negative e↵ects of the silicon substrate could be avoided by using a metallic reflecting surface on top of silicon, which e↵ectively isolates the antenna from the silicon. However, this approach has the shortcoming of having to implement the antenna on the usually very thin silicon oxide layer of a typical CMOS fabrication process (10’s of μm). This forces the antenna to be in a very close proximity (less than one hundredth of a wavelength) to the reflecting surface. In this regime, the use of conventional metallic reflecting
surface for silicon shielding has severe e↵ects on the antenna performance as it tends to reduce the antenna radiation resistance resulting in most of the energy being absorbed rather than radiated.
In this work, the use of specially patterned reflecting surfaces for improving on- chip antenna performance is investigated. By using a periodic metallic surface on top of a grounded substrate, the structure can mimic the behavior of a perfect mag- netic conductor, hence called Artificial Magnetic Conductor (AMC) surface. Unlike conventional ground plane reflecting surfaces, AMC surfaces generally enhance the radiation and impedance characteristics of close-by antennas. Based on this property, a ring-based AMC reflecting surface has been designed in the oxide layer for on-chip antennas operating at 94 GHz. Furthermore, a folded dipole antenna with its associ- ated planar feeding structures has been optimized and integrated with the developed ring-based AMC surface. The proposed design is then fabricated at KAUST clean- room facilities. Prototype characterization showed very promising results with good correlation to simulations, with the antenna exhibiting an impedance bandwidth of 10% (90-100 GHz) and peak gain of -1.4 dBi, which is the highest gain reported for on-chip antennas at this frequency band without the use of any external o↵-chip components or post-fabrication steps.
Subjects/Keywords: one-chip antenna; System-on-chip; artificla magnetic conductor; hight impedence surface; mm-wave
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Record Details
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❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Nafe, M. (2015). Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz. (Thesis). King Abdullah University of Science and Technology. Retrieved from http://hdl.handle.net/10754/565638
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Nafe, Mahmoud. “Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz.” 2015. Thesis, King Abdullah University of Science and Technology. Accessed October 14, 2019.
http://hdl.handle.net/10754/565638.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Nafe, Mahmoud. “Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz.” 2015. Web. 14 Oct 2019.
Vancouver:
Nafe M. Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz. [Internet] [Thesis]. King Abdullah University of Science and Technology; 2015. [cited 2019 Oct 14].
Available from: http://hdl.handle.net/10754/565638.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Nafe M. Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz. [Thesis]. King Abdullah University of Science and Technology; 2015. Available from: http://hdl.handle.net/10754/565638
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
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