subject:(System on chip)

University of Manitoba

1. Cook, Darcy Philip. A multiprocessng system-on-chip framework targeting stream-oriented applications.

Degree: Electrical and Computer Engineering, 2011, University of Manitoba

URL: http://hdl.handle.net/1993/4383

► Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be… (more)

Subjects/Keywords: system-on-chip; multiprocessing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Cook, D. P. (2011). A multiprocessng system-on-chip framework targeting stream-oriented applications. (Masters Thesis). University of Manitoba. Retrieved from http://hdl.handle.net/1993/4383

Chicago Manual of Style (16^th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Masters Thesis, University of Manitoba. Accessed March 07, 2021. http://hdl.handle.net/1993/4383.

MLA Handbook (7^th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Web. 07 Mar 2021.

Vancouver:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Internet] [Masters thesis]. University of Manitoba; 2011. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1993/4383.

Council of Science Editors:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Masters Thesis]. University of Manitoba; 2011. Available from: http://hdl.handle.net/1993/4383

Texas A&M University

2. Malave-Bonet, Javier. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.

Degree: MS, Computer Engineering, 2012, Texas A&M University

URL: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

► Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused… (more)

▼ Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused on broad topics such as NOC component micro-architecture, fault-tolerant communication, and system memory architecture. Nonetheless, the design of lowlatency, high-bandwidth, low-power and area-efficient NOC is extremely complex due to the conflicting nature of these design objectives. Benchmarks are an indispensable tool in the design process; providing thorough measurement and fair comparison between designs in order to achieve optimal results (i.e performance, cost, quality of service). This research proposes a benchmarking platform called NoCBench for evaluating the performance of Network-on-chip. Although previous research has proposed standard guidelines to develop benchmarks for Network-on-Chip, this work moves forward and proposes a System-C based simulation platform for system-level design exploration. It will provide an initial set of synthetic benchmarks for on-chip network interconnection validation along with an initial set of standardized processing cores, NOC components, and system-wide services. The benchmarks were constructed using synthetic applications described by Task Graphs For Free (TGFF) task graphs extracted from the E3S benchmark suite. Two benchmarks were used for characterization: Consumer and Networking. They are characterized based on throughput and latency. Case studies show how they can be used to evaluate metrics beyond throughput and latency (i.e. traffic distribution). The contribution of this work is two-fold: 1) This study provides a methodology for benchmark creation and characterization using NoCBench that evaluates important metrics in NOC design (i.e. end-to-end packet delay, throughput). 2) The developed full-system simulation platform provides a complete environment for further benchmark characterization on NOC based MpSoC as well as system-level design space exploration. Advisors/Committee Members: Mahapatra, Rabi N. (advisor), Bettati, Riccardo (committee member), Gratz, Paul (committee member).

Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Chicago Manual of Style (16^th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Masters Thesis, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

MLA Handbook (7^th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 07 Mar 2021.

Vancouver:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Council of Science Editors:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

3. Magnos Roberto Pizzoni. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.

Degree: 2010, Universidade do Vale do Itajaí

URL: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

►

Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos… (more)

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Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos utilizando-se blocos de silício reutilizáveis (núcleos). Com as novas tecnologias de integração, será possível construir sistema com várias dezenas a centenas de núcleos em um mesmo chip. Tais sistemas terão alto poder de processamento, mas irá requerer estruturas de comunicação reutilizáveis com desempenho escalável, o que não é possível de ser obtido com as arquiteturas usadas atualmente, baseadas no barramento. É consenso na comunidade acadêmica e na indústria que a melhor solução para esse problema é baseada em estruturas de interconexão com canais chaveados por roteadores as chamadas Redes-em-Chip ou NoCs (Networks-on-Chip). Atualmente, diversos grupos de pesquisa trabalham investigando diferentes aspectos sobre NoCs e a grande maioria desses trabalhos utiliza ambientes de simulação para exploração arquitetural e avaliação de desempenho. No entanto, em modelos detalhados e com precisão de ciclo, o tempo de simulação é bastante alto, o que limita a quantidade de ciclos a serem simulados. Após a validação e a avaliação baseada em simulação, usualmente, realiza-se a síntese da NoC em FPGA (Field Programmable Gate Array) para realizar a sua validação física. Para tal, é necessário construir um sistema com núcleos conectados à rede e que produzam o tráfego que permitam validar a arquitetura implementada. Este projeto insere-se nesse contexto e busca desenvolver uma infra-estrutura de apoio à pesquisa sobre NoCs por meio da disponibilização de geradores de tráfego sintetizáveis para validação física e para a avaliação de desempenho de NoCs em dispositivos do tipo FPGA. A idéia é que essa infra-instrutora facilite a validação da rede e a realização de experimentos de análise de desempenho mais rapidamente e com maior precisão do que aqueles realizados em ambientes de simulação. Neste trabalho, foram desenvolvidos componentes de hardware e de software para a construção da plataforma proposta

With the evolution of the circuit manufacturer processes is becoming possible to integrate complete systems in a single chip, which are built of reusable silicon-based blocks (cores). With the advent of new integration technologies, it will be possible to build a system with several tens to hundreds of cores in the same chip. Such systems will have a higher processing power, but will require reusable communication structures with scalable performance, which is not possible to be obtained with the current bus-based architectures. The consensus in the academic community and industry is that the best solution for this problem is based on interconnection architectures with switching channels by routers the so called chip-networks or NoCs (Networks-on-Chip). Nowadays, several groups of research investigate different aspects of NoCs and the majority of the work being done uses simulation environments for architectural exploration and performance evaluation. However, in detailed models…

Advisors/Committee Members: Cesar Augusto Tischer, Alejandro Rafael Garcia Ramirez, Michelle Silva Wangham.

Subjects/Keywords: System-on-Chip; Network-on-Chip; Avaliação de desempenho; CIENCIA DA COMPUTACAO; Circuitos integrados; System-on-Chip; Network-on-Chip; Performance

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APA (6^th Edition):

Pizzoni, M. R. (2010). PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Thesis, Universidade do Vale do Itajaí. Accessed March 07, 2021. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Web. 07 Mar 2021.

Vancouver:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2010. [cited 2021 Mar 07]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Thesis]. Universidade do Vale do Itajaí; 2010. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Anna University

4. Saravanakumar U. An investigation on macro and micro Architectures for network on chip;.

Degree: An investigation on macro and micro Architectures for network on chip, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/40748

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As the technology scales down more processors or Processing newlineElements PEs are integrated in the same die and such technology is called as newlineMultiprocessor System… (more)

Subjects/Keywords: Microarchitectural aims; Multiprocessor System on Chip; Network on Chip

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APA (6^th Edition):

U, S. (2015). An investigation on macro and micro Architectures for network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Thesis, Anna University. Accessed March 07, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Web. 07 Mar 2021.

Vancouver:

U S. An investigation on macro and micro Architectures for network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 07]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

U S. An investigation on macro and micro Architectures for network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Viswanathan N. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.

Degree: Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/33543

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Three dimensional integration is one of the emerging techniques newlineto find solution for the global interconnect delay challenges faced in the newlineadvanced VLSI ULSI technology… (more)

Subjects/Keywords: Network on Chip; System on Chip; Through Silicon Via

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APA (6^th Edition):

N, V. (2015). Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Thesis, Anna University. Accessed March 07, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Web. 07 Mar 2021.

Vancouver:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 07]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Anna University

6. Maheswari M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;.

Degree: Novel approaches in the design of Reliable custom topology for Application specific network on chip, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/39199

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Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed… (more)

Subjects/Keywords: Digital Signal Processor; Intellectual Property; Networks on Chip; System on Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

M, M. (2015). Novel approaches in the design of Reliable custom topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/39199

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed March 07, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/39199.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Web. 07 Mar 2021.

Vancouver:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 07]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Anna University

7. Maheswari M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;.

Degree: Novel approaches in the design of Reliable custom topology for Application specific network on chip, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/41574

►

Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed… (more)

Subjects/Keywords: Digital Signal Processor; Networks on Chip; System on Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

M, M. (2015). Novel approaches in the design of Reliable custom topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/41574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed March 07, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/41574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Web. 07 Mar 2021.

Vancouver:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 07]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Texas A&M University

8. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: PhD, Computer Engineering, 2012, Texas A&M University

URL: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

► With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Chicago Manual of Style (16^th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Doctoral Dissertation, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

MLA Handbook (7^th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 07 Mar 2021.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

University of New South Wales

9. Hussain, Mubashir. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.

Degree: Computer Science & Engineering, 2018, University of New South Wales

URL: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

► Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system… (more)

▼ Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system may involve different parties, especially for the design of system-on-chip (SoC) where the high complexity of the design has pushed designers towards using the third-party components that may have been modified with malicious additions without notice of the designer.Such a malicious modification (known as hardware Trojan) may be very small and can escape the scrutiny of the offline circuit-level testing and appear in the final product, which creates a new class of threats that have to be addressed at the hardware level and at the runtime.For SoCs, one of the most vulnerable components is the communication sub-system, called network-on-chip (NoC). NoC is able to access all components in the system and can be an easy target for varied attacks.This thesis aims at the hardware Trojan inside the router of a NoC. When activated, the Trojan can modify passing packets for two different purposes: 1) hijacking packets to harvest information carried by the packet; 2) manipulating the packet to alter the packet data. Both attacks can be tackled by the authentication.But unlike the software level authentication designs in the traditional networking system, the authentication in NoC has on-chip overhead issues.The thesis investigates three designs: one for packet hijacking attack detection, one for packet integrity attack detection, and one for Trojan location detection. Each design has a different dominant overhead issue. We, therefore, have a different optimization objective in the design.For the packet hijacking attack detection, we target the overhead on the chip cost and we present a customization design. For the packet data integrity authentication, the main concern is the bandwidth consumption caused by the large tag size and we introduce a progressive authentication scheme to reduce the bandwidth overhead. For the Trojan location detection, we propose a dynamic search algorithm to minimize the energy consumption.We have conducted a range of extensive experiments on each design, which demonstrate the effectiveness of our design approaches. Advisors/Committee Members: Guo, Hui, UNSW.

Subjects/Keywords: System-on-Chip; Hardware Trojan; Network-on-Chip; Hardware Security

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APA (6^th Edition):

Hussain, M. (2018). Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

Chicago Manual of Style (16^th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Doctoral Dissertation, University of New South Wales. Accessed March 07, 2021. http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

MLA Handbook (7^th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Web. 07 Mar 2021.

Vancouver:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2021 Mar 07]. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

Council of Science Editors:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

University of Victoria

10. Shiran, Vahid. Design and optimization of terahertz waveguides with low loss and dispersion.

Degree: Department of Electrical and Computer Engineering, 2020, University of Victoria

URL: http://hdl.handle.net/1828/12090

► Electromagnetic waves in the terahertz spectral range have gained significant research focus due to their applications in various fields of science. To effectively generate and… (more)

▼ Electromagnetic waves in the terahertz spectral range have gained significant research focus due to their applications in various fields of science. To effectively generate and integrate terahertz waves in systems, appropriate waveguide design is critical. Conventionally waveguides have been used to control the propagation of electromagnetic waves. A waveguide with low loss and dispersion is always preferred. But achieving these characteristics is quite challenging especially if operating in the terahertz spectral range. There are inherent material and geometric limitations that exist for terahertz waveguides. It is therefore important to optimize the design to enable their use in applications efficiently. This thesis investigates the characteristics of three primary terahertz waveguides based on the underlying theory and results obtained from simulations. The three waveguides are parallel-plate waveguides, two-wire waveguides, and coplanar striplines. The work in this thesis mostly focuses on coplanar striplines, optimal for building a highly efficient commercial and portable terahertz system-on-chip (TSOC). The contribution of the thesis is around the use of different types of passive components mounted on a thin commercial Silicon Nitride membrane. A bias tee is introduced which is a combination of interdigitated electrodes and a meander inductor. The length of the interdigitated electrodes and the gap between them are 55 um and 5 um, respectively. The S21 parameter for this structure ranges from -24 dB/mm at near-zero frequencies to -0.8 dB/mm at 1 THz. This indicates that the designed bias tee can appropriately block low frequencies. Split-ring resonators are also used to act as band-stop filters. The resonant frequency of the resonator depends on the radii of the split-rings. In the optimized design, the internal radius of the outer ring is 25 um and the external radius of the inner ring is 20 um. This results in a narrowband band-stop filter with its resonant frequency centered at 701 GHz. The optimized final TSOC design discussed in this work uses these passive components placed on the Silicon Nitride membrane and is shown to have a total loss that is 3 dB/mm less than any of the previous work for terahertz frequencies. Advisors/Committee Members: Darcie, Thomas Edward (supervisor).

Subjects/Keywords: Terahertz waveguide; On-chip-system; Low loss

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APA (6^th Edition):

Shiran, V. (2020). Design and optimization of terahertz waveguides with low loss and dispersion. (Masters Thesis). University of Victoria. Retrieved from http://hdl.handle.net/1828/12090

Chicago Manual of Style (16^th Edition):

Shiran, Vahid. “Design and optimization of terahertz waveguides with low loss and dispersion.” 2020. Masters Thesis, University of Victoria. Accessed March 07, 2021. http://hdl.handle.net/1828/12090.

MLA Handbook (7^th Edition):

Shiran, Vahid. “Design and optimization of terahertz waveguides with low loss and dispersion.” 2020. Web. 07 Mar 2021.

Vancouver:

Shiran V. Design and optimization of terahertz waveguides with low loss and dispersion. [Internet] [Masters thesis]. University of Victoria; 2020. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1828/12090.

Council of Science Editors:

Shiran V. Design and optimization of terahertz waveguides with low loss and dispersion. [Masters Thesis]. University of Victoria; 2020. Available from: http://hdl.handle.net/1828/12090

Texas A&M University

11. Dollie, Patrick Kofi Mensah. Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique.

Degree: MS, Electrical Engineering, 2018, Texas A&M University

URL: http://hdl.handle.net/1969.1/174653

► The concept full chip integration of circuits has gained traction over the years with the push towards system-on-chip (SoC) designs which serve the niche for… (more)

Subjects/Keywords: system-on-chip; low dropout regulator

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APA (6^th Edition):

Dollie, P. K. M. (2018). Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/174653

Chicago Manual of Style (16^th Edition):

Dollie, Patrick Kofi Mensah. “Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique.” 2018. Masters Thesis, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/174653.

MLA Handbook (7^th Edition):

Dollie, Patrick Kofi Mensah. “Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique.” 2018. Web. 07 Mar 2021.

Vancouver:

Dollie PKM. Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/174653.

Council of Science Editors:

Dollie PKM. Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/174653

12. Tulasidas, Sivanesan. Secure expandable communication framework for POCT system development and deployment.

Degree: PhD, 2018, Brunel University

URL: http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056

► Health-care delivery in developing countries has many challenges because they do not have enough resources for meeting the healthcare needs and they lack testing lab… (more)

▼ Health-care delivery in developing countries has many challenges because they do not have enough resources for meeting the healthcare needs and they lack testing lab infras- tructures in communities. It has been proven that Point-Of-Care (POC) testing can be considered as one of the ways to resolve the crisis in healthcare delivery in these com- munities. The POC testing is a mission critical processes in which the patient conduct tests outside of laboratory environment and it needs a secure communication system of architecture support which the research refers as POCT system Almost every ten years there will be a new radio access technology (RAT) is released in the wireless communication system evolution which is primarily driven by the 3GPP standards organisation. It is challenging to develop a predictable communication sys- tem in an environment of frequent changes originated by the 3GPP and the wireless operators. The scalable and expandable network architecture is needed for cost-effective network management, deployment and operation of the POC devices. Security mecha- nisms are necessary to address the specific threats associated with POCT system. Se- curity mechanisms are necessary to address the specific threats associated with POCT system. The POCT system communication must provide secure storage and secure com- munication to maintain patient data privacy and security. The Federal Drug Admin- istration (FDA) reports the leading causes of defects and system failures in medical devices are caused by gaps between the requirements, implementation and testing. The research was conducted, and technical research contributions are made to resolve the issues and challenges related to the POCT system. A communication protocol implemented at the application level, independent of radio access technologies. A new methodology was created by combining Easy Approach to Requirement Specifications (EARS) methodology and Use Case Maps (UCM) model which is a new approach and it addresses the concerns raised by the FDA. Secure cloud architecture was created which is a new way of data storage and security algorithms models were designed to address the security threats in the POCT system. The security algorithms, secure cloud architecture and the communication protocol coexist together to provide Radio access technology Independent Secure and Expandable (RISE) POCT system. These are the contributions to new knowledge that came out of the research. The research was conducted with a team of experts who are the subject matter experts in the areas such as microfluidics, bio-medical, mechanical engineering and medicine.

Subjects/Keywords: 621.381; Lab on chip system development

10 more images…

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APA (6^th Edition):

Tulasidas, S. (2018). Secure expandable communication framework for POCT system development and deployment. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056

Chicago Manual of Style (16^th Edition):

Tulasidas, Sivanesan. “Secure expandable communication framework for POCT system development and deployment.” 2018. Doctoral Dissertation, Brunel University. Accessed March 07, 2021. http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056.

MLA Handbook (7^th Edition):

Tulasidas, Sivanesan. “Secure expandable communication framework for POCT system development and deployment.” 2018. Web. 07 Mar 2021.

Vancouver:

Tulasidas S. Secure expandable communication framework for POCT system development and deployment. [Internet] [Doctoral dissertation]. Brunel University; 2018. [cited 2021 Mar 07]. Available from: http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056.

Council of Science Editors:

Tulasidas S. Secure expandable communication framework for POCT system development and deployment. [Doctoral Dissertation]. Brunel University; 2018. Available from: http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056

University of Utah

13. You, Junbok. Design and optimization of asynchronous network-on-chip.

Degree: PhD, Electrical & Computer Engineering, 2011, University of Utah

URL: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633

► The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on… (more)

▼ The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on an asynchronous NoC link will also vary depending on the wire length between sender and receiver. This work explores the benefit to NoC performance, area, and energy when this property is used to optimize bandwidth on specific links based on its bandwidth required by a target SoC design. Three asynchronous routers were designed for implementing of asynchronous NoCs. Simple routing scheme and single-flit packet format lead to performance- and area-efficient router designs. Their performance was evaluated in consideration of link wire delay. Comprehensive analysis of pipeline latch insertion in asynchronous communication links is performed in regard to link bandwidth. Optimal placement of pipeline latch for maximizing benefit to increase of bandwidth is described. Specific methods are proposed for performance, area and energy optimization, respectively. Performance optimization is achieved by increasing bandwidth of high trafficked and high utilized links in an NoC, as inserting pipeline latches in those links. Through decrease of bandwidth of links with low traffic and low utilization by halving data-path width, reduction of wire area of an NoC is accomplished. Energy optimization is performed using wide spacing between wires in links with high energy consumption. An analytical model for asynchronous link bandwidth estimation is presented. It is utilized to deploy NoC optimization methods as identifying adequate links for each optimization method. Energy and latency characteristics of an asynchronous NoC are compared to a similarly-designed synchronous NoC. The results indicate that the asynchronous network has lower energy, and link-specific bandwidth optimization has improved NoC performance. Evaluation of proposed optimization methods by employing to an asynchronous NoC shows achievements of performance enhancement, wire area reduction and wire energy saving.

Subjects/Keywords: Asynchronous circuit design; Digital VLSI design; Interconnect system; Network-on-chip; System-on-chip

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APA (6^th Edition):

You, J. (2011). Design and optimization of asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633

Chicago Manual of Style (16^th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed March 07, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

MLA Handbook (7^th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Web. 07 Mar 2021.

Vancouver:

You J. Design and optimization of asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2021 Mar 07]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

Council of Science Editors:

You J. Design and optimization of asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633

Texas A&M University

14. Jeong, Sehoon. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.

Degree: PhD, Biomedical Engineering, 2018, Texas A&M University

URL: http://hdl.handle.net/1969.1/173360

► Neurological diseases are a major challenge to reach new therapies. However, physiological signals that regulate neurodegeneration in the central nervous system (CNS) are still little… (more)

▼ Neurological diseases are a major challenge to reach new therapies. However, physiological signals that regulate neurodegeneration in the central nervous system (CNS) are still little known since there is no suitable in vitro model for studying the basis of localized cells and molecules. Here this dissertation presents the development of biomimetic microsystems that reconstitute neurophysiologically important functional brain and neurovascular interface in the CNS. The brain organs-on-chips can recapitulate pharmacological responses and complex interactions between different types of cells that are mediated by the extracellular matrix and intercellular junctions within the organ model. Since the developed microsystems have a biomimetic tissue structure, it is possible to more accurately function and simulate the delivery and penetration of the drug compound in vivo than the 2D cell monolayer in the conventional culture model or the prior microfluidics. The developed brain chip is composed of four culture chambers with 10 aggregate traps and multi-electrode arrays enable electrical stimulation for 40 neuronal aggregates as well as drug stimulation. Uniform 150 μm aggregates from the microwell can be cultured for 4 weeks. This system developed for the study of CNS myelin formation showed that the 10Hz of electrical stimulation for the promotion of myelination was successfully confirmed with 500 nM retinoic acid treatment results in the automatic image analysis. iii The other developed blood-brain barrier (BBB) chip consists of 4 × 4 microfluidic channel arrays and 16 channel multi-electrode arrays, able to electrically analyze 16 sites. Co-culture BBB-on-a-chip contains neurovascular endothelium separated from primary astrocyte by a porous membrane that allows cell-cell interactions through the membrane. In this platform, the effects of astrocyte-coculture, extracellular matrix, and in vivo shear stress level on barrier permeability were characterized through TEER measurements and dextran permeability assays. Also, despite the presence of BBB, monocyte infiltration into the CNS was observed by monocyte chemotactic protein (CCL2), which corresponds to the early event of brain injury. Finally, the system developed to address these pharmacological problems for drug development showed how drugs work in brain vessels (histamine) and brain tissues (tetrodotoxin), as well as delivering drugs from brain vessels to brain tissue (atenolol). Advisors/Committee Members: Han, Arum (advisor), Li, Jianrong (advisor), McShane, Mike (committee member), Gaharwar, Akhilesh (committee member).

Subjects/Keywords: Brain organ-on-a-chip; Microfluidic blood-brain barrier-on-a-chip; Neuroinflammation-on-a-chip; Drug screening system

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APA (6^th Edition):

Jeong, S. (2018). Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173360

Chicago Manual of Style (16^th Edition):

Jeong, Sehoon. “Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.” 2018. Doctoral Dissertation, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/173360.

MLA Handbook (7^th Edition):

Jeong, Sehoon. “Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.” 2018. Web. 07 Mar 2021.

Vancouver:

Jeong S. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. [Internet] [Doctoral dissertation]. Texas A&M University; 2018. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/173360.

Council of Science Editors:

Jeong S. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. [Doctoral Dissertation]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173360

15. Papastefanakis, Ermis. Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC).

Degree: Docteur es, Informatique, 2017, Université Paris-Est

URL: http://www.theses.fr/2017PESC1137

► L'évolution de Systems-on-Chip (SoCs) est rapide et le nombre des processeurs augmente conduisant à la transition des les plates-formes Multi-core vers les Manycore. Dans telles… (more)

▼ L'évolution de Systems-on-Chip (SoCs) est rapide et le nombre des processeurs augmente conduisant à la transition des les plates-formes Multi-core vers les Manycore. Dans telles plates-formes, l'architecture d'interconnexion a également décalé des bus traditionnels vers les Réseaux sur puce (NoC) afin de faire face à la mise en échelle. Les NoC permettent aux processeurs d'échanger des informations avec la mémoire et les périphériques lors de l'exécution d'une tâche et d'effectuer plusieurs communications en parallèle. Les plates-formes basées sur un NoC sont aussi présentes dans des systèmes embarqués, caractérisés par des exigences comme la prédictibilité, la sécurité et la criticité mixte. Afin de fournir telles fonctionnalités dans les plates-formes commerciales existantes, il faut prendre en considération le NoC qui est un élément clé ayant un impact important sur les performances d'un SoC. Une tâche échange des informations à travers du NoC et par conséquent, son temps d'exécution dépend du temps de transmission des flux qu'elle génère. En calculant le temps de transmission de pire cas (WCTT) des flux dans le NoC, une étape est faite vers le calcul du temps d'exécution de pire cas (WCET) d'une tâche. Ceci contribue à la prédictibilité globale du système. De plus, en prenant en compte les politiques d'arbitrage dans le NoC, il est possible de fournir des garanties de sécurité contre des tâches compromises qui pourraient essayer de saturer les ressources du système (attaque DoS). Dans les systèmes critiques de sécurité, une distinction des tâches par rapport à leur niveau de criticité, permet aux tâches de criticité mixte de coexister et d'exécuter en harmonie. De plus, ça permet aux tâches critiques de maintenir leurs temps d'exécution au prix de tâches de faible criticité qui seront ralenties ou arrêtées. Cette thèse vise à fournir des méthodes et des mécanismes dans le but de contribuer aux axes de prédictibilité, de sécurité et de criticité mixte dans les architectures Manycore basées sur Noc. En outre, l'incitation consiste à relever conjointement les défis dans ces trois axes en tenant compte de leur impact mutuel. Chaque axe a été étudié individuellement, mais très peu de recherche prend en compte leur interdépendance. Cette fusion des aspects est de plus en plus intrinsèque dans des domaines tels que Internet-of-Things, Cyber-Physical Systems (CPS), véhicules connectés et autonomes qui gagnent de l'élan. La raison en est leur haut degré de connectivité qui crée une grande surface d'exposition ainsi que leur présence croissante qui rend l'impact des attaques sévère et visible. Les contributions de cette thèse consistent en une méthode pour fournir une prédictibilité aux flux dans le NoC, un mécanisme pour la sécurité du NoC et une boîte à outils pour la génération de trafic utilisée pour l'analyse comparative. La première contribution est une adaptation de l'approche de la trajectoire traditionnellement utilisée dans les réseaux avioniques (AFDX) pour calculer le WCET. Dans cette thèse, nous identifions… Advisors/Committee Members: George, Laurent (thesis director).

Subjects/Keywords: Network on Chip; System on Chip; Architectures embarquées; Qualité de service; Criticalité mixte; Network on Chip; System on Chip; Embedded architectures; Quality of service; Mixed criticality

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Papastefanakis, E. (2017). Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC). (Doctoral Dissertation). Université Paris-Est. Retrieved from http://www.theses.fr/2017PESC1137

Chicago Manual of Style (16^th Edition):

Papastefanakis, Ermis. “Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC).” 2017. Doctoral Dissertation, Université Paris-Est. Accessed March 07, 2021. http://www.theses.fr/2017PESC1137.

MLA Handbook (7^th Edition):

Papastefanakis, Ermis. “Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC).” 2017. Web. 07 Mar 2021.

Vancouver:

Papastefanakis E. Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC). [Internet] [Doctoral dissertation]. Université Paris-Est; 2017. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2017PESC1137.

Council of Science Editors:

Papastefanakis E. Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC). [Doctoral Dissertation]. Université Paris-Est; 2017. Available from: http://www.theses.fr/2017PESC1137

Universidade do Rio Grande do Sul

16. Reinbrecht, Cezar Rodolfo Wedig. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.

Degree: 2012, Universidade do Rio Grande do Sul

URL: http://hdl.handle.net/10183/67148

►

Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas… (more)

▼

Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas com múltiplos processadores num chip (MPSoCs, do inglês MultiProcessor System-on-Chip). Essa possibilidade de integração permite inserir dezenas de Elementos de Processamento (EPs) nos circuitos integrados atuais, e já se projeta centenas de EPs para os sistemas da próxima década (ITRS, 2011). Nesse cenário, um dos principais desafios se refere ao serviço de interconexão dos EPs, que deve apresentar um desempenho de comunicação necessário para as aplicações em execução sem comprometer as limitações de consumo de área e energia do circuito. Nos primeiros sistemas multiprocessados, com poucos nodos, arquiteturas baseadas em barramento foram suficientes para cumprir esses requisitos. Porém, o número de elementos nos sistemas recentes aumentou rapidamente, tornando as redes-em-chip a solução mais apropriada, por aliar escalabilidade e reuso na mesma estrutura. Contudo, diante da previsão de que essa tendência de aumento se manterá retorna a discussão se as redes-em-chip atuais continuarão adequadas para os futuros sistemas. De fato, o custo das redes-em-chip convencionais pode se tornar proibitivo para as escalas dos circuitos em um futuro próximo. Novas propostas têm sido apresentadas na literatura científica onde se podem destacar duas principais estratégias de projeto às redes de interconexão: reconfiguração arquitetural e organização hierárquica da topologia. A reconfiguração arquitetural permite obter uma grande eficiência, independente do tipo de aplicação em execução, pois uma das alternativas é projetar o circuito para que ele se auto adapte conforme os requisitos de desempenho para cada aplicação. Por outro lado, arquiteturas organizadas em topologias hierárquicas são desenvolvidas para uma estrutura computacional definida em tempo de projeto, sendo mais eficazes para uma classe de aplicações. O presente trabalho explora a sinergia da combinação das potencialidades das duas soluções e propõe uma nova estrutura que oferece melhor desempenho para uma classe maior de aplicações apropriada para os futuros sistemas. Como resultado foi implementada uma arquitetura adaptativa chamada MINoC (Multiple Interconnections Networks-on-Chip), uma arquitetura organizada em hierarquia, chamada HiCIT (Hierarchical Crossbar-based Interconnection Topology) e uma simbiose de ambas culminando na arquitetura hierárquica adaptativa HASIN (Hierarchical Adaptive Switching Interconnection Network). São apresentados resultados que mostram a eficiência desses conceitos validando a proposta hierárquica adaptativa.

With the advent of submicron processes, the number of transistors integrated on a single chip has reached levels that allowed the design of Multiprocessor Systems-on-Chip (MPSoCs). This capability allows the integration of several processing elements (PEs) in integrated circuits designed nowadays. In the next decade it is expected that hundreds of PEs…

Advisors/Committee Members: Susin, Altamiro Amadeu.

Subjects/Keywords: Microeletrônica; MPSoCs; Network-on-chip; Sistemas embarcados; MPSoC; Interconnections; Adaptive architecture; System-on-chip

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APA (6^th Edition):

Reinbrecht, C. R. W. (2012). Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/67148

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Reinbrecht, Cezar Rodolfo Wedig. “Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed March 07, 2021. http://hdl.handle.net/10183/67148.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Reinbrecht, Cezar Rodolfo Wedig. “Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.” 2012. Web. 07 Mar 2021.

Vancouver:

Reinbrecht CRW. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10183/67148.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reinbrecht CRW. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/67148

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Utah

17. Gebhardt, Daniel J. Energy-efficient design of an asynchronous network-on-chip.

Degree: PhD, Computer Science, 2011, University of Utah

URL: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

► Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are… (more)

Subjects/Keywords: Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip

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APA (6^th Edition):

Gebhardt, D. J. (2011). Energy-efficient design of an asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Chicago Manual of Style (16^th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed March 07, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

MLA Handbook (7^th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Web. 07 Mar 2021.

Vancouver:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2021 Mar 07]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

Council of Science Editors:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Washington State University

18. [No author]. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .

Degree: 2017, Washington State University

URL: http://hdl.handle.net/2376/13038

► In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and… (more)

▼ In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and highly scalable platform suitable for both data- and compute-intensive applications. The performance of a manycore architecture is highly dependent on the capabilities of its communication backbone, namely the Network on-chip (NoC). An efficient NoC designed for a manycore platform must align the connectivity of the NoC with the application’s on-chip traffic patterns. Analysis on the inter-core traffic patterns exhibited by various Big Data applications reveal irregular memory access behaviors that give rise to long-range on-chip communication requirements. In addition to the irregular memory access patterns, many of the modern applications also necessitate dense collective communication capabilities among the on-chip nodes. Under collective communication, either a single source node transmits data to all the other nodes in the system (one-to-all) or all the nodes in the system communicate with a single destination node (all-to-one). Wireless NoC is an emerging paradigm to design high bandwidth and energy efficient communication backbone for manycore chips. Previous works show that the wireless links can establish low-latency data-transfers even between physically distant on-chip nodes. In addition, with its inherent broadcast capability, the on-chip wireless links are highly suited to perform efficient collective-communication. Thus, employing on-chip wireless links one can design efficient communication infrastructures for manycore platforms running high performance Big Data processing. This dissertation focuses on designing a hybrid (wireline + wireless) network-on-chip architecture (called WiNoC) capable of low-latency collective communication. First, we leverage the knowledge gained from studying small-world graphs to design low hop count WiNoC topologies. Next, we augment the WiNoC with suitable data-transfer mechanisms to ensure a congestion-free high performance NoC. On overall, this work indicates on-chip communication challenges arise from manycore Big Data processing and proposes a wireless-enabled high performance and energy efficient NoC capable of addressing these challenges. Advisors/Committee Members: Pande, Partha Pratim (advisor).

Subjects/Keywords: Computer engineering; Big Data; Graph Analytics; MapReduce; Network-on-Chip; System-on-Chip; Wireless NoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

author], [. (2017). COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/13038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .” 2017. Thesis, Washington State University. Accessed March 07, 2021. http://hdl.handle.net/2376/13038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .” 2017. Web. 07 Mar 2021.

Vancouver:

author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . [Internet] [Thesis]. Washington State University; 2017. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/2376/13038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . [Thesis]. Washington State University; 2017. Available from: http://hdl.handle.net/2376/13038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Texas A&M University

19. Yang, Yoon Seok. Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design.

Degree: PhD, Computer Engineering, 2012, Texas A&M University

URL: http://hdl.handle.net/1969.1/191999

► This dissertation presents three design solutions to support several key system-on-chip (SoC) issues to achieve low-power and high performance. These are: 1) joint source and… (more)

▼ This dissertation presents three design solutions to support several key system-on-chip (SoC) issues to achieve low-power and high performance. These are: 1) joint source and channel decoding (JSCD) schemes for low-power SoCs used in portable multimedia systems, 2) efficient on-chip interconnect architecture for massive multimedia data streaming on multiprocessor SoCs (MPSoCs), and 3) data processing architecture for low-power SoCs in distributed sensor network (DSS) systems and its implementation. The first part includes a low-power embedded low density parity check code (LDPC) - H.264 joint decoding architecture to lower the baseband energy consumption of a channel decoder using joint source decoding and dynamic voltage and frequency scaling (DVFS). A low-power multiple-input multiple-output (MIMO) and H.264 video joint detector/decoder design that minimizes energy for portable, wireless embedded systems is also designed. In the second part, a link-level quality of service (QoS) scheme using unequal error protection (UEP) for low-power network-on-chip (NoC) and low latency on-chip network designs for MPSoCs is proposed. This part contains WaveSync, a low-latency focused network-on-chip architecture for globally-asynchronous locally-synchronous (GALS) designs and a simultaneous dual-path routing (SDPR) scheme utilizing path diversity present in typical mesh topology network-on-chips. SDPR is akin to having a higher link width but without the significant hardware overhead associated with simple bus width scaling. The last part shows data processing unit designs for embedded SoCs. We propose a data processing and control logic design for a new radiation detection sensor system generating data at or above Peta-bits-per-second level. Implementation results show that the intended clock rate is achieved within the power target of less than 200mW. We also present a digital signal processing (DSP) accelerator supporting configurable MAC, FFT, FIR, and 3-D cross product operations for embedded SoCs. It consumes 12.35mW along with 0.167mm2 area at 333MHz. Advisors/Committee Members: Choi, Gwan S (advisor), Gratz, Paul V (committee member), Kish, Laszlo B (committee member), Sarin, Vivek (committee member).

Subjects/Keywords: accelerator; digital signal processing; low-latency; network-on-chip; low-power; system-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yang, Y. S. (2012). Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/191999

Chicago Manual of Style (16^th Edition):

Yang, Yoon Seok. “Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design.” 2012. Doctoral Dissertation, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/191999.

MLA Handbook (7^th Edition):

Yang, Yoon Seok. “Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design.” 2012. Web. 07 Mar 2021.

Vancouver:

Yang YS. Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/191999.

Council of Science Editors:

Yang YS. Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/191999

Oklahoma State University

20. Williams, Seth Adam. Benchmarking ARM-based Application Integrated Systems.

Degree: School of Electrical & Computer Engineering, 2011, Oklahoma State University

URL: http://hdl.handle.net/11244/10295

► ARM Holding Ltd. is in a very good position; by owning a very prolific instruction set architecture (named ARM) and licensing it to other companies… (more)

Subjects/Keywords: arm; embedded benchmarks; package-on-package; system-on-chip

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APA (6^th Edition):

Williams, S. A. (2011). Benchmarking ARM-based Application Integrated Systems. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/10295

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Thesis, Oklahoma State University. Accessed March 07, 2021. http://hdl.handle.net/11244/10295.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Web. 07 Mar 2021.

Vancouver:

Williams SA. Benchmarking ARM-based Application Integrated Systems. [Internet] [Thesis]. Oklahoma State University; 2011. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/11244/10295.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Williams SA. Benchmarking ARM-based Application Integrated Systems. [Thesis]. Oklahoma State University; 2011. Available from: http://hdl.handle.net/11244/10295

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Psarras, Anastasios. High-performance networks-on-chip.

Degree: 2017, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ)

URL: http://hdl.handle.net/10442/hedi/41266

► Over the last two decades, we have witnessed a fundamental paradigm shift in digital system design: the transition to the multi-core realm. Naturally, the multi-core… (more)

▼ Over the last two decades, we have witnessed a fundamental paradigm shift in digital system design: the transition to the multi-core realm. Naturally, the multi-core domain has elevated the criticality of the on-chip interconnection fabric, which is now tasked with satisfying amplified communication demands. Owing to their scalability attributes, Networks-on-Chip (NoC) have established their position as the de facto communication medium in multi-core systems. To sustain system scalability into the many-core domain (with potentially hundreds of cores), it is imperative that the NoC's hardware cost is minimized, while not sacrificing network performance.To this end, we propose three alternative architectures that can significantly improve the performance of NoCs, or lead to an overall lower power consumption.The first one is a pipelined router architecture, called ShortPath, that parallelizes - for the first time - the allocation steps involved in the operation of a VC-based router without resorting to speculation. Most importantly, ShortPath is augmented with an always-productive pipeline bypassing mechanism, which skips all stages without contention, and "fast-forwards" the flits to the first encountered point of contention.The other two approaches exploit fast link traversal, after appropriate wire engineering, to rapidly transfer flits between adjacent routers (connected with links of reasonable, short-to-medium length of up to a few millimeters) in half a clock cycle. Under this clocking principle, two design alternatives are explored, which allow for half-cycle and Double-Data-Rate (DDR) link traversal. The proposed approaches can markedly increase network performance, or decrease the area/power cost of the NoC. Although not obvious at first glance, half-cycle link traversal opens up new possibilities for reducing wire capacitance. By harnessing these opportunities, the half-cycle-delay requirement becomes easier to achieve and potentially extends half-cycle traversal capabilities to longer links. To tackle longer links, novel DDR dual-stream elastic buffers are proposed for pipelining the links while still following DDR flow control.As multi/many-core architectures evolve, the demands on the NoC are amplified. In addition to high performance and physical scalability, the NoC is increasingly required to also provide specialized functionality, such as network virtualization, flow isolation, and quality-of-service guarantees. Although traditional architectures supporting Virtual Channels (VCs) offer the resources for flow partitioning and isolation, an adversarial workload can still interfere and degrade the performance of other workloads that are active in a different set of VCs. Motivated by this aspect, we present PhaseNoC, a truly non interfering VC-based architecture that adopts time-division multiplexing at the VC level. Distinct flows, or application domains, mapped to disjoint sets of VCs are isolated, both inside the router's pipeline, and at the network level. Any latency overhead is minimized by…

Subjects/Keywords: Δίκτυα σε Ολοκληρωμένα Κυκλώματα; Ολοκληρωμένα κυκλώματα; Πολυπύρηνοι επεξεργαστές; Συστήματα σε Ολοκληρωμένα Κυκλώματα; Networks-on-Chip; VLSI; Multi-core architectures; Chip Multi-Processors; System-on-chip; On-chip Interconnection Networks

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Psarras, A. (2017). High-performance networks-on-chip. (Thesis). Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Retrieved from http://hdl.handle.net/10442/hedi/41266

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Psarras, Anastasios. “High-performance networks-on-chip.” 2017. Thesis, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Accessed March 07, 2021. http://hdl.handle.net/10442/hedi/41266.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Psarras, Anastasios. “High-performance networks-on-chip.” 2017. Web. 07 Mar 2021.

Vancouver:

Psarras A. High-performance networks-on-chip. [Internet] [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2017. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10442/hedi/41266.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Psarras A. High-performance networks-on-chip. [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2017. Available from: http://hdl.handle.net/10442/hedi/41266

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

22. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: MSc Engg, Faculty of Engineering, 2011, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/1408

► A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Vikas, G. (2011). Power Optimal Network-On-Chip Interconnect Design. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/1408

Chicago Manual of Style (16^th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2011. Masters Thesis, Indian Institute of Science. Accessed March 07, 2021. http://etd.iisc.ac.in/handle/2005/1408.

MLA Handbook (7^th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2011. Web. 07 Mar 2021.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Masters thesis]. Indian Institute of Science; 2011. [cited 2021 Mar 07]. Available from: http://etd.iisc.ac.in/handle/2005/1408.

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Masters Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ac.in/handle/2005/1408

Universidade do Rio Grande do Norte

23. Araújo, Sílvio Roberto Fernandes de. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .

Degree: 2008, Universidade do Rio Grande do Norte

URL: http://repositorio.ufrn.br/handle/123456789/17969

► The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the… (more)

▼ The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform Advisors/Committee Members: Silva, Ivan Saraiva (advisor), CPF:43728090425 (advisor), http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2 (advisor).

Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Thesis, Universidade do Rio Grande do Norte. Accessed March 07, 2021. http://repositorio.ufrn.br/handle/123456789/17969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Web. 07 Mar 2021.

Vancouver:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2008. [cited 2021 Mar 07]. Available from: http://repositorio.ufrn.br/handle/123456789/17969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Thesis]. Universidade do Rio Grande do Norte; 2008. Available from: http://repositorio.ufrn.br/handle/123456789/17969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Sílvio Roberto Fernandes de Araújo. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.

Degree: 2008, Universidade Federal do Rio Grande do Norte

URL: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541

►

O aumento na capacidade de integração de transistores permitiu o desenvolvimento de sistemas completos, com inúmeros componentes, dentro de um único chip, são os chamados… (more)

▼

O aumento na capacidade de integração de transistores permitiu o desenvolvimento de sistemas completos, com inúmeros componentes, dentro de um único chip, são os chamados SoCs (System-on-Chip). No entanto, o subsistema de interconexão utilizado pode limitar a escalabilidade dos SoCs, como os barramentos, ou ser uma solução ad hoc, como a hierarquia de barramentos. Desse modo, a solução ideal para interconexão no SoCs são as redes em chip ou NoCs (Network-on-Chip). As NoCs permitem múltiplas conexão ponto-a-ponto entre os componente e podem ser reusadas em projetos diversos. Entretanto, o uso de NoCs pode representar o aumento na complexidade do projeto do sistema, da área em chip e/ou potência dissipada. Dessa forma, é necessário ampliar o horizonte de utilização dos sistemas ou quebrar o paradigma do seu desenvolvimento. Assim, é proposto um sistema baseado em uma NoC, onde as aplicações são descritas em forma de pacotes e executadas de roteador em roteador durante o percurso entre origem e destino dos pacotes, sem a necessidade do uso de processadores convencionais. Para permitir a execução de aplicações, independente do número de instruções e das dimensões da rede, foi desenvolvido o algoritmo spiral complement, que permite re-rotear pacotes até que todas as instruções contidas nele sejam executadas. Portanto, o objetivo desse trabalho foi estudar a viabilidade do desenvolvimento de tal sistema, denominado sistema IPNoSys. Nesse estudo, foi desenvolvida em SystemC, com precisão de ciclo, uma ferramenta para simulação do sistema, a qual permite executar aplicações implementadas na linguagem de descrição de pacotes, também desenvolvida para esse fim. Através da ferramenta podem ser obtidos diversos resultados que permitem avaliar o funcionamento e desempenho do sistema. A metodologia empregada para descrição das aplicações corresponde, a priori, em obter o grafo de fluxo de dados da aplicação em alto nível, e desse grafo descrevê-la em um ou mais pacotes. Utilizando essa metodologia, foram realizados três estudos de casos: contador, DCT-2D e adição de ponto flutuante. O contador foi usado para avaliar a capacidade do sistema em tratar situações de deadlock e executar aplicações em paralelo. A DCT-2D foi utilizada para realizar comparações com a plataforma STORM. E, finalmente, a adição de ponto flutuante teve como objetivo ser usada como rotina de tratamento de uma instrução não implementada em hardware. Os resultados de simulação apontam favoravelmente com relação à viabilidade do desenvolvimento do sistema IPNoSys. Mostrando que é possível executar aplicações em forma de pacotes, inclusive paralelamente, sem interrupções provocadas por eventuais deadlocks, e ainda indicam maior eficiência do sistema IPNoSys a respeito do tempo de execução comparada a plataforma STORM

The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs,…

Advisors/Committee Members: Eduardo Bráulio Wanderley Netto, Fernando Rangel de Sousa, Ivan Saraiva Silva, Sérgio Bampi.

Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; SISTEMAS DE COMPUTACAO; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. (Thesis). Universidade Federal do Rio Grande do Norte. Retrieved from http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.” 2008. Thesis, Universidade Federal do Rio Grande do Norte. Accessed March 07, 2021. http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.” 2008. Web. 07 Mar 2021.

Vancouver:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. [Internet] [Thesis]. Universidade Federal do Rio Grande do Norte; 2008. [cited 2021 Mar 07]. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. [Thesis]. Universidade Federal do Rio Grande do Norte; 2008. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade do Rio Grande do Norte

25. Araújo, Sílvio Roberto Fernandes de. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .

Degree: 2008, Universidade do Rio Grande do Norte

URL: http://repositorio.ufrn.br/handle/123456789/17969

► The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the… (more)

▼ The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform Advisors/Committee Members: Silva, Ivan Saraiva (advisor), CPF:43728090425 (advisor), http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2 (advisor).

Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17969

Chicago Manual of Style (16^th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Masters Thesis, Universidade do Rio Grande do Norte. Accessed March 07, 2021. http://repositorio.ufrn.br/handle/123456789/17969.

MLA Handbook (7^th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Web. 07 Mar 2021.

Vancouver:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2008. [cited 2021 Mar 07]. Available from: http://repositorio.ufrn.br/handle/123456789/17969.

Council of Science Editors:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Masters Thesis]. Universidade do Rio Grande do Norte; 2008. Available from: http://repositorio.ufrn.br/handle/123456789/17969

Universidade do Rio Grande do Sul

26. Briao, Eduardo Wenzel. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.

Degree: 2008, Universidade do Rio Grande do Sul

URL: http://hdl.handle.net/10183/13157

►

A complexidade no projeto de sistemas eletrônicos tem aumentado devido à evolução tecnológica e permite a concepção de sistemas inteiros em um único chip (SoCs… (more)

▼

A complexidade no projeto de sistemas eletrônicos tem aumentado devido à evolução tecnológica e permite a concepção de sistemas inteiros em um único chip (SoCs – do inglês, Systems-on-Chip). Com o objetivo de reduzir a alta complexidade de projeto, custos de projeto e o tempo de lançamento do produto no mercado, os sistemas são desenvolvidos em módulos funcionais, pré-verificados e pré-projetados, denominados de núcleos de propriedade intelectual (IP – do inglês, Intellectual Property). Esses núcleos IP podem ser reutilizados de outros projetos ou adquiridos de terceiros. Entretanto, é necessário prover uma estrutura de comunicação para interligar esses núcleos e as estruturas atuais (barramentos) são inadequadas para atender as necessidades dos futuros SoCs (compartilhamento de banda, falta de escalabilidade). As redes-em-chip (NoCs{ XE "NoCs" } – do inglês, Networks-on-Chip) vêm sendo apresentadas como uma solução para atender essas restrições. No desenvolvimento de sistemas embarcados baseados em redes-em-chip, deve-se personalizar a rede para atendimento de restrições. Essa exploração de espaço de projeto (EEP), segundo uma infinidade de trabalhos, é realizada em tempo de projeto, supondo-se que é conhecido o perfil das aplicações que devem ser executadas pelo sistema. No entanto, cada vez mais sistemas embarcados aproximam-se de dispositivos genéricos de processamento (como palmtops), onde as tarefas a serem executadas não são inteiramente conhecidas a priori. Com a mudança dinâmica da carga de trabalho de um sistema embarcado, a busca pelo atendimento de requisitos pode então ser enfrentada por mecanismos adaptativos, que implementam dinamicamente a EEP. No âmbito deste trabalho, a EEP em tempo de execução provê mecanismos adaptativos que deverão realizar suas funções para atendimento de restrições de projeto. Consequentemente, EEP em tempo de execução pode permitir resultados ainda melhores, no que diz respeito a sistemas embarcados com restrições de projetos rígidas. É possível maximizar o tempo de duração da energia da bateria que alimenta um sistema embarcado ou, até mesmo, diminuir a taxa de perda de deadlines em um sistema de tempo real soft, realocando em tempo de execução tarefas de modo a gerar menor taxa de comunicação entre os processadores, desde que o sistema seja executado em um tempo suficiente para amortizar os custos de migração. Neste trabalho, foi utilizada a combinação de heurísticas de alocação da área dos Sistemas Computacionais Distribuídos como, por exemplo, algoritmos bin-packing e linear clustering. Resultados mostraram que a realocação de tarefas, utilizando uma combinação Worst-Fit e Linear Clustering, reduziu o consumo de energia e a taxa de perda de deadlines em 17% e 37%, respectivamente, utilizando o modelo de migração por cópia.

The complexity of electronic systems design has been increasing due to the technological evolution, which now allows the inclusion of a complete system on a single chip (SoC – System-on-Chip). In order to cope with the corresponding design complexity…

Advisors/Committee Members: Wagner, Flavio Rech.

Subjects/Keywords: Embedded systems; Microeletrônica; Design space exploration; Network-on-chip; Systemon- chip; Distributed system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Briao, E. W. (2008). Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/13157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Briao, Eduardo Wenzel. “Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed March 07, 2021. http://hdl.handle.net/10183/13157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Briao, Eduardo Wenzel. “Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.” 2008. Web. 07 Mar 2021.

Vancouver:

Briao EW. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10183/13157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Briao EW. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/13157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

King Abdullah University of Science and Technology

27. Nafe, Mahmoud. Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz.

Degree: Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division, 2015, King Abdullah University of Science and Technology

URL: http://hdl.handle.net/10754/565638

► Nowadays, there is a growing demand for high frequency-bandwidth mm-wave (30-300 GHz) electronic wireless transceiver systems to support applications such as high data-rate wireless communication… (more)

▼ Nowadays, there is a growing demand for high frequency-bandwidth mm-wave (30-300 GHz) electronic wireless transceiver systems to support applications such as high data-rate wireless communication and high resolution imaging. Such mm-wave systems are becoming more feasible due to the extreme transistor downscaling in silicon-based integrated circuits, which enabled densely-integrated high-speed elec- tronics operating up to more than 100 GHz with low fabrication cost. To further enhance system integrability, it is required to implement all wireless system compo- nents on the chip. Presently, the last major barrier to true System-on-Chip (SoC) realization is the antenna implementation on the silicon chip. Although at mm-wave frequencies the antenna size becomes small enough to fit on chip, the antenna performance is greatly deteriorated due the high conductivity and high relative permittivity of the silicon substrate. The negative e↵ects of the silicon substrate could be avoided by using a metallic reflecting surface on top of silicon, which e↵ectively isolates the antenna from the silicon. However, this approach has the shortcoming of having to implement the antenna on the usually very thin silicon oxide layer of a typical CMOS fabrication process (10’s of μm). This forces the antenna to be in a very close proximity (less than one hundredth of a wavelength) to the reflecting surface. In this regime, the use of conventional metallic reflecting surface for silicon shielding has severe e↵ects on the antenna performance as it tends to reduce the antenna radiation resistance resulting in most of the energy being absorbed rather than radiated. In this work, the use of specially patterned reflecting surfaces for improving on- chip antenna performance is investigated. By using a periodic metallic surface on top of a grounded substrate, the structure can mimic the behavior of a perfect mag- netic conductor, hence called Artificial Magnetic Conductor (AMC) surface. Unlike conventional ground plane reflecting surfaces, AMC surfaces generally enhance the radiation and impedance characteristics of close-by antennas. Based on this property, a ring-based AMC reflecting surface has been designed in the oxide layer for on-chip antennas operating at 94 GHz. Furthermore, a folded dipole antenna with its associ- ated planar feeding structures has been optimized and integrated with the developed ring-based AMC surface. The proposed design is then fabricated at KAUST clean- room facilities. Prototype characterization showed very promising results with good correlation to simulations, with the antenna exhibiting an impedance bandwidth of 10% (90-100 GHz) and peak gain of -1.4 dBi, which is the highest gain reported for on-chip antennas at this frequency band without the use of any external o↵-chip components or post-fabrication steps. Advisors/Committee Members: Shamim, Atif (advisor), Salama, Khaled N. (committee member), Bagci, Hakan (committee member).

Subjects/Keywords: one-chip antenna; System-on-chip; artificla magnetic conductor; hight impedence surface; mm-wave

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Nafe, M. (2015). Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz. (Thesis). King Abdullah University of Science and Technology. Retrieved from http://hdl.handle.net/10754/565638

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Nafe, Mahmoud. “Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz.” 2015. Thesis, King Abdullah University of Science and Technology. Accessed March 07, 2021. http://hdl.handle.net/10754/565638.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Nafe, Mahmoud. “Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz.” 2015. Web. 07 Mar 2021.

Vancouver:

Nafe M. Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz. [Internet] [Thesis]. King Abdullah University of Science and Technology; 2015. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10754/565638.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nafe M. Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz. [Thesis]. King Abdullah University of Science and Technology; 2015. Available from: http://hdl.handle.net/10754/565638

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

28. Basavaraj, T. NoC Design & Optimization of Multicore Media Processors.

Degree: PhD, Faculty of Engineering, 2018, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/3296

► Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of… (more)

▼ Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of designing large chips by decoupling computation from communication. SoCs and CMPs have a multiplicity of communicating entities like programmable processing elements, hardware acceleration engines, memory blocks as well as off-chip interfaces. With power having become a serious design constraint[5], there is a great need for designing NoC which meets the target communication requirements, while minimizing power using all the tricks available at the architecture, microarchitecture and circuit levels of the de-sign. This thesis presents a holistic, QoS based, power optimal design solution of a NoC inside a CMP taking into account link microarchitecture and processor tile configurations. Guaranteeing QoS by NoCs involves guaranteeing bandwidth and throughput for connections and deterministic latencies in communication paths. Label Switching based Network-on-Chip(LS-NoC) uses a centralized LS-NoC Management framework that engineers traffic into QoS guaranteed routes. LS-NoC uses label switching, enables band-width reservation, allows physical link sharing and leverages advantages of both packet and circuit switching techniques. A flow identification algorithm takes into account band-width available in individual links to establish QoS guaranteed routes. LS-NoC caters to the requirements of streaming applications where communication channels are fixed over the lifetime of the application. The proposed NoC framework inherently supports heterogeneous and ad-hoc SoC designs. A multicast, broadcast capable label switched router for the LS-NoC has been de-signed, verified, synthesized, placed and routed and timing analyzed. A 5 port, 256 bit data bus, 4 bit label router occupies 0.431 mm2 in 130nm and delivers peak band-width of80Gbits/s per link at312.5MHz. LS Router is estimated to consume 43.08 mW. Bandwidth and latency guarantees of LS-NoC have been demonstrated on streaming applications like Hiper LAN/2 and Object Recognition Processor, Constant Bit Rate traffic patterns and video decoder traﬃc representing Variable Bit Rate traffic. LS-NoC was found to have a competitive figure of merit with state-of-the-art NoCs providing QoS. We envision the use of LS-NoC in general purpose CMPs where applications demand deterministic latencies and hard bandwidth requirements. Design variables for interconnect exploration include wire width, wire spacing, repeater size and spacing, degree of pipelining, supply, threshold voltage, activity and coupling factors. An optimal link configuration in terms of number of pipeline stages for a given length of link and desired operating frequency is arrived at. Optimal configurations of all links in the NoC are identified and a power-performance optimal NoC is presented. We presents a latency, power and performance trade-off study of NoCs using link microarchitecture exploration. The design and implementation of a… Advisors/Committee Members: Amrutur, Bharadwaj (advisor).

Subjects/Keywords: Network-On-Chip (NOC); Quality of Service (QOS); Label Switched Network On Chip (LS-NoC); Chip Multiprocessor Designs; Multicore Media Processors; Network-On-Chip (NOC) - Design and Construction; System on Chip (SoC); Link Microarchitectural Exploration, Network-on-Chip (NOC); Tile Exploration - Chip Multiprocessors (CMP); Ford-Fulkerson’s MaxFlow Algorithm; Flow Algorithm; Network-on-Chips; On-Chip Interconnection Networks; Microarchitecture Exploration; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Basavaraj, T. (2018). NoC Design & Optimization of Multicore Media Processors. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3296

Chicago Manual of Style (16^th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed March 07, 2021. http://etd.iisc.ac.in/handle/2005/3296.

MLA Handbook (7^th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2018. Web. 07 Mar 2021.

Vancouver:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2021 Mar 07]. Available from: http://etd.iisc.ac.in/handle/2005/3296.

Council of Science Editors:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3296

University of California – Irvine

29. Sarma, Santanu. Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.

Degree: Computer Science, 2016, University of California – Irvine

URL: http://www.escholarship.org/uc/item/0578m1bz

► Embedded systems are increasingly seeing the need for self-awareness to operate autonomously in the face of uncertainty and unpredictability in the environment, the applications they… (more)

Subjects/Keywords: Computer science; Chemical engineering; Cyber-Physical-System-on-Chip; Multiprocessor System-on-Chip; On-chip Machine Learning; Predictive Models; Self-Aware SoC; Smart Embedded Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Sarma, S. (2016). Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/0578m1bz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Sarma, Santanu. “Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.” 2016. Thesis, University of California – Irvine. Accessed March 07, 2021. http://www.escholarship.org/uc/item/0578m1bz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Sarma, Santanu. “Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.” 2016. Web. 07 Mar 2021.

Vancouver:

Sarma S. Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform. [Internet] [Thesis]. University of California – Irvine; 2016. [cited 2021 Mar 07]. Available from: http://www.escholarship.org/uc/item/0578m1bz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sarma S. Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform. [Thesis]. University of California – Irvine; 2016. Available from: http://www.escholarship.org/uc/item/0578m1bz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade do Rio Grande do Norte

30. Araújo, Sílvio Roberto Fernandes de. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .

Degree: 2012, Universidade do Rio Grande do Norte

URL: http://repositorio.ufrn.br/handle/123456789/17948

► It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features… (more)

▼ It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it Advisors/Committee Members: Silva, Ivan Saraiva (advisor), CPF:43728090425 (advisor), http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2 (advisor).

Subjects/Keywords: Multiprocessador em chip; MPSoC; Redes em chip; NoC; Algoritmo spiral complement; Sistema IPNoSys; Multiprocessor on chip; MPSoC; Network-on-chip; NoC; Spiral complement algorithm; IPNoSys system

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Araújo, S. R. F. d. (2012). Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Thesis, Universidade do Rio Grande do Norte. Accessed March 07, 2021. http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Web. 07 Mar 2021.

Vancouver:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2012. [cited 2021 Mar 07]. Available from: http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Thesis]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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Open Access Theses and Dissertations