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You searched for subject:(System on chip). Showing records 1 – 30 of 340 total matches.

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University of Manitoba

1. Cook, Darcy Philip. A multiprocessng system-on-chip framework targeting stream-oriented applications.

Degree: Electrical and Computer Engineering, 2011, University of Manitoba

 Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be… (more)

Subjects/Keywords: system-on-chip; multiprocessing

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APA (6th Edition):

Cook, D. P. (2011). A multiprocessng system-on-chip framework targeting stream-oriented applications. (Masters Thesis). University of Manitoba. Retrieved from http://hdl.handle.net/1993/4383

Chicago Manual of Style (16th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Masters Thesis, University of Manitoba. Accessed March 07, 2021. http://hdl.handle.net/1993/4383.

MLA Handbook (7th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Web. 07 Mar 2021.

Vancouver:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Internet] [Masters thesis]. University of Manitoba; 2011. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1993/4383.

Council of Science Editors:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Masters Thesis]. University of Manitoba; 2011. Available from: http://hdl.handle.net/1993/4383


Texas A&M University

2. Malave-Bonet, Javier. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.

Degree: MS, Computer Engineering, 2012, Texas A&M University

 Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused… (more)

Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C

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APA (6th Edition):

Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Chicago Manual of Style (16th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Masters Thesis, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

MLA Handbook (7th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 07 Mar 2021.

Vancouver:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Council of Science Editors:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

3. Magnos Roberto Pizzoni. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.

Degree: 2010, Universidade do Vale do Itajaí

Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos… (more)

Subjects/Keywords: System-on-Chip; Network-on-Chip; Avaliação de desempenho; CIENCIA DA COMPUTACAO; Circuitos integrados; System-on-Chip; Network-on-Chip; Performance

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APA (6th Edition):

Pizzoni, M. R. (2010). PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Thesis, Universidade do Vale do Itajaí. Accessed March 07, 2021. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Web. 07 Mar 2021.

Vancouver:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2010. [cited 2021 Mar 07]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Thesis]. Universidade do Vale do Itajaí; 2010. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

4. Saravanakumar U. An investigation on macro and micro Architectures for network on chip;.

Degree: An investigation on macro and micro Architectures for network on chip, 2015, Anna University

As the technology scales down more processors or Processing newlineElements PEs are integrated in the same die and such technology is called as newlineMultiprocessor System(more)

Subjects/Keywords: Microarchitectural aims; Multiprocessor System on Chip; Network on Chip

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APA (6th Edition):

U, S. (2015). An investigation on macro and micro Architectures for network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Thesis, Anna University. Accessed March 07, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Web. 07 Mar 2021.

Vancouver:

U S. An investigation on macro and micro Architectures for network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 07]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

U S. An investigation on macro and micro Architectures for network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Viswanathan N. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.

Degree: Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters, 2015, Anna University

Three dimensional integration is one of the emerging techniques newlineto find solution for the global interconnect delay challenges faced in the newlineadvanced VLSI ULSI technology… (more)

Subjects/Keywords: Network on Chip; System on Chip; Through Silicon Via

Page 1

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APA (6th Edition):

N, V. (2015). Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Thesis, Anna University. Accessed March 07, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Web. 07 Mar 2021.

Vancouver:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 07]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

6. Maheswari M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;.

Degree: Novel approaches in the design of Reliable custom topology for Application specific network on chip, 2015, Anna University

Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed… (more)

Subjects/Keywords: Digital Signal Processor; Intellectual Property; Networks on Chip; System on Chip

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APA (6th Edition):

M, M. (2015). Novel approaches in the design of Reliable custom topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/39199

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed March 07, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/39199.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Web. 07 Mar 2021.

Vancouver:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 07]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

7. Maheswari M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;.

Degree: Novel approaches in the design of Reliable custom topology for Application specific network on chip, 2015, Anna University

Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed… (more)

Subjects/Keywords: Digital Signal Processor; Networks on Chip; System on Chip

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APA (6th Edition):

M, M. (2015). Novel approaches in the design of Reliable custom topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/41574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed March 07, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/41574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Web. 07 Mar 2021.

Vancouver:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 07]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

8. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: PhD, Computer Engineering, 2012, Texas A&M University

 With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

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APA (6th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Chicago Manual of Style (16th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Doctoral Dissertation, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

MLA Handbook (7th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 07 Mar 2021.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526


University of New South Wales

9. Hussain, Mubashir. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.

Degree: Computer Science & Engineering, 2018, University of New South Wales

 Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system(more)

Subjects/Keywords: System-on-Chip; Hardware Trojan; Network-on-Chip; Hardware Security

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APA (6th Edition):

Hussain, M. (2018). Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Doctoral Dissertation, University of New South Wales. Accessed March 07, 2021. http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

MLA Handbook (7th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Web. 07 Mar 2021.

Vancouver:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2021 Mar 07]. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

Council of Science Editors:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true


University of Victoria

10. Shiran, Vahid. Design and optimization of terahertz waveguides with low loss and dispersion.

Degree: Department of Electrical and Computer Engineering, 2020, University of Victoria

 Electromagnetic waves in the terahertz spectral range have gained significant research focus due to their applications in various fields of science. To effectively generate and… (more)

Subjects/Keywords: Terahertz waveguide; On-chip-system; Low loss

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APA (6th Edition):

Shiran, V. (2020). Design and optimization of terahertz waveguides with low loss and dispersion. (Masters Thesis). University of Victoria. Retrieved from http://hdl.handle.net/1828/12090

Chicago Manual of Style (16th Edition):

Shiran, Vahid. “Design and optimization of terahertz waveguides with low loss and dispersion.” 2020. Masters Thesis, University of Victoria. Accessed March 07, 2021. http://hdl.handle.net/1828/12090.

MLA Handbook (7th Edition):

Shiran, Vahid. “Design and optimization of terahertz waveguides with low loss and dispersion.” 2020. Web. 07 Mar 2021.

Vancouver:

Shiran V. Design and optimization of terahertz waveguides with low loss and dispersion. [Internet] [Masters thesis]. University of Victoria; 2020. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1828/12090.

Council of Science Editors:

Shiran V. Design and optimization of terahertz waveguides with low loss and dispersion. [Masters Thesis]. University of Victoria; 2020. Available from: http://hdl.handle.net/1828/12090


Texas A&M University

11. Dollie, Patrick Kofi Mensah. Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique.

Degree: MS, Electrical Engineering, 2018, Texas A&M University

 The concept full chip integration of circuits has gained traction over the years with the push towards system-on-chip (SoC) designs which serve the niche for… (more)

Subjects/Keywords: system-on-chip; low dropout regulator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dollie, P. K. M. (2018). Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/174653

Chicago Manual of Style (16th Edition):

Dollie, Patrick Kofi Mensah. “Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique.” 2018. Masters Thesis, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/174653.

MLA Handbook (7th Edition):

Dollie, Patrick Kofi Mensah. “Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique.” 2018. Web. 07 Mar 2021.

Vancouver:

Dollie PKM. Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/174653.

Council of Science Editors:

Dollie PKM. Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/174653

12. Tulasidas, Sivanesan. Secure expandable communication framework for POCT system development and deployment.

Degree: PhD, 2018, Brunel University

 Health-care delivery in developing countries has many challenges because they do not have enough resources for meeting the healthcare needs and they lack testing lab… (more)

Subjects/Keywords: 621.381; Lab on chip system development

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APA (6th Edition):

Tulasidas, S. (2018). Secure expandable communication framework for POCT system development and deployment. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056

Chicago Manual of Style (16th Edition):

Tulasidas, Sivanesan. “Secure expandable communication framework for POCT system development and deployment.” 2018. Doctoral Dissertation, Brunel University. Accessed March 07, 2021. http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056.

MLA Handbook (7th Edition):

Tulasidas, Sivanesan. “Secure expandable communication framework for POCT system development and deployment.” 2018. Web. 07 Mar 2021.

Vancouver:

Tulasidas S. Secure expandable communication framework for POCT system development and deployment. [Internet] [Doctoral dissertation]. Brunel University; 2018. [cited 2021 Mar 07]. Available from: http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056.

Council of Science Editors:

Tulasidas S. Secure expandable communication framework for POCT system development and deployment. [Doctoral Dissertation]. Brunel University; 2018. Available from: http://bura.brunel.ac.uk/handle/2438/17132 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.765056


University of Utah

13. You, Junbok. Design and optimization of asynchronous network-on-chip.

Degree: PhD, Electrical & Computer Engineering, 2011, University of Utah

 The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on… (more)

Subjects/Keywords: Asynchronous circuit design; Digital VLSI design; Interconnect system; Network-on-chip; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

You, J. (2011). Design and optimization of asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633

Chicago Manual of Style (16th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed March 07, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

MLA Handbook (7th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Web. 07 Mar 2021.

Vancouver:

You J. Design and optimization of asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2021 Mar 07]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

Council of Science Editors:

You J. Design and optimization of asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633


Texas A&M University

14. Jeong, Sehoon. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.

Degree: PhD, Biomedical Engineering, 2018, Texas A&M University

 Neurological diseases are a major challenge to reach new therapies. However, physiological signals that regulate neurodegeneration in the central nervous system (CNS) are still little… (more)

Subjects/Keywords: Brain organ-on-a-chip; Microfluidic blood-brain barrier-on-a-chip; Neuroinflammation-on-a-chip; Drug screening system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jeong, S. (2018). Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173360

Chicago Manual of Style (16th Edition):

Jeong, Sehoon. “Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.” 2018. Doctoral Dissertation, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/173360.

MLA Handbook (7th Edition):

Jeong, Sehoon. “Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.” 2018. Web. 07 Mar 2021.

Vancouver:

Jeong S. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. [Internet] [Doctoral dissertation]. Texas A&M University; 2018. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/173360.

Council of Science Editors:

Jeong S. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. [Doctoral Dissertation]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173360

15. Papastefanakis, Ermis. Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC).

Degree: Docteur es, Informatique, 2017, Université Paris-Est

 L'évolution de Systems-on-Chip (SoCs) est rapide et le nombre des processeurs augmente conduisant à la transition des les plates-formes Multi-core vers les Manycore. Dans telles… (more)

Subjects/Keywords: Network on Chip; System on Chip; Architectures embarquées; Qualité de service; Criticalité mixte; Network on Chip; System on Chip; Embedded architectures; Quality of service; Mixed criticality

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Papastefanakis, E. (2017). Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC). (Doctoral Dissertation). Université Paris-Est. Retrieved from http://www.theses.fr/2017PESC1137

Chicago Manual of Style (16th Edition):

Papastefanakis, Ermis. “Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC).” 2017. Doctoral Dissertation, Université Paris-Est. Accessed March 07, 2021. http://www.theses.fr/2017PESC1137.

MLA Handbook (7th Edition):

Papastefanakis, Ermis. “Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC).” 2017. Web. 07 Mar 2021.

Vancouver:

Papastefanakis E. Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC). [Internet] [Doctoral dissertation]. Université Paris-Est; 2017. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2017PESC1137.

Council of Science Editors:

Papastefanakis E. Design and quality of service of mixed criticality systems in embedded architectures based on Network-on-Chip (NoC) : Dimensionnement et Qualité de Service pour les systèmes à criticité mixte dans les architectures embarquées à base de Network on Chip (NoC). [Doctoral Dissertation]. Université Paris-Est; 2017. Available from: http://www.theses.fr/2017PESC1137


Universidade do Rio Grande do Sul

16. Reinbrecht, Cezar Rodolfo Wedig. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.

Degree: 2012, Universidade do Rio Grande do Sul

Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas… (more)

Subjects/Keywords: Microeletrônica; MPSoCs; Network-on-chip; Sistemas embarcados; MPSoC; Interconnections; Adaptive architecture; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Reinbrecht, C. R. W. (2012). Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/67148

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reinbrecht, Cezar Rodolfo Wedig. “Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed March 07, 2021. http://hdl.handle.net/10183/67148.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reinbrecht, Cezar Rodolfo Wedig. “Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.” 2012. Web. 07 Mar 2021.

Vancouver:

Reinbrecht CRW. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10183/67148.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reinbrecht CRW. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/67148

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

17. Gebhardt, Daniel J. Energy-efficient design of an asynchronous network-on-chip.

Degree: PhD, Computer Science, 2011, University of Utah

 Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are… (more)

Subjects/Keywords: Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gebhardt, D. J. (2011). Energy-efficient design of an asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Chicago Manual of Style (16th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed March 07, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

MLA Handbook (7th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Web. 07 Mar 2021.

Vancouver:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2021 Mar 07]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

Council of Science Editors:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871


Washington State University

18. [No author]. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .

Degree: 2017, Washington State University

 In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and… (more)

Subjects/Keywords: Computer engineering; Big Data; Graph Analytics; MapReduce; Network-on-Chip; System-on-Chip; Wireless NoC

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APA (6th Edition):

author], [. (2017). COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/13038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .” 2017. Thesis, Washington State University. Accessed March 07, 2021. http://hdl.handle.net/2376/13038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .” 2017. Web. 07 Mar 2021.

Vancouver:

author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . [Internet] [Thesis]. Washington State University; 2017. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/2376/13038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . [Thesis]. Washington State University; 2017. Available from: http://hdl.handle.net/2376/13038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

19. Yang, Yoon Seok. Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design.

Degree: PhD, Computer Engineering, 2012, Texas A&M University

 This dissertation presents three design solutions to support several key system-on-chip (SoC) issues to achieve low-power and high performance. These are: 1) joint source and… (more)

Subjects/Keywords: accelerator; digital signal processing; low-latency; network-on-chip; low-power; system-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, Y. S. (2012). Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/191999

Chicago Manual of Style (16th Edition):

Yang, Yoon Seok. “Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design.” 2012. Doctoral Dissertation, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/191999.

MLA Handbook (7th Edition):

Yang, Yoon Seok. “Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design.” 2012. Web. 07 Mar 2021.

Vancouver:

Yang YS. Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/191999.

Council of Science Editors:

Yang YS. Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/191999


Oklahoma State University

20. Williams, Seth Adam. Benchmarking ARM-based Application Integrated Systems.

Degree: School of Electrical & Computer Engineering, 2011, Oklahoma State University

 ARM Holding Ltd. is in a very good position; by owning a very prolific instruction set architecture (named ARM) and licensing it to other companies… (more)

Subjects/Keywords: arm; embedded benchmarks; package-on-package; system-on-chip

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APA (6th Edition):

Williams, S. A. (2011). Benchmarking ARM-based Application Integrated Systems. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/10295

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Thesis, Oklahoma State University. Accessed March 07, 2021. http://hdl.handle.net/11244/10295.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Web. 07 Mar 2021.

Vancouver:

Williams SA. Benchmarking ARM-based Application Integrated Systems. [Internet] [Thesis]. Oklahoma State University; 2011. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/11244/10295.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Williams SA. Benchmarking ARM-based Application Integrated Systems. [Thesis]. Oklahoma State University; 2011. Available from: http://hdl.handle.net/11244/10295

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Psarras, Anastasios. High-performance networks-on-chip.

Degree: 2017, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ)

 Over the last two decades, we have witnessed a fundamental paradigm shift in digital system design: the transition to the multi-core realm. Naturally, the multi-core… (more)

Subjects/Keywords: Δίκτυα σε Ολοκληρωμένα Κυκλώματα; Ολοκληρωμένα κυκλώματα; Πολυπύρηνοι επεξεργαστές; Συστήματα σε Ολοκληρωμένα Κυκλώματα; Networks-on-Chip; VLSI; Multi-core architectures; Chip Multi-Processors; System-on-chip; On-chip Interconnection Networks

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APA (6th Edition):

Psarras, A. (2017). High-performance networks-on-chip. (Thesis). Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Retrieved from http://hdl.handle.net/10442/hedi/41266

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Psarras, Anastasios. “High-performance networks-on-chip.” 2017. Thesis, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Accessed March 07, 2021. http://hdl.handle.net/10442/hedi/41266.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Psarras, Anastasios. “High-performance networks-on-chip.” 2017. Web. 07 Mar 2021.

Vancouver:

Psarras A. High-performance networks-on-chip. [Internet] [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2017. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10442/hedi/41266.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Psarras A. High-performance networks-on-chip. [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2017. Available from: http://hdl.handle.net/10442/hedi/41266

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

22. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: MSc Engg, Faculty of Engineering, 2011, Indian Institute of Science

 A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vikas, G. (2011). Power Optimal Network-On-Chip Interconnect Design. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/1408

Chicago Manual of Style (16th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2011. Masters Thesis, Indian Institute of Science. Accessed March 07, 2021. http://etd.iisc.ac.in/handle/2005/1408.

MLA Handbook (7th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2011. Web. 07 Mar 2021.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Masters thesis]. Indian Institute of Science; 2011. [cited 2021 Mar 07]. Available from: http://etd.iisc.ac.in/handle/2005/1408.

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Masters Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ac.in/handle/2005/1408


Universidade do Rio Grande do Norte

23. Araújo, Sílvio Roberto Fernandes de. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .

Degree: 2008, Universidade do Rio Grande do Norte

 The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the… (more)

Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Thesis, Universidade do Rio Grande do Norte. Accessed March 07, 2021. http://repositorio.ufrn.br/handle/123456789/17969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Web. 07 Mar 2021.

Vancouver:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2008. [cited 2021 Mar 07]. Available from: http://repositorio.ufrn.br/handle/123456789/17969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Thesis]. Universidade do Rio Grande do Norte; 2008. Available from: http://repositorio.ufrn.br/handle/123456789/17969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Sílvio Roberto Fernandes de Araújo. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.

Degree: 2008, Universidade Federal do Rio Grande do Norte

O aumento na capacidade de integração de transistores permitiu o desenvolvimento de sistemas completos, com inúmeros componentes, dentro de um único chip, são os chamados… (more)

Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; SISTEMAS DE COMPUTACAO; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system

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APA (6th Edition):

Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. (Thesis). Universidade Federal do Rio Grande do Norte. Retrieved from http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.” 2008. Thesis, Universidade Federal do Rio Grande do Norte. Accessed March 07, 2021. http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.” 2008. Web. 07 Mar 2021.

Vancouver:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. [Internet] [Thesis]. Universidade Federal do Rio Grande do Norte; 2008. [cited 2021 Mar 07]. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. [Thesis]. Universidade Federal do Rio Grande do Norte; 2008. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

25. Araújo, Sílvio Roberto Fernandes de. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .

Degree: 2008, Universidade do Rio Grande do Norte

 The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the… (more)

Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17969

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Masters Thesis, Universidade do Rio Grande do Norte. Accessed March 07, 2021. http://repositorio.ufrn.br/handle/123456789/17969.

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Web. 07 Mar 2021.

Vancouver:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2008. [cited 2021 Mar 07]. Available from: http://repositorio.ufrn.br/handle/123456789/17969.

Council of Science Editors:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Masters Thesis]. Universidade do Rio Grande do Norte; 2008. Available from: http://repositorio.ufrn.br/handle/123456789/17969


Universidade do Rio Grande do Sul

26. Briao, Eduardo Wenzel. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.

Degree: 2008, Universidade do Rio Grande do Sul

A complexidade no projeto de sistemas eletrônicos tem aumentado devido à evolução tecnológica e permite a concepção de sistemas inteiros em um único chip (SoCs… (more)

Subjects/Keywords: Embedded systems; Microeletrônica; Design space exploration; Network-on-chip; Systemon- chip; Distributed system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Briao, E. W. (2008). Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/13157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Briao, Eduardo Wenzel. “Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed March 07, 2021. http://hdl.handle.net/10183/13157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Briao, Eduardo Wenzel. “Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip.” 2008. Web. 07 Mar 2021.

Vancouver:

Briao EW. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10183/13157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Briao EW. Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/13157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


King Abdullah University of Science and Technology

27. Nafe, Mahmoud. Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz.

Degree: Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division, 2015, King Abdullah University of Science and Technology

 Nowadays, there is a growing demand for high frequency-bandwidth mm-wave (30-300 GHz) electronic wireless transceiver systems to support applications such as high data-rate wireless communication… (more)

Subjects/Keywords: one-chip antenna; System-on-chip; artificla magnetic conductor; hight impedence surface; mm-wave

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nafe, M. (2015). Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz. (Thesis). King Abdullah University of Science and Technology. Retrieved from http://hdl.handle.net/10754/565638

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nafe, Mahmoud. “Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz.” 2015. Thesis, King Abdullah University of Science and Technology. Accessed March 07, 2021. http://hdl.handle.net/10754/565638.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nafe, Mahmoud. “Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz.” 2015. Web. 07 Mar 2021.

Vancouver:

Nafe M. Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz. [Internet] [Thesis]. King Abdullah University of Science and Technology; 2015. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10754/565638.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nafe M. Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz. [Thesis]. King Abdullah University of Science and Technology; 2015. Available from: http://hdl.handle.net/10754/565638

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

28. Basavaraj, T. NoC Design & Optimization of Multicore Media Processors.

Degree: PhD, Faculty of Engineering, 2018, Indian Institute of Science

 Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of… (more)

Subjects/Keywords: Network-On-Chip (NOC); Quality of Service (QOS); Label Switched Network On Chip (LS-NoC); Chip Multiprocessor Designs; Multicore Media Processors; Network-On-Chip (NOC) - Design and Construction; System on Chip (SoC); Link Microarchitectural Exploration, Network-on-Chip (NOC); Tile Exploration - Chip Multiprocessors (CMP); Ford-Fulkerson’s MaxFlow Algorithm; Flow Algorithm; Network-on-Chips; On-Chip Interconnection Networks; Microarchitecture Exploration; Computer Science

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APA (6th Edition):

Basavaraj, T. (2018). NoC Design & Optimization of Multicore Media Processors. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3296

Chicago Manual of Style (16th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed March 07, 2021. http://etd.iisc.ac.in/handle/2005/3296.

MLA Handbook (7th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2018. Web. 07 Mar 2021.

Vancouver:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2021 Mar 07]. Available from: http://etd.iisc.ac.in/handle/2005/3296.

Council of Science Editors:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3296


University of California – Irvine

29. Sarma, Santanu. Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.

Degree: Computer Science, 2016, University of California – Irvine

 Embedded systems are increasingly seeing the need for self-awareness to operate autonomously in the face of uncertainty and unpredictability in the environment, the applications they… (more)

Subjects/Keywords: Computer science; Chemical engineering; Cyber-Physical-System-on-Chip; Multiprocessor System-on-Chip; On-chip Machine Learning; Predictive Models; Self-Aware SoC; Smart Embedded Systems

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APA (6th Edition):

Sarma, S. (2016). Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/0578m1bz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sarma, Santanu. “Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.” 2016. Thesis, University of California – Irvine. Accessed March 07, 2021. http://www.escholarship.org/uc/item/0578m1bz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sarma, Santanu. “Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.” 2016. Web. 07 Mar 2021.

Vancouver:

Sarma S. Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform. [Internet] [Thesis]. University of California – Irvine; 2016. [cited 2021 Mar 07]. Available from: http://www.escholarship.org/uc/item/0578m1bz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sarma S. Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform. [Thesis]. University of California – Irvine; 2016. Available from: http://www.escholarship.org/uc/item/0578m1bz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

30. Araújo, Sílvio Roberto Fernandes de. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .

Degree: 2012, Universidade do Rio Grande do Norte

 It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features… (more)

Subjects/Keywords: Multiprocessador em chip; MPSoC; Redes em chip; NoC; Algoritmo spiral complement; Sistema IPNoSys; Multiprocessor on chip; MPSoC; Network-on-chip; NoC; Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2012). Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Thesis, Universidade do Rio Grande do Norte. Accessed March 07, 2021. http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Web. 07 Mar 2021.

Vancouver:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2012. [cited 2021 Mar 07]. Available from: http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Thesis]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [12]

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