subject:(System on a chip)

Texas A&M University

1. Jeong, Sehoon. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.

Degree: PhD, Biomedical Engineering, 2018, Texas A&M University

URL: http://hdl.handle.net/1969.1/173360

► Neurological diseases are a major challenge to reach new therapies. However, physiological signals that regulate neurodegeneration in the central nervous system (CNS) are still little… (more)

▼ Neurological diseases are a major challenge to reach new therapies. However, physiological signals that regulate neurodegeneration in the central nervous system (CNS) are still little known since there is no suitable in vitro model for studying the basis of localized cells and molecules. Here this dissertation presents the development of biomimetic microsystems that reconstitute neurophysiologically important functional brain and neurovascular interface in the CNS. The brain organs-on-chips can recapitulate pharmacological responses and complex interactions between different types of cells that are mediated by the extracellular matrix and intercellular junctions within the organ model. Since the developed microsystems have a biomimetic tissue structure, it is possible to more accurately function and simulate the delivery and penetration of the drug compound in vivo than the 2D cell monolayer in the conventional culture model or the prior microfluidics. The developed brain chip is composed of four culture chambers with 10 aggregate traps and multi-electrode arrays enable electrical stimulation for 40 neuronal aggregates as well as drug stimulation. Uniform 150 μm aggregates from the microwell can be cultured for 4 weeks. This system developed for the study of CNS myelin formation showed that the 10Hz of electrical stimulation for the promotion of myelination was successfully confirmed with 500 nM retinoic acid treatment results in the automatic image analysis. iii The other developed blood-brain barrier (BBB) chip consists of 4 × 4 microfluidic channel arrays and 16 channel multi-electrode arrays, able to electrically analyze 16 sites. Co-culture BBB-on-a-chip contains neurovascular endothelium separated from primary astrocyte by a porous membrane that allows cell-cell interactions through the membrane. In this platform, the effects of astrocyte-coculture, extracellular matrix, and in vivo shear stress level on barrier permeability were characterized through TEER measurements and dextran permeability assays. Also, despite the presence of BBB, monocyte infiltration into the CNS was observed by monocyte chemotactic protein (CCL2), which corresponds to the early event of brain injury. Finally, the system developed to address these pharmacological problems for drug development showed how drugs work in brain vessels (histamine) and brain tissues (tetrodotoxin), as well as delivering drugs from brain vessels to brain tissue (atenolol). Advisors/Committee Members: Han, Arum (advisor), Li, Jianrong (advisor), McShane, Mike (committee member), Gaharwar, Akhilesh (committee member).

Subjects/Keywords: Brain organ-on-a-chip; Microfluidic blood-brain barrier-on-a-chip; Neuroinflammation-on-a-chip; Drug screening system

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APA (6^th Edition):

Jeong, S. (2018). Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173360

Chicago Manual of Style (16^th Edition):

Jeong, Sehoon. “Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.” 2018. Doctoral Dissertation, Texas A&M University. Accessed March 05, 2021. http://hdl.handle.net/1969.1/173360.

MLA Handbook (7^th Edition):

Jeong, Sehoon. “Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.” 2018. Web. 05 Mar 2021.

Vancouver:

Jeong S. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. [Internet] [Doctoral dissertation]. Texas A&M University; 2018. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1969.1/173360.

Council of Science Editors:

Jeong S. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. [Doctoral Dissertation]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173360

Texas Tech University

2. Eravelli, Shruti. Multi-generational test plan generation and execution in advanced mixed signal controllers.

Degree: Electrical and Computer Engineering, 2011, Texas Tech University

URL: http://hdl.handle.net/2346/ETD-TTU-2011-05-1291

► Most integrated circuits are evolutionary. This is especially true in the realm of system-on-a-chip (SoC) devices that combine multiple functions monolithically. Electronic systems that begin… (more)

Subjects/Keywords: Characterization; Testing; System-on-a-chip; Performance; Motherboard; Daughter board

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APA (6^th Edition):

Eravelli, S. (2011). Multi-generational test plan generation and execution in advanced mixed signal controllers. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/ETD-TTU-2011-05-1291

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Eravelli, Shruti. “Multi-generational test plan generation and execution in advanced mixed signal controllers.” 2011. Thesis, Texas Tech University. Accessed March 05, 2021. http://hdl.handle.net/2346/ETD-TTU-2011-05-1291.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Eravelli, Shruti. “Multi-generational test plan generation and execution in advanced mixed signal controllers.” 2011. Web. 05 Mar 2021.

Vancouver:

Eravelli S. Multi-generational test plan generation and execution in advanced mixed signal controllers. [Internet] [Thesis]. Texas Tech University; 2011. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2346/ETD-TTU-2011-05-1291.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Eravelli S. Multi-generational test plan generation and execution in advanced mixed signal controllers. [Thesis]. Texas Tech University; 2011. Available from: http://hdl.handle.net/2346/ETD-TTU-2011-05-1291

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Ryerson University

3. Tino, Anita. Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures.

Degree: 2011, Ryerson University

URL: https://digital.library.ryerson.ca/islandora/object/RULA%3A1213

► Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works… (more)

Subjects/Keywords: Networks on a chip – Design; Networks on a chip – Mathematical models; Networks on a chip; Systems on a chip – Design; Systems on a chip – Mathematical models; Systems on a chip

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APA (6^th Edition):

Tino, A. (2011). Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tino, Anita. “Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures.” 2011. Thesis, Ryerson University. Accessed March 05, 2021. https://digital.library.ryerson.ca/islandora/object/RULA%3A1213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tino, Anita. “Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures.” 2011. Web. 05 Mar 2021.

Vancouver:

Tino A. Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures. [Internet] [Thesis]. Ryerson University; 2011. [cited 2021 Mar 05]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tino A. Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures. [Thesis]. Ryerson University; 2011. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Manitoba

4. Cook, Darcy Philip. A multiprocessng system-on-chip framework targeting stream-oriented applications.

Degree: Electrical and Computer Engineering, 2011, University of Manitoba

URL: http://hdl.handle.net/1993/4383

► Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be… (more)

Subjects/Keywords: system-on-chip; multiprocessing

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APA (6^th Edition):

Cook, D. P. (2011). A multiprocessng system-on-chip framework targeting stream-oriented applications. (Masters Thesis). University of Manitoba. Retrieved from http://hdl.handle.net/1993/4383

Chicago Manual of Style (16^th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Masters Thesis, University of Manitoba. Accessed March 05, 2021. http://hdl.handle.net/1993/4383.

MLA Handbook (7^th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Web. 05 Mar 2021.

Vancouver:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Internet] [Masters thesis]. University of Manitoba; 2011. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1993/4383.

Council of Science Editors:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Masters Thesis]. University of Manitoba; 2011. Available from: http://hdl.handle.net/1993/4383

Ryerson University

5. Gharan, Masoud Oveis. Virtual channel organization and arbitration for network on chip router architecure.

Degree: 2016, Ryerson University

URL: https://digital.library.ryerson.ca/islandora/object/RULA%3A5048

► The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the… (more)

▼ The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

Subjects/Keywords: Systems on a chip; Networks on a chip

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APA (6^th Edition):

Gharan, M. O. (2016). Virtual channel organization and arbitration for network on chip router architecure. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Gharan, Masoud Oveis. “Virtual channel organization and arbitration for network on chip router architecure.” 2016. Thesis, Ryerson University. Accessed March 05, 2021. https://digital.library.ryerson.ca/islandora/object/RULA%3A5048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Gharan, Masoud Oveis. “Virtual channel organization and arbitration for network on chip router architecure.” 2016. Web. 05 Mar 2021.

Vancouver:

Gharan MO. Virtual channel organization and arbitration for network on chip router architecure. [Internet] [Thesis]. Ryerson University; 2016. [cited 2021 Mar 05]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gharan MO. Virtual channel organization and arbitration for network on chip router architecure. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Hong Kong University of Science and Technology

6. Qian, Zhiliang. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.

Degree: 2014, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html

► With technology scaling down, hundreds and thousands processing elements (PEs) can be integrated on a single chip. Consequently, the embedded systems have led to the… (more)

▼ With technology scaling down, hundreds and thousands processing elements (PEs) can be integrated on a single chip. Consequently, the embedded systems have led to the advent of multi-core System-on-Chip (MPSoC) design and the high performance computer architectures have evolved into Chip Multi-processor (CMP) platforms. A scalable and modular solution to the interconnecting problem becomes critically important. Network-on-chip (NoC) has been proposed as an efficient solution to handle this distinctive challenge by providing efficient and scalable communication infrastructures among the on-chip resources. In this thesis, we have explored the high performance NoC design for MPSoC and CMP structures from the performance modeling in the offline design phase to the routing algorithm and NoC architecture optimization. More specifically, we first deal with the issue of how to estimate an NoC design fast and accurately in the synthesis inner loop. The simulation based evaluation method besides being slow, provides little insight to guide the optimization process of the NoC synthesis loop. Therefore, fast and accurate analytical models for NoC-based multicore performance evaluation are strongly desired to better explore the design space. For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations before the system is built or taped-out. Then, for high performance NoC designs, we tackle one of the most important problems, i.e., the routing algorithms design with different design constraints and objectives. For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs). For improving the reliability, a routing algorithm to achieve maximum performance under fault is proposed. Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization. In particular, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bi-directional channel, our proposed flit-level speedup scheme also allows flits within the same packet to be transmitted simultaneously on the bi-directional channel. We also propose a flexible NoC architecture which takes advantage of a dynamic distributed routing algorithm and improves the NoC communication performance with minimal energy overhead. This proposed NoC architecture exploits the self-reconfigurable bidirectional channels to increase the effective bandwidth and uses express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. From the simulation results on both synthetic traffic and real workload traces, significantly performance improvement in terms of latency and throughput can be achieved.

Subjects/Keywords: Systems on a chip ; Design and construction ; Networks on a chip

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APA (6^th Edition):

Qian, Z. (2014). High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Qian, Zhiliang. “High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed March 05, 2021. http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Qian, Zhiliang. “High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.” 2014. Web. 05 Mar 2021.

Vancouver:

Qian Z. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2021 Mar 05]. Available from: http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Qian Z. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

7. Chen, Tai-Feng. A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925

► Signature is an effective lossy compression method to reduce signal trace size at the possible cost of trace precision and implementation cost for different kinds… (more)

Subjects/Keywords: Multiple Signature Compaction Method; Signature Based Tracing Methodology; System-on-a-Chip(SoC)

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APA (6^th Edition):

Chen, T. (2016). A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Tai-Feng. “A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification.” 2016. Thesis, NSYSU. Accessed March 05, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Tai-Feng. “A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification.” 2016. Web. 05 Mar 2021.

Vancouver:

Chen T. A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Mar 05]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen T. A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Alberta

8. Ho, Sunny. VLSI Design and System Integration for a USB Genetic Amplification Platform.

Degree: MS, Department of Electrical and Computer Engineering, 2012, University of Alberta

URL: https://era.library.ualberta.ca/files/1544bp58m

► We demonstrate the feasibility of USB-powered portable genetic amplification. One of the central processes within medical or biological genetic methods is polymerase chain reaction (PCR).… (more)

Subjects/Keywords: lab-on-a-chip; VLSI; polymerase chain reaction; genetic amplification; microfluidic system; biomedical; USB

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APA (6^th Edition):

Ho, S. (2012). VLSI Design and System Integration for a USB Genetic Amplification Platform. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/1544bp58m

Chicago Manual of Style (16^th Edition):

Ho, Sunny. “VLSI Design and System Integration for a USB Genetic Amplification Platform.” 2012. Masters Thesis, University of Alberta. Accessed March 05, 2021. https://era.library.ualberta.ca/files/1544bp58m.

MLA Handbook (7^th Edition):

Ho, Sunny. “VLSI Design and System Integration for a USB Genetic Amplification Platform.” 2012. Web. 05 Mar 2021.

Vancouver:

Ho S. VLSI Design and System Integration for a USB Genetic Amplification Platform. [Internet] [Masters thesis]. University of Alberta; 2012. [cited 2021 Mar 05]. Available from: https://era.library.ualberta.ca/files/1544bp58m.

Council of Science Editors:

Ho S. VLSI Design and System Integration for a USB Genetic Amplification Platform. [Masters Thesis]. University of Alberta; 2012. Available from: https://era.library.ualberta.ca/files/1544bp58m

9. Lange, Hendrik. Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen.

Degree: 2007, Technische Universität Dortmund

URL: http://hdl.handle.net/2003/24853

► Die vorliegende Arbeit befasst sich mit Analysemethoden für grobgranulare rekonfigurierbare Prozessorarchitekturen. Es wird ein modellbasiertes Verfahren vorgestellt, mit dessen Hilfe derartige Hardwarestrukturen auf einfache Weise… (more)

Subjects/Keywords: Grobgranulare Architekturen; Prozessorarchitektur; Rekonfigurierbare Architekturen; System-on-a-Chip; VLSI-Eigenschaften; 620

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APA (6^th Edition):

Lange, H. (2007). Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen. (Thesis). Technische Universität Dortmund. Retrieved from http://hdl.handle.net/2003/24853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lange, Hendrik. “Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen.” 2007. Thesis, Technische Universität Dortmund. Accessed March 05, 2021. http://hdl.handle.net/2003/24853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lange, Hendrik. “Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen.” 2007. Web. 05 Mar 2021.

Vancouver:

Lange H. Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen. [Internet] [Thesis]. Technische Universität Dortmund; 2007. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2003/24853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lange H. Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen. [Thesis]. Technische Universität Dortmund; 2007. Available from: http://hdl.handle.net/2003/24853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toronto

10. Wong, Jeremy. Integration of Cellular Analysis Methods into Microphysiological Vascular Models.

Degree: PhD, 2020, University of Toronto

URL: http://hdl.handle.net/1807/100898

► Microphysiological systems, also known as organ-on-a-chip systems, possess significant potential as organotypic models of human tissues, including vascular tissue interfaces that are ubiquitous throughout the… (more)

▼ Microphysiological systems, also known as organ-on-a-chip systems, possess significant potential as organotypic models of human tissues, including vascular tissue interfaces that are ubiquitous throughout the human body. As microfluidic systems, organs-on-chips also possess significant untapped analytical potential. Cellular analysis in organs-on-chips, however, currently relies on standard methods designed for traditional in vitro cell culture vessels like microtiter plates. These methods disturb the cell culture environment, rely on multiple manual steps and are not designed to operate in small microfluidic volumes. The aim of this thesis was to design and develop online cellular analysis methods that are suitable for integration into the organotypic microenvironment of microvessel-on-a-chip models. Cellular analysis methods for cell secretion and barrier function monitoring were specifically considered. For integrated cell secretion monitoring, a numerical study correlated physiological shear flow to biosensor reaction kinetics in a microfluidic vascular model with online biosensing. Three critical parameters (critical shear stress, Peclet and Biot numbers) in conjunction with the numerical analysis enabled the minimization of biosensor response times while preserving physiological shear flows. For integrated barrier function monitoring, endothelial permeability was measured online in a Transwell-based microfluidic vascular model using a novel electrochemical permeability assay. Unlike the standard fluorescence-based permeability assay, this enabled endothelial permeability to be measured directly on-chip inside an incubator without the need for manual sampling, or bulky and costly optical instrumentation. Finally, the electrochemical permeability assay was implemented in a hydrogel-based microfluidic vascular model with gel-embedded electrodes. Online endothelial permeability measurements were performed in a 3D culture environment, demonstrating the ability of the assay to operate in the low volume organotypic microenvironments characteristic of microphysiological systems. The miniaturized electrochemical format is furthermore suitable for parallelization and higher throughput analysis. In summary, the integration of cellular analysis methods is critical to fulfilling the tremendous promise of microphysiological systems. The capability to perform multiparametric online analysis at the cellular level has the potential to set these systems apart from current models of the human organism. Advisors/Committee Members: Simmons, Craig, Biomedical Engineering.

Subjects/Keywords: biosensor; endothelial permeability; in vitro cell culture; integrated system; organ on a chip; TEER; 0541

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APA (6^th Edition):

Wong, J. (2020). Integration of Cellular Analysis Methods into Microphysiological Vascular Models. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/100898

Chicago Manual of Style (16^th Edition):

Wong, Jeremy. “Integration of Cellular Analysis Methods into Microphysiological Vascular Models.” 2020. Doctoral Dissertation, University of Toronto. Accessed March 05, 2021. http://hdl.handle.net/1807/100898.

MLA Handbook (7^th Edition):

Wong, Jeremy. “Integration of Cellular Analysis Methods into Microphysiological Vascular Models.” 2020. Web. 05 Mar 2021.

Vancouver:

Wong J. Integration of Cellular Analysis Methods into Microphysiological Vascular Models. [Internet] [Doctoral dissertation]. University of Toronto; 2020. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1807/100898.

Council of Science Editors:

Wong J. Integration of Cellular Analysis Methods into Microphysiological Vascular Models. [Doctoral Dissertation]. University of Toronto; 2020. Available from: http://hdl.handle.net/1807/100898

11. Hosic, Sanjin. Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier.

Degree: PhD, Department of Chemical Engineering, 2019, Northeastern University

URL: http://hdl.handle.net/2047/D20317949

► Two decades ago, it was demonstrated that electrical vagal nerve stimulation (VNS) inhibits gastrointestinal (GI) inflammation. In-vivo studies concluded that VNS inhibits GI inflammation by… (more)

▼ Two decades ago, it was demonstrated that electrical vagal nerve stimulation (VNS) inhibits gastrointestinal (GI) inflammation. In-vivo studies concluded that VNS inhibits GI inflammation by releasing neurotransmitter acetylcholine (ACh) from efferent vagus nerve fibers which binds intestinal macrophage nicotinic acetylcholine receptors (nAChRs), inhibiting pro-inflammatory cytokine tumor necrosis factor alpha (TNF-α) production. The next decade of research demonstrated that ACh activated intestinal epithelial cell (IEC) muscarinic acetylcholine receptors (mAChRs) to ameliorate epithelial barrier integrity. However, several contradictory studies were published. One plausible explanation for the discrepancies is differential mAChR expression and/or biological function between GI cell lines. Evidently, our cellular understanding of cholinergic regulation of the intestinal epithelium is in its infancy. Nevertheless, bioelectric medicine may potentially augment inflammatory bowel disease (IBD) treatment, warranting further investigation of cholinergic regulation of the intestinal epithelium. This research leveraged primary human organoids and microfluidics to develop physiologically relevant models for studying cholinergic regulation of intestinal epithelial barrier integrity. Primary human intestinal organoids were dissociated and seeded on Transwell inserts. The primary epithelium exhibited functional differences as compared to immortalized epithelium: increased barrier integrity, increased and polarized interleukin 8 (IL-8) secretion, and the presence of both absorptive enterocytes and secretory goblet cells. TNF-α was used to model an inflamed state exhibiting increased paracellular permeability, apoptosis, and basal IL-8 production. Quantitative immunofluorescent image segmentation and analysis demonstrated that TNF-α reduced epithelial integrity through both apoptosis and tight junction (TJ) rearrangement while epithelial cells adopted a distinct phenotype that sealed TJs. Though the primary epithelium expressed the previously implicated subtype M3 muscarinic receptor, neither nAChR nor mAChR activation inhibited TNF-α induced inflammation as previously described. However, maChR activation decreased transcellular transport of a 70 kDa dextran. Temporally resolved experiments confirmed that mAChR activation of primary epithelium does not augment the shedding of TNF receptor 1 (TNFR1) to attenuate TNF- α signaling as previously described. The results demonstrated a first application of primary human organoid technology toward studying cholinergic regulation of intestinal epithelial barrier integrity. Microfluidic cell culture devices, termed organ chips, lend advantages to traditional static Transwell culture. An organ chip manufacturing technique was developed, circumventing cost, throughput, and scalability disadvantages of traditional microfabrication. The technique was validated by culturing Caco-2 monolayers in a bi- layer architecture and by integrating primary monolayers and organoids in a novel tri- layer…

Subjects/Keywords: cholinergic; epithelium; microfluidic; microphysiological system; organoid; organ-on-a-chip; Bioengineering; Biomedical engineering; Cellular biology

11 more images…

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APA (6^th Edition):

Hosic, S. (2019). Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20317949

Chicago Manual of Style (16^th Edition):

Hosic, Sanjin. “Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier.” 2019. Doctoral Dissertation, Northeastern University. Accessed March 05, 2021. http://hdl.handle.net/2047/D20317949.

MLA Handbook (7^th Edition):

Hosic, Sanjin. “Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier.” 2019. Web. 05 Mar 2021.

Vancouver:

Hosic S. Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier. [Internet] [Doctoral dissertation]. Northeastern University; 2019. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2047/D20317949.

Council of Science Editors:

Hosic S. Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier. [Doctoral Dissertation]. Northeastern University; 2019. Available from: http://hdl.handle.net/2047/D20317949

12. Salman, Abbas Ali Abulwohab. Miniaturised system for DNA analysis.

Degree: PhD, 2013, Teesside University

URL: https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218

► The growing markets for analytical techniques in areas such as pathogen detection, clinical analysis, forensic investigation, environmental analysis and food analysis require the development of… (more)

▼ The growing markets for analytical techniques in areas such as pathogen detection, clinical analysis, forensic investigation, environmental analysis and food analysis require the development of devices with simultaneous high performance, speed, simplicity and low cost. Analysis of deoxyribonucleic acid (DNA) has been enhanced by use of the polymerase chain reaction (PCR) technique, which is now a widely used tool for in vitro amplification of nucleic acids. In this work, a miniaturised PCR system comprising a microfluidic PCR chip, novel heating method and fluorescence detection unit was developed. PCR chip with reactants were shunted along three temperature zones in a fine polycarbonate chip. The polycarbonate PCR chip was fabricated using milling and thermal fusion binding for sealing of the cover. Thermal-cycling within the microfluidic chip was achieved by programmable shunting of the chip between three double side temperature zones with different temperatures to accomplish the denaturation, annealing and elongation steps necessary for PCR amplification. This thermal-cycling model potentially improves PCR efficacy because it increases the ramping rates for heating and cooling the PCR mixture. The detection unit comprises a photo-detector and Light Emitting Diode (LED) as the source of excitation. The detection limit of the system was determined on the PCR chip using Fluorescein isothiocyanate (FITC) as a fluorophore dye. The detection limit achieved was 7.8 pg ml-1 or (19.7 pmol) of FITC. The chromosomal DNA used in this work was extracted from non-pathogenic K-12 subtype of Escherichia coli (E. coli). The investigations showed that the system was capable of performing PCR amplification with different annealing temperature ranging from 54 to 68 °C, targeting three different sizes of PCR products of 250, 552 and 1500 bp. The prototype thermal-cycler and PCR chip were used successfully to amplify the three sizes and the results were compared with same fragments amplified on a conventional PCR .thermal-cycler machine. The method used for comparison was gel electrophoresis. In addition, a fluorescence detection system was employed for detecting of PCR products using SYBR Green I fluorescent dye. The whole system allows for developments of low cost, easy to use and portable instruments.

Subjects/Keywords: 572.8; PLR shunting system; portable PCR device; DNA Analysis; miniaturisation; lab on a chip

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APA (6^th Edition):

Salman, A. A. A. (2013). Miniaturised system for DNA analysis. (Doctoral Dissertation). Teesside University. Retrieved from https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218

Chicago Manual of Style (16^th Edition):

Salman, Abbas Ali Abulwohab. “Miniaturised system for DNA analysis.” 2013. Doctoral Dissertation, Teesside University. Accessed March 05, 2021. https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218.

MLA Handbook (7^th Edition):

Salman, Abbas Ali Abulwohab. “Miniaturised system for DNA analysis.” 2013. Web. 05 Mar 2021.

Vancouver:

Salman AAA. Miniaturised system for DNA analysis. [Internet] [Doctoral dissertation]. Teesside University; 2013. [cited 2021 Mar 05]. Available from: https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218.

Council of Science Editors:

Salman AAA. Miniaturised system for DNA analysis. [Doctoral Dissertation]. Teesside University; 2013. Available from: https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218

University of Illinois – Urbana-Champaign

13. Kemmerer, Warren Hargon. Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/90847

► While SystemC models provide a promising solution to the complex problem of HW/SW co-design within the system-on-chip paradigm, such requires a detailed annotation of transaction… (more)

Subjects/Keywords: Simulation; Central processing unit (CPU); System on a chip (SoC); Phase; Convergence; SystemC

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APA (6^th Edition):

Kemmerer, W. H. (2016). Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kemmerer, Warren Hargon. “Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed March 05, 2021. http://hdl.handle.net/2142/90847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kemmerer, Warren Hargon. “Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.” 2016. Web. 05 Mar 2021.

Vancouver:

Kemmerer WH. Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2142/90847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kemmerer WH. Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arizona

14. Landsiedel, Emma Catherine. High-Speed White Light Interferometry for Imaging Applications .

Degree: 2019, University of Arizona

URL: http://hdl.handle.net/10150/633073

► An extended depth of field imaging system was developed for in-line inspection for the semiconductor industry. The system produces a single, two-dimensional, in-focus image of… (more)

▼ An extended depth of field imaging system was developed for in-line inspection for the semiconductor industry. The system produces a single, two-dimensional, in-focus image of objects such as integrated circuits or other computer chip components. The system must be high resolution and have a large depth of field to capture small details at all heights of the object. The system must operate quickly since it is used on an assembly line and also must produce true color images, since color can be an indicator of issues with an inspected object. The system uses white light interferometry (WLI) as a means of finding focus across the field of view. The interferometer vertically scans through different focus positions. Fringes from WLI only occur near best focus, or zero optical path difference (OPD). A “vision sensor,” which detects changes in irradiance, outputs events when the irradiance changes for each pixel, which only occurs in a narrow depth fringe region. A depth map of the object is created from this information and informs a separate imaging sensor of best focus depth for individual pixels. The imaging sensor captures pixels at their best focus, and the scanning combines the individual pixel information to create the in focus, two-dimensional image. This thesis details the development of the system concept, the design of the system, and modeling of white light interference in general as well as its use in modeling system performance. The system designed has a 0.6-mm x 0.8-mm field of view with 1.5-μm object size mapping to an image sensor pixel. The system has a 500-μm depth of focus with depth resolution of 3 μm and creates true color images. The prototype of the system is expected to create the final image in around 1 second. The speed is limited by capabilities of current detectors rather than the method itself, and it is expected the system can become significantly faster in a few years, such that full image capture can occur in a time of 40 ms. Advisors/Committee Members: Koshel, Richard J (advisor), Ashok, Amit (committeemember), Kim, Dae Wook (committeemember).

Subjects/Keywords: extended depth of field; interferometry; machine vision; microscopy; system on a chip; vision sensor

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APA (6^th Edition):

Landsiedel, E. C. (2019). High-Speed White Light Interferometry for Imaging Applications . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/633073

Chicago Manual of Style (16^th Edition):

Landsiedel, Emma Catherine. “High-Speed White Light Interferometry for Imaging Applications .” 2019. Masters Thesis, University of Arizona. Accessed March 05, 2021. http://hdl.handle.net/10150/633073.

MLA Handbook (7^th Edition):

Landsiedel, Emma Catherine. “High-Speed White Light Interferometry for Imaging Applications .” 2019. Web. 05 Mar 2021.

Vancouver:

Landsiedel EC. High-Speed White Light Interferometry for Imaging Applications . [Internet] [Masters thesis]. University of Arizona; 2019. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/10150/633073.

Council of Science Editors:

Landsiedel EC. High-Speed White Light Interferometry for Imaging Applications . [Masters Thesis]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/633073

University of Maryland

15. Pang, Cheng. Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks.

Degree: Mechanical Engineering, 2013, University of Maryland

URL: http://hdl.handle.net/1903/14798

► Wireless sensor networks (WSNs) have been widely used in various applications to acquire distributed information through cooperative efforts of sensor nodes. Most of the sensor… (more)

▼ Wireless sensor networks (WSNs) have been widely used in various applications to acquire distributed information through cooperative efforts of sensor nodes. Most of the sensor nodes used in WSNs are based on mechanical or electrical sensing mechanisms, which are susceptible to electromagnetic interference (EMI) and can hardly be used in harsh environments. Although these disadvantages of conventional sensor nodes can be overcome by employing optical sensing methods, traditional optical systems are usually bulky and expensive, which can hardly be implemented in WSNs. Recently, the emerging technologies of silicon photonics and photonic crystal promise a solution of integrating a complete optical system through a complementary metal-oxide-semiconductor (CMOS) process. However, such an integration still remains a challenge. The overall objective of this dissertation work is to develop a smart multifunctional optical system-on-a-chip (SOC) sensor platform capable of both phase modulation and wavelength tuningfor heterogeneous sensing, and implement this platform in a sensor node to achieve an optical WSN for various applications, including those in harsh environments. The contributions of this dissertation work are summarized as follows. i)A smart multifunctional optical SOC sensor platform for heterogeneous sensing has beendeveloped for the first time. This platform can be used to perform phase modulation and demodulation in a low coherence interferometric configuration or wavelength tuning in a spectrum sensing configuration.The multifunctional optical sensor platform is developed through hybrid integration of a light source, an optical modulator, and multiple photodetectors. As the key component of the SOC platform, two types of modulators, namely, the opto-mechanical and electro-optical modulators, are investigated. For the first time, interrogating different types of heterogeneous sensors, including various Fabry-Perot (FP) sensors and fiber Bragg grating (FBG) sensors, with a single SOC sensor platform, is demonstrated. ii)Enhanced understanding of the principles of the multifunctional optical platform withanopto-mechanical modulator has been achieved.As a representative of opto-mechanical modulators, a microelectromechanical systems (MEMS) based FP tunable filter is thoroughly investigated through mechanical and optical modeling. The FP tunable filter is studied for both phase modulation and wavelength tuning, and design guidelines are developed based on the modeling and parametric studies. It is found that the MEMS tunable filter can achieve a large modulation depth, but it suffers from a trade-off between modulation depth and speed. iii) A novel silicon electro-optical modulator based on microring structures for optical phase modulation and wavelength tuning has been designed. To overcome the limitations of the opto-mechanical modulators including low modulation speed and mechanical instability, a CMOS compatible high speed electro-optical silicon modulator is designed, which combines microring and photonic… Advisors/Committee Members: Yu, Miao (advisor).

Subjects/Keywords: Mechanical engineering; fiber optics; optical system-on-a-chip; wireless sensor network

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APA (6^th Edition):

Pang, C. (2013). Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks. (Thesis). University of Maryland. Retrieved from http://hdl.handle.net/1903/14798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pang, Cheng. “Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks.” 2013. Thesis, University of Maryland. Accessed March 05, 2021. http://hdl.handle.net/1903/14798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pang, Cheng. “Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks.” 2013. Web. 05 Mar 2021.

Vancouver:

Pang C. Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks. [Internet] [Thesis]. University of Maryland; 2013. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1903/14798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pang C. Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks. [Thesis]. University of Maryland; 2013. Available from: http://hdl.handle.net/1903/14798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Massey University

16. Chou, Steven Chun-Wei. An investigation into the application of microfluidics to the analysis of chromosome conformation.

Degree: MS, Molecular BioScience, 2011, Massey University

URL: http://hdl.handle.net/10179/2804

► Ever since the discovery of DNA, biologists have been striving to unravel its mysteries. Many efforts have been made over the years to further our… (more)

▼ Ever since the discovery of DNA, biologists have been striving to unravel its mysteries. Many efforts have been made over the years to further our understanding of genes, what they do and how they function. Genomes exist as a 3D structure inside the nucleus and they are not randomly arranged. However, there are still many gaps in the knowledge of how the structure fills this 3D space. Using chromosome conformation capture (3C) and other methods based on proximity ligation, interactions between different sections on the chromosome can be captured. A computer simulated 3D chromosome model can then be created based on the interaction data. Currently, global interaction maps can only be created for populations of cells. The overall goal of this research is to develop a protocol that will enable the capture of chromosome interactions within a single cell. This requires the use of microfluidic chips due to the minute quantity of DNA within a single cell. Therefore the main objectives of this research are to: 1) build and test a microfluidic system (lab-on-a-chip or LOC) that will aid in the capture of interand intra- chromosomal interactions of a single cell; and 2) characterize the restriction and ligation of DNA that will be performed in a microfluidic system. In order to assess the efficiency of DNA digestion within microfluidic chips, EcoRI and MspI digestion kinetics within microtubes is first characterized to establish a base line for comparison with digestion kinetics within microfluidic chips. The Km, Vmax and Kcat for EcoRI within microtubes are 32 nM, 0.14 nM s-1 and 1.4 fmol s-1 U-1 respectively. The Km, Vmax and Kcat for MspI within microtubes are 125 nM, 1.46 nM s-1 and 29.2 fmol s-1 U-1 respectively. On the other hand, the digestion kinetics within microfluidic chips is undetermined, because both restriction enzymes exhibit non-specific nuclease activity within microfluidic chips under the conditions tested. The exhibition of non-specific nuclease activity is unexpected and causes ligation of DNA performed in microfluidic chips to fail. The non-specific nuclease activity of EcoRI and MspI within microfluidic chips is also problematic for the overall goal of developing a protocol that will enable the capture of chromosome interactions within a single cell, because the non-specific nuclease activity would cause loss of template and random variations in results obtained.

Subjects/Keywords: Chromosome analysis; Lab-on-a-chip; Microfluidic system; Microfluidic chips; Chromosome interactions

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APA (6^th Edition):

Chou, S. C. (2011). An investigation into the application of microfluidics to the analysis of chromosome conformation. (Masters Thesis). Massey University. Retrieved from http://hdl.handle.net/10179/2804

Chicago Manual of Style (16^th Edition):

Chou, Steven Chun-Wei. “An investigation into the application of microfluidics to the analysis of chromosome conformation.” 2011. Masters Thesis, Massey University. Accessed March 05, 2021. http://hdl.handle.net/10179/2804.

MLA Handbook (7^th Edition):

Chou, Steven Chun-Wei. “An investigation into the application of microfluidics to the analysis of chromosome conformation.” 2011. Web. 05 Mar 2021.

Vancouver:

Chou SC. An investigation into the application of microfluidics to the analysis of chromosome conformation. [Internet] [Masters thesis]. Massey University; 2011. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/10179/2804.

Council of Science Editors:

Chou SC. An investigation into the application of microfluidics to the analysis of chromosome conformation. [Masters Thesis]. Massey University; 2011. Available from: http://hdl.handle.net/10179/2804

Brigham Young University

17. Ramstedt, Clayton D. Modular 3D Printer System Software For Research Environments.

Degree: MS, 2020, Brigham Young University

URL: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9688&context=etd

► The Nordin group at Brigham Young University has been focused on developing 3D printing technology for fabrication of lab-on-a-chip (microfluidic) devices since 2013. As… (more)

Subjects/Keywords: SLA 3D printing; microfluidics; lab on a chip; system software architecture; Engineering

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APA (6^th Edition):

Ramstedt, C. D. (2020). Modular 3D Printer System Software For Research Environments. (Masters Thesis). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9688&context=etd

Chicago Manual of Style (16^th Edition):

Ramstedt, Clayton D. “Modular 3D Printer System Software For Research Environments.” 2020. Masters Thesis, Brigham Young University. Accessed March 05, 2021. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9688&context=etd.

MLA Handbook (7^th Edition):

Ramstedt, Clayton D. “Modular 3D Printer System Software For Research Environments.” 2020. Web. 05 Mar 2021.

Vancouver:

Ramstedt CD. Modular 3D Printer System Software For Research Environments. [Internet] [Masters thesis]. Brigham Young University; 2020. [cited 2021 Mar 05]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9688&context=etd.

Council of Science Editors:

Ramstedt CD. Modular 3D Printer System Software For Research Environments. [Masters Thesis]. Brigham Young University; 2020. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9688&context=etd

Texas A&M University

18. Malave-Bonet, Javier. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.

Degree: MS, Computer Engineering, 2012, Texas A&M University

URL: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

► Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused… (more)

▼ Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused on broad topics such as NOC component micro-architecture, fault-tolerant communication, and system memory architecture. Nonetheless, the design of lowlatency, high-bandwidth, low-power and area-efficient NOC is extremely complex due to the conflicting nature of these design objectives. Benchmarks are an indispensable tool in the design process; providing thorough measurement and fair comparison between designs in order to achieve optimal results (i.e performance, cost, quality of service). This research proposes a benchmarking platform called NoCBench for evaluating the performance of Network-on-chip. Although previous research has proposed standard guidelines to develop benchmarks for Network-on-Chip, this work moves forward and proposes a System-C based simulation platform for system-level design exploration. It will provide an initial set of synthetic benchmarks for on-chip network interconnection validation along with an initial set of standardized processing cores, NOC components, and system-wide services. The benchmarks were constructed using synthetic applications described by Task Graphs For Free (TGFF) task graphs extracted from the E3S benchmark suite. Two benchmarks were used for characterization: Consumer and Networking. They are characterized based on throughput and latency. Case studies show how they can be used to evaluate metrics beyond throughput and latency (i.e. traffic distribution). The contribution of this work is two-fold: 1) This study provides a methodology for benchmark creation and characterization using NoCBench that evaluates important metrics in NOC design (i.e. end-to-end packet delay, throughput). 2) The developed full-system simulation platform provides a complete environment for further benchmark characterization on NOC based MpSoC as well as system-level design space exploration. Advisors/Committee Members: Mahapatra, Rabi N. (advisor), Bettati, Riccardo (committee member), Gratz, Paul (committee member).

Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C

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APA (6^th Edition):

Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Chicago Manual of Style (16^th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Masters Thesis, Texas A&M University. Accessed March 05, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

MLA Handbook (7^th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 05 Mar 2021.

Vancouver:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Council of Science Editors:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

University of Toronto

19. Nejatian, Maryam. Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells.

Degree: 2020, University of Toronto

URL: http://hdl.handle.net/1807/103356

►

Traditional in vitro alveolar epithelial cell (AEC) models lack physiological architectural cues required for regulating cell functionality. While 3D AEC organoids incorporate some characteristics of… (more)

Subjects/Keywords: alveoli; alveoli-on-a-chip; Lung-on-chip; microfluidic; organ-on-chip; 0541

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Nejatian, M. (2020). Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/103356

Chicago Manual of Style (16^th Edition):

Nejatian, Maryam. “Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells.” 2020. Masters Thesis, University of Toronto. Accessed March 05, 2021. http://hdl.handle.net/1807/103356.

MLA Handbook (7^th Edition):

Nejatian, Maryam. “Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells.” 2020. Web. 05 Mar 2021.

Vancouver:

Nejatian M. Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells. [Internet] [Masters thesis]. University of Toronto; 2020. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1807/103356.

Council of Science Editors:

Nejatian M. Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells. [Masters Thesis]. University of Toronto; 2020. Available from: http://hdl.handle.net/1807/103356

20. Magnos Roberto Pizzoni. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.

Degree: 2010, Universidade do Vale do Itajaí

URL: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

►

Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos… (more)

▼

Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos utilizando-se blocos de silício reutilizáveis (núcleos). Com as novas tecnologias de integração, será possível construir sistema com várias dezenas a centenas de núcleos em um mesmo chip. Tais sistemas terão alto poder de processamento, mas irá requerer estruturas de comunicação reutilizáveis com desempenho escalável, o que não é possível de ser obtido com as arquiteturas usadas atualmente, baseadas no barramento. É consenso na comunidade acadêmica e na indústria que a melhor solução para esse problema é baseada em estruturas de interconexão com canais chaveados por roteadores as chamadas Redes-em-Chip ou NoCs (Networks-on-Chip). Atualmente, diversos grupos de pesquisa trabalham investigando diferentes aspectos sobre NoCs e a grande maioria desses trabalhos utiliza ambientes de simulação para exploração arquitetural e avaliação de desempenho. No entanto, em modelos detalhados e com precisão de ciclo, o tempo de simulação é bastante alto, o que limita a quantidade de ciclos a serem simulados. Após a validação e a avaliação baseada em simulação, usualmente, realiza-se a síntese da NoC em FPGA (Field Programmable Gate Array) para realizar a sua validação física. Para tal, é necessário construir um sistema com núcleos conectados à rede e que produzam o tráfego que permitam validar a arquitetura implementada. Este projeto insere-se nesse contexto e busca desenvolver uma infra-estrutura de apoio à pesquisa sobre NoCs por meio da disponibilização de geradores de tráfego sintetizáveis para validação física e para a avaliação de desempenho de NoCs em dispositivos do tipo FPGA. A idéia é que essa infra-instrutora facilite a validação da rede e a realização de experimentos de análise de desempenho mais rapidamente e com maior precisão do que aqueles realizados em ambientes de simulação. Neste trabalho, foram desenvolvidos componentes de hardware e de software para a construção da plataforma proposta

With the evolution of the circuit manufacturer processes is becoming possible to integrate complete systems in a single chip, which are built of reusable silicon-based blocks (cores). With the advent of new integration technologies, it will be possible to build a system with several tens to hundreds of cores in the same chip. Such systems will have a higher processing power, but will require reusable communication structures with scalable performance, which is not possible to be obtained with the current bus-based architectures. The consensus in the academic community and industry is that the best solution for this problem is based on interconnection architectures with switching channels by routers the so called chip-networks or NoCs (Networks-on-Chip). Nowadays, several groups of research investigate different aspects of NoCs and the majority of the work being done uses simulation environments for architectural exploration and performance evaluation. However, in detailed models…

Advisors/Committee Members: Cesar Augusto Tischer, Alejandro Rafael Garcia Ramirez, Michelle Silva Wangham.

Subjects/Keywords: System-on-Chip; Network-on-Chip; Avaliação de desempenho; CIENCIA DA COMPUTACAO; Circuitos integrados; System-on-Chip; Network-on-Chip; Performance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Pizzoni, M. R. (2010). PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Thesis, Universidade do Vale do Itajaí. Accessed March 05, 2021. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Web. 05 Mar 2021.

Vancouver:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2010. [cited 2021 Mar 05]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Thesis]. Universidade do Vale do Itajaí; 2010. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Anna University

21. Saravanakumar U. An investigation on macro and micro Architectures for network on chip;.

Degree: An investigation on macro and micro Architectures for network on chip, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/40748

►

As the technology scales down more processors or Processing newlineElements PEs are integrated in the same die and such technology is called as newlineMultiprocessor System… (more)

Subjects/Keywords: Microarchitectural aims; Multiprocessor System on Chip; Network on Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

U, S. (2015). An investigation on macro and micro Architectures for network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Thesis, Anna University. Accessed March 05, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Web. 05 Mar 2021.

Vancouver:

U S. An investigation on macro and micro Architectures for network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 05]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

U S. An investigation on macro and micro Architectures for network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Viswanathan N. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.

Degree: Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/33543

►

Three dimensional integration is one of the emerging techniques newlineto find solution for the global interconnect delay challenges faced in the newlineadvanced VLSI ULSI technology… (more)

Subjects/Keywords: Network on Chip; System on Chip; Through Silicon Via

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APA (6^th Edition):

N, V. (2015). Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Thesis, Anna University. Accessed March 05, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Web. 05 Mar 2021.

Vancouver:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 05]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Anna University

23. Maheswari M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;.

Degree: Novel approaches in the design of Reliable custom topology for Application specific network on chip, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/39199

►

Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed… (more)

Subjects/Keywords: Digital Signal Processor; Intellectual Property; Networks on Chip; System on Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

M, M. (2015). Novel approaches in the design of Reliable custom topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/39199

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed March 05, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/39199.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Web. 05 Mar 2021.

Vancouver:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 05]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Anna University

24. Maheswari M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;.

Degree: Novel approaches in the design of Reliable custom topology for Application specific network on chip, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/41574

►

Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed… (more)

Subjects/Keywords: Digital Signal Processor; Networks on Chip; System on Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

M, M. (2015). Novel approaches in the design of Reliable custom topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/41574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed March 05, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/41574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Web. 05 Mar 2021.

Vancouver:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 05]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Texas A&M University

25. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: PhD, Computer Engineering, 2012, Texas A&M University

URL: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

► With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Chicago Manual of Style (16^th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Doctoral Dissertation, Texas A&M University. Accessed March 05, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

MLA Handbook (7^th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 05 Mar 2021.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

University of New South Wales

26. Hussain, Mubashir. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.

Degree: Computer Science & Engineering, 2018, University of New South Wales

URL: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

► Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system… (more)

▼ Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system may involve different parties, especially for the design of system-on-chip (SoC) where the high complexity of the design has pushed designers towards using the third-party components that may have been modified with malicious additions without notice of the designer.Such a malicious modification (known as hardware Trojan) may be very small and can escape the scrutiny of the offline circuit-level testing and appear in the final product, which creates a new class of threats that have to be addressed at the hardware level and at the runtime.For SoCs, one of the most vulnerable components is the communication sub-system, called network-on-chip (NoC). NoC is able to access all components in the system and can be an easy target for varied attacks.This thesis aims at the hardware Trojan inside the router of a NoC. When activated, the Trojan can modify passing packets for two different purposes: 1) hijacking packets to harvest information carried by the packet; 2) manipulating the packet to alter the packet data. Both attacks can be tackled by the authentication.But unlike the software level authentication designs in the traditional networking system, the authentication in NoC has on-chip overhead issues.The thesis investigates three designs: one for packet hijacking attack detection, one for packet integrity attack detection, and one for Trojan location detection. Each design has a different dominant overhead issue. We, therefore, have a different optimization objective in the design.For the packet hijacking attack detection, we target the overhead on the chip cost and we present a customization design. For the packet data integrity authentication, the main concern is the bandwidth consumption caused by the large tag size and we introduce a progressive authentication scheme to reduce the bandwidth overhead. For the Trojan location detection, we propose a dynamic search algorithm to minimize the energy consumption.We have conducted a range of extensive experiments on each design, which demonstrate the effectiveness of our design approaches. Advisors/Committee Members: Guo, Hui, UNSW.

Subjects/Keywords: System-on-Chip; Hardware Trojan; Network-on-Chip; Hardware Security

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hussain, M. (2018). Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

Chicago Manual of Style (16^th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Doctoral Dissertation, University of New South Wales. Accessed March 05, 2021. http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

MLA Handbook (7^th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Web. 05 Mar 2021.

Vancouver:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2021 Mar 05]. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

Council of Science Editors:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

University of Alberta

27. Martin, Benjamin R. CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip.

Degree: MS, Department of Electrical and Computer Engineering, 2011, University of Alberta

URL: https://era.library.ualberta.ca/files/2r36tz867

► One application for lab-on-a-chip (LOC) devices is performing miniaturized laboratory tests. These devices would be ideal for point-of-care medical diagnostic applications; however, many still rely… (more)

Subjects/Keywords: Capillary Electrophoresis; Lab-on-a-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Martin, B. R. (2011). CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/2r36tz867

Chicago Manual of Style (16^th Edition):

Martin, Benjamin R. “CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip.” 2011. Masters Thesis, University of Alberta. Accessed March 05, 2021. https://era.library.ualberta.ca/files/2r36tz867.

MLA Handbook (7^th Edition):

Martin, Benjamin R. “CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip.” 2011. Web. 05 Mar 2021.

Vancouver:

Martin BR. CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip. [Internet] [Masters thesis]. University of Alberta; 2011. [cited 2021 Mar 05]. Available from: https://era.library.ualberta.ca/files/2r36tz867.

Council of Science Editors:

Martin BR. CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip. [Masters Thesis]. University of Alberta; 2011. Available from: https://era.library.ualberta.ca/files/2r36tz867

University of Alberta

28. Behnam Dehkordi, Mohammad. Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies.

Degree: PhD, Department of Electrical and Computer Engineering, 2012, University of Alberta

URL: https://era.library.ualberta.ca/files/h702q7124

► Genetic analysis is not widely used for disease diagnostics as it is costly and very labour/infrastructure intensive. We believe that by employing both microelectronic and… (more)

Subjects/Keywords: microelectronics; lab-on-a-chip; microfluidics; CMOS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Behnam Dehkordi, M. (2012). Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/h702q7124

Chicago Manual of Style (16^th Edition):

Behnam Dehkordi, Mohammad. “Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies.” 2012. Doctoral Dissertation, University of Alberta. Accessed March 05, 2021. https://era.library.ualberta.ca/files/h702q7124.

MLA Handbook (7^th Edition):

Behnam Dehkordi, Mohammad. “Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies.” 2012. Web. 05 Mar 2021.

Vancouver:

Behnam Dehkordi M. Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies. [Internet] [Doctoral dissertation]. University of Alberta; 2012. [cited 2021 Mar 05]. Available from: https://era.library.ualberta.ca/files/h702q7124.

Council of Science Editors:

Behnam Dehkordi M. Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies. [Doctoral Dissertation]. University of Alberta; 2012. Available from: https://era.library.ualberta.ca/files/h702q7124

Texas A&M University

29. Guzman, Adrian. The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies.

Degree: MS, Electrical Engineering, 2012, Texas A&M University

URL: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11773

► Microdroplet microfluidics has gained much interested in the past decade due to its ability to conduct a wide variety of biological and microfluidic experiments with… (more)

▼ Microdroplet microfluidics has gained much interested in the past decade due to its ability to conduct a wide variety of biological and microfluidic experiments with extremely high repeatability on a mass scale. In particular the ability to culture multiple batches of cells by creating microdroplets with a single encapsulated cell and observe their growth overtime allows for specific conditioning of cells. In addition, when conducting co-culture experiment the induction of a certain stimulus may provide observational rare differences in growth that may be characterized by harnessing a single batch of cells out of thousands of samples. This thesis first presents a variety of microdroplet microfluidic devices that use specific techniques to sufficiently produce, synchronize, merge, and analyze microdroplets. Although many of the devices are capable of producing stable droplets and somewhat efficient synchronization, the overall merging efficiency for most passive or active merging methods alone is lacking. Improvements on such methods and the incorporation of multiple merging methods can lead to a higher overall merging efficiency and greater droplet stability. Also, multiple droplet detection methods can be employed to analyze cellular growth under different conditions, while passive or active sorting methods can be used to acquire particular microdroplet samples downstream. The work presented in this thesis entails the characterization and detailed analysis of all aspects of microdroplet microfluidics necessary to adequately produce a microdroplet co-culture device for microbial studies. This includes the incorporation of multiple microdroplet generators for the production of water droplets immersed in oil serving as bio-reactors for cell culture experiments. In addition, multiple microdroplet synchronization devices were tested to sufficiently align multiple trains of droplets for downstream merging using a variety of passive, active, or combination merging methods. In particular, the use of an electric field can cause destabilization of the surfactant surrounding a microdroplet and allow for the formation of a liquid bridge. The formation of this liquid bridge in conjunction with passive merging methods can lead to droplet electrocoalescence. The incorporation of a more uniform electric field that reduces the angle between the droplet dipole moment and E-field can lead to better droplet merging while reducing voltage and frequency requirements observed in previously publications. The testing, observation, and optimization of such aspects of microdroplet microfluidics are crucial for the advancement and production of sound microdroplet culture devices for a variety of applications including the analysis of dangerous pathogenic substances, drug testing or delivery, and genetic studies. Advisors/Committee Members: Han, Arum (advisor), Kameoka, Jun (committee member), Zou, Jun (committee member), Meissner, Kennith (committee member).

Subjects/Keywords: microdroplet; electrocoalescence; bioreactor; lab on a chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Guzman, A. (2012). The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11773

Chicago Manual of Style (16^th Edition):

Guzman, Adrian. “The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies.” 2012. Masters Thesis, Texas A&M University. Accessed March 05, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11773.

MLA Handbook (7^th Edition):

Guzman, Adrian. “The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies.” 2012. Web. 05 Mar 2021.

Vancouver:

Guzman A. The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11773.

Council of Science Editors:

Guzman A. The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11773

University of Waterloo

30. Mao, Shinong. Development of a Novel Microwave Sensing System for Lab on a Chip Applications.

Degree: 2018, University of Waterloo

URL: http://hdl.handle.net/10012/14271

► Microwave technology presents tremendous potential as a remote-sensing technology for a wide range of applications spanning from life science research to food industries, pharmaceutical research,… (more)

▼ Microwave technology presents tremendous potential as a remote-sensing technology for a wide range of applications spanning from life science research to food industries, pharmaceutical research, and new material discoveries. Integration of microwave sensing with microfluidics for sample processing makes it an ideal choice for point of care applications highly demanded in resourcelimited areas. The vast majority of the existing microwave sensors are manufactured using sophisticated soft lithography technology which has largely limited its development and applications. There is a large demand for developing new fabrication approaches for the feasibility of mass production at a reasonable cost. In this thesis, a new, yet simple method is developed to fabricate split ring resonator (SRR) based microwave sensors. A simple RLC model is used to characterize the resonant frequency of the SRR, and the equations for calculating the RLC’s resonant frequency is modified to predict the SRR’s resonant frequency base on its geometry. The design is also validated by comparing the simulation results obtained using the commercial software HFSS, and measurements from a real SRR developed sensor. The double ring structure was fabricated onto a printed circuit board by using the industrial photolithograph method. Coating with PDMS and epoxy layer as the passivation layer was tested and compared. Two testing approaches using the SRR sensor developed in this thesis are implemented in this thesis. Their performance for real-time sensing is characterized by applying it to differentiate chemical diary samples and other chemical solutions. In the dipping mode, the sensor is dipped in the material under test (MUT), and in the microfluidic channel mode, the sensor is integrated with a microchannel. The MUT is characterized by analyzing the spectrum data of the reflection coefficient as the function of frequencies. Experimental results indicate that this sensor is capable of differentiating various liquid samples such as DI water, ethanol, isopropanol, oil and salt solutions. Linear relationships between the resonant frequency and the concentrations of chemical composites are also observed in ethanol solutions (0-90%), and salt solutions (NaCl). This sensor is also used to differentiate various milk samples and milk dilutions and it is capable of distinguishing milks with different fat percentages and protein contents. A fully customized vector network analyzer (VNA) is also developed. The circuit structure is designed by referring the existing customized VNAs that were implemented in previous work by iv other lab colleagues. Modifications are made including replacement of the microwave source, using Arduino platform to perform controlling and data acquisition, addition of a harmonic filtering device, and development of a calibration algorithm. The device is validated by comparing its measuring result with a commercial VNA. The customized VNA is able to output a similar spectrum pattern as the commercial VNA,…

Subjects/Keywords: Microwave Sensing; Lab on a Chip

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APA (6^th Edition):

Mao, S. (2018). Development of a Novel Microwave Sensing System for Lab on a Chip Applications. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14271

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Mao, Shinong. “Development of a Novel Microwave Sensing System for Lab on a Chip Applications.” 2018. Thesis, University of Waterloo. Accessed March 05, 2021. http://hdl.handle.net/10012/14271.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Mao, Shinong. “Development of a Novel Microwave Sensing System for Lab on a Chip Applications.” 2018. Web. 05 Mar 2021.

Vancouver:

Mao S. Development of a Novel Microwave Sensing System for Lab on a Chip Applications. [Internet] [Thesis]. University of Waterloo; 2018. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/10012/14271.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mao S. Development of a Novel Microwave Sensing System for Lab on a Chip Applications. [Thesis]. University of Waterloo; 2018. Available from: http://hdl.handle.net/10012/14271

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations