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You searched for subject:(System on a chip). Showing records 1 – 30 of 102086 total matches.

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Texas A&M University

1. Jeong, Sehoon. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.

Degree: PhD, Biomedical Engineering, 2018, Texas A&M University

 Neurological diseases are a major challenge to reach new therapies. However, physiological signals that regulate neurodegeneration in the central nervous system (CNS) are still little… (more)

Subjects/Keywords: Brain organ-on-a-chip; Microfluidic blood-brain barrier-on-a-chip; Neuroinflammation-on-a-chip; Drug screening system

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APA (6th Edition):

Jeong, S. (2018). Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173360

Chicago Manual of Style (16th Edition):

Jeong, Sehoon. “Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.” 2018. Doctoral Dissertation, Texas A&M University. Accessed March 05, 2021. http://hdl.handle.net/1969.1/173360.

MLA Handbook (7th Edition):

Jeong, Sehoon. “Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies.” 2018. Web. 05 Mar 2021.

Vancouver:

Jeong S. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. [Internet] [Doctoral dissertation]. Texas A&M University; 2018. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1969.1/173360.

Council of Science Editors:

Jeong S. Microfabricated Brain Organ-On-A-Chip Systems for Neurophysiological Studies. [Doctoral Dissertation]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173360


Texas Tech University

2. Eravelli, Shruti. Multi-generational test plan generation and execution in advanced mixed signal controllers.

Degree: Electrical and Computer Engineering, 2011, Texas Tech University

 Most integrated circuits are evolutionary. This is especially true in the realm of system-on-a-chip (SoC) devices that combine multiple functions monolithically. Electronic systems that begin… (more)

Subjects/Keywords: Characterization; Testing; System-on-a-chip; Performance; Motherboard; Daughter board

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APA (6th Edition):

Eravelli, S. (2011). Multi-generational test plan generation and execution in advanced mixed signal controllers. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/ETD-TTU-2011-05-1291

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Eravelli, Shruti. “Multi-generational test plan generation and execution in advanced mixed signal controllers.” 2011. Thesis, Texas Tech University. Accessed March 05, 2021. http://hdl.handle.net/2346/ETD-TTU-2011-05-1291.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Eravelli, Shruti. “Multi-generational test plan generation and execution in advanced mixed signal controllers.” 2011. Web. 05 Mar 2021.

Vancouver:

Eravelli S. Multi-generational test plan generation and execution in advanced mixed signal controllers. [Internet] [Thesis]. Texas Tech University; 2011. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2346/ETD-TTU-2011-05-1291.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Eravelli S. Multi-generational test plan generation and execution in advanced mixed signal controllers. [Thesis]. Texas Tech University; 2011. Available from: http://hdl.handle.net/2346/ETD-TTU-2011-05-1291

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

3. Tino, Anita. Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures.

Degree: 2011, Ryerson University

 Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works… (more)

Subjects/Keywords: Networks on a chip  – Design; Networks on a chip  – Mathematical models; Networks on a chip; Systems on a chip  – Design; Systems on a chip  – Mathematical models; Systems on a chip

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APA (6th Edition):

Tino, A. (2011). Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tino, Anita. “Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures.” 2011. Thesis, Ryerson University. Accessed March 05, 2021. https://digital.library.ryerson.ca/islandora/object/RULA%3A1213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tino, Anita. “Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures.” 2011. Web. 05 Mar 2021.

Vancouver:

Tino A. Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures. [Internet] [Thesis]. Ryerson University; 2011. [cited 2021 Mar 05]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tino A. Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures. [Thesis]. Ryerson University; 2011. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Manitoba

4. Cook, Darcy Philip. A multiprocessng system-on-chip framework targeting stream-oriented applications.

Degree: Electrical and Computer Engineering, 2011, University of Manitoba

 Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be… (more)

Subjects/Keywords: system-on-chip; multiprocessing

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APA (6th Edition):

Cook, D. P. (2011). A multiprocessng system-on-chip framework targeting stream-oriented applications. (Masters Thesis). University of Manitoba. Retrieved from http://hdl.handle.net/1993/4383

Chicago Manual of Style (16th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Masters Thesis, University of Manitoba. Accessed March 05, 2021. http://hdl.handle.net/1993/4383.

MLA Handbook (7th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Web. 05 Mar 2021.

Vancouver:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Internet] [Masters thesis]. University of Manitoba; 2011. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1993/4383.

Council of Science Editors:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Masters Thesis]. University of Manitoba; 2011. Available from: http://hdl.handle.net/1993/4383


Ryerson University

5. Gharan, Masoud Oveis. Virtual channel organization and arbitration for network on chip router architecure.

Degree: 2016, Ryerson University

 The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the… (more)

Subjects/Keywords: Systems on a chip; Networks on a chip

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APA (6th Edition):

Gharan, M. O. (2016). Virtual channel organization and arbitration for network on chip router architecure. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gharan, Masoud Oveis. “Virtual channel organization and arbitration for network on chip router architecure.” 2016. Thesis, Ryerson University. Accessed March 05, 2021. https://digital.library.ryerson.ca/islandora/object/RULA%3A5048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gharan, Masoud Oveis. “Virtual channel organization and arbitration for network on chip router architecure.” 2016. Web. 05 Mar 2021.

Vancouver:

Gharan MO. Virtual channel organization and arbitration for network on chip router architecure. [Internet] [Thesis]. Ryerson University; 2016. [cited 2021 Mar 05]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gharan MO. Virtual channel organization and arbitration for network on chip router architecure. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

6. Qian, Zhiliang. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.

Degree: 2014, Hong Kong University of Science and Technology

 With technology scaling down, hundreds and thousands processing elements (PEs) can be integrated on a single chip. Consequently, the embedded systems have led to the… (more)

Subjects/Keywords: Systems on a chip ; Design and construction ; Networks on a chip

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APA (6th Edition):

Qian, Z. (2014). High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Qian, Zhiliang. “High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed March 05, 2021. http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Qian, Zhiliang. “High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.” 2014. Web. 05 Mar 2021.

Vancouver:

Qian Z. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2021 Mar 05]. Available from: http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Qian Z. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Chen, Tai-Feng. A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Signature is an effective lossy compression method to reduce signal trace size at the possible cost of trace precision and implementation cost for different kinds… (more)

Subjects/Keywords: Multiple Signature Compaction Method; Signature Based Tracing Methodology; System-on-a-Chip(SoC)

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APA (6th Edition):

Chen, T. (2016). A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Tai-Feng. “A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification.” 2016. Thesis, NSYSU. Accessed March 05, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Tai-Feng. “A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification.” 2016. Web. 05 Mar 2021.

Vancouver:

Chen T. A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Mar 05]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen T. A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Alberta

8. Ho, Sunny. VLSI Design and System Integration for a USB Genetic Amplification Platform.

Degree: MS, Department of Electrical and Computer Engineering, 2012, University of Alberta

 We demonstrate the feasibility of USB-powered portable genetic amplification. One of the central processes within medical or biological genetic methods is polymerase chain reaction (PCR).… (more)

Subjects/Keywords: lab-on-a-chip; VLSI; polymerase chain reaction; genetic amplification; microfluidic system; biomedical; USB

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APA (6th Edition):

Ho, S. (2012). VLSI Design and System Integration for a USB Genetic Amplification Platform. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/1544bp58m

Chicago Manual of Style (16th Edition):

Ho, Sunny. “VLSI Design and System Integration for a USB Genetic Amplification Platform.” 2012. Masters Thesis, University of Alberta. Accessed March 05, 2021. https://era.library.ualberta.ca/files/1544bp58m.

MLA Handbook (7th Edition):

Ho, Sunny. “VLSI Design and System Integration for a USB Genetic Amplification Platform.” 2012. Web. 05 Mar 2021.

Vancouver:

Ho S. VLSI Design and System Integration for a USB Genetic Amplification Platform. [Internet] [Masters thesis]. University of Alberta; 2012. [cited 2021 Mar 05]. Available from: https://era.library.ualberta.ca/files/1544bp58m.

Council of Science Editors:

Ho S. VLSI Design and System Integration for a USB Genetic Amplification Platform. [Masters Thesis]. University of Alberta; 2012. Available from: https://era.library.ualberta.ca/files/1544bp58m

9. Lange, Hendrik. Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen.

Degree: 2007, Technische Universität Dortmund

 Die vorliegende Arbeit befasst sich mit Analysemethoden für grobgranulare rekonfigurierbare Prozessorarchitekturen. Es wird ein modellbasiertes Verfahren vorgestellt, mit dessen Hilfe derartige Hardwarestrukturen auf einfache Weise… (more)

Subjects/Keywords: Grobgranulare Architekturen; Prozessorarchitektur; Rekonfigurierbare Architekturen; System-on-a-Chip; VLSI-Eigenschaften; 620

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APA (6th Edition):

Lange, H. (2007). Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen. (Thesis). Technische Universität Dortmund. Retrieved from http://hdl.handle.net/2003/24853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lange, Hendrik. “Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen.” 2007. Thesis, Technische Universität Dortmund. Accessed March 05, 2021. http://hdl.handle.net/2003/24853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lange, Hendrik. “Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen.” 2007. Web. 05 Mar 2021.

Vancouver:

Lange H. Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen. [Internet] [Thesis]. Technische Universität Dortmund; 2007. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2003/24853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lange H. Modellbasierte Effizienzanalyse grobgranularer rekonfigurierbarer Prozessorarchitekturen. [Thesis]. Technische Universität Dortmund; 2007. Available from: http://hdl.handle.net/2003/24853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

10. Wong, Jeremy. Integration of Cellular Analysis Methods into Microphysiological Vascular Models.

Degree: PhD, 2020, University of Toronto

 Microphysiological systems, also known as organ-on-a-chip systems, possess significant potential as organotypic models of human tissues, including vascular tissue interfaces that are ubiquitous throughout the… (more)

Subjects/Keywords: biosensor; endothelial permeability; in vitro cell culture; integrated system; organ on a chip; TEER; 0541

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APA (6th Edition):

Wong, J. (2020). Integration of Cellular Analysis Methods into Microphysiological Vascular Models. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/100898

Chicago Manual of Style (16th Edition):

Wong, Jeremy. “Integration of Cellular Analysis Methods into Microphysiological Vascular Models.” 2020. Doctoral Dissertation, University of Toronto. Accessed March 05, 2021. http://hdl.handle.net/1807/100898.

MLA Handbook (7th Edition):

Wong, Jeremy. “Integration of Cellular Analysis Methods into Microphysiological Vascular Models.” 2020. Web. 05 Mar 2021.

Vancouver:

Wong J. Integration of Cellular Analysis Methods into Microphysiological Vascular Models. [Internet] [Doctoral dissertation]. University of Toronto; 2020. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1807/100898.

Council of Science Editors:

Wong J. Integration of Cellular Analysis Methods into Microphysiological Vascular Models. [Doctoral Dissertation]. University of Toronto; 2020. Available from: http://hdl.handle.net/1807/100898

11. Hosic, Sanjin. Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier.

Degree: PhD, Department of Chemical Engineering, 2019, Northeastern University

 Two decades ago, it was demonstrated that electrical vagal nerve stimulation (VNS) inhibits gastrointestinal (GI) inflammation. In-vivo studies concluded that VNS inhibits GI inflammation by… (more)

Subjects/Keywords: cholinergic; epithelium; microfluidic; microphysiological system; organoid; organ-on-a-chip; Bioengineering; Biomedical engineering; Cellular biology

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APA (6th Edition):

Hosic, S. (2019). Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20317949

Chicago Manual of Style (16th Edition):

Hosic, Sanjin. “Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier.” 2019. Doctoral Dissertation, Northeastern University. Accessed March 05, 2021. http://hdl.handle.net/2047/D20317949.

MLA Handbook (7th Edition):

Hosic, Sanjin. “Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier.” 2019. Web. 05 Mar 2021.

Vancouver:

Hosic S. Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier. [Internet] [Doctoral dissertation]. Northeastern University; 2019. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2047/D20317949.

Council of Science Editors:

Hosic S. Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier. [Doctoral Dissertation]. Northeastern University; 2019. Available from: http://hdl.handle.net/2047/D20317949

12. Salman, Abbas Ali Abulwohab. Miniaturised system for DNA analysis.

Degree: PhD, 2013, Teesside University

 The growing markets for analytical techniques in areas such as pathogen detection, clinical analysis, forensic investigation, environmental analysis and food analysis require the development of… (more)

Subjects/Keywords: 572.8; PLR shunting system; portable PCR device; DNA Analysis; miniaturisation; lab on a chip

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APA (6th Edition):

Salman, A. A. A. (2013). Miniaturised system for DNA analysis. (Doctoral Dissertation). Teesside University. Retrieved from https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218

Chicago Manual of Style (16th Edition):

Salman, Abbas Ali Abulwohab. “Miniaturised system for DNA analysis.” 2013. Doctoral Dissertation, Teesside University. Accessed March 05, 2021. https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218.

MLA Handbook (7th Edition):

Salman, Abbas Ali Abulwohab. “Miniaturised system for DNA analysis.” 2013. Web. 05 Mar 2021.

Vancouver:

Salman AAA. Miniaturised system for DNA analysis. [Internet] [Doctoral dissertation]. Teesside University; 2013. [cited 2021 Mar 05]. Available from: https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218.

Council of Science Editors:

Salman AAA. Miniaturised system for DNA analysis. [Doctoral Dissertation]. Teesside University; 2013. Available from: https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218


University of Illinois – Urbana-Champaign

13. Kemmerer, Warren Hargon. Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 While SystemC models provide a promising solution to the complex problem of HW/SW co-design within the system-on-chip paradigm, such requires a detailed annotation of transaction… (more)

Subjects/Keywords: Simulation; Central processing unit (CPU); System on a chip (SoC); Phase; Convergence; SystemC

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APA (6th Edition):

Kemmerer, W. H. (2016). Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kemmerer, Warren Hargon. “Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed March 05, 2021. http://hdl.handle.net/2142/90847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kemmerer, Warren Hargon. “Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.” 2016. Web. 05 Mar 2021.

Vancouver:

Kemmerer WH. Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2142/90847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kemmerer WH. Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

14. Landsiedel, Emma Catherine. High-Speed White Light Interferometry for Imaging Applications .

Degree: 2019, University of Arizona

 An extended depth of field imaging system was developed for in-line inspection for the semiconductor industry. The system produces a single, two-dimensional, in-focus image of… (more)

Subjects/Keywords: extended depth of field; interferometry; machine vision; microscopy; system on a chip; vision sensor

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APA (6th Edition):

Landsiedel, E. C. (2019). High-Speed White Light Interferometry for Imaging Applications . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/633073

Chicago Manual of Style (16th Edition):

Landsiedel, Emma Catherine. “High-Speed White Light Interferometry for Imaging Applications .” 2019. Masters Thesis, University of Arizona. Accessed March 05, 2021. http://hdl.handle.net/10150/633073.

MLA Handbook (7th Edition):

Landsiedel, Emma Catherine. “High-Speed White Light Interferometry for Imaging Applications .” 2019. Web. 05 Mar 2021.

Vancouver:

Landsiedel EC. High-Speed White Light Interferometry for Imaging Applications . [Internet] [Masters thesis]. University of Arizona; 2019. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/10150/633073.

Council of Science Editors:

Landsiedel EC. High-Speed White Light Interferometry for Imaging Applications . [Masters Thesis]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/633073


University of Maryland

15. Pang, Cheng. Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks.

Degree: Mechanical Engineering, 2013, University of Maryland

 Wireless sensor networks (WSNs) have been widely used in various applications to acquire distributed information through cooperative efforts of sensor nodes. Most of the sensor… (more)

Subjects/Keywords: Mechanical engineering; fiber optics; optical system-on-a-chip; wireless sensor network

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APA (6th Edition):

Pang, C. (2013). Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks. (Thesis). University of Maryland. Retrieved from http://hdl.handle.net/1903/14798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pang, Cheng. “Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks.” 2013. Thesis, University of Maryland. Accessed March 05, 2021. http://hdl.handle.net/1903/14798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pang, Cheng. “Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks.” 2013. Web. 05 Mar 2021.

Vancouver:

Pang C. Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks. [Internet] [Thesis]. University of Maryland; 2013. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1903/14798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pang C. Investigation into Smart Multifunctional Optical System-On-A-Chip Sensor Platform and Its Applications in Optical Wireless Sensor Networks. [Thesis]. University of Maryland; 2013. Available from: http://hdl.handle.net/1903/14798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Massey University

16. Chou, Steven Chun-Wei. An investigation into the application of microfluidics to the analysis of chromosome conformation.

Degree: MS, Molecular BioScience, 2011, Massey University

 Ever since the discovery of DNA, biologists have been striving to unravel its mysteries. Many efforts have been made over the years to further our… (more)

Subjects/Keywords: Chromosome analysis; Lab-on-a-chip; Microfluidic system; Microfluidic chips; Chromosome interactions

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APA (6th Edition):

Chou, S. C. (2011). An investigation into the application of microfluidics to the analysis of chromosome conformation. (Masters Thesis). Massey University. Retrieved from http://hdl.handle.net/10179/2804

Chicago Manual of Style (16th Edition):

Chou, Steven Chun-Wei. “An investigation into the application of microfluidics to the analysis of chromosome conformation.” 2011. Masters Thesis, Massey University. Accessed March 05, 2021. http://hdl.handle.net/10179/2804.

MLA Handbook (7th Edition):

Chou, Steven Chun-Wei. “An investigation into the application of microfluidics to the analysis of chromosome conformation.” 2011. Web. 05 Mar 2021.

Vancouver:

Chou SC. An investigation into the application of microfluidics to the analysis of chromosome conformation. [Internet] [Masters thesis]. Massey University; 2011. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/10179/2804.

Council of Science Editors:

Chou SC. An investigation into the application of microfluidics to the analysis of chromosome conformation. [Masters Thesis]. Massey University; 2011. Available from: http://hdl.handle.net/10179/2804


Brigham Young University

17. Ramstedt, Clayton D. Modular 3D Printer System Software For Research Environments.

Degree: MS, 2020, Brigham Young University

  The Nordin group at Brigham Young University has been focused on developing 3D printing technology for fabrication of lab-on-a-chip (microfluidic) devices since 2013. As… (more)

Subjects/Keywords: SLA 3D printing; microfluidics; lab on a chip; system software architecture; Engineering

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APA (6th Edition):

Ramstedt, C. D. (2020). Modular 3D Printer System Software For Research Environments. (Masters Thesis). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9688&context=etd

Chicago Manual of Style (16th Edition):

Ramstedt, Clayton D. “Modular 3D Printer System Software For Research Environments.” 2020. Masters Thesis, Brigham Young University. Accessed March 05, 2021. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9688&context=etd.

MLA Handbook (7th Edition):

Ramstedt, Clayton D. “Modular 3D Printer System Software For Research Environments.” 2020. Web. 05 Mar 2021.

Vancouver:

Ramstedt CD. Modular 3D Printer System Software For Research Environments. [Internet] [Masters thesis]. Brigham Young University; 2020. [cited 2021 Mar 05]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9688&context=etd.

Council of Science Editors:

Ramstedt CD. Modular 3D Printer System Software For Research Environments. [Masters Thesis]. Brigham Young University; 2020. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9688&context=etd


Texas A&M University

18. Malave-Bonet, Javier. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.

Degree: MS, Computer Engineering, 2012, Texas A&M University

 Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused… (more)

Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C

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APA (6th Edition):

Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Chicago Manual of Style (16th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Masters Thesis, Texas A&M University. Accessed March 05, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

MLA Handbook (7th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 05 Mar 2021.

Vancouver:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Council of Science Editors:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662


University of Toronto

19. Nejatian, Maryam. Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells.

Degree: 2020, University of Toronto

Traditional in vitro alveolar epithelial cell (AEC) models lack physiological architectural cues required for regulating cell functionality. While 3D AEC organoids incorporate some characteristics of… (more)

Subjects/Keywords: alveoli; alveoli-on-a-chip; Lung-on-chip; microfluidic; organ-on-chip; 0541

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APA (6th Edition):

Nejatian, M. (2020). Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/103356

Chicago Manual of Style (16th Edition):

Nejatian, Maryam. “Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells.” 2020. Masters Thesis, University of Toronto. Accessed March 05, 2021. http://hdl.handle.net/1807/103356.

MLA Handbook (7th Edition):

Nejatian, Maryam. “Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells.” 2020. Web. 05 Mar 2021.

Vancouver:

Nejatian M. Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells. [Internet] [Masters thesis]. University of Toronto; 2020. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1807/103356.

Council of Science Editors:

Nejatian M. Design of a System with a 3D Biomimetic Stretchable Substrate for Maintenance and Study of Alveolar Epithelial Cells. [Masters Thesis]. University of Toronto; 2020. Available from: http://hdl.handle.net/1807/103356

20. Magnos Roberto Pizzoni. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.

Degree: 2010, Universidade do Vale do Itajaí

Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos… (more)

Subjects/Keywords: System-on-Chip; Network-on-Chip; Avaliação de desempenho; CIENCIA DA COMPUTACAO; Circuitos integrados; System-on-Chip; Network-on-Chip; Performance

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APA (6th Edition):

Pizzoni, M. R. (2010). PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Thesis, Universidade do Vale do Itajaí. Accessed March 05, 2021. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Web. 05 Mar 2021.

Vancouver:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2010. [cited 2021 Mar 05]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Thesis]. Universidade do Vale do Itajaí; 2010. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

21. Saravanakumar U. An investigation on macro and micro Architectures for network on chip;.

Degree: An investigation on macro and micro Architectures for network on chip, 2015, Anna University

As the technology scales down more processors or Processing newlineElements PEs are integrated in the same die and such technology is called as newlineMultiprocessor System(more)

Subjects/Keywords: Microarchitectural aims; Multiprocessor System on Chip; Network on Chip

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APA (6th Edition):

U, S. (2015). An investigation on macro and micro Architectures for network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Thesis, Anna University. Accessed March 05, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Web. 05 Mar 2021.

Vancouver:

U S. An investigation on macro and micro Architectures for network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 05]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

U S. An investigation on macro and micro Architectures for network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Viswanathan N. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.

Degree: Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters, 2015, Anna University

Three dimensional integration is one of the emerging techniques newlineto find solution for the global interconnect delay challenges faced in the newlineadvanced VLSI ULSI technology… (more)

Subjects/Keywords: Network on Chip; System on Chip; Through Silicon Via

Page 1

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APA (6th Edition):

N, V. (2015). Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Thesis, Anna University. Accessed March 05, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Web. 05 Mar 2021.

Vancouver:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 05]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

23. Maheswari M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;.

Degree: Novel approaches in the design of Reliable custom topology for Application specific network on chip, 2015, Anna University

Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed… (more)

Subjects/Keywords: Digital Signal Processor; Intellectual Property; Networks on Chip; System on Chip

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APA (6th Edition):

M, M. (2015). Novel approaches in the design of Reliable custom topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/39199

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed March 05, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/39199.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Web. 05 Mar 2021.

Vancouver:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 05]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39199

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

24. Maheswari M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;.

Degree: Novel approaches in the design of Reliable custom topology for Application specific network on chip, 2015, Anna University

Continued Technology scaling helps the designer to interconnect newlinelarge number of Intellectual Property IP blocks like Digital Signal Processor newline DSP hardware accelerator high speed… (more)

Subjects/Keywords: Digital Signal Processor; Networks on Chip; System on Chip

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APA (6th Edition):

M, M. (2015). Novel approaches in the design of Reliable custom topology for Application specific network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/41574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Thesis, Anna University. Accessed March 05, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/41574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

M, Maheswari. “Novel approaches in the design of Reliable custom topology for Application specific network on chip;.” 2015. Web. 05 Mar 2021.

Vancouver:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 05]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M M. Novel approaches in the design of Reliable custom topology for Application specific network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

25. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: PhD, Computer Engineering, 2012, Texas A&M University

 With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

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APA (6th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Chicago Manual of Style (16th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Doctoral Dissertation, Texas A&M University. Accessed March 05, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

MLA Handbook (7th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 05 Mar 2021.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526


University of New South Wales

26. Hussain, Mubashir. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.

Degree: Computer Science & Engineering, 2018, University of New South Wales

 Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system(more)

Subjects/Keywords: System-on-Chip; Hardware Trojan; Network-on-Chip; Hardware Security

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APA (6th Edition):

Hussain, M. (2018). Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Doctoral Dissertation, University of New South Wales. Accessed March 05, 2021. http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

MLA Handbook (7th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Web. 05 Mar 2021.

Vancouver:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2021 Mar 05]. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

Council of Science Editors:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true


University of Alberta

27. Martin, Benjamin R. CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip.

Degree: MS, Department of Electrical and Computer Engineering, 2011, University of Alberta

 One application for lab-on-a-chip (LOC) devices is performing miniaturized laboratory tests. These devices would be ideal for point-of-care medical diagnostic applications; however, many still rely… (more)

Subjects/Keywords: Capillary Electrophoresis; Lab-on-a-chip

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APA (6th Edition):

Martin, B. R. (2011). CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/2r36tz867

Chicago Manual of Style (16th Edition):

Martin, Benjamin R. “CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip.” 2011. Masters Thesis, University of Alberta. Accessed March 05, 2021. https://era.library.ualberta.ca/files/2r36tz867.

MLA Handbook (7th Edition):

Martin, Benjamin R. “CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip.” 2011. Web. 05 Mar 2021.

Vancouver:

Martin BR. CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip. [Internet] [Masters thesis]. University of Alberta; 2011. [cited 2021 Mar 05]. Available from: https://era.library.ualberta.ca/files/2r36tz867.

Council of Science Editors:

Martin BR. CMOS Instrumentation for Genetic Analysis Lab-on-a-Chip. [Masters Thesis]. University of Alberta; 2011. Available from: https://era.library.ualberta.ca/files/2r36tz867


University of Alberta

28. Behnam Dehkordi, Mohammad. Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies.

Degree: PhD, Department of Electrical and Computer Engineering, 2012, University of Alberta

 Genetic analysis is not widely used for disease diagnostics as it is costly and very labour/infrastructure intensive. We believe that by employing both microelectronic and… (more)

Subjects/Keywords: microelectronics; lab-on-a-chip; microfluidics; CMOS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Behnam Dehkordi, M. (2012). Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/h702q7124

Chicago Manual of Style (16th Edition):

Behnam Dehkordi, Mohammad. “Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies.” 2012. Doctoral Dissertation, University of Alberta. Accessed March 05, 2021. https://era.library.ualberta.ca/files/h702q7124.

MLA Handbook (7th Edition):

Behnam Dehkordi, Mohammad. “Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies.” 2012. Web. 05 Mar 2021.

Vancouver:

Behnam Dehkordi M. Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies. [Internet] [Doctoral dissertation]. University of Alberta; 2012. [cited 2021 Mar 05]. Available from: https://era.library.ualberta.ca/files/h702q7124.

Council of Science Editors:

Behnam Dehkordi M. Miniaturized genetic analysis systems based on microelectronic and microfluidic technologies. [Doctoral Dissertation]. University of Alberta; 2012. Available from: https://era.library.ualberta.ca/files/h702q7124


Texas A&M University

29. Guzman, Adrian. The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies.

Degree: MS, Electrical Engineering, 2012, Texas A&M University

 Microdroplet microfluidics has gained much interested in the past decade due to its ability to conduct a wide variety of biological and microfluidic experiments with… (more)

Subjects/Keywords: microdroplet; electrocoalescence; bioreactor; lab on a chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Guzman, A. (2012). The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11773

Chicago Manual of Style (16th Edition):

Guzman, Adrian. “The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies.” 2012. Masters Thesis, Texas A&M University. Accessed March 05, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11773.

MLA Handbook (7th Edition):

Guzman, Adrian. “The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies.” 2012. Web. 05 Mar 2021.

Vancouver:

Guzman A. The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11773.

Council of Science Editors:

Guzman A. The Development of a High-throughput Microdroplet Bioreactor Device for Microbial Studies. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11773


University of Waterloo

30. Mao, Shinong. Development of a Novel Microwave Sensing System for Lab on a Chip Applications.

Degree: 2018, University of Waterloo

 Microwave technology presents tremendous potential as a remote-sensing technology for a wide range of applications spanning from life science research to food industries, pharmaceutical research,… (more)

Subjects/Keywords: Microwave Sensing; Lab on a Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mao, S. (2018). Development of a Novel Microwave Sensing System for Lab on a Chip Applications. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14271

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mao, Shinong. “Development of a Novel Microwave Sensing System for Lab on a Chip Applications.” 2018. Thesis, University of Waterloo. Accessed March 05, 2021. http://hdl.handle.net/10012/14271.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mao, Shinong. “Development of a Novel Microwave Sensing System for Lab on a Chip Applications.” 2018. Web. 05 Mar 2021.

Vancouver:

Mao S. Development of a Novel Microwave Sensing System for Lab on a Chip Applications. [Internet] [Thesis]. University of Waterloo; 2018. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/10012/14271.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mao S. Development of a Novel Microwave Sensing System for Lab on a Chip Applications. [Thesis]. University of Waterloo; 2018. Available from: http://hdl.handle.net/10012/14271

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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