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University: Virginia Tech

You searched for subject:(System on Chip). Showing records 1 – 12 of 12 total matches.

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Virginia Tech

1. Burrow, Ryan David. Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 Complex modern systems, from unmanned aircraft system to industrial plants are almost always controlled digitally. These digital control systems (DCSes) need to be verified for… (more)

Subjects/Keywords: digital control system; programmable system-on-chip; model checking; input/output processor; malware resilience

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APA (6th Edition):

Burrow, R. D. (2019). Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/89903

Chicago Manual of Style (16th Edition):

Burrow, Ryan David. “Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms.” 2019. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/89903.

MLA Handbook (7th Edition):

Burrow, Ryan David. “Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms.” 2019. Web. 18 Jan 2020.

Vancouver:

Burrow RD. Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/89903.

Council of Science Editors:

Burrow RD. Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/89903


Virginia Tech

2. Bucciero, Mark Benjamin. The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer.

Degree: MS, Electrical and Computer Engineering, 2004, Virginia Tech

 Current processor designs use additional transistors to add functionality that improves performance. These features tend to exploit instruction level parallelism. However, a point of diminishing… (more)

Subjects/Keywords: system on chip; single chip computer; SCMP; node; Processor; parallel

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APA (6th Edition):

Bucciero, M. B. (2004). The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/9968

Chicago Manual of Style (16th Edition):

Bucciero, Mark Benjamin. “The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer.” 2004. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/9968.

MLA Handbook (7th Edition):

Bucciero, Mark Benjamin. “The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer.” 2004. Web. 18 Jan 2020.

Vancouver:

Bucciero MB. The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer. [Internet] [Masters thesis]. Virginia Tech; 2004. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/9968.

Council of Science Editors:

Bucciero MB. The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer. [Masters Thesis]. Virginia Tech; 2004. Available from: http://hdl.handle.net/10919/9968


Virginia Tech

3. Guo, Xu. Secure and Efficient Implementations of Cryptographic Primitives.

Degree: PhD, Electrical and Computer Engineering, 2012, Virginia Tech

 Nowadays pervasive computing opens up many new challenges. Personal and sensitive data and computations are distributed over a wide range of computing devices. This presents… (more)

Subjects/Keywords: Block Cipher; Side-Channel Attacks; SHA-3; Hash Function; System-on-Chip; Cryptographic Coprocessor; Elliptic Curve Cryptography; Fault Attacks

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APA (6th Edition):

Guo, X. (2012). Secure and Efficient Implementations of Cryptographic Primitives. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/27702

Chicago Manual of Style (16th Edition):

Guo, Xu. “Secure and Efficient Implementations of Cryptographic Primitives.” 2012. Doctoral Dissertation, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/27702.

MLA Handbook (7th Edition):

Guo, Xu. “Secure and Efficient Implementations of Cryptographic Primitives.” 2012. Web. 18 Jan 2020.

Vancouver:

Guo X. Secure and Efficient Implementations of Cryptographic Primitives. [Internet] [Doctoral dissertation]. Virginia Tech; 2012. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/27702.

Council of Science Editors:

Guo X. Secure and Efficient Implementations of Cryptographic Primitives. [Doctoral Dissertation]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/27702


Virginia Tech

4. Gunjal, Abhinav Shivram. Trusted Software Updates for Secure Enclaves in Industrial Control Systems.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 Industrial Control Systems (ICSs) manage critical infrastructures such as water treatment facilities, petroleum refineries, and power plants. ICSs are networked through Information Technology (IT) infrastructure… (more)

Subjects/Keywords: Industrial control systems; programmable logic controller; industrial control systems security; secure enclaves; software updates; configurable system-on-chip

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APA (6th Edition):

Gunjal, A. S. (2017). Trusted Software Updates for Secure Enclaves in Industrial Control Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/79130

Chicago Manual of Style (16th Edition):

Gunjal, Abhinav Shivram. “Trusted Software Updates for Secure Enclaves in Industrial Control Systems.” 2017. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/79130.

MLA Handbook (7th Edition):

Gunjal, Abhinav Shivram. “Trusted Software Updates for Secure Enclaves in Industrial Control Systems.” 2017. Web. 18 Jan 2020.

Vancouver:

Gunjal AS. Trusted Software Updates for Secure Enclaves in Industrial Control Systems. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/79130.

Council of Science Editors:

Gunjal AS. Trusted Software Updates for Secure Enclaves in Industrial Control Systems. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/79130


Virginia Tech

5. Adhipathi, Pradeep. Model based approach to Hardware/ Software Partitioning of SOC Designs.

Degree: MS, Electrical and Computer Engineering, 2003, Virginia Tech

 As the IT industry marks a paradigm shift from the traditional system design model to System-On-Chip (SOC) design, the design of custom hardware, embedded processors… (more)

Subjects/Keywords: hardware modeling; partitioning; system on chip; co-design

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APA (6th Edition):

Adhipathi, P. (2003). Model based approach to Hardware/ Software Partitioning of SOC Designs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/9986

Chicago Manual of Style (16th Edition):

Adhipathi, Pradeep. “Model based approach to Hardware/ Software Partitioning of SOC Designs.” 2003. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/9986.

MLA Handbook (7th Edition):

Adhipathi, Pradeep. “Model based approach to Hardware/ Software Partitioning of SOC Designs.” 2003. Web. 18 Jan 2020.

Vancouver:

Adhipathi P. Model based approach to Hardware/ Software Partitioning of SOC Designs. [Internet] [Masters thesis]. Virginia Tech; 2003. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/9986.

Council of Science Editors:

Adhipathi P. Model based approach to Hardware/ Software Partitioning of SOC Designs. [Masters Thesis]. Virginia Tech; 2003. Available from: http://hdl.handle.net/10919/9986


Virginia Tech

6. Sagisi, Joseph Lozano. HE-MT6D: A Network Security Processor with Hardware Engine for Moving Target IPv6 Defense (MT6D) over 1 Gbps IEEE 802.3 Ethernet.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 Traditional static network addressing allows attackers the incredible advantage of taking time to plan and execute attacks against a network. To counter, Moving Target IPv6… (more)

Subjects/Keywords: IPv6 Security; Moving Target Defense; Network Security Processor; FPGA; Moving Target IPv6 Defense; System on Chip; Packet Processor

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APA (6th Edition):

Sagisi, J. L. (2017). HE-MT6D: A Network Security Processor with Hardware Engine for Moving Target IPv6 Defense (MT6D) over 1 Gbps IEEE 802.3 Ethernet. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/86789

Chicago Manual of Style (16th Edition):

Sagisi, Joseph Lozano. “HE-MT6D: A Network Security Processor with Hardware Engine for Moving Target IPv6 Defense (MT6D) over 1 Gbps IEEE 802.3 Ethernet.” 2017. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/86789.

MLA Handbook (7th Edition):

Sagisi, Joseph Lozano. “HE-MT6D: A Network Security Processor with Hardware Engine for Moving Target IPv6 Defense (MT6D) over 1 Gbps IEEE 802.3 Ethernet.” 2017. Web. 18 Jan 2020.

Vancouver:

Sagisi JL. HE-MT6D: A Network Security Processor with Hardware Engine for Moving Target IPv6 Defense (MT6D) over 1 Gbps IEEE 802.3 Ethernet. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/86789.

Council of Science Editors:

Sagisi JL. HE-MT6D: A Network Security Processor with Hardware Engine for Moving Target IPv6 Defense (MT6D) over 1 Gbps IEEE 802.3 Ethernet. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/86789


Virginia Tech

7. La Fratta, Patrick Anthony. Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology.

Degree: MS, Electrical and Computer Engineering, 2005, Virginia Tech

  As single-chip systems are predicted to soon contain over a billion transistors, design methodologies are evolving dramatically to account for the fast evolution of… (more)

Subjects/Keywords: Parallel Computing; Methodology; System-on-a-Chip; SCMP; System-level Design

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APA (6th Edition):

La Fratta, P. A. (2005). Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32424

Chicago Manual of Style (16th Edition):

La Fratta, Patrick Anthony. “Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology.” 2005. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/32424.

MLA Handbook (7th Edition):

La Fratta, Patrick Anthony. “Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology.” 2005. Web. 18 Jan 2020.

Vancouver:

La Fratta PA. Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology. [Internet] [Masters thesis]. Virginia Tech; 2005. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/32424.

Council of Science Editors:

La Fratta PA. Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology. [Masters Thesis]. Virginia Tech; 2005. Available from: http://hdl.handle.net/10919/32424


Virginia Tech

8. Gold, Brian. Balancing Performance, Area, and Power in an On-Chip Network.

Degree: MS, Electrical and Computer Engineering, 2003, Virginia Tech

 Several trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire… (more)

Subjects/Keywords: area; virtual channels; SCMP; power; network; router; crossbar switch; single chip computer; message passing; system on chip

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APA (6th Edition):

Gold, B. (2003). Balancing Performance, Area, and Power in an On-Chip Network. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34137

Chicago Manual of Style (16th Edition):

Gold, Brian. “Balancing Performance, Area, and Power in an On-Chip Network.” 2003. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/34137.

MLA Handbook (7th Edition):

Gold, Brian. “Balancing Performance, Area, and Power in an On-Chip Network.” 2003. Web. 18 Jan 2020.

Vancouver:

Gold B. Balancing Performance, Area, and Power in an On-Chip Network. [Internet] [Masters thesis]. Virginia Tech; 2003. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/34137.

Council of Science Editors:

Gold B. Balancing Performance, Area, and Power in an On-Chip Network. [Masters Thesis]. Virginia Tech; 2003. Available from: http://hdl.handle.net/10919/34137


Virginia Tech

9. Mathaikutty, Deepak Abraham. Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design.

Degree: PhD, Electrical and Computer Engineering, 2007, Virginia Tech

 This dissertation addresses two important problems in reusing intellectual properties (IPs) in the form of reusable design or verification components. The first problem is associated… (more)

Subjects/Keywords: ESTEREL; SystemC; System On Chip; Microprocessor; Metamodeling; Model-driven Design and Validation; Type inference; Reflection; Metamodel; Coverage metric

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APA (6th Edition):

Mathaikutty, D. A. (2007). Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29598

Chicago Manual of Style (16th Edition):

Mathaikutty, Deepak Abraham. “Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design.” 2007. Doctoral Dissertation, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/29598.

MLA Handbook (7th Edition):

Mathaikutty, Deepak Abraham. “Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design.” 2007. Web. 18 Jan 2020.

Vancouver:

Mathaikutty DA. Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design. [Internet] [Doctoral dissertation]. Virginia Tech; 2007. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/29598.

Council of Science Editors:

Mathaikutty DA. Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design. [Doctoral Dissertation]. Virginia Tech; 2007. Available from: http://hdl.handle.net/10919/29598

10. Franklin, Zane Ryan. Using High-level Synthesis to Predict and Preempt Attacks on Industrial Control Systems.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 As the rate and severity of malicious software attacks have escalated, industrial control systems (ICSes) have emerged as a particularly vulnerable target. ICSes govern the… (more)

Subjects/Keywords: Industrial control systems; security; reconfigurable platform; high-level synthesis; system-on-chip

…embedded processor lends itself well to a system-on-chip (SoC) design. This work… …measures. Chapter 3 describes the target platform as well as the general system-on-chip design… …distinct, lends itself well to a system-on-chip (SoC) implementation. Because of the… …of hardware and software, a programmable SoC is even more appropriate. A system-on-chip… …Programmable System-on-Chip Overview 17 Target Platform Xilinx’s Zynq-7000 SoC is divided into two… 

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APA (6th Edition):

Franklin, Z. R. (2014). Using High-level Synthesis to Predict and Preempt Attacks on Industrial Control Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/47491

Chicago Manual of Style (16th Edition):

Franklin, Zane Ryan. “Using High-level Synthesis to Predict and Preempt Attacks on Industrial Control Systems.” 2014. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/47491.

MLA Handbook (7th Edition):

Franklin, Zane Ryan. “Using High-level Synthesis to Predict and Preempt Attacks on Industrial Control Systems.” 2014. Web. 18 Jan 2020.

Vancouver:

Franklin ZR. Using High-level Synthesis to Predict and Preempt Attacks on Industrial Control Systems. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/47491.

Council of Science Editors:

Franklin ZR. Using High-level Synthesis to Predict and Preempt Attacks on Industrial Control Systems. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/47491

11. Raghuraman, Shashank. Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 The proliferation of embedded smart devices for the Internet-of-Things necessitates a constant search for smaller and power-efficient hardware. The need to ensure security of such… (more)

Subjects/Keywords: Logic synthesis; Cryptographic hardware; Circuit minimization; Leon-3; System-on-Chip; Authenticated encryption hardware

…of System-on-Chip integration on the area, power, and performance of ciphers for… …area, delay, and power consumption of logic-minimized circuits on chip. • Analyzed the impact… …integration on Authenticated Encryption Ciphers 81 5.1 Introduction… …primarily require reduction in silicon area. On the other hand, shared applications in the cloud… …eventually lead to research that predominantly focuses on minimizing the logic complexity of… 

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APA (6th Edition):

Raghuraman, S. (2019). Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/91462

Chicago Manual of Style (16th Edition):

Raghuraman, Shashank. “Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation.” 2019. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/91462.

MLA Handbook (7th Edition):

Raghuraman, Shashank. “Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation.” 2019. Web. 18 Jan 2020.

Vancouver:

Raghuraman S. Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/91462.

Council of Science Editors:

Raghuraman S. Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/91462

12. Chiluvuri, Nayana Teja. A Trusted Autonomic Architecture to Safeguard Cyber-Physical Control Leaf Nodes and Protect Process Integrity.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Cyber-physical systems are networked through IT infrastructure and susceptible to malware. Threats targeting process control are much more safety-critical than traditional computing systems since they… (more)

Subjects/Keywords: Process control systems; cyber-physical systems; autonomic systems; programmable logic controller; remote terminal unit; human-machine interface; FPGA; trust; configurable system-on-chip; heterogeneous computing; high-level synthesis

…perceptron SoC System-on-chip MMU Memory management unit MSR Machine status register OS Operating… …realized on a configurable system-on-chip (SoC) platform for a rotary inverted pendulum… …guards on the system is located within the IOI. Trust is essential in the implementation of… …Hierarchical topology of a DCS or SCADA system. . . . . . . . . . . . . . . 9 3.1 The control… …leaf nodes with TAIGA. . . . . . . . . . . . . . . . . 20 3.4 TAIGA’s realization on a… 

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APA (6th Edition):

Chiluvuri, N. T. (2015). A Trusted Autonomic Architecture to Safeguard Cyber-Physical Control Leaf Nodes and Protect Process Integrity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/56572

Chicago Manual of Style (16th Edition):

Chiluvuri, Nayana Teja. “A Trusted Autonomic Architecture to Safeguard Cyber-Physical Control Leaf Nodes and Protect Process Integrity.” 2015. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/56572.

MLA Handbook (7th Edition):

Chiluvuri, Nayana Teja. “A Trusted Autonomic Architecture to Safeguard Cyber-Physical Control Leaf Nodes and Protect Process Integrity.” 2015. Web. 18 Jan 2020.

Vancouver:

Chiluvuri NT. A Trusted Autonomic Architecture to Safeguard Cyber-Physical Control Leaf Nodes and Protect Process Integrity. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/56572.

Council of Science Editors:

Chiluvuri NT. A Trusted Autonomic Architecture to Safeguard Cyber-Physical Control Leaf Nodes and Protect Process Integrity. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/56572

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