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Dates: 2010 – 2014

You searched for subject:(System on Chip). Showing records 1 – 30 of 99 total matches.

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University of Manitoba

1. Cook, Darcy Philip. A multiprocessng system-on-chip framework targeting stream-oriented applications.

Degree: Electrical and Computer Engineering, 2011, University of Manitoba

 Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be… (more)

Subjects/Keywords: system-on-chip; multiprocessing

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APA (6th Edition):

Cook, D. P. (2011). A multiprocessng system-on-chip framework targeting stream-oriented applications. (Masters Thesis). University of Manitoba. Retrieved from http://hdl.handle.net/1993/4383

Chicago Manual of Style (16th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Masters Thesis, University of Manitoba. Accessed January 21, 2020. http://hdl.handle.net/1993/4383.

MLA Handbook (7th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Web. 21 Jan 2020.

Vancouver:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Internet] [Masters thesis]. University of Manitoba; 2011. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/1993/4383.

Council of Science Editors:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Masters Thesis]. University of Manitoba; 2011. Available from: http://hdl.handle.net/1993/4383


Texas A&M University

2. Malave-Bonet, Javier. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.

Degree: 2012, Texas A&M University

 Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused… (more)

Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C

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APA (6th Edition):

Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Thesis, Texas A&M University. Accessed January 21, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 21 Jan 2020.

Vancouver:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Magnos Roberto Pizzoni. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.

Degree: 2010, Universidade do Vale do Itajaí

Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos… (more)

Subjects/Keywords: System-on-Chip; Network-on-Chip; Avaliação de desempenho; CIENCIA DA COMPUTACAO; Circuitos integrados; System-on-Chip; Network-on-Chip; Performance

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APA (6th Edition):

Pizzoni, M. R. (2010). PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Thesis, Universidade do Vale do Itajaí. Accessed January 21, 2020. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Web. 21 Jan 2020.

Vancouver:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2010. [cited 2020 Jan 21]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Thesis]. Universidade do Vale do Itajaí; 2010. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

4. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: 2012, Texas A&M University

 With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

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APA (6th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Thesis, Texas A&M University. Accessed January 21, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 21 Jan 2020.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

5. Escudero Martínez, M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.

Degree: 2010, Delft University of Technology

 Prototyping Systems on Chip (SoC) on FPGA technology improves the time that the de- signer needs to spend in the verification stage when developing new… (more)

Subjects/Keywords: network on chip; NoC; system on chip; SoC; bridge; FPGA; prototyping

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APA (6th Edition):

Escudero Martínez, M. (2010). An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847

Chicago Manual of Style (16th Edition):

Escudero Martínez, M. “An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.” 2010. Masters Thesis, Delft University of Technology. Accessed January 21, 2020. http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847.

MLA Handbook (7th Edition):

Escudero Martínez, M. “An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.” 2010. Web. 21 Jan 2020.

Vancouver:

Escudero Martínez M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 Jan 21]. Available from: http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847.

Council of Science Editors:

Escudero Martínez M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847


University of New South Wales

6. Avnit, Karin. Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters.

Degree: Computer Science & Engineering, 2010, University of New South Wales

 The field of chip design is characterized by contradictory pressures to reduce time-to-market and maintain a high level of reliability. As a result, module reuse… (more)

Subjects/Keywords: System-on-Chip; Formal Methods; Protocol converter

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APA (6th Edition):

Avnit, K. (2010). Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/44701 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8001/SOURCE01?view=true

Chicago Manual of Style (16th Edition):

Avnit, Karin. “Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters.” 2010. Doctoral Dissertation, University of New South Wales. Accessed January 21, 2020. http://handle.unsw.edu.au/1959.4/44701 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8001/SOURCE01?view=true.

MLA Handbook (7th Edition):

Avnit, Karin. “Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters.” 2010. Web. 21 Jan 2020.

Vancouver:

Avnit K. Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters. [Internet] [Doctoral dissertation]. University of New South Wales; 2010. [cited 2020 Jan 21]. Available from: http://handle.unsw.edu.au/1959.4/44701 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8001/SOURCE01?view=true.

Council of Science Editors:

Avnit K. Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters. [Doctoral Dissertation]. University of New South Wales; 2010. Available from: http://handle.unsw.edu.au/1959.4/44701 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8001/SOURCE01?view=true


University of Utah

7. You, Junbok. Design and optimization of asynchronous network-on-chip.

Degree: PhD, Electrical & Computer Engineering, 2011, University of Utah

 The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on… (more)

Subjects/Keywords: Asynchronous circuit design; Digital VLSI design; Interconnect system; Network-on-chip; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

You, J. (2011). Design and optimization of asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633

Chicago Manual of Style (16th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed January 21, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

MLA Handbook (7th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Web. 21 Jan 2020.

Vancouver:

You J. Design and optimization of asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2020 Jan 21]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

Council of Science Editors:

You J. Design and optimization of asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633


University of Utah

8. Gebhardt, Daniel J. Energy-efficient design of an asynchronous network-on-chip.

Degree: PhD, Computer Science, 2011, University of Utah

 Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are… (more)

Subjects/Keywords: Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip

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APA (6th Edition):

Gebhardt, D. J. (2011). Energy-efficient design of an asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Chicago Manual of Style (16th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed January 21, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

MLA Handbook (7th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Web. 21 Jan 2020.

Vancouver:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2020 Jan 21]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

Council of Science Editors:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871


Universidade do Rio Grande do Sul

9. Reinbrecht, Cezar Rodolfo Wedig. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.

Degree: 2012, Universidade do Rio Grande do Sul

Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas… (more)

Subjects/Keywords: Microeletrônica; MPSoCs; Network-on-chip; Sistemas embarcados; MPSoC; Interconnections; Adaptive architecture; System-on-chip

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APA (6th Edition):

Reinbrecht, C. R. W. (2012). Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/67148

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reinbrecht, Cezar Rodolfo Wedig. “Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed January 21, 2020. http://hdl.handle.net/10183/67148.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reinbrecht, Cezar Rodolfo Wedig. “Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs.” 2012. Web. 21 Jan 2020.

Vancouver:

Reinbrecht CRW. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/10183/67148.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reinbrecht CRW. Desenvolvimento e avaliação de redes-em-chip hierárquicas e reconfiguráveis para MPSoCs. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/67148

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oklahoma State University

10. Williams, Seth Adam. Benchmarking ARM-based Application Integrated Systems.

Degree: School of Electrical & Computer Engineering, 2011, Oklahoma State University

 ARM Holding Ltd. is in a very good position; by owning a very prolific instruction set architecture (named ARM) and licensing it to other companies… (more)

Subjects/Keywords: arm; embedded benchmarks; package-on-package; system-on-chip

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APA (6th Edition):

Williams, S. A. (2011). Benchmarking ARM-based Application Integrated Systems. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/10295

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Thesis, Oklahoma State University. Accessed January 21, 2020. http://hdl.handle.net/11244/10295.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Web. 21 Jan 2020.

Vancouver:

Williams SA. Benchmarking ARM-based Application Integrated Systems. [Internet] [Thesis]. Oklahoma State University; 2011. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/11244/10295.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Williams SA. Benchmarking ARM-based Application Integrated Systems. [Thesis]. Oklahoma State University; 2011. Available from: http://hdl.handle.net/11244/10295

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

11. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: 2010, Indian Institute of Science

 A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

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APA (6th Edition):

Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed January 21, 2020. http://hdl.handle.net/2005/1408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 21 Jan 2020.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/2005/1408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://hdl.handle.net/2005/1408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

12. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: 2010, Indian Institute of Science

 A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed January 21, 2020. http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 21 Jan 2020.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Jan 21]. Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

13. Basavaraj, T. NoC Design & Optimization of Multicore Media Processors.

Degree: 2013, Indian Institute of Science

 Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of… (more)

Subjects/Keywords: Network-On-Chip (NOC); Quality of Service (QOS); Label Switched Network On Chip (LS-NoC); Chip Multiprocessor Designs; Multicore Media Processors; Network-On-Chip (NOC) - Design and Construction; System on Chip (SoC); Link Microarchitectural Exploration, Network-on-Chip (NOC); Tile Exploration - Chip Multiprocessors (CMP); Ford-Fulkerson’s MaxFlow Algorithm; Flow Algorithm; Network-on-Chips; On-Chip Interconnection Networks; Microarchitecture Exploration; Computer Science

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APA (6th Edition):

Basavaraj, T. (2013). NoC Design & Optimization of Multicore Media Processors. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Thesis, Indian Institute of Science. Accessed January 21, 2020. http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Web. 21 Jan 2020.

Vancouver:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 Jan 21]. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

14. Araújo, Sílvio Roberto Fernandes de. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .

Degree: 2012, Universidade do Rio Grande do Norte

 It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features… (more)

Subjects/Keywords: Multiprocessador em chip; MPSoC; Redes em chip; NoC; Algoritmo spiral complement; Sistema IPNoSys; Multiprocessor on chip; MPSoC; Network-on-chip; NoC; Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2012). Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . (Doctoral Dissertation). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17948

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Doctoral Dissertation, Universidade do Rio Grande do Norte. Accessed January 21, 2020. http://repositorio.ufrn.br/handle/123456789/17948.

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Web. 21 Jan 2020.

Vancouver:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Internet] [Doctoral dissertation]. Universidade do Rio Grande do Norte; 2012. [cited 2020 Jan 21]. Available from: http://repositorio.ufrn.br/handle/123456789/17948.

Council of Science Editors:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Doctoral Dissertation]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/17948


Universidade do Rio Grande do Norte

15. Araújo, Sílvio Roberto Fernandes de. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .

Degree: 2012, Universidade do Rio Grande do Norte

 It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features… (more)

Subjects/Keywords: Multiprocessador em chip; MPSoC; Redes em chip; NoC; Algoritmo spiral complement; Sistema IPNoSys; Multiprocessor on chip; MPSoC; Network-on-chip; NoC; Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2012). Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Thesis, Universidade do Rio Grande do Norte. Accessed January 21, 2020. http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Web. 21 Jan 2020.

Vancouver:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2012. [cited 2020 Jan 21]. Available from: http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Thesis]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

16. Meakin, Benjamin LaSalle. Multicore system design with XUM: the extensible Utah multicore project.

Degree: MS;, College of Engineering; (School of);, 2010, University of Utah

 With the advent of aggressively scaled multicore processors utilizing increasingly complex on-chip communication architectures, the need for efficient and standardized interfaces between parallel programs and… (more)

Subjects/Keywords: Embedded system; Message passing; Multicore; On-chip network

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Meakin, B. L. (2010). Multicore system design with XUM: the extensible Utah multicore project. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/252/rec/795

Chicago Manual of Style (16th Edition):

Meakin, Benjamin LaSalle. “Multicore system design with XUM: the extensible Utah multicore project.” 2010. Masters Thesis, University of Utah. Accessed January 21, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/252/rec/795.

MLA Handbook (7th Edition):

Meakin, Benjamin LaSalle. “Multicore system design with XUM: the extensible Utah multicore project.” 2010. Web. 21 Jan 2020.

Vancouver:

Meakin BL. Multicore system design with XUM: the extensible Utah multicore project. [Internet] [Masters thesis]. University of Utah; 2010. [cited 2020 Jan 21]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/252/rec/795.

Council of Science Editors:

Meakin BL. Multicore system design with XUM: the extensible Utah multicore project. [Masters Thesis]. University of Utah; 2010. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/252/rec/795


Penn State University

17. Park, Sungho. system-on-chip integration of heterogeneous accelerators for perceptual computing.

Degree: PhD, Computer Science and Engineering, 2013, Penn State University

 Traditional microprocessor design has seen radical shifts over the past few years. The challenges of excessive power consumption led to the shift from faster and… (more)

Subjects/Keywords: perceptual computing; system-on-chip; heterogeneous accelerator; stream processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, S. (2013). system-on-chip integration of heterogeneous accelerators for perceptual computing. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/19218

Chicago Manual of Style (16th Edition):

Park, Sungho. “system-on-chip integration of heterogeneous accelerators for perceptual computing.” 2013. Doctoral Dissertation, Penn State University. Accessed January 21, 2020. https://etda.libraries.psu.edu/catalog/19218.

MLA Handbook (7th Edition):

Park, Sungho. “system-on-chip integration of heterogeneous accelerators for perceptual computing.” 2013. Web. 21 Jan 2020.

Vancouver:

Park S. system-on-chip integration of heterogeneous accelerators for perceptual computing. [Internet] [Doctoral dissertation]. Penn State University; 2013. [cited 2020 Jan 21]. Available from: https://etda.libraries.psu.edu/catalog/19218.

Council of Science Editors:

Park S. system-on-chip integration of heterogeneous accelerators for perceptual computing. [Doctoral Dissertation]. Penn State University; 2013. Available from: https://etda.libraries.psu.edu/catalog/19218


University of Toronto

18. Smolyakov, Vadim. A Fault-tolerant Strategy for Embedded-memory SoC OFDM Receivers.

Degree: 2012, University of Toronto

The International Technology Roadmap for Semiconductors projects that embedded memories will occupy increasing System-on-Chip area. The growing density of integration increases the likelihood of fabrication… (more)

Subjects/Keywords: Fault-Tolerance; Embedded-Memory; System-on-Chip; Baseband Signal Processing; 0544

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Smolyakov, V. (2012). A Fault-tolerant Strategy for Embedded-memory SoC OFDM Receivers. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/42901

Chicago Manual of Style (16th Edition):

Smolyakov, Vadim. “A Fault-tolerant Strategy for Embedded-memory SoC OFDM Receivers.” 2012. Masters Thesis, University of Toronto. Accessed January 21, 2020. http://hdl.handle.net/1807/42901.

MLA Handbook (7th Edition):

Smolyakov, Vadim. “A Fault-tolerant Strategy for Embedded-memory SoC OFDM Receivers.” 2012. Web. 21 Jan 2020.

Vancouver:

Smolyakov V. A Fault-tolerant Strategy for Embedded-memory SoC OFDM Receivers. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/1807/42901.

Council of Science Editors:

Smolyakov V. A Fault-tolerant Strategy for Embedded-memory SoC OFDM Receivers. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/42901


University of Guelph

19. Best, Joel. Real-Time Operating System Hardware Extension Core for System-on-Chip Designs .

Degree: 2013, University of Guelph

 This thesis presents a real-time operating system hardware extension core which supports the integration of hardware accelerators into real-time system-on-chip designs as hardware tasks. The… (more)

Subjects/Keywords: Real-Time Systems; System-on-Chip; Hardware Accelerators; Reconfigurable Logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Best, J. (2013). Real-Time Operating System Hardware Extension Core for System-on-Chip Designs . (Thesis). University of Guelph. Retrieved from https://atrium.lib.uoguelph.ca/xmlui/handle/10214/5257

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Best, Joel. “Real-Time Operating System Hardware Extension Core for System-on-Chip Designs .” 2013. Thesis, University of Guelph. Accessed January 21, 2020. https://atrium.lib.uoguelph.ca/xmlui/handle/10214/5257.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Best, Joel. “Real-Time Operating System Hardware Extension Core for System-on-Chip Designs .” 2013. Web. 21 Jan 2020.

Vancouver:

Best J. Real-Time Operating System Hardware Extension Core for System-on-Chip Designs . [Internet] [Thesis]. University of Guelph; 2013. [cited 2020 Jan 21]. Available from: https://atrium.lib.uoguelph.ca/xmlui/handle/10214/5257.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Best J. Real-Time Operating System Hardware Extension Core for System-on-Chip Designs . [Thesis]. University of Guelph; 2013. Available from: https://atrium.lib.uoguelph.ca/xmlui/handle/10214/5257

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

20. Matos, Débora da Silva Motta. Interfaces parametrizáveis para aplicações interconectadas por uma rede-em-chip.

Degree: 2010, Universidade do Rio Grande do Sul

As redes-em-chip (NoCs) surgiram como uma alternativa aos atuais problemas de interconexão decorrentes da redução da escala de tecnologia de fabricação de circuitos integrados. O… (more)

Subjects/Keywords: Network interfaces; Microeletrônica; Network-on-chip; Testes : Sistemas digitais; H.264 video decoder; Interconnection solutions; Processing elements; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Matos, D. d. S. M. (2010). Interfaces parametrizáveis para aplicações interconectadas por uma rede-em-chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/27659

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matos, Débora da Silva Motta. “Interfaces parametrizáveis para aplicações interconectadas por uma rede-em-chip.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed January 21, 2020. http://hdl.handle.net/10183/27659.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matos, Débora da Silva Motta. “Interfaces parametrizáveis para aplicações interconectadas por uma rede-em-chip.” 2010. Web. 21 Jan 2020.

Vancouver:

Matos DdSM. Interfaces parametrizáveis para aplicações interconectadas por uma rede-em-chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/10183/27659.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matos DdSM. Interfaces parametrizáveis para aplicações interconectadas por uma rede-em-chip. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/27659

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

21. Kunz, Leonardo. Memória transacional em hardware para sistemas embarcados multiprocessados conectados por redes-em-chip.

Degree: 2010, Universidade do Rio Grande do Sul

A Memória Transacional (TM) surgiu nos últimos anos como uma nova solução para sincronização em sistemas multiprocessados de memória compartilhada, permitindo explorar melhor o paralelismo… (more)

Subjects/Keywords: Microeletrônica; Hardware transactional memory; Sistemas embarcados; Multiprocessor system-on-chip; SoC; Network-on-chip; Embedded systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kunz, L. (2010). Memória transacional em hardware para sistemas embarcados multiprocessados conectados por redes-em-chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/28739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kunz, Leonardo. “Memória transacional em hardware para sistemas embarcados multiprocessados conectados por redes-em-chip.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed January 21, 2020. http://hdl.handle.net/10183/28739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kunz, Leonardo. “Memória transacional em hardware para sistemas embarcados multiprocessados conectados por redes-em-chip.” 2010. Web. 21 Jan 2020.

Vancouver:

Kunz L. Memória transacional em hardware para sistemas embarcados multiprocessados conectados por redes-em-chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/10183/28739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kunz L. Memória transacional em hardware para sistemas embarcados multiprocessados conectados por redes-em-chip. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/28739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

22. Verschoor, M. Design of a Crypto Core for Securing Intra System-on-Chip Communication:.

Degree: 2011, Delft University of Technology

 Interconnect centric security in multi core System-on-Chip (SoC) is an area of increasing concern. Monitoring and manipulation of the SoC interconnect yields great potential to… (more)

Subjects/Keywords: SoC; Security; Interconnect; NoC; System on Chip; Network on Chip; SoC-TLS; Cryptography; Message Authentication Code

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Verschoor, M. (2011). Design of a Crypto Core for Securing Intra System-on-Chip Communication:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:aab2a30f-3388-4d73-a6e4-7dee0c9c8903

Chicago Manual of Style (16th Edition):

Verschoor, M. “Design of a Crypto Core for Securing Intra System-on-Chip Communication:.” 2011. Masters Thesis, Delft University of Technology. Accessed January 21, 2020. http://resolver.tudelft.nl/uuid:aab2a30f-3388-4d73-a6e4-7dee0c9c8903.

MLA Handbook (7th Edition):

Verschoor, M. “Design of a Crypto Core for Securing Intra System-on-Chip Communication:.” 2011. Web. 21 Jan 2020.

Vancouver:

Verschoor M. Design of a Crypto Core for Securing Intra System-on-Chip Communication:. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2020 Jan 21]. Available from: http://resolver.tudelft.nl/uuid:aab2a30f-3388-4d73-a6e4-7dee0c9c8903.

Council of Science Editors:

Verschoor M. Design of a Crypto Core for Securing Intra System-on-Chip Communication:. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:aab2a30f-3388-4d73-a6e4-7dee0c9c8903

23. Salman, Abbas Ali Abulwohab. Miniaturised system for DNA analysis.

Degree: PhD, 2013, Teesside University

 The growing markets for analytical techniques in areas such as pathogen detection, clinical analysis, forensic investigation, environmental analysis and food analysis require the development of… (more)

Subjects/Keywords: 572.8; PLR shunting system; portable PCR device; DNA Analysis; miniaturisation; lab on a chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Salman, A. A. A. (2013). Miniaturised system for DNA analysis. (Doctoral Dissertation). Teesside University. Retrieved from http://hdl.handle.net/10149/316214

Chicago Manual of Style (16th Edition):

Salman, Abbas Ali Abulwohab. “Miniaturised system for DNA analysis.” 2013. Doctoral Dissertation, Teesside University. Accessed January 21, 2020. http://hdl.handle.net/10149/316214.

MLA Handbook (7th Edition):

Salman, Abbas Ali Abulwohab. “Miniaturised system for DNA analysis.” 2013. Web. 21 Jan 2020.

Vancouver:

Salman AAA. Miniaturised system for DNA analysis. [Internet] [Doctoral dissertation]. Teesside University; 2013. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/10149/316214.

Council of Science Editors:

Salman AAA. Miniaturised system for DNA analysis. [Doctoral Dissertation]. Teesside University; 2013. Available from: http://hdl.handle.net/10149/316214


University of Alberta

24. Ho, Sunny. VLSI Design and System Integration for a USB Genetic Amplification Platform.

Degree: MS, Department of Electrical and Computer Engineering, 2012, University of Alberta

 We demonstrate the feasibility of USB-powered portable genetic amplification. One of the central processes within medical or biological genetic methods is polymerase chain reaction (PCR).… (more)

Subjects/Keywords: lab-on-a-chip; VLSI; polymerase chain reaction; genetic amplification; microfluidic system; biomedical; USB

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ho, S. (2012). VLSI Design and System Integration for a USB Genetic Amplification Platform. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/1544bp58m

Chicago Manual of Style (16th Edition):

Ho, Sunny. “VLSI Design and System Integration for a USB Genetic Amplification Platform.” 2012. Masters Thesis, University of Alberta. Accessed January 21, 2020. https://era.library.ualberta.ca/files/1544bp58m.

MLA Handbook (7th Edition):

Ho, Sunny. “VLSI Design and System Integration for a USB Genetic Amplification Platform.” 2012. Web. 21 Jan 2020.

Vancouver:

Ho S. VLSI Design and System Integration for a USB Genetic Amplification Platform. [Internet] [Masters thesis]. University of Alberta; 2012. [cited 2020 Jan 21]. Available from: https://era.library.ualberta.ca/files/1544bp58m.

Council of Science Editors:

Ho S. VLSI Design and System Integration for a USB Genetic Amplification Platform. [Masters Thesis]. University of Alberta; 2012. Available from: https://era.library.ualberta.ca/files/1544bp58m


The Ohio State University

25. Liu, Wei. Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification.

Degree: PhD, Electrical and Computer Engineering, 2014, The Ohio State University

 In recent years, with the explosive increase of the wireless communication and consumer electronics products, the advanced system solutions which have powerful computation capability and… (more)

Subjects/Keywords: Electrical Engineering; Low Dropout Regulator, Intellectual Property , System On Chip, Verification, modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, W. (2014). Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1398967795

Chicago Manual of Style (16th Edition):

Liu, Wei. “Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification.” 2014. Doctoral Dissertation, The Ohio State University. Accessed January 21, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1398967795.

MLA Handbook (7th Edition):

Liu, Wei. “Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification.” 2014. Web. 21 Jan 2020.

Vancouver:

Liu W. Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification. [Internet] [Doctoral dissertation]. The Ohio State University; 2014. [cited 2020 Jan 21]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1398967795.

Council of Science Editors:

Liu W. Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification. [Doctoral Dissertation]. The Ohio State University; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1398967795


Universidade do Rio Grande do Sul

26. Bonatto, Alexsandro Cristóvão. Controle adaptativo para acesso à memória compartilhada em sistemas em chip.

Degree: 2014, Universidade do Rio Grande do Sul

Acessos simultâneos gerados por Elementos de Processamento (EP) contidos nos Sistemas em Chip (SoC) para um único canal de memória externa coloca desafios que requerem… (more)

Subjects/Keywords: Microeletrônica; Memory subsystem; Circuitos integrados; Integrated circuits; Memory hierarchy; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bonatto, A. C. (2014). Controle adaptativo para acesso à memória compartilhada em sistemas em chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/109193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bonatto, Alexsandro Cristóvão. “Controle adaptativo para acesso à memória compartilhada em sistemas em chip.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed January 21, 2020. http://hdl.handle.net/10183/109193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bonatto, Alexsandro Cristóvão. “Controle adaptativo para acesso à memória compartilhada em sistemas em chip.” 2014. Web. 21 Jan 2020.

Vancouver:

Bonatto AC. Controle adaptativo para acesso à memória compartilhada em sistemas em chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/10183/109193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bonatto AC. Controle adaptativo para acesso à memória compartilhada em sistemas em chip. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/109193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Massey University

27. Chou, Steven Chun-Wei. An investigation into the application of microfluidics to the analysis of chromosome conformation.

Degree: MS, Molecular BioScience, 2011, Massey University

 Ever since the discovery of DNA, biologists have been striving to unravel its mysteries. Many efforts have been made over the years to further our… (more)

Subjects/Keywords: Chromosome analysis; Lab-on-a-chip; Microfluidic system; Microfluidic chips; Chromosome interactions

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chou, S. C. (2011). An investigation into the application of microfluidics to the analysis of chromosome conformation. (Masters Thesis). Massey University. Retrieved from http://hdl.handle.net/10179/2804

Chicago Manual of Style (16th Edition):

Chou, Steven Chun-Wei. “An investigation into the application of microfluidics to the analysis of chromosome conformation.” 2011. Masters Thesis, Massey University. Accessed January 21, 2020. http://hdl.handle.net/10179/2804.

MLA Handbook (7th Edition):

Chou, Steven Chun-Wei. “An investigation into the application of microfluidics to the analysis of chromosome conformation.” 2011. Web. 21 Jan 2020.

Vancouver:

Chou SC. An investigation into the application of microfluidics to the analysis of chromosome conformation. [Internet] [Masters thesis]. Massey University; 2011. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/10179/2804.

Council of Science Editors:

Chou SC. An investigation into the application of microfluidics to the analysis of chromosome conformation. [Masters Thesis]. Massey University; 2011. Available from: http://hdl.handle.net/10179/2804


King Abdullah University of Science and Technology

28. Rojas, Jhonathan Prieto. Advanced Nanofabrication Process Development for Self-Powered System-on-Chip.

Degree: 2010, King Abdullah University of Science and Technology

 In this work the development of a Self-Powered System-On-Chip is explored by examining two components of process development in different perspectives. On one side, an… (more)

Subjects/Keywords: Self-Powered System-On-Chip; Novel sustainable energy component; Scalable nano-patterning

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rojas, J. P. (2010). Advanced Nanofabrication Process Development for Self-Powered System-on-Chip. (Thesis). King Abdullah University of Science and Technology. Retrieved from http://hdl.handle.net/10754/134734

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rojas, Jhonathan Prieto. “Advanced Nanofabrication Process Development for Self-Powered System-on-Chip.” 2010. Thesis, King Abdullah University of Science and Technology. Accessed January 21, 2020. http://hdl.handle.net/10754/134734.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rojas, Jhonathan Prieto. “Advanced Nanofabrication Process Development for Self-Powered System-on-Chip.” 2010. Web. 21 Jan 2020.

Vancouver:

Rojas JP. Advanced Nanofabrication Process Development for Self-Powered System-on-Chip. [Internet] [Thesis]. King Abdullah University of Science and Technology; 2010. [cited 2020 Jan 21]. Available from: http://hdl.handle.net/10754/134734.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rojas JP. Advanced Nanofabrication Process Development for Self-Powered System-on-Chip. [Thesis]. King Abdullah University of Science and Technology; 2010. Available from: http://hdl.handle.net/10754/134734

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Salman, Abbas Ali Abulwohab. Miniaturised system for DNA analysis.

Degree: PhD, 2013, Teesside University

 The growing markets for analytical techniques in areas such as pathogen detection, clinical analysis, forensic investigation, environmental analysis and food analysis require the development of… (more)

Subjects/Keywords: 572.8; PLR shunting system; portable PCR device; DNA Analysis; miniaturisation; lab on a chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Salman, A. A. A. (2013). Miniaturised system for DNA analysis. (Doctoral Dissertation). Teesside University. Retrieved from https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218

Chicago Manual of Style (16th Edition):

Salman, Abbas Ali Abulwohab. “Miniaturised system for DNA analysis.” 2013. Doctoral Dissertation, Teesside University. Accessed January 21, 2020. https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218.

MLA Handbook (7th Edition):

Salman, Abbas Ali Abulwohab. “Miniaturised system for DNA analysis.” 2013. Web. 21 Jan 2020.

Vancouver:

Salman AAA. Miniaturised system for DNA analysis. [Internet] [Doctoral dissertation]. Teesside University; 2013. [cited 2020 Jan 21]. Available from: https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218.

Council of Science Editors:

Salman AAA. Miniaturised system for DNA analysis. [Doctoral Dissertation]. Teesside University; 2013. Available from: https://research.tees.ac.uk/en/studentTheses/ab708af4-296f-4876-a559-66a287844cbb ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606218

30. Sepúlveda Flórez, Martha Johanna. Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança.

Degree: PhD, Microeletrônica, 2011, University of São Paulo

Os atuais sistemas eletrônicos desenvolvidos na forma de SoCs (Sistemas-sobre-Silício) são caracterizados pelo incremento de informação crítica que é capturada, armazenada e processada. Com a… (more)

Subjects/Keywords: Estrutura de comunicação; Network-on-Chip (NoC); Qualidade de serviços; Quality of Security Service (QoSS); Quality-of-Service (QoS); Redes; Security; Segurança; Silício (Sistemas; Projeto); System-on-Chip (SoC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sepúlveda Flórez, M. J. (2011). Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04112011-140055/ ;

Chicago Manual of Style (16th Edition):

Sepúlveda Flórez, Martha Johanna. “Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança.” 2011. Doctoral Dissertation, University of São Paulo. Accessed January 21, 2020. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04112011-140055/ ;.

MLA Handbook (7th Edition):

Sepúlveda Flórez, Martha Johanna. “Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança.” 2011. Web. 21 Jan 2020.

Vancouver:

Sepúlveda Flórez MJ. Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança. [Internet] [Doctoral dissertation]. University of São Paulo; 2011. [cited 2020 Jan 21]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04112011-140055/ ;.

Council of Science Editors:

Sepúlveda Flórez MJ. Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança. [Doctoral Dissertation]. University of São Paulo; 2011. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04112011-140055/ ;

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