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You searched for subject:(System on Chip). Showing records 1 – 30 of 107 total matches.

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University of Florida

1. Sadi, Mehdi Zahid. On-Chip Structures for Reliability Management of System-On-Chips.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Florida

 With aggressive technology scaling in the finfet era the transistor density per unit chip area has increased significantly over the past decade. As a result… (more)

Subjects/Keywords: reliability  – system-on-chip  – vlsi

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APA (6th Edition):

Sadi, M. Z. (2017). On-Chip Structures for Reliability Management of System-On-Chips. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0051010

Chicago Manual of Style (16th Edition):

Sadi, Mehdi Zahid. “On-Chip Structures for Reliability Management of System-On-Chips.” 2017. Doctoral Dissertation, University of Florida. Accessed January 29, 2020. http://ufdc.ufl.edu/UFE0051010.

MLA Handbook (7th Edition):

Sadi, Mehdi Zahid. “On-Chip Structures for Reliability Management of System-On-Chips.” 2017. Web. 29 Jan 2020.

Vancouver:

Sadi MZ. On-Chip Structures for Reliability Management of System-On-Chips. [Internet] [Doctoral dissertation]. University of Florida; 2017. [cited 2020 Jan 29]. Available from: http://ufdc.ufl.edu/UFE0051010.

Council of Science Editors:

Sadi MZ. On-Chip Structures for Reliability Management of System-On-Chips. [Doctoral Dissertation]. University of Florida; 2017. Available from: http://ufdc.ufl.edu/UFE0051010


Penn State University

2. Vaidyanathan, Balaji. RELIABILITY ANALYSIS AND OPTIMIZATION FOR.

Degree: PhD, Computer Science and Engineering, 2009, Penn State University

System-on-Chip occupies a major share of electronic market with products ranging from consumer electronics like cellphone, iPod, gaming machines, PDA, netbooks, smartbooks, and safety critical… (more)

Subjects/Keywords: circuit reliability; system-on-chip

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APA (6th Edition):

Vaidyanathan, B. (2009). RELIABILITY ANALYSIS AND OPTIMIZATION FOR. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/10443

Chicago Manual of Style (16th Edition):

Vaidyanathan, Balaji. “RELIABILITY ANALYSIS AND OPTIMIZATION FOR.” 2009. Doctoral Dissertation, Penn State University. Accessed January 29, 2020. https://etda.libraries.psu.edu/catalog/10443.

MLA Handbook (7th Edition):

Vaidyanathan, Balaji. “RELIABILITY ANALYSIS AND OPTIMIZATION FOR.” 2009. Web. 29 Jan 2020.

Vancouver:

Vaidyanathan B. RELIABILITY ANALYSIS AND OPTIMIZATION FOR. [Internet] [Doctoral dissertation]. Penn State University; 2009. [cited 2020 Jan 29]. Available from: https://etda.libraries.psu.edu/catalog/10443.

Council of Science Editors:

Vaidyanathan B. RELIABILITY ANALYSIS AND OPTIMIZATION FOR. [Doctoral Dissertation]. Penn State University; 2009. Available from: https://etda.libraries.psu.edu/catalog/10443


Texas A&M University

3. Malave-Bonet, Javier. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.

Degree: 2012, Texas A&M University

 Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused… (more)

Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C

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APA (6th Edition):

Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Thesis, Texas A&M University. Accessed January 29, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 29 Jan 2020.

Vancouver:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

4. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: 2012, Texas A&M University

 With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

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APA (6th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Thesis, Texas A&M University. Accessed January 29, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 29 Jan 2020.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

5. You, Junbok. Design and optimization of asynchronous network-on-chip.

Degree: PhD, Electrical & Computer Engineering, 2011, University of Utah

 The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on… (more)

Subjects/Keywords: Asynchronous circuit design; Digital VLSI design; Interconnect system; Network-on-chip; System-on-chip

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APA (6th Edition):

You, J. (2011). Design and optimization of asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633

Chicago Manual of Style (16th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed January 29, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

MLA Handbook (7th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Web. 29 Jan 2020.

Vancouver:

You J. Design and optimization of asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2020 Jan 29]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

Council of Science Editors:

You J. Design and optimization of asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633


University of Utah

6. Gebhardt, Daniel J. Energy-efficient design of an asynchronous network-on-chip.

Degree: PhD, Computer Science, 2011, University of Utah

 Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are… (more)

Subjects/Keywords: Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip

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APA (6th Edition):

Gebhardt, D. J. (2011). Energy-efficient design of an asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Chicago Manual of Style (16th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed January 29, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

MLA Handbook (7th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Web. 29 Jan 2020.

Vancouver:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2020 Jan 29]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

Council of Science Editors:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871


Washington State University

7. [No author]. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .

Degree: 2017, Washington State University

 In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and… (more)

Subjects/Keywords: Computer engineering; Big Data; Graph Analytics; MapReduce; Network-on-Chip; System-on-Chip; Wireless NoC

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APA (6th Edition):

author], [. (2017). COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/13038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .” 2017. Thesis, Washington State University. Accessed January 29, 2020. http://hdl.handle.net/2376/13038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .” 2017. Web. 29 Jan 2020.

Vancouver:

author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . [Internet] [Thesis]. Washington State University; 2017. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2376/13038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . [Thesis]. Washington State University; 2017. Available from: http://hdl.handle.net/2376/13038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oklahoma State University

8. Williams, Seth Adam. Benchmarking ARM-based Application Integrated Systems.

Degree: School of Electrical & Computer Engineering, 2011, Oklahoma State University

 ARM Holding Ltd. is in a very good position; by owning a very prolific instruction set architecture (named ARM) and licensing it to other companies… (more)

Subjects/Keywords: arm; embedded benchmarks; package-on-package; system-on-chip

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APA (6th Edition):

Williams, S. A. (2011). Benchmarking ARM-based Application Integrated Systems. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/10295

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Thesis, Oklahoma State University. Accessed January 29, 2020. http://hdl.handle.net/11244/10295.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Williams, Seth Adam. “Benchmarking ARM-based Application Integrated Systems.” 2011. Web. 29 Jan 2020.

Vancouver:

Williams SA. Benchmarking ARM-based Application Integrated Systems. [Internet] [Thesis]. Oklahoma State University; 2011. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/11244/10295.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Williams SA. Benchmarking ARM-based Application Integrated Systems. [Thesis]. Oklahoma State University; 2011. Available from: http://hdl.handle.net/11244/10295

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Irvine

9. Sarma, Santanu. Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.

Degree: Computer Science, 2016, University of California – Irvine

 Embedded systems are increasingly seeing the need for self-awareness to operate autonomously in the face of uncertainty and unpredictability in the environment, the applications they… (more)

Subjects/Keywords: Computer science; Chemical engineering; Cyber-Physical-System-on-Chip; Multiprocessor System-on-Chip; On-chip Machine Learning; Predictive Models; Self-Aware SoC; Smart Embedded Systems

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APA (6th Edition):

Sarma, S. (2016). Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/0578m1bz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sarma, Santanu. “Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.” 2016. Thesis, University of California – Irvine. Accessed January 29, 2020. http://www.escholarship.org/uc/item/0578m1bz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sarma, Santanu. “Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.” 2016. Web. 29 Jan 2020.

Vancouver:

Sarma S. Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform. [Internet] [Thesis]. University of California – Irvine; 2016. [cited 2020 Jan 29]. Available from: http://www.escholarship.org/uc/item/0578m1bz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sarma S. Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform. [Thesis]. University of California – Irvine; 2016. Available from: http://www.escholarship.org/uc/item/0578m1bz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

10. Meakin, Benjamin LaSalle. Multicore system design with XUM: the extensible Utah multicore project.

Degree: MS;, College of Engineering; (School of);, 2010, University of Utah

 With the advent of aggressively scaled multicore processors utilizing increasingly complex on-chip communication architectures, the need for efficient and standardized interfaces between parallel programs and… (more)

Subjects/Keywords: Embedded system; Message passing; Multicore; On-chip network

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APA (6th Edition):

Meakin, B. L. (2010). Multicore system design with XUM: the extensible Utah multicore project. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/252/rec/795

Chicago Manual of Style (16th Edition):

Meakin, Benjamin LaSalle. “Multicore system design with XUM: the extensible Utah multicore project.” 2010. Masters Thesis, University of Utah. Accessed January 29, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/252/rec/795.

MLA Handbook (7th Edition):

Meakin, Benjamin LaSalle. “Multicore system design with XUM: the extensible Utah multicore project.” 2010. Web. 29 Jan 2020.

Vancouver:

Meakin BL. Multicore system design with XUM: the extensible Utah multicore project. [Internet] [Masters thesis]. University of Utah; 2010. [cited 2020 Jan 29]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/252/rec/795.

Council of Science Editors:

Meakin BL. Multicore system design with XUM: the extensible Utah multicore project. [Masters Thesis]. University of Utah; 2010. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/252/rec/795


Penn State University

11. Park, Sungho. system-on-chip integration of heterogeneous accelerators for perceptual computing.

Degree: PhD, Computer Science and Engineering, 2013, Penn State University

 Traditional microprocessor design has seen radical shifts over the past few years. The challenges of excessive power consumption led to the shift from faster and… (more)

Subjects/Keywords: perceptual computing; system-on-chip; heterogeneous accelerator; stream processing

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APA (6th Edition):

Park, S. (2013). system-on-chip integration of heterogeneous accelerators for perceptual computing. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/19218

Chicago Manual of Style (16th Edition):

Park, Sungho. “system-on-chip integration of heterogeneous accelerators for perceptual computing.” 2013. Doctoral Dissertation, Penn State University. Accessed January 29, 2020. https://etda.libraries.psu.edu/catalog/19218.

MLA Handbook (7th Edition):

Park, Sungho. “system-on-chip integration of heterogeneous accelerators for perceptual computing.” 2013. Web. 29 Jan 2020.

Vancouver:

Park S. system-on-chip integration of heterogeneous accelerators for perceptual computing. [Internet] [Doctoral dissertation]. Penn State University; 2013. [cited 2020 Jan 29]. Available from: https://etda.libraries.psu.edu/catalog/19218.

Council of Science Editors:

Park S. system-on-chip integration of heterogeneous accelerators for perceptual computing. [Doctoral Dissertation]. Penn State University; 2013. Available from: https://etda.libraries.psu.edu/catalog/19218


University of Southern California

12. Durmus, Hakan. Resettable higher order Delta-Sigma converters for imaging applications.

Degree: PhD, Electrical Engineering, 2009, University of Southern California

 This thesis introduces resettable higher-order Delta-Sigma analog-to-digital converters (ADCs) suitable for imaging applications. Higher order Delta-Sigma converters were not preferred in imagers for several reasons:… (more)

Subjects/Keywords: low power; high resolution; converter; delta-sigma; imaging; system-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Durmus, H. (2009). Resettable higher order Delta-Sigma converters for imaging applications. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/558844/rec/5544

Chicago Manual of Style (16th Edition):

Durmus, Hakan. “Resettable higher order Delta-Sigma converters for imaging applications.” 2009. Doctoral Dissertation, University of Southern California. Accessed January 29, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/558844/rec/5544.

MLA Handbook (7th Edition):

Durmus, Hakan. “Resettable higher order Delta-Sigma converters for imaging applications.” 2009. Web. 29 Jan 2020.

Vancouver:

Durmus H. Resettable higher order Delta-Sigma converters for imaging applications. [Internet] [Doctoral dissertation]. University of Southern California; 2009. [cited 2020 Jan 29]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/558844/rec/5544.

Council of Science Editors:

Durmus H. Resettable higher order Delta-Sigma converters for imaging applications. [Doctoral Dissertation]. University of Southern California; 2009. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/558844/rec/5544


Princeton University

13. Subramanyan, Pramod. Deriving Abstractions to Address Hardware Platform Security Challenges .

Degree: PhD, 2017, Princeton University

 Today's computing devices store and process an enormous amount of security-critical assets. These assets are a lucrative target for cybercriminals and protecting them from malicious… (more)

Subjects/Keywords: abstraction; formal; hardware; security; system-on-chip; verification

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APA (6th Edition):

Subramanyan, P. (2017). Deriving Abstractions to Address Hardware Platform Security Challenges . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01kd17cw359

Chicago Manual of Style (16th Edition):

Subramanyan, Pramod. “Deriving Abstractions to Address Hardware Platform Security Challenges .” 2017. Doctoral Dissertation, Princeton University. Accessed January 29, 2020. http://arks.princeton.edu/ark:/88435/dsp01kd17cw359.

MLA Handbook (7th Edition):

Subramanyan, Pramod. “Deriving Abstractions to Address Hardware Platform Security Challenges .” 2017. Web. 29 Jan 2020.

Vancouver:

Subramanyan P. Deriving Abstractions to Address Hardware Platform Security Challenges . [Internet] [Doctoral dissertation]. Princeton University; 2017. [cited 2020 Jan 29]. Available from: http://arks.princeton.edu/ark:/88435/dsp01kd17cw359.

Council of Science Editors:

Subramanyan P. Deriving Abstractions to Address Hardware Platform Security Challenges . [Doctoral Dissertation]. Princeton University; 2017. Available from: http://arks.princeton.edu/ark:/88435/dsp01kd17cw359


Colorado State University

14. Kapadia, Nishit. Design-time and run-time frameworks for multi-objective optimization of 2D and 3D NoC-based multicore computing systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Colorado State University

 As a result of semiconductor technology scaling persisting over the last five decades, chip designers are today faced with the task of managing over a… (more)

Subjects/Keywords: Design automation; Network on chip; System-level CAD; Multicore; Algorithms; Optimization

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APA (6th Edition):

Kapadia, N. (2016). Design-time and run-time frameworks for multi-objective optimization of 2D and 3D NoC-based multicore computing systems. (Doctoral Dissertation). Colorado State University. Retrieved from http://hdl.handle.net/10217/173346

Chicago Manual of Style (16th Edition):

Kapadia, Nishit. “Design-time and run-time frameworks for multi-objective optimization of 2D and 3D NoC-based multicore computing systems.” 2016. Doctoral Dissertation, Colorado State University. Accessed January 29, 2020. http://hdl.handle.net/10217/173346.

MLA Handbook (7th Edition):

Kapadia, Nishit. “Design-time and run-time frameworks for multi-objective optimization of 2D and 3D NoC-based multicore computing systems.” 2016. Web. 29 Jan 2020.

Vancouver:

Kapadia N. Design-time and run-time frameworks for multi-objective optimization of 2D and 3D NoC-based multicore computing systems. [Internet] [Doctoral dissertation]. Colorado State University; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10217/173346.

Council of Science Editors:

Kapadia N. Design-time and run-time frameworks for multi-objective optimization of 2D and 3D NoC-based multicore computing systems. [Doctoral Dissertation]. Colorado State University; 2016. Available from: http://hdl.handle.net/10217/173346


University of California – Irvine

15. Marafie, Zahraa A M R H. Energy Optimization for Two-Dimensional NoCs Using Genetic Algorithms.

Degree: Electrical and Computer Engineering, 2016, University of California – Irvine

 The steadfast development of the computers world kept marching along with Moore’s predictions in the last two decades. Concurring to Moore’s prediction, more transistors result… (more)

Subjects/Keywords: Computer engineering; Energy Optimization; Genetic Algorithms; Low Power Design; Network-on-Chip (NoC); System-on-Chip (SoC)

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APA (6th Edition):

Marafie, Z. A. M. R. H. (2016). Energy Optimization for Two-Dimensional NoCs Using Genetic Algorithms. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/17c2b5rs

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Marafie, Zahraa A M R H. “Energy Optimization for Two-Dimensional NoCs Using Genetic Algorithms.” 2016. Thesis, University of California – Irvine. Accessed January 29, 2020. http://www.escholarship.org/uc/item/17c2b5rs.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Marafie, Zahraa A M R H. “Energy Optimization for Two-Dimensional NoCs Using Genetic Algorithms.” 2016. Web. 29 Jan 2020.

Vancouver:

Marafie ZAMRH. Energy Optimization for Two-Dimensional NoCs Using Genetic Algorithms. [Internet] [Thesis]. University of California – Irvine; 2016. [cited 2020 Jan 29]. Available from: http://www.escholarship.org/uc/item/17c2b5rs.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Marafie ZAMRH. Energy Optimization for Two-Dimensional NoCs Using Genetic Algorithms. [Thesis]. University of California – Irvine; 2016. Available from: http://www.escholarship.org/uc/item/17c2b5rs

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

16. Zhou, Wenjia. A lightweight DSP framework for OMAP3530-driven embedded devices.

Degree: MS, 1200, 2015, University of Illinois – Urbana-Champaign

 This thesis provides a lightweight framework, called MiniDSP, for OMAP3530 heterogeneous dual core SoC to run tasks on its DSP co-processor. This framework is composed… (more)

Subjects/Keywords: Digital signal processor (DSP); Embedded system; Multi-core system on chip (SoC); Device driver

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APA (6th Edition):

Zhou, W. (2015). A lightweight DSP framework for OMAP3530-driven embedded devices. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/73020

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Wenjia. “A lightweight DSP framework for OMAP3530-driven embedded devices.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed January 29, 2020. http://hdl.handle.net/2142/73020.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Wenjia. “A lightweight DSP framework for OMAP3530-driven embedded devices.” 2015. Web. 29 Jan 2020.

Vancouver:

Zhou W. A lightweight DSP framework for OMAP3530-driven embedded devices. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2142/73020.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou W. A lightweight DSP framework for OMAP3530-driven embedded devices. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/73020

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

17. Burrow, Ryan David. Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 Complex modern systems, from unmanned aircraft system to industrial plants are almost always controlled digitally. These digital control systems (DCSes) need to be verified for… (more)

Subjects/Keywords: digital control system; programmable system-on-chip; model checking; input/output processor; malware resilience

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APA (6th Edition):

Burrow, R. D. (2019). Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/89903

Chicago Manual of Style (16th Edition):

Burrow, Ryan David. “Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms.” 2019. Masters Thesis, Virginia Tech. Accessed January 29, 2020. http://hdl.handle.net/10919/89903.

MLA Handbook (7th Edition):

Burrow, Ryan David. “Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms.” 2019. Web. 29 Jan 2020.

Vancouver:

Burrow RD. Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10919/89903.

Council of Science Editors:

Burrow RD. Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/89903


University of Illinois – Urbana-Champaign

18. Kemmerer, Warren Hargon. Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 While SystemC models provide a promising solution to the complex problem of HW/SW co-design within the system-on-chip paradigm, such requires a detailed annotation of transaction… (more)

Subjects/Keywords: Simulation; Central processing unit (CPU); System on a chip (SoC); Phase; Convergence; SystemC

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APA (6th Edition):

Kemmerer, W. H. (2016). Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kemmerer, Warren Hargon. “Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed January 29, 2020. http://hdl.handle.net/2142/90847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kemmerer, Warren Hargon. “Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.” 2016. Web. 29 Jan 2020.

Vancouver:

Kemmerer WH. Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2142/90847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kemmerer WH. Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rice University

19. Chen, Peiyu. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.

Degree: PhD, Electrical & Computer Eng., 2018, Rice University

 Short impulses in millimeter-wave (mm-wave) and THz regimes (30 GHz - 30 THz) have a potentially large bandwidth that can be exploited for various applications,… (more)

Subjects/Keywords: integrated circuits; RF; mm-wave; THz; broadband system; picosecond; impulse; on-chip antennas; femtosecond laser

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APA (6th Edition):

Chen, P. (2018). Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/102474

Chicago Manual of Style (16th Edition):

Chen, Peiyu. “Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.” 2018. Doctoral Dissertation, Rice University. Accessed January 29, 2020. http://hdl.handle.net/1911/102474.

MLA Handbook (7th Edition):

Chen, Peiyu. “Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.” 2018. Web. 29 Jan 2020.

Vancouver:

Chen P. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. [Internet] [Doctoral dissertation]. Rice University; 2018. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1911/102474.

Council of Science Editors:

Chen P. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. [Doctoral Dissertation]. Rice University; 2018. Available from: http://hdl.handle.net/1911/102474


Rice University

20. Chen, Peiyu. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.

Degree: PhD, Electrical & Computer Eng., 2018, Rice University

 Short impulses in millimeter-wave (mm-wave) and THz regimes (30 GHz - 30 THz) have a potentially large bandwidth that can be exploited for various applications,… (more)

Subjects/Keywords: integrated circuits; RF; mm-wave; THz; broadband system; picosecond; impulse; on-chip antennas; femtosecond laser

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, P. (2018). Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/102473

Chicago Manual of Style (16th Edition):

Chen, Peiyu. “Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.” 2018. Doctoral Dissertation, Rice University. Accessed January 29, 2020. http://hdl.handle.net/1911/102473.

MLA Handbook (7th Edition):

Chen, Peiyu. “Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.” 2018. Web. 29 Jan 2020.

Vancouver:

Chen P. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. [Internet] [Doctoral dissertation]. Rice University; 2018. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1911/102473.

Council of Science Editors:

Chen P. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. [Doctoral Dissertation]. Rice University; 2018. Available from: http://hdl.handle.net/1911/102473


Rice University

21. Chen, Peiyu. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.

Degree: PhD, Electrical & Computer Eng., 2018, Rice University

 Short impulses in millimeter-wave (mm-wave) and THz regimes (30 GHz - 30 THz) have a potentially large bandwidth that can be exploited for various applications,… (more)

Subjects/Keywords: integrated circuits; RF; mm-wave; THz; broadband system; picosecond; impulse; on-chip antennas; femtosecond laser

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, P. (2018). Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/102475

Chicago Manual of Style (16th Edition):

Chen, Peiyu. “Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.” 2018. Doctoral Dissertation, Rice University. Accessed January 29, 2020. http://hdl.handle.net/1911/102475.

MLA Handbook (7th Edition):

Chen, Peiyu. “Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.” 2018. Web. 29 Jan 2020.

Vancouver:

Chen P. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. [Internet] [Doctoral dissertation]. Rice University; 2018. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1911/102475.

Council of Science Editors:

Chen P. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. [Doctoral Dissertation]. Rice University; 2018. Available from: http://hdl.handle.net/1911/102475


The Ohio State University

22. Liu, Wei. Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification.

Degree: PhD, Electrical and Computer Engineering, 2014, The Ohio State University

 In recent years, with the explosive increase of the wireless communication and consumer electronics products, the advanced system solutions which have powerful computation capability and… (more)

Subjects/Keywords: Electrical Engineering; Low Dropout Regulator, Intellectual Property , System On Chip, Verification, modeling

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APA (6th Edition):

Liu, W. (2014). Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1398967795

Chicago Manual of Style (16th Edition):

Liu, Wei. “Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification.” 2014. Doctoral Dissertation, The Ohio State University. Accessed January 29, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1398967795.

MLA Handbook (7th Edition):

Liu, Wei. “Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification.” 2014. Web. 29 Jan 2020.

Vancouver:

Liu W. Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification. [Internet] [Doctoral dissertation]. The Ohio State University; 2014. [cited 2020 Jan 29]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1398967795.

Council of Science Editors:

Liu W. Analysis and Development of A Trusted Low Dropout Regulator (LDO) Model For Intellectual Property (IP) Reuse Aiming at System Verification. [Doctoral Dissertation]. The Ohio State University; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1398967795


Carnegie Mellon University

23. Guney, Metin G. High Dynamic Range CMOS-MEMS Capacitive Accelerometer Array with Drift Compensation.

Degree: 2018, Carnegie Mellon University

 This thesis explains the design, fabrication and characterization steps of a high dynamic range CMOS-MEMS capacitive accelerometer array and on-chip environmental sensors for bias drift… (more)

Subjects/Keywords: Accelerometer; Bias Instability; High-G Shock Test; Inertial Sensor; Sensor Array; System on Chip

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APA (6th Edition):

Guney, M. G. (2018). High Dynamic Range CMOS-MEMS Capacitive Accelerometer Array with Drift Compensation. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/1155

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guney, Metin G. “High Dynamic Range CMOS-MEMS Capacitive Accelerometer Array with Drift Compensation.” 2018. Thesis, Carnegie Mellon University. Accessed January 29, 2020. http://repository.cmu.edu/dissertations/1155.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guney, Metin G. “High Dynamic Range CMOS-MEMS Capacitive Accelerometer Array with Drift Compensation.” 2018. Web. 29 Jan 2020.

Vancouver:

Guney MG. High Dynamic Range CMOS-MEMS Capacitive Accelerometer Array with Drift Compensation. [Internet] [Thesis]. Carnegie Mellon University; 2018. [cited 2020 Jan 29]. Available from: http://repository.cmu.edu/dissertations/1155.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guney MG. High Dynamic Range CMOS-MEMS Capacitive Accelerometer Array with Drift Compensation. [Thesis]. Carnegie Mellon University; 2018. Available from: http://repository.cmu.edu/dissertations/1155

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boston University

24. Bu, Lake. Design of secure and trustworthy system-on-chip architectures using hardware-based root-of-trust techniques.

Degree: PhD, Electrical & Computer Engineering, 2019, Boston University

 Cyber-security is now a critical concern in a wide range of embedded computing modules, communications systems, and connected devices. These devices are used in medical… (more)

Subjects/Keywords: Computer engineering; Computer architecture; Cryptography; Hardware; Root-of-trust; Security; System-on-chip

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APA (6th Edition):

Bu, L. (2019). Design of secure and trustworthy system-on-chip architectures using hardware-based root-of-trust techniques. (Doctoral Dissertation). Boston University. Retrieved from http://hdl.handle.net/2144/36148

Chicago Manual of Style (16th Edition):

Bu, Lake. “Design of secure and trustworthy system-on-chip architectures using hardware-based root-of-trust techniques.” 2019. Doctoral Dissertation, Boston University. Accessed January 29, 2020. http://hdl.handle.net/2144/36148.

MLA Handbook (7th Edition):

Bu, Lake. “Design of secure and trustworthy system-on-chip architectures using hardware-based root-of-trust techniques.” 2019. Web. 29 Jan 2020.

Vancouver:

Bu L. Design of secure and trustworthy system-on-chip architectures using hardware-based root-of-trust techniques. [Internet] [Doctoral dissertation]. Boston University; 2019. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2144/36148.

Council of Science Editors:

Bu L. Design of secure and trustworthy system-on-chip architectures using hardware-based root-of-trust techniques. [Doctoral Dissertation]. Boston University; 2019. Available from: http://hdl.handle.net/2144/36148


Northeastern University

25. Hosic, Sanjin. Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier.

Degree: PhD, Department of Chemical Engineering, 2019, Northeastern University

 Two decades ago, it was demonstrated that electrical vagal nerve stimulation (VNS) inhibits gastrointestinal (GI) inflammation. In-vivo studies concluded that VNS inhibits GI inflammation by… (more)

Subjects/Keywords: cholinergic; epithelium; microfluidic; microphysiological system; organoid; organ-on-a-chip; Bioengineering; Biomedical engineering; Cellular biology

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APA (6th Edition):

Hosic, S. (2019). Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20317949

Chicago Manual of Style (16th Edition):

Hosic, Sanjin. “Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier.” 2019. Doctoral Dissertation, Northeastern University. Accessed January 29, 2020. http://hdl.handle.net/2047/D20317949.

MLA Handbook (7th Edition):

Hosic, Sanjin. “Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier.” 2019. Web. 29 Jan 2020.

Vancouver:

Hosic S. Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier. [Internet] [Doctoral dissertation]. Northeastern University; 2019. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2047/D20317949.

Council of Science Editors:

Hosic S. Harnessing Patient-derived Organoids And Microfluidics To Investigate Cholinergic Regulation Of The Epithelial Barrier. [Doctoral Dissertation]. Northeastern University; 2019. Available from: http://hdl.handle.net/2047/D20317949


University of Arizona

26. Landsiedel, Emma Catherine. High-Speed White Light Interferometry for Imaging Applications .

Degree: 2019, University of Arizona

 An extended depth of field imaging system was developed for in-line inspection for the semiconductor industry. The system produces a single, two-dimensional, in-focus image of… (more)

Subjects/Keywords: extended depth of field; interferometry; machine vision; microscopy; system on a chip; vision sensor

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APA (6th Edition):

Landsiedel, E. C. (2019). High-Speed White Light Interferometry for Imaging Applications . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/633073

Chicago Manual of Style (16th Edition):

Landsiedel, Emma Catherine. “High-Speed White Light Interferometry for Imaging Applications .” 2019. Masters Thesis, University of Arizona. Accessed January 29, 2020. http://hdl.handle.net/10150/633073.

MLA Handbook (7th Edition):

Landsiedel, Emma Catherine. “High-Speed White Light Interferometry for Imaging Applications .” 2019. Web. 29 Jan 2020.

Vancouver:

Landsiedel EC. High-Speed White Light Interferometry for Imaging Applications . [Internet] [Masters thesis]. University of Arizona; 2019. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10150/633073.

Council of Science Editors:

Landsiedel EC. High-Speed White Light Interferometry for Imaging Applications . [Masters Thesis]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/633073


Rice University

27. Chen, Peiyu. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.

Degree: PhD, Engineering, 2018, Rice University

 Short impulses in millimeter-wave (mm-wave) and THz regimes (30 GHz - 30 THz) have a potentially large bandwidth that can be exploited for various applications,… (more)

Subjects/Keywords: integrated circuits; RF; mm-wave; THz; broadband system; picosecond; impulse; on-chip antennas; femtosecond laser

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, P. (2018). Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/102472

Chicago Manual of Style (16th Edition):

Chen, Peiyu. “Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.” 2018. Doctoral Dissertation, Rice University. Accessed January 29, 2020. http://hdl.handle.net/1911/102472.

MLA Handbook (7th Edition):

Chen, Peiyu. “Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon.” 2018. Web. 29 Jan 2020.

Vancouver:

Chen P. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. [Internet] [Doctoral dissertation]. Rice University; 2018. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1911/102472.

Council of Science Editors:

Chen P. Design Techniques and Measurement Methods for Broadband Millimeter-Wave and THz Systems in Silicon. [Doctoral Dissertation]. Rice University; 2018. Available from: http://hdl.handle.net/1911/102472


Georgia Tech

28. Hassan, Syed Minhaj. Exploiting on-chip memory concurrency in 3d manycore architectures.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases… (more)

Subjects/Keywords: 3D memory systems; Network-on-chip; 3D system thermal analysis; Memory-level parallelism; DRAM

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APA (6th Edition):

Hassan, S. M. (2016). Exploiting on-chip memory concurrency in 3d manycore architectures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56251

Chicago Manual of Style (16th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Doctoral Dissertation, Georgia Tech. Accessed January 29, 2020. http://hdl.handle.net/1853/56251.

MLA Handbook (7th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Web. 29 Jan 2020.

Vancouver:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1853/56251.

Council of Science Editors:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56251


Iowa State University

29. Roggow, Daniel. Real-time ellipse detection on an embedded reconfigurable system-on-chip.

Degree: 2017, Iowa State University

 Computer vision algorithms have historically been difficult to deploy in resource-constrained embedded systems. Ellipse detection or fitting is an important subproblem in computer vision, and… (more)

Subjects/Keywords: ellipse detection; embedded computer vision; reconfigurable computing; system on chip; Computer Engineering

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APA (6th Edition):

Roggow, D. (2017). Real-time ellipse detection on an embedded reconfigurable system-on-chip. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/15407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Roggow, Daniel. “Real-time ellipse detection on an embedded reconfigurable system-on-chip.” 2017. Thesis, Iowa State University. Accessed January 29, 2020. https://lib.dr.iastate.edu/etd/15407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Roggow, Daniel. “Real-time ellipse detection on an embedded reconfigurable system-on-chip.” 2017. Web. 29 Jan 2020.

Vancouver:

Roggow D. Real-time ellipse detection on an embedded reconfigurable system-on-chip. [Internet] [Thesis]. Iowa State University; 2017. [cited 2020 Jan 29]. Available from: https://lib.dr.iastate.edu/etd/15407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Roggow D. Real-time ellipse detection on an embedded reconfigurable system-on-chip. [Thesis]. Iowa State University; 2017. Available from: https://lib.dr.iastate.edu/etd/15407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

30. Saxena, Sagar. A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band.

Degree: MS, Computer Engineering, 2017, Rochester Institute of Technology

  Network-on-Chips (NoCs) have emerged as a communication infrastructure for the multi-core System-on-Chips (SoCs). Despite its advantages, due to the multi-hop communication over the metal… (more)

Subjects/Keywords: Chip-to-chip communication; Graphene-based THz-band antennas; Multichip system; Phase based communication protocol; Terahertz band communication; Wireless network-on-chip

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APA (6th Edition):

Saxena, S. (2017). A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9628

Chicago Manual of Style (16th Edition):

Saxena, Sagar. “A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed January 29, 2020. https://scholarworks.rit.edu/theses/9628.

MLA Handbook (7th Edition):

Saxena, Sagar. “A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band.” 2017. Web. 29 Jan 2020.

Vancouver:

Saxena S. A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Jan 29]. Available from: https://scholarworks.rit.edu/theses/9628.

Council of Science Editors:

Saxena S. A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9628

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