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You searched for subject:(Successive approximation register analog to digital converter SAR ADC design). Showing records 1 – 30 of 98691 total matches.

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University of Illinois – Urbana-Champaign

1. Shah, Aarti Mahesh Kumar. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed… (more)

Subjects/Keywords: Analog-to-digital converters; High speed successive approximation register (SAR); Delta-sigma modulators; Quantizer; Medium resolution successive approximation register (SAR); Time-interleaved successive approximation register (TI SAR); Time-interleaved analog-to-digital converter (ADC); Higher order delta-sigma modulator design; Delta-sigma simulink models; Successive approximation register analog-to-digital converter (SAR ADC) design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shah, A. M. K. (2017). Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Aarti Mahesh Kumar. “Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed December 09, 2019. http://hdl.handle.net/2142/97465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Aarti Mahesh Kumar. “Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.” 2017. Web. 09 Dec 2019.

Vancouver:

Shah AMK. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2142/97465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah AMK. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boston University

2. Yang, Jiao. Design of a low power 8-bit A/D converter for wireless neural recorder applications.

Degree: MS, Electrical & Computer Engineering, 2017, Boston University

 Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues… (more)

Subjects/Keywords: Electrical engineering; Energy-saving capacitor array; Low power design; Neural recorder applications; Successive approximation register analog-to-digital converter (SAR-ADC)

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APA (6th Edition):

Yang, J. (2017). Design of a low power 8-bit A/D converter for wireless neural recorder applications. (Masters Thesis). Boston University. Retrieved from http://hdl.handle.net/2144/23685

Chicago Manual of Style (16th Edition):

Yang, Jiao. “Design of a low power 8-bit A/D converter for wireless neural recorder applications.” 2017. Masters Thesis, Boston University. Accessed December 09, 2019. http://hdl.handle.net/2144/23685.

MLA Handbook (7th Edition):

Yang, Jiao. “Design of a low power 8-bit A/D converter for wireless neural recorder applications.” 2017. Web. 09 Dec 2019.

Vancouver:

Yang J. Design of a low power 8-bit A/D converter for wireless neural recorder applications. [Internet] [Masters thesis]. Boston University; 2017. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2144/23685.

Council of Science Editors:

Yang J. Design of a low power 8-bit A/D converter for wireless neural recorder applications. [Masters Thesis]. Boston University; 2017. Available from: http://hdl.handle.net/2144/23685


Southern Illinois University

3. Sekar, Ramgopal. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.

Degree: MS, Electrical and Computer Engineering, 2010, Southern Illinois University

  In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC(more)

Subjects/Keywords: Analog to Digital Converters; Low Power Design; Successive Approximation Register ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sekar, R. (2010). LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. (Masters Thesis). Southern Illinois University. Retrieved from http://opensiuc.lib.siu.edu/theses/350

Chicago Manual of Style (16th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Masters Thesis, Southern Illinois University. Accessed December 09, 2019. http://opensiuc.lib.siu.edu/theses/350.

MLA Handbook (7th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Web. 09 Dec 2019.

Vancouver:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Internet] [Masters thesis]. Southern Illinois University; 2010. [cited 2019 Dec 09]. Available from: http://opensiuc.lib.siu.edu/theses/350.

Council of Science Editors:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Masters Thesis]. Southern Illinois University; 2010. Available from: http://opensiuc.lib.siu.edu/theses/350


University of Michigan

4. Fredenburg, Jeffrey Alan. Noise-Shaping SAR ADCs.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 This work investigates hybrid analog-to-digital converters (ADCs) that combine the phenomenal energy efficiency of successive-approximation (SAR) ADCs with the resolution enhancement strategies used by noise-shaping… (more)

Subjects/Keywords: Analog-to-Digital Converter; Noise-shaping SAR; Successive-approximation ADC; Analog Circuits; Electrical Engineering; Engineering

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APA (6th Edition):

Fredenburg, J. A. (2015). Noise-Shaping SAR ADCs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113647

Chicago Manual of Style (16th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Doctoral Dissertation, University of Michigan. Accessed December 09, 2019. http://hdl.handle.net/2027.42/113647.

MLA Handbook (7th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Web. 09 Dec 2019.

Vancouver:

Fredenburg JA. Noise-Shaping SAR ADCs. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2027.42/113647.

Council of Science Editors:

Fredenburg JA. Noise-Shaping SAR ADCs. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113647


NSYSU

5. Chung, Meng-hsun. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt… (more)

Subjects/Keywords: Analog-to-Digital Converter; ADC; Binary-Search ADC; Successive Approximation; SAR ADC; Time-Interleaved; Non-overlapping circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chung, M. (2015). A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed December 09, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 09 Dec 2019.

Vancouver:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Dec 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

6. Shafik, Ayman Osama Amin Mohamed. Equalization Architectures for High Speed ADC-Based Serial I/O Receivers.

Degree: PhD, Electrical Engineering, 2016, Texas A&M University

 The growth in worldwide network tra?c due to the rise of cloud computing and wireless video consumption has required servers and routers to support increased… (more)

Subjects/Keywords: ADC-Based Receiver; Analog-To-Digital Converter (ADC); Bit-Error Rate (BER); Decision Feedback Equalizer (DFE); Digital Equalization; Embedded Equalization; Feed-Forward Equalizer (FFE); Statistical Modeling; Successive Approximation Register (SAR); Time Interleaving

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shafik, A. O. A. M. (2016). Equalization Architectures for High Speed ADC-Based Serial I/O Receivers. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156875

Chicago Manual of Style (16th Edition):

Shafik, Ayman Osama Amin Mohamed. “Equalization Architectures for High Speed ADC-Based Serial I/O Receivers.” 2016. Doctoral Dissertation, Texas A&M University. Accessed December 09, 2019. http://hdl.handle.net/1969.1/156875.

MLA Handbook (7th Edition):

Shafik, Ayman Osama Amin Mohamed. “Equalization Architectures for High Speed ADC-Based Serial I/O Receivers.” 2016. Web. 09 Dec 2019.

Vancouver:

Shafik AOAM. Equalization Architectures for High Speed ADC-Based Serial I/O Receivers. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1969.1/156875.

Council of Science Editors:

Shafik AOAM. Equalization Architectures for High Speed ADC-Based Serial I/O Receivers. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156875


Oregon State University

7. Leung, Jerry. Data driven optimization in SAR ADC.

Degree: MS, Electrical and Computer Engineering, 2014, Oregon State University

 Recent publications show that successive approximation register (SAR) analog to digital converters (ADC) are capable of achieving high efficiency over other ADC topologies. Furthermore, techniques… (more)

Subjects/Keywords: SAR; Successive approximation analog-to-digital converters

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APA (6th Edition):

Leung, J. (2014). Data driven optimization in SAR ADC. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/54631

Chicago Manual of Style (16th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Masters Thesis, Oregon State University. Accessed December 09, 2019. http://hdl.handle.net/1957/54631.

MLA Handbook (7th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Web. 09 Dec 2019.

Vancouver:

Leung J. Data driven optimization in SAR ADC. [Internet] [Masters thesis]. Oregon State University; 2014. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1957/54631.

Council of Science Editors:

Leung J. Data driven optimization in SAR ADC. [Masters Thesis]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/54631


NSYSU

8. Chen, Guan-Ting. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 In this thesis, a 10-bit resolution analog-to-digital converter with 100MHz sampling frequency is proposed. In terms of design, in order to improve the conversion speed,… (more)

Subjects/Keywords: 2b/Cycle; Non-binary Error Correction; Alternate Technique; Successive Approximation Register; Analog to Digital Converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, G. (2018). A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Guan-Ting. “A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.” 2018. Thesis, NSYSU. Accessed December 09, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Guan-Ting. “A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.” 2018. Web. 09 Dec 2019.

Vancouver:

Chen G. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Dec 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen G. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Chen, Yan-Lin. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 In this thesis, a 10-bit, 10 MS/s dual-mode analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18ï­m process technology.… (more)

Subjects/Keywords: Dual-Mode; Edge Image; Image Sensor; Analog to Digital Converter; Successive Approximation Register

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APA (6th Edition):

Chen, Y. (2018). A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yan-Lin. “A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.” 2018. Thesis, NSYSU. Accessed December 09, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yan-Lin. “A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.” 2018. Web. 09 Dec 2019.

Vancouver:

Chen Y. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Dec 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

10. Chaturvedi, Vikram. Low Power and Low Area Techniques for Neural Recording Application.

Degree: 2012, Indian Institute of Science

 Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has… (more)

Subjects/Keywords: Neural Signal Processing; Nervous System - Electric Signals; Brain Machine Interface; Neural Recording System; Neural Recording Front End; Neural Low Noise Amplifiers; Successive Approximation Analog to Digital Converter; Neural Recording Application; Neural Recording Front End (NRFE).; FlipDAC; Quaternary Capacitor Switching; ANALOG-TO-DIGITAL Converter (ADC); SAR ADC Design; Neural Physiology

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APA (6th Edition):

Chaturvedi, V. (2012). Low Power and Low Area Techniques for Neural Recording Application. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/3167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chaturvedi, Vikram. “Low Power and Low Area Techniques for Neural Recording Application.” 2012. Thesis, Indian Institute of Science. Accessed December 09, 2019. http://hdl.handle.net/2005/3167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chaturvedi, Vikram. “Low Power and Low Area Techniques for Neural Recording Application.” 2012. Web. 09 Dec 2019.

Vancouver:

Chaturvedi V. Low Power and Low Area Techniques for Neural Recording Application. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2005/3167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chaturvedi V. Low Power and Low Area Techniques for Neural Recording Application. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/3167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

11. Liu, Wenbo. Low-power high-performance SAR ADC design with digital calibration techniques.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized… (more)

Subjects/Keywords: successive-approximation-register (SAR) analog-to-digital converters (ADC); redundancy; sub-radix-2; Nonlinearity; digital calibration; linear equalizer; generalized linear equalizer; perturbation; bit-wise correlation; channel mismatch; time-interleaved analog-to-digital converters (ADC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, W. (2011). Low-power high-performance SAR ADC design with digital calibration techniques. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18623

Chicago Manual of Style (16th Edition):

Liu, Wenbo. “Low-power high-performance SAR ADC design with digital calibration techniques.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 09, 2019. http://hdl.handle.net/2142/18623.

MLA Handbook (7th Edition):

Liu, Wenbo. “Low-power high-performance SAR ADC design with digital calibration techniques.” 2011. Web. 09 Dec 2019.

Vancouver:

Liu W. Low-power high-performance SAR ADC design with digital calibration techniques. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2142/18623.

Council of Science Editors:

Liu W. Low-power high-performance SAR ADC design with digital calibration techniques. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18623

12. Zeloufi, Mohamed. Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2016, Grenoble Alpes

 À l’horizon 2024, l’expérience ATLAS prévoit de fonctionner à des luminosités 10 fois supérieures à la configuration actuelle. Par conséquent, l’électronique actuelle de lecture ne… (more)

Subjects/Keywords: Convertisseur Analogique-Numérique (CAN); Conversion à approximations successives (SAR); Redondance; Algorithme de commutation; Correction numérique; Tensions de référence; Analog-Digital Converter (ADC); Successive Approximation Register (SAR); Redundancy; Switching algorithm; Digital calibration; Reference voltages; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zeloufi, M. (2016). Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2016GREAT115

Chicago Manual of Style (16th Edition):

Zeloufi, Mohamed. “Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC.” 2016. Doctoral Dissertation, Grenoble Alpes. Accessed December 09, 2019. http://www.theses.fr/2016GREAT115.

MLA Handbook (7th Edition):

Zeloufi, Mohamed. “Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC.” 2016. Web. 09 Dec 2019.

Vancouver:

Zeloufi M. Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2016. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2016GREAT115.

Council of Science Editors:

Zeloufi M. Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC. [Doctoral Dissertation]. Grenoble Alpes; 2016. Available from: http://www.theses.fr/2016GREAT115


NSYSU

13. Bai, Je-Wei. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 In this thesis, a 10-bit, 80 MS/s analog-to-digital converter with a 1 V supply voltage is implemented by using the TSMC 90nm process technology. This… (more)

Subjects/Keywords: non-binary digital error correction; digital error correction; 2b/Cycle; Successive Approximation Register; Analog to Digital Converter

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APA (6th Edition):

Bai, J. (2016). A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Thesis, NSYSU. Accessed December 09, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Web. 09 Dec 2019.

Vancouver:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Internet] [Thesis]. NSYSU; 2016. [cited 2019 Dec 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

14. Zhang, Dai. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.

Degree: Electrical Engineering, 2009, Linköping University

Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system.… (more)

Subjects/Keywords: Analog-to-digital converter (ADC); charge redistribution; CMOS; low power; low supply voltage; successive approximation; latched comparator; Electrical engineering; Elektroteknik

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APA (6th Edition):

Zhang, D. (2009). Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Thesis, Linköping University. Accessed December 09, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Web. 09 Dec 2019.

Vancouver:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Internet] [Thesis]. Linköping University; 2009. [cited 2019 Dec 09]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Thesis]. Linköping University; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Chen, Bang-Cyuan. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 A high speed and low power Pipelined-SAR ADC is proposed in this thesis. The Flash ADC which is often found in traditional Pipelined ADC is… (more)

Subjects/Keywords: SAR; ADC; Low Power; Pipelined-SAR ADC; Pipelined; Analog-to-Digital Converter

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APA (6th Edition):

Chen, B. (2013). A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Bang-Cyuan. “A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.” 2013. Thesis, NSYSU. Accessed December 09, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Bang-Cyuan. “A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.” 2013. Web. 09 Dec 2019.

Vancouver:

Chen B. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen B. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

16. Mirhaj, Seyed Arash. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.

Degree: Electrical Engineering, 2014, UCLA

 In recent years, Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) has received significant attention due to its well-known energy and hardware efficiency, which also benefits even… (more)

Subjects/Keywords: Electrical engineering; Analog to Digital Converter; Calibration; Piecewise Linear; SAR-ADC

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APA (6th Edition):

Mirhaj, S. A. (2014). Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9jx6c9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mirhaj, Seyed Arash. “Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.” 2014. Thesis, UCLA. Accessed December 09, 2019. http://www.escholarship.org/uc/item/9jx6c9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mirhaj, Seyed Arash. “Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.” 2014. Web. 09 Dec 2019.

Vancouver:

Mirhaj SA. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. [Internet] [Thesis]. UCLA; 2014. [cited 2019 Dec 09]. Available from: http://www.escholarship.org/uc/item/9jx6c9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mirhaj SA. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/9jx6c9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Nova

17. Fitas, Ricardo Jorge Barros. Study of a Time Assisted SAR ADC.

Degree: 2017, Universidade Nova

 The demand for low power systems has been increasing in recent years and Analogto- Digital Converters (ADCs) are key blocks of many of these systems… (more)

Subjects/Keywords: Analog-to-Digital Converter; Successive Approximation Register; Time-to- Digital Converter; Low power; Time; Bypass Window; Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática

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APA (6th Edition):

Fitas, R. J. B. (2017). Study of a Time Assisted SAR ADC. (Thesis). Universidade Nova. Retrieved from https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/30820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fitas, Ricardo Jorge Barros. “Study of a Time Assisted SAR ADC.” 2017. Thesis, Universidade Nova. Accessed December 09, 2019. https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/30820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fitas, Ricardo Jorge Barros. “Study of a Time Assisted SAR ADC.” 2017. Web. 09 Dec 2019.

Vancouver:

Fitas RJB. Study of a Time Assisted SAR ADC. [Internet] [Thesis]. Universidade Nova; 2017. [cited 2019 Dec 09]. Available from: https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/30820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fitas RJB. Study of a Time Assisted SAR ADC. [Thesis]. Universidade Nova; 2017. Available from: https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/30820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

18. Gao, Yang. An Energy Efficient Asynchronous Time-Domain Comparator.

Degree: 2013, Texas A&M University

 In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long… (more)

Subjects/Keywords: Analog-to-digital converter; asynchronous circuits; comparator; successive approximation

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APA (6th Edition):

Gao, Y. (2013). An Energy Efficient Asynchronous Time-Domain Comparator. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Thesis, Texas A&M University. Accessed December 09, 2019. http://hdl.handle.net/1969.1/149314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Web. 09 Dec 2019.

Vancouver:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1969.1/149314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

19. Chen, Long. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.

Degree: PhD, Electrical and Computer engineering, 2016, University of Texas – Austin

 This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two… (more)

Subjects/Keywords: Analog-to-digital converter; SAR ADC; ADC; Low power; Comparator; High speed

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APA (6th Edition):

Chen, L. (2016). Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/40286

Chicago Manual of Style (16th Edition):

Chen, Long. “Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.” 2016. Doctoral Dissertation, University of Texas – Austin. Accessed December 09, 2019. http://hdl.handle.net/2152/40286.

MLA Handbook (7th Edition):

Chen, Long. “Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.” 2016. Web. 09 Dec 2019.

Vancouver:

Chen L. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2016. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2152/40286.

Council of Science Editors:

Chen L. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. [Doctoral Dissertation]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/40286


University of Texas – Austin

20. Fontaine, Robert Alexander. Investigation of 10-bit SAR ADC using flip-flip bypass circuit.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by… (more)

Subjects/Keywords: SAR; Successive Approximation Register; ADC; Flip-flop bypass

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APA (6th Edition):

Fontaine, R. A. (2013). Investigation of 10-bit SAR ADC using flip-flip bypass circuit. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/24011

Chicago Manual of Style (16th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Masters Thesis, University of Texas – Austin. Accessed December 09, 2019. http://hdl.handle.net/2152/24011.

MLA Handbook (7th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Web. 09 Dec 2019.

Vancouver:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2152/24011.

Council of Science Editors:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/24011


Texas A&M University

21. Larsson, Andreas 1978-. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.

Degree: 2012, Texas A&M University

 The miniaturization and digitization of modern microelectronic systems have made Analog-to-Digital converters (ADC) key building components in many applications. Internet and entertainment technologies demand higher… (more)

Subjects/Keywords: Analog/Mixed Signal Design; Switched-Capacitor; Analog-To-Digital Converter (ADC)

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APA (6th Edition):

Larsson, A. 1. (2012). Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148307

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Thesis, Texas A&M University. Accessed December 09, 2019. http://hdl.handle.net/1969.1/148307.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Web. 09 Dec 2019.

Vancouver:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1969.1/148307.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148307

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

22. Collins, Nicholas. Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 During the past decade, SAR ADCs have enjoyed increasing prominence due to their inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power… (more)

Subjects/Keywords: Mismatch in SAR ADCs; Mismatch in Successive Approximation Analog-to-Digital Converters; Electrical Engineering; Engineering

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APA (6th Edition):

Collins, N. (2017). Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/138630

Chicago Manual of Style (16th Edition):

Collins, Nicholas. “Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs.” 2017. Doctoral Dissertation, University of Michigan. Accessed December 09, 2019. http://hdl.handle.net/2027.42/138630.

MLA Handbook (7th Edition):

Collins, Nicholas. “Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs.” 2017. Web. 09 Dec 2019.

Vancouver:

Collins N. Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2027.42/138630.

Council of Science Editors:

Collins N. Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/138630


Oregon State University

23. Guerber, Jon. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and… (more)

Subjects/Keywords: SAR ADC; Analog-to-digital converters

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APA (6th Edition):

Guerber, J. (2012). Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/36019

Chicago Manual of Style (16th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed December 09, 2019. http://hdl.handle.net/1957/36019.

MLA Handbook (7th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Web. 09 Dec 2019.

Vancouver:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1957/36019.

Council of Science Editors:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/36019


NSYSU

24. Lo, Ching-Wen. High Speed SAR Analog to Digital Converter Design.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In this thesis, the circuits are designing with TSMC 90nm CMOS process and 1.2V of supply voltage. The speed and resolution of ADC are 8-bit… (more)

Subjects/Keywords: Bootstrapped switch; Dynamic Comparator; Successive Approximation; Low power; Analog-to-Digital Converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lo, C. (2014). High Speed SAR Analog to Digital Converter Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Thesis, NSYSU. Accessed December 09, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Web. 09 Dec 2019.

Vancouver:

Lo C. High Speed SAR Analog to Digital Converter Design. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Dec 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lo C. High Speed SAR Analog to Digital Converter Design. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Zhian Tabasy, Ehsan. Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications.

Degree: 2015, Texas A&M University

 As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced.… (more)

Subjects/Keywords: Analog to Digital Converter (ADC); Embedded Equalization; ADC-Based Receiver; Decision Feedback Equalizer (DFE); Embedded Equalization; Feed-Forward Equalizer (FFE); Serial Link; Successive Approximation Register (SAR); Time Interleaving; Wireline

analog-to-digital converter (ADC)-based serial link receivers (Fig. 1.1)… …architectures are briefly introduced and successive approximation register (SAR) topology… …a capacitive digital-to-analog converter (CDAC) performing the signal scaling… …4.1.2 SAR ADC with Low-Overhead Embedded FFE and DFE . . . 4.1.3 ADC Design… …ADC is another promising approach to both reduce ADC resolution and digital equalization… 

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APA (6th Edition):

Zhian Tabasy, E. (2015). Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/155223

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhian Tabasy, Ehsan. “Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications.” 2015. Thesis, Texas A&M University. Accessed December 09, 2019. http://hdl.handle.net/1969.1/155223.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhian Tabasy, Ehsan. “Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications.” 2015. Web. 09 Dec 2019.

Vancouver:

Zhian Tabasy E. Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1969.1/155223.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhian Tabasy E. Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/155223

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

26. Lanot, Alisson Jamie Cruz. Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga.

Degree: 2014, Universidade do Rio Grande do Sul

Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que… (more)

Subjects/Keywords: Analog to digital converters; Conversor analogico/digital; Circuitos integrados; Successive approximation register; Single event effects; Single event transients; Fault mitigation techniques

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APA (6th Edition):

Lanot, A. J. C. (2014). Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/114478

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lanot, Alisson Jamie Cruz. “Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed December 09, 2019. http://hdl.handle.net/10183/114478.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lanot, Alisson Jamie Cruz. “Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga.” 2014. Web. 09 Dec 2019.

Vancouver:

Lanot AJC. Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10183/114478.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lanot AJC. Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/114478

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Moorthy, Sriram. Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit.

Degree: 2014, University of Waterloo

 The Successive Approximation Analog-to-Digital converter (SAR-ADC) is a popular architecture due to its low power, simple design, and reasonable resolution and speed. Due to the… (more)

Subjects/Keywords: ADC SAR-ADC Analog-to-Digital Converters Voltage-Referece Successive Approximation

…across Ctop Successive Approximation Register Successive Approximation Analog-to-Digital… …are the Analog-to-Digital converter (ADC) and the Digital-to-Analog converter… …searches” for the appropriate digital output. The Successive Approximation ADC (SAR-ADC)… …comparator and the Successive Approximation Register (SAR) work together to make a binary… …Qtop SAR SAR-ADC SFDR SHA SNDR SNR SoC THD Vbottom Verror VF S Vin VLSB Vref Vtop Analog-to… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moorthy, S. (2014). Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/9011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Moorthy, Sriram. “Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit.” 2014. Thesis, University of Waterloo. Accessed December 09, 2019. http://hdl.handle.net/10012/9011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Moorthy, Sriram. “Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit.” 2014. Web. 09 Dec 2019.

Vancouver:

Moorthy S. Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit. [Internet] [Thesis]. University of Waterloo; 2014. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10012/9011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Moorthy S. Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit. [Thesis]. University of Waterloo; 2014. Available from: http://hdl.handle.net/10012/9011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Grenoble

28. Regis, Guillaume. Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning.

Degree: Docteur es, Physique Expérimentale et Instrumentation, 2011, Université de Grenoble

Le domaine de l'instrumentation des capteurs est en constante évolution. Ce travail propose la conception des éléments clefs qui constituent les chaines d'instrumentations de capteurs… (more)

Subjects/Keywords: Convertisseur Analogique/Numérique; CAN SAR; CAN Sigma Delta; Chaine d’amplification analogique; Analog-to-Digital Converter; ADC SAR; ADC Sigma Delta; Analog amplifier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Regis, G. (2011). Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2011GRENA001

Chicago Manual of Style (16th Edition):

Regis, Guillaume. “Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning.” 2011. Doctoral Dissertation, Université de Grenoble. Accessed December 09, 2019. http://www.theses.fr/2011GRENA001.

MLA Handbook (7th Edition):

Regis, Guillaume. “Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning.” 2011. Web. 09 Dec 2019.

Vancouver:

Regis G. Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning. [Internet] [Doctoral dissertation]. Université de Grenoble; 2011. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2011GRENA001.

Council of Science Editors:

Regis G. Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning. [Doctoral Dissertation]. Université de Grenoble; 2011. Available from: http://www.theses.fr/2011GRENA001


Tokyo Institute of Technology / 東京工業大学

29. Lin, James Tzu-Chin. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.

Degree: 博士(学術), 2014, Tokyo Institute of Technology / 東京工業大学

 This thesis presents a design strategy for ultra-low-voltage (ULV) high-speed analog-to-digital converters (ADCs). To verify the proposed design strategy, three unique ULV high-speed ADCs and… (more)

Subjects/Keywords: analog-to-digital converters (ADCs); charge-steering; dynamic amplifier; high-speed; interpolation; ultra-low-voltage (ULV); flash ADCs; successive approximation register (SAR) ADCs; pipelined ADCs; pipelined-SAR ADCs; FoM-delay (FD) product

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, J. T. (2014). Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. (Thesis). Tokyo Institute of Technology / 東京工業大学. Retrieved from http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, James Tzu-Chin. “Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.” 2014. Thesis, Tokyo Institute of Technology / 東京工業大学. Accessed December 09, 2019. http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, James Tzu-Chin. “Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.” 2014. Web. 09 Dec 2019.

Vancouver:

Lin JT. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. [Internet] [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. [cited 2019 Dec 09]. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin JT. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Tokyo Institute of Technology / 東京工業大学

30. Lin, James Tzu-Chin. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.

Degree: 博士(学術), 2014, Tokyo Institute of Technology / 東京工業大学

 This thesis presents a design strategy for ultra-low-voltage (ULV) high-speed analog-to-digital converters (ADCs). To verify the proposed design strategy, three unique ULV high-speed ADCs and… (more)

Subjects/Keywords: analog-to-digital converters (ADCs); charge-steering; dynamic amplifier; high-speed; interpolation; ultra-low-voltage (ULV); flash ADCs; successive approximation register (SAR) ADCs; pipelined ADCs; pipelined-SAR ADCs; FoM-delay (FD) product

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, J. T. (2014). Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. (Thesis). Tokyo Institute of Technology / 東京工業大学. Retrieved from http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, James Tzu-Chin. “Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.” 2014. Thesis, Tokyo Institute of Technology / 東京工業大学. Accessed December 09, 2019. http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, James Tzu-Chin. “Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.” 2014. Web. 09 Dec 2019.

Vancouver:

Lin JT. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. [Internet] [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. [cited 2019 Dec 09]. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin JT. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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