Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Stuck at fault). Showing records 1 – 3 of 3 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


Texas A&M University

1. Layek, Ritwik. Pathways, Networks and Therapy: A Boolean Approach to Systems Biology.

Degree: PhD, Electrical Engineering, 2012, Texas A&M University

The area of systems biology evolved in an attempt to introduce mathematical systems theory principles in biology. Although we believe that all biological processes are essentially chemical reactions, describing those using precise mathematical rules is not easy, primarily due to the complexity and enormity of biological systems. Here we introduce a formal approach for modeling biological dynamical relationships and diseases such as cancer. The immediate motivation behind this research is the urgency to find a practicable cure of cancer, the emperor of all maladies. Unlike other deadly endemic diseases such as plague, dengue and AIDS, cancer is characteristically heterogenic and hence requires a closer look into the genesis of the disease. The actual cause of cancer lies within our physiology. The process of cell division holds the clue to unravel the mysteries surrounding this disease. In normal scenario, all control mechanisms work in tandem and cell divides only when the division is required, for instance, to heal a wound platelet derived growth factor triggers cell division. The control mechanism is tightly regulated by several biochemical interactions commonly known as signal transduction pathways. However, from mathematical point of view, these pathways are marginal in nature and unable to cope with the multi-variability of a heterogenic disease like cancer. The present research is possibly one first attempt towards unraveling the mysteries surrounding the dynamics of a proliferating cell. A novel yet simple methodology is developed to bring all the marginal knowledge of the signaling pathways together to form the simplest mathematical abstract known as the Boolean Network. The malfunctioning in the cell by genetic mutations is formally modeled as stuck-at faults in the underlying Network. Finally a mathematical methodology is discovered to optimally find out the possible best combination drug therapy which can drive the cell from an undesirable condition of proliferation to a desirable condition of quiescence or apoptosis. Although, the complete biological validation was beyond the scope of the current research, the process of in-vitro validation has been already initiated by our collaborators. Once validated, this research will lead to a bright future in the field on personalized cancer therapy. Advisors/Committee Members: Datta, Aniruddha (advisor), Dougherty, Edward R. (advisor), Bhattacharyya, Shankar P. (committee member), Sivakumar, N (committee member).

Subjects/Keywords: Systems Biology; Boolean Network; Probabilistic Boolean Network; Markov Chain; State transition diagram; Dynamic Programming; Therapeutic Intervention; Karnaugh Map; Signal Transduction Pathways; Regulatory Networks; DNA damage pathways; P53; Cancer; Cell Cycle; Growth Factor Mediated Pathways; Targeted Therapy; Combination Drug; Genetic Mutation; Stuck-at Faults; Fault Detection; Fault Classification

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Layek, R. (2012). Pathways, Networks and Therapy: A Boolean Approach to Systems Biology. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829

Chicago Manual of Style (16th Edition):

Layek, Ritwik. “Pathways, Networks and Therapy: A Boolean Approach to Systems Biology.” 2012. Doctoral Dissertation, Texas A&M University. Accessed March 04, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829.

MLA Handbook (7th Edition):

Layek, Ritwik. “Pathways, Networks and Therapy: A Boolean Approach to Systems Biology.” 2012. Web. 04 Mar 2021.

Vancouver:

Layek R. Pathways, Networks and Therapy: A Boolean Approach to Systems Biology. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829.

Council of Science Editors:

Layek R. Pathways, Networks and Therapy: A Boolean Approach to Systems Biology. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829

2. Velaga, Srikirti. Fault Modeling and Analysis for Multiple-Voltage Power Supplies in Low-Power Design.

Degree: MS, Engineering and Applied Science: Computer Engineering, 2013, University of Cincinnati

Over the past decade, with increasing advancements in technology, low-power design has become one of the most focused areas. Technology goes decreasing and the number of functionalities on a single IC increases. Process variations play a huge role during fabrication of devices with low feature sizes. Low-power design techniques pose a number of challenges during the design phase as well as the testing phase. One of the most commonly used technique for power reduction is using multi-voltage domains on the chip where each block can work at different supply voltages irrespective of the other blocks. Testing these designs implies testing at all operational voltages to ensure 100% fault coverage. The disadvantage of this brute-force solution is in the greatly increasing test cost and the test time.This research is focused on analyzing fault models and their behavior in multi-voltage power supplies and reducing test cost by suggesting a single test voltage for the fault models considered. Logical and temporal fault are considered in this work. Simulations are done using standard circuits that are designed using a 45nm technology with defects injected into them. The results obtained give a solid conclusion in the voltage that is to be used for maximum fault coverage. Advisors/Committee Members: Jone, Wen Ben (Committee Chair).

Subjects/Keywords: Computer Engineering; stuck at fault model in circuits; multi voltage design

…List of Figures 2.1 Single stuck-at fault… …31 3.7a Stuck-at 1 fault in a two-input NAND gate… …32 3.8 Stuck-at 0 fault in a two-input NAND gate… …25 3.9 Simulation result for stuck-at 1 fault at input A of the NAND gate… …31 3.10 Simulation result for stuck-at 0 fault at input A of the NAND gate… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Velaga, S. (2013). Fault Modeling and Analysis for Multiple-Voltage Power Supplies in Low-Power Design. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1368026670

Chicago Manual of Style (16th Edition):

Velaga, Srikirti. “Fault Modeling and Analysis for Multiple-Voltage Power Supplies in Low-Power Design.” 2013. Masters Thesis, University of Cincinnati. Accessed March 04, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1368026670.

MLA Handbook (7th Edition):

Velaga, Srikirti. “Fault Modeling and Analysis for Multiple-Voltage Power Supplies in Low-Power Design.” 2013. Web. 04 Mar 2021.

Vancouver:

Velaga S. Fault Modeling and Analysis for Multiple-Voltage Power Supplies in Low-Power Design. [Internet] [Masters thesis]. University of Cincinnati; 2013. [cited 2021 Mar 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1368026670.

Council of Science Editors:

Velaga S. Fault Modeling and Analysis for Multiple-Voltage Power Supplies in Low-Power Design. [Masters Thesis]. University of Cincinnati; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1368026670

3. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This dissertation shows that high-level synthesis also has the power to address validation and reliability challenges through three automated solutions targeting three key stages in the hardware design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment error detection. Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software implementation at a fine temporal and spatial granularity to detect logic bugs. An integrated backtrace process delivers source-code meaning to the hardware designer, pinpointing the location of bug activation and providing a strong hint for potential bug fixes. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself. A variation of this solution tailored for rapid post-silicon validation of accelerator designs is hybrid hashing: inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using hybrid hashing, we demonstrate an improvement in error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. Hybrid hashing also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. Hybrid hashing incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by hybrid hashing. Finally, our solution for post-deployment error detection is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling… Advisors/Committee Members: Chen, Deming (advisor), Chen, Deming (Committee Chair), Hwu, Wen-Mei W (committee member), Wong, Martin D F (committee member), Kim, Nam Sung (committee member).

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…to the gate with the stuck-at fault are such that the output should be 1 (0). The… …as stuck-at faults: wires that are supposed to be the output of a logic gate are stuck at… …though the final value arrives too late. 1.2.2 Stuck-at Faults Fabrication defects result in… …gate outputs being stuck at either a 0 or a 1. The more dramatic wear-out problems that cause… …a net from its original driver and connect it to a constant logic 0 or 1 instead. Stuck-at… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 04 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

.