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You searched for subject:(Static Timing Analysis). Showing records 1 – 30 of 30 total matches.

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University of Ottawa

1. Fu, Jingyi J.Y. Delay Analysis of Digital Circuits Using Prony's Method .

Degree: 2011, University of Ottawa

 This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in… (more)

Subjects/Keywords: Prony's method; Timing Analysis; Obreshokov; numerical method; Dynamic Timing Analysis (DTA); Static Timing Analysis (STA)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fu, J. J. Y. (2011). Delay Analysis of Digital Circuits Using Prony's Method . (Thesis). University of Ottawa. Retrieved from http://hdl.handle.net/10393/20125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fu, Jingyi J Y. “Delay Analysis of Digital Circuits Using Prony's Method .” 2011. Thesis, University of Ottawa. Accessed December 08, 2019. http://hdl.handle.net/10393/20125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fu, Jingyi J Y. “Delay Analysis of Digital Circuits Using Prony's Method .” 2011. Web. 08 Dec 2019.

Vancouver:

Fu JJY. Delay Analysis of Digital Circuits Using Prony's Method . [Internet] [Thesis]. University of Ottawa; 2011. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/10393/20125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fu JJY. Delay Analysis of Digital Circuits Using Prony's Method . [Thesis]. University of Ottawa; 2011. Available from: http://hdl.handle.net/10393/20125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

2. Kim, Hyun Sung. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.

Degree: 2009, Texas A&M University

 As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the… (more)

Subjects/Keywords: Statistical Static Timing Analysis; power supply noise

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APA (6th Edition):

Kim, H. S. (2009). Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Hyun Sung. “Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.” 2009. Thesis, Texas A&M University. Accessed December 08, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-1902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Hyun Sung. “Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.” 2009. Web. 08 Dec 2019.

Vancouver:

Kim HS. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim HS. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

3. Shriram, Vignesh. Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits.

Degree: M.S.E.E., Electrical/Computer Engineering, 2019, University of Minnesota

 Coupling capacitance is becoming increasingly problematic at the more advanced technology nodes and affects the timing and sign-off timeline of integrated circuits (ICs). As the… (more)

Subjects/Keywords: coupling capacitance; static timing analysis; VLSI

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APA (6th Edition):

Shriram, V. (2019). Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/206136

Chicago Manual of Style (16th Edition):

Shriram, Vignesh. “Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits.” 2019. Masters Thesis, University of Minnesota. Accessed December 08, 2019. http://hdl.handle.net/11299/206136.

MLA Handbook (7th Edition):

Shriram, Vignesh. “Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits.” 2019. Web. 08 Dec 2019.

Vancouver:

Shriram V. Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits. [Internet] [Masters thesis]. University of Minnesota; 2019. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/11299/206136.

Council of Science Editors:

Shriram V. Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits. [Masters Thesis]. University of Minnesota; 2019. Available from: http://hdl.handle.net/11299/206136


NSYSU

4. Hsieh, Kai-Yang. Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 Small Delay Defect (SDD) is one kind of the signal transition delay faults. It could not be detected via traditional delay testing method because the… (more)

Subjects/Keywords: Commercial ATPG Tool; False Path; Statistical Static Timing Analysis; Timing-aware ATPG; Small Delay Defect

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APA (6th Edition):

Hsieh, K. (2013). Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsieh, Kai-Yang. “Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection.” 2013. Thesis, NSYSU. Accessed December 08, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsieh, Kai-Yang. “Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection.” 2013. Web. 08 Dec 2019.

Vancouver:

Hsieh K. Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh K. Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Ko, Xue-Da. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 With the improvement of semiconductor manufacturing processes, the power consumption of the integrated circuit(IC) is growing rapidly. Therefore, the power consumption reduction of IC is… (more)

Subjects/Keywords: Static Timing Analysis; Level Converter; Critical Path; Multiple-Supply Voltage

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APA (6th Edition):

Ko, X. (2013). Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Thesis, NSYSU. Accessed December 08, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Web. 08 Dec 2019.

Vancouver:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Case Western Reserve University

6. Krishnamurthy, Sivasubramaniam T. STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.

Degree: MSs (Engineering), Computer Engineering, 2008, Case Western Reserve University

 As designers build complex digital circuits with ever diminishing device sizes, there is a need to obtain fast circuits with low hardware overhead. Critical path… (more)

Subjects/Keywords: Static Timing Analysis; Partitioning; Heuristics; Microprocessors; Digital Logic; VLSI

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APA (6th Edition):

Krishnamurthy, S. T. (2008). STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS. (Masters Thesis). Case Western Reserve University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462

Chicago Manual of Style (16th Edition):

Krishnamurthy, Sivasubramaniam T. “STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.” 2008. Masters Thesis, Case Western Reserve University. Accessed December 08, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

MLA Handbook (7th Edition):

Krishnamurthy, Sivasubramaniam T. “STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.” 2008. Web. 08 Dec 2019.

Vancouver:

Krishnamurthy ST. STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS. [Internet] [Masters thesis]. Case Western Reserve University; 2008. [cited 2019 Dec 08]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

Council of Science Editors:

Krishnamurthy ST. STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS. [Masters Thesis]. Case Western Reserve University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462

7. Gaspar, Nuno Miguel Pires. Timing analysis: from predictions to certificates.

Degree: 2010, RCAAP

 In real-time systems timing properties must be satisfied in order to guarantee that deadlines will be met. In this context, the calculation of theworst-case execution… (more)

Subjects/Keywords: Timing analysis; Worst-case execution time; Static analysis; Fixpoint computation; Abstract interpretation; Abstraction-carrying code

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APA (6th Edition):

Gaspar, N. M. P. (2010). Timing analysis: from predictions to certificates. (Thesis). RCAAP. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gaspar, Nuno Miguel Pires. “Timing analysis: from predictions to certificates.” 2010. Thesis, RCAAP. Accessed December 08, 2019. http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gaspar, Nuno Miguel Pires. “Timing analysis: from predictions to certificates.” 2010. Web. 08 Dec 2019.

Vancouver:

Gaspar NMP. Timing analysis: from predictions to certificates. [Internet] [Thesis]. RCAAP; 2010. [cited 2019 Dec 08]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gaspar NMP. Timing analysis: from predictions to certificates. [Thesis]. RCAAP; 2010. Available from: http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

8. Joshi, Prasad. Static timing analysis of GasP.

Degree: MS, Electrical Engineering, 2008, University of Southern California

 The 6-4 GasP family of asynchronous circuits has been sought for its potential advantages of ultra-high performance and low power especially in the processor and… (more)

Subjects/Keywords: GasP; static timing analysis; asynchronous; STA

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APA (6th Edition):

Joshi, P. (2008). Static timing analysis of GasP. (Masters Thesis). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/128888/rec/6036

Chicago Manual of Style (16th Edition):

Joshi, Prasad. “Static timing analysis of GasP.” 2008. Masters Thesis, University of Southern California. Accessed December 08, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/128888/rec/6036.

MLA Handbook (7th Edition):

Joshi, Prasad. “Static timing analysis of GasP.” 2008. Web. 08 Dec 2019.

Vancouver:

Joshi P. Static timing analysis of GasP. [Internet] [Masters thesis]. University of Southern California; 2008. [cited 2019 Dec 08]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/128888/rec/6036.

Council of Science Editors:

Joshi P. Static timing analysis of GasP. [Masters Thesis]. University of Southern California; 2008. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/128888/rec/6036

9. Kang, Sang Yeol. Providing Static Timing Anlaysis Support for an ARM7 Processor Platform.

Degree: MS, Computer Engineering, 2008, North Carolina State University

 Scratchpad memory provides faster speed but smaller capacity than other memories do in embedded systems. It provides a visibly heterogeneous memory hierarchy rather than abstracting… (more)

Subjects/Keywords: Static Timing Analysis; WCET; BCET

…ABSTRACT KANG, SANG YEOL. Providing Static Timing Analysis Support for an ARM7 Processor… …program’s timing information. Based on the WCET and BCET estimated by static timing analysis, the… …unstructured code are also identified, which make static timing analysis more difficult. A control… …In addition, the static timing analysis framework of this study is implemented by the tool… …execution times. Providing Static Timing Analysis Support for an ARM7 Processor Platform by Sang… 

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APA (6th Edition):

Kang, S. Y. (2008). Providing Static Timing Anlaysis Support for an ARM7 Processor Platform. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kang, Sang Yeol. “Providing Static Timing Anlaysis Support for an ARM7 Processor Platform.” 2008. Thesis, North Carolina State University. Accessed December 08, 2019. http://www.lib.ncsu.edu/resolver/1840.16/1546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kang, Sang Yeol. “Providing Static Timing Anlaysis Support for an ARM7 Processor Platform.” 2008. Web. 08 Dec 2019.

Vancouver:

Kang SY. Providing Static Timing Anlaysis Support for an ARM7 Processor Platform. [Internet] [Thesis]. North Carolina State University; 2008. [cited 2019 Dec 08]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kang SY. Providing Static Timing Anlaysis Support for an ARM7 Processor Platform. [Thesis]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

10. WANG, CHIH-KUAN. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

 This thesis presents an iterative, crosstalk aware timing analyzer. Parameters such as slew rate, voltage supply, coupling capacitance, and load capacitance are shown to affect… (more)

Subjects/Keywords: crosstalk; capacitive crosstalk; dual-vdd; timing analysis; static timing analysis

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APA (6th Edition):

WANG, C. (2006). AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235

Chicago Manual of Style (16th Edition):

WANG, CHIH-KUAN. “AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER.” 2006. Masters Thesis, University of Cincinnati. Accessed December 08, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235.

MLA Handbook (7th Edition):

WANG, CHIH-KUAN. “AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER.” 2006. Web. 08 Dec 2019.

Vancouver:

WANG C. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2019 Dec 08]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235.

Council of Science Editors:

WANG C. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235


Universidade do Rio Grande do Sul

11. Machado, Lucas. KL-cut based remapping.

Degree: 2013, Universidade do Rio Grande do Sul

This work introduces the concept of k-cuts and kl-cuts on top of a mapped circuit in a netlist representation. Such new approach is derived from… (more)

Subjects/Keywords: Digital circuits; Microeletrônica; Logic synthesis; Circuitos digitais; Technology mapping; Cut enumeration; Static timing analysis; Remapping; Lithography

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APA (6th Edition):

Machado, L. (2013). KL-cut based remapping. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/116138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Machado, Lucas. “KL-cut based remapping.” 2013. Thesis, Universidade do Rio Grande do Sul. Accessed December 08, 2019. http://hdl.handle.net/10183/116138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Machado, Lucas. “KL-cut based remapping.” 2013. Web. 08 Dec 2019.

Vancouver:

Machado L. KL-cut based remapping. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2013. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/10183/116138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Machado L. KL-cut based remapping. [Thesis]. Universidade do Rio Grande do Sul; 2013. Available from: http://hdl.handle.net/10183/116138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

12. Choi, Munkang. Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis.

Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech

 As semiconductor technology advances into the nano-scale era and more functional blocks are added into systems on chip (SoC), the interface between circuit design and… (more)

Subjects/Keywords: DFM; Lithography; CMP; Within-die variation; Static timing analysis

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APA (6th Edition):

Choi, M. (2007). Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/14544

Chicago Manual of Style (16th Edition):

Choi, Munkang. “Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis.” 2007. Doctoral Dissertation, Georgia Tech. Accessed December 08, 2019. http://hdl.handle.net/1853/14544.

MLA Handbook (7th Edition):

Choi, Munkang. “Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis.” 2007. Web. 08 Dec 2019.

Vancouver:

Choi M. Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/1853/14544.

Council of Science Editors:

Choi M. Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/14544


University of Southern California

13. Prakash, Mallika. Library characterization and static timing analysis of asynchornous circuits.

Degree: MS, Computer Engineering, 2007, University of Southern California

 For main stream acceptance of asynchronous circuits, a mature EDA tool flow is necessary that leverages off commercially available libraries and tools for synchronous circuits.… (more)

Subjects/Keywords: asynchornous circuits; library characterization; static timing analysis

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APA (6th Edition):

Prakash, M. (2007). Library characterization and static timing analysis of asynchornous circuits. (Masters Thesis). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/593805/rec/3810

Chicago Manual of Style (16th Edition):

Prakash, Mallika. “Library characterization and static timing analysis of asynchornous circuits.” 2007. Masters Thesis, University of Southern California. Accessed December 08, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/593805/rec/3810.

MLA Handbook (7th Edition):

Prakash, Mallika. “Library characterization and static timing analysis of asynchornous circuits.” 2007. Web. 08 Dec 2019.

Vancouver:

Prakash M. Library characterization and static timing analysis of asynchornous circuits. [Internet] [Masters thesis]. University of Southern California; 2007. [cited 2019 Dec 08]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/593805/rec/3810.

Council of Science Editors:

Prakash M. Library characterization and static timing analysis of asynchornous circuits. [Masters Thesis]. University of Southern California; 2007. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/593805/rec/3810


University of Minnesota

14. Marella, Sravan. Performance variations due to layout-dependent stress in VLSI circuits.

Degree: PhD, Electrical Engineering, 2015, University of Minnesota

 Layout-dependent stress is a significant source of variability in advanced VLSI technologies that impacts circuit performance. Mechanical stress affects transistor electrical parameters mobility and threshold… (more)

Subjects/Keywords: 3D-IC; FinFET; Layout dependent mechanical stress; Shallow trench isolation; Static Timing Analysis; Through silicon via

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APA (6th Edition):

Marella, S. (2015). Performance variations due to layout-dependent stress in VLSI circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/175249

Chicago Manual of Style (16th Edition):

Marella, Sravan. “Performance variations due to layout-dependent stress in VLSI circuits.” 2015. Doctoral Dissertation, University of Minnesota. Accessed December 08, 2019. http://hdl.handle.net/11299/175249.

MLA Handbook (7th Edition):

Marella, Sravan. “Performance variations due to layout-dependent stress in VLSI circuits.” 2015. Web. 08 Dec 2019.

Vancouver:

Marella S. Performance variations due to layout-dependent stress in VLSI circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2015. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/11299/175249.

Council of Science Editors:

Marella S. Performance variations due to layout-dependent stress in VLSI circuits. [Doctoral Dissertation]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/175249


University of Illinois – Urbana-Champaign

15. Lucas, Gregory M. Timing Analysis and Behavioral Synthesis with Process Variation.

Degree: MS, Electrical and Computer Engineering, 2009, University of Illinois – Urbana-Champaign

 The move to deep submicron processes has brought about new problems that designers must contend with in order to obtain functional circuits. Process variation has… (more)

Subjects/Keywords: process variation; high-level synthesis; behavioral synthesis; statistical static timing analysis; SSTA; multi-cycle; multi-clock

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lucas, G. M. (2009). Timing Analysis and Behavioral Synthesis with Process Variation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/11966

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lucas, Gregory M. “Timing Analysis and Behavioral Synthesis with Process Variation.” 2009. Thesis, University of Illinois – Urbana-Champaign. Accessed December 08, 2019. http://hdl.handle.net/2142/11966.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lucas, Gregory M. “Timing Analysis and Behavioral Synthesis with Process Variation.” 2009. Web. 08 Dec 2019.

Vancouver:

Lucas GM. Timing Analysis and Behavioral Synthesis with Process Variation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2009. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/2142/11966.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lucas GM. Timing Analysis and Behavioral Synthesis with Process Variation. [Thesis]. University of Illinois – Urbana-Champaign; 2009. Available from: http://hdl.handle.net/2142/11966

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

16. Ramaprasad, Harini. Analytical Bounding Data Cache Behavior for Real-Time Systems.

Degree: PhD, Computer Science, 2008, North Carolina State University

 This dissertation presents data cache analysis techniques that make it feasible to predict data cache behavior and to bound the worst-case execution time for a… (more)

Subjects/Keywords: WCET; data cache; static timing analysis; real-time

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APA (6th Edition):

Ramaprasad, H. (2008). Analytical Bounding Data Cache Behavior for Real-Time Systems. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/4583

Chicago Manual of Style (16th Edition):

Ramaprasad, Harini. “Analytical Bounding Data Cache Behavior for Real-Time Systems.” 2008. Doctoral Dissertation, North Carolina State University. Accessed December 08, 2019. http://www.lib.ncsu.edu/resolver/1840.16/4583.

MLA Handbook (7th Edition):

Ramaprasad, Harini. “Analytical Bounding Data Cache Behavior for Real-Time Systems.” 2008. Web. 08 Dec 2019.

Vancouver:

Ramaprasad H. Analytical Bounding Data Cache Behavior for Real-Time Systems. [Internet] [Doctoral dissertation]. North Carolina State University; 2008. [cited 2019 Dec 08]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4583.

Council of Science Editors:

Ramaprasad H. Analytical Bounding Data Cache Behavior for Real-Time Systems. [Doctoral Dissertation]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4583


North Carolina State University

17. Patil, Kaustubh Sambhaji. Compositional Static Cache Analysis Using Module-level Abstraction.

Degree: MS, Computer Science, 2003, North Carolina State University

Static cache analysis is utilized for timing analysis to derive worst-case execution time of a program. Such analysis is constrained by the requirement of an… (more)

Subjects/Keywords: compositional approach; timing analysis; static cache simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patil, K. S. (2003). Compositional Static Cache Analysis Using Module-level Abstraction. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Patil, Kaustubh Sambhaji. “Compositional Static Cache Analysis Using Module-level Abstraction.” 2003. Thesis, North Carolina State University. Accessed December 08, 2019. http://www.lib.ncsu.edu/resolver/1840.16/1445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Patil, Kaustubh Sambhaji. “Compositional Static Cache Analysis Using Module-level Abstraction.” 2003. Web. 08 Dec 2019.

Vancouver:

Patil KS. Compositional Static Cache Analysis Using Module-level Abstraction. [Internet] [Thesis]. North Carolina State University; 2003. [cited 2019 Dec 08]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Patil KS. Compositional Static Cache Analysis Using Module-level Abstraction. [Thesis]. North Carolina State University; 2003. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Jesuthasan, Jude Arun Selvan. Incremental Timing-Driven Placement with Displacement Constraint.

Degree: 2015, University of Waterloo

 In the modern deep-submicron Very Large Integrated Circuit(VLSI) design flow intercon- nect delays are becoming major limiting factor for timing closure. Traditional placement algorithms such… (more)

Subjects/Keywords: Timing closure; Timing-driven placement; Placement density; Static timing analysis; Algorithm

Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.4 Problem… …3.2.2 Parallel Static Timing Analysis . . . . . . . . . . . . . . . . . . . . 30 3.2.3… …Computer Aided Design STA Static Timing Analysis TNS Total Negative Slack WNS Worst Negative… …using a metric knows as slacks, which is obtained by performing Static Timing Analysis (… …placement objectives and timing-driven placement. We also describe static timing analysis… 

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APA (6th Edition):

Jesuthasan, J. A. S. (2015). Incremental Timing-Driven Placement with Displacement Constraint. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/9461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jesuthasan, Jude Arun Selvan. “Incremental Timing-Driven Placement with Displacement Constraint.” 2015. Thesis, University of Waterloo. Accessed December 08, 2019. http://hdl.handle.net/10012/9461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jesuthasan, Jude Arun Selvan. “Incremental Timing-Driven Placement with Displacement Constraint.” 2015. Web. 08 Dec 2019.

Vancouver:

Jesuthasan JAS. Incremental Timing-Driven Placement with Displacement Constraint. [Internet] [Thesis]. University of Waterloo; 2015. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/10012/9461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jesuthasan JAS. Incremental Timing-Driven Placement with Displacement Constraint. [Thesis]. University of Waterloo; 2015. Available from: http://hdl.handle.net/10012/9461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Shen, Yiren. Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits.

Degree: 2016, Texas A&M University

 Adaptive circuit design is a power-efficient approach to handle variations. Compared to conventional circuits, its implementation is more complicated especially when we deal with the… (more)

Subjects/Keywords: parallel acceleration; adaptive circuits; statistical static timing analysis

…also fundamental to provide assurance for design timing closure. Static Timing Analysis (… …variations more effectively, statistical static timing analysis (SSTA) was proposed and… …static timing analysis with PCA (Principal Component Analysis). It is demonstrated in… …Circuits 7 II-C. Static Timing Analysis STA is a fundamental tool to support VLSI circuit… …variations especially the spatial correlation. II-D. Statistical Static Timing Analysis The SSTA… 

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APA (6th Edition):

Shen, Y. (2016). Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shen, Yiren. “Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits.” 2016. Thesis, Texas A&M University. Accessed December 08, 2019. http://hdl.handle.net/1969.1/156792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shen, Yiren. “Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits.” 2016. Web. 08 Dec 2019.

Vancouver:

Shen Y. Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits. [Internet] [Thesis]. Texas A&M University; 2016. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/1969.1/156792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shen Y. Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits. [Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

20. Chilstedt, Scott E. Architecture and CAD for carbon nanomaterial integrated circuits.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 The ITRS (International Technology Roadmap for Semiconductors) has recommended that carbon-based transistors be given further study as a potential ???Beyond CMOS??? technology. Unlike traditional devices… (more)

Subjects/Keywords: Carbon Nanotubes; Graphene Nanoribbons; Carbon Nanomaterial Transistors; Nanoelectronic Architectures; Field programmable carbon nanotube array (FPCNA); Variation-Aware CAD; Discretized statistical static timing analysis (SSTA)

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APA (6th Edition):

Chilstedt, S. E. (2010). Architecture and CAD for carbon nanomaterial integrated circuits. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/15969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chilstedt, Scott E. “Architecture and CAD for carbon nanomaterial integrated circuits.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed December 08, 2019. http://hdl.handle.net/2142/15969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chilstedt, Scott E. “Architecture and CAD for carbon nanomaterial integrated circuits.” 2010. Web. 08 Dec 2019.

Vancouver:

Chilstedt SE. Architecture and CAD for carbon nanomaterial integrated circuits. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/2142/15969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chilstedt SE. Architecture and CAD for carbon nanomaterial integrated circuits. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/15969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Li, Chaobo. Gate-level timing analysis and waveform evaluation.

Degree: PhD, Electrical Engineering and Computer Science, 2015, Syracuse University

Static timing analysis (STA) is an integral part of modern VLSI chip design. Table lookup based methods are widely used in current industry due… (more)

Subjects/Keywords: interconnection; static timing analysis; table lookup; waveform; Engineering

timing analysis can be categorized into dynamic or static. Dynamic timing analysis requires a… …7 2.1 Introduction Static timing analysis (STA) is largely used in CMOS circuit… …89 viii 1 Chapter 1 Introduction Timing analysis is an integral part of modern Very… …Large-Scale-Integration (VLSI) chip design. Timing analysis, such as functional… …Timing Analysis (STA) checks if the design meets the timing constraints. SPICE is the… 

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APA (6th Edition):

Li, C. (2015). Gate-level timing analysis and waveform evaluation. (Doctoral Dissertation). Syracuse University. Retrieved from https://surface.syr.edu/etd/220

Chicago Manual of Style (16th Edition):

Li, Chaobo. “Gate-level timing analysis and waveform evaluation.” 2015. Doctoral Dissertation, Syracuse University. Accessed December 08, 2019. https://surface.syr.edu/etd/220.

MLA Handbook (7th Edition):

Li, Chaobo. “Gate-level timing analysis and waveform evaluation.” 2015. Web. 08 Dec 2019.

Vancouver:

Li C. Gate-level timing analysis and waveform evaluation. [Internet] [Doctoral dissertation]. Syracuse University; 2015. [cited 2019 Dec 08]. Available from: https://surface.syr.edu/etd/220.

Council of Science Editors:

Li C. Gate-level timing analysis and waveform evaluation. [Doctoral Dissertation]. Syracuse University; 2015. Available from: https://surface.syr.edu/etd/220

22. Zheng, X.Y. Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:.

Degree: 2012, Delft University of Technology

Static Timing Analysis (STA) is one approach to verify the timing of a digital circuit. The currently used Gate Level Model (GLM) has limitations on… (more)

Subjects/Keywords: Static Timing Analysis; Verilog-AMS; transistor level model; spectre; polynomial curve fitting; statistical timing analysis

…56 xiv 1 Introduction Static Timing Analysis (STA) is an approach to… …path, which is usually done by Static Timing Analysis (STA). STA is static because… …11 12 13 13 14 15 16 16 18 18 20 4 Deterministic Timing Analysis 4.1 Direct Current (… …Statistical Timing Analysis 5.1 The sensitivity of the transistor model… …deterministic timing analysis simulation . . . . . . . . . 2.1 2.2 2.3 2.4 2.5 2.6 Definition of… 

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APA (6th Edition):

Zheng, X. Y. (2012). Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:84ff0f8e-ec0a-4b77-8fa9-9df7eaef6b60

Chicago Manual of Style (16th Edition):

Zheng, X Y. “Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:.” 2012. Masters Thesis, Delft University of Technology. Accessed December 08, 2019. http://resolver.tudelft.nl/uuid:84ff0f8e-ec0a-4b77-8fa9-9df7eaef6b60.

MLA Handbook (7th Edition):

Zheng, X Y. “Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:.” 2012. Web. 08 Dec 2019.

Vancouver:

Zheng XY. Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2019 Dec 08]. Available from: http://resolver.tudelft.nl/uuid:84ff0f8e-ec0a-4b77-8fa9-9df7eaef6b60.

Council of Science Editors:

Zheng XY. Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:84ff0f8e-ec0a-4b77-8fa9-9df7eaef6b60

23. Pendela Venkata Ramanjuneya, Suryanarayana. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits.

Degree: MS, Engineering : Computer Engineering, 2010, University of Cincinnati

 Much of the Semiconductor Industry’s success can be attributed to Moore’s law whichstates that the number of transistors on an integrated circuit would double approximatelyevery… (more)

Subjects/Keywords: Electrical Engineering; sta; timing; process variations; ssta; static timing analysis; standard cell

…a new class of STA called Statistical Static Timing Analysis (SSTA). Another… …Timing Analysis engine in the figure. The authors envision the usage of a Interval Valued Static… …developed in C++ which performs interval valued static timing analysis that can guide the… …of future work in Chapter 6. 14 Chapter 2 Static Timing Analysis Static Timing Analysis… …0.406534, 0.51187"); } 23 Chapter 3 Interval Valued Static Timing Analysis 3.1… 

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APA (6th Edition):

Pendela Venkata Ramanjuneya, S. (2010). Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324

Chicago Manual of Style (16th Edition):

Pendela Venkata Ramanjuneya, Suryanarayana. “Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits.” 2010. Masters Thesis, University of Cincinnati. Accessed December 08, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324.

MLA Handbook (7th Edition):

Pendela Venkata Ramanjuneya, Suryanarayana. “Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits.” 2010. Web. 08 Dec 2019.

Vancouver:

Pendela Venkata Ramanjuneya S. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. [Internet] [Masters thesis]. University of Cincinnati; 2010. [cited 2019 Dec 08]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324.

Council of Science Editors:

Pendela Venkata Ramanjuneya S. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. [Masters Thesis]. University of Cincinnati; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324

24. Tsiampas, Michail. Timing analysis and power integrity of integrated circuits in technologies below 60nm.

Degree: 2019, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας

 Technology Process continues to evolve, scaling down transistor sizes aiming to decrease power supply nominal voltages as the easiest way to lower the power footprint.… (more)

Subjects/Keywords: Ανάλυση ισχύος; Ανάλυση χρονισμού; Πτώση τάσης; Στατική ανάλυση χρονισμού; Δυναμική ανάλυση χρονισμού; Μηχανή στατιστικής πρόβλεψης; Θεωρία ακραίων τιμών; Γραμμικός αναλυτής; Γραμμές μεταφοράς; Power integrity; Timing analysis; Voltage - drop; Statistical prediction engine; Static timing analysis; Statistical prediction engine; Extreme value theory; Linear solver; Transmission lines; Bivariate joint process variation

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APA (6th Edition):

Tsiampas, M. (2019). Timing analysis and power integrity of integrated circuits in technologies below 60nm. (Thesis). University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Retrieved from http://hdl.handle.net/10442/hedi/45356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsiampas, Michail. “Timing analysis and power integrity of integrated circuits in technologies below 60nm.” 2019. Thesis, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Accessed December 08, 2019. http://hdl.handle.net/10442/hedi/45356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsiampas, Michail. “Timing analysis and power integrity of integrated circuits in technologies below 60nm.” 2019. Web. 08 Dec 2019.

Vancouver:

Tsiampas M. Timing analysis and power integrity of integrated circuits in technologies below 60nm. [Internet] [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2019. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/10442/hedi/45356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsiampas M. Timing analysis and power integrity of integrated circuits in technologies below 60nm. [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2019. Available from: http://hdl.handle.net/10442/hedi/45356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Aftabjahani, Seyed-Abdollah. Compact variation-aware standard cells for statistical static timing analysis.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 This dissertation reports on a new methodology to characterize and simulate a standard cell library to be used for statistical static timing analysis. A compact… (more)

Subjects/Keywords: Variation-aware standard cell modeling; Process and environmental variation; Variation-aware waveform modeling; Statistical static timing analysis; Static timing analysis; Integrated circuits; Microelectronics; Standard cells

…Exchange Format SSM Symetric Standardized Model SSTA Statistical Static Timing Analysis STA… …Static Timing Analysis SVD Singular Value Decomposition T Temperature TPHL Waveform… …library to be used for statistical static timing analysis. A compact variation-aware timing… …summary of the main contributions of this work to the statistical static timing analysis: (… …statistical static timing analysis authored by Dr. David Blaauw et al. [1] and Dr… 

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APA (6th Edition):

Aftabjahani, S. (2011). Compact variation-aware standard cells for statistical static timing analysis. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41129

Chicago Manual of Style (16th Edition):

Aftabjahani, Seyed-Abdollah. “Compact variation-aware standard cells for statistical static timing analysis.” 2011. Doctoral Dissertation, Georgia Tech. Accessed December 08, 2019. http://hdl.handle.net/1853/41129.

MLA Handbook (7th Edition):

Aftabjahani, Seyed-Abdollah. “Compact variation-aware standard cells for statistical static timing analysis.” 2011. Web. 08 Dec 2019.

Vancouver:

Aftabjahani S. Compact variation-aware standard cells for statistical static timing analysis. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/1853/41129.

Council of Science Editors:

Aftabjahani S. Compact variation-aware standard cells for statistical static timing analysis. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/41129

26. Rogachev, Artem. Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits.

Degree: MS, 1200, 2012, University of Illinois – Urbana-Champaign

 With technology scaling, the variability of device parameters continues to increase. Both performance and power consumption are quite sensitive to process parameters (PP) such as… (more)

Subjects/Keywords: Compact Modeling; Graphene Nano Ribbons; Statistical Static Timing Analysis; Process Variations; Thermal

…CHAPTER 2 TEMPERATURE-AWARE STATISTICAL STATIC TIMING ANALYSIS This work was a joint effort with… …statistical static timing analysis (SSTA) and the MC simulation. Lu characterized the… …temperature during timing analysis, most of the existing SSTA works do not take this into… …and supply variations during timing analysis. The authors of [8] obtain the… …algorithms to understand the complexity vs. accuracy trade-off for the timing analysis algorithm… 

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APA (6th Edition):

Rogachev, A. (2012). Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/32079

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rogachev, Artem. “Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits.” 2012. Thesis, University of Illinois – Urbana-Champaign. Accessed December 08, 2019. http://hdl.handle.net/2142/32079.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rogachev, Artem. “Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits.” 2012. Web. 08 Dec 2019.

Vancouver:

Rogachev A. Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2012. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/2142/32079.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rogachev A. Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits. [Thesis]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/32079

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

27. Feng, Zhuo. Modeling and Analysis of Large-Scale On-Chip Interconnects.

Degree: 2010, Texas A&M University

 As IC technologies scale to the nanometer regime, efficient and accurate modeling and analysis of VLSI systems with billions of transistors and interconnects becomes increasingly… (more)

Subjects/Keywords: process variation; statistical circuit modeling and analysis; model order reduction; statistical parameter dimension reduction; reduced rank regression; design-dependent interconnect corner extraction; statistical static timing analysis; power grid analysis; circuit simulation; general-purpose computation on graphics processing unit; GPU; massively parallel computing; multigrid; CUDA programming language; multi-core programming

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Feng, Z. (2010). Modeling and Analysis of Large-Scale On-Chip Interconnects. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Feng, Zhuo. “Modeling and Analysis of Large-Scale On-Chip Interconnects.” 2010. Thesis, Texas A&M University. Accessed December 08, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Feng, Zhuo. “Modeling and Analysis of Large-Scale On-Chip Interconnects.” 2010. Web. 08 Dec 2019.

Vancouver:

Feng Z. Modeling and Analysis of Large-Scale On-Chip Interconnects. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Feng Z. Modeling and Analysis of Large-Scale On-Chip Interconnects. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

28. Das, Bishnu Prasad. Random Local Delay Variability : On-chip Measurement And Modeling.

Degree: 2009, Indian Institute of Science

 This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in… (more)

Subjects/Keywords: Electronic Gates - Design; On-chip Management And Construction; Electronic Gate Delay - Modeling; Random Local Delay Variation; On-chip Gate Delay Measurement; Process Voltage And Temperature Gate Delay Model; Electronic Gate Delay - Measurement; Statistical Static Timing Analysis (SSTA); Gate Delay Variability Measurement; Delay Variability; On-chip Measurement; Gate Delay Models; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, B. P. (2009). Random Local Delay Variability : On-chip Measurement And Modeling. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Thesis, Indian Institute of Science. Accessed December 08, 2019. http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Web. 08 Dec 2019.

Vancouver:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

29. Neikter, Carl-Fredrik. Cache Prediction and Execution Time Analysis on Real-Time MPSoC.

Degree: Computer and Information Science, 2008, Linköping University

  Real-time systems do not only require that the logical operations are correct. Equally important is that the specified time constraints always are complied. This… (more)

Subjects/Keywords: Real-time systems; MPSoC; static timing analysis; worst case execution time; cache memory; cache analysis; data flow analysis; control flow graph; task generation; randomization; Computer Sciences; Datavetenskap (datalogi); Computer Engineering; Datorteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Neikter, C. (2008). Cache Prediction and Execution Time Analysis on Real-Time MPSoC. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15394

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Neikter, Carl-Fredrik. “Cache Prediction and Execution Time Analysis on Real-Time MPSoC.” 2008. Thesis, Linköping University. Accessed December 08, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15394.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Neikter, Carl-Fredrik. “Cache Prediction and Execution Time Analysis on Real-Time MPSoC.” 2008. Web. 08 Dec 2019.

Vancouver:

Neikter C. Cache Prediction and Execution Time Analysis on Real-Time MPSoC. [Internet] [Thesis]. Linköping University; 2008. [cited 2019 Dec 08]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15394.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Neikter C. Cache Prediction and Execution Time Analysis on Real-Time MPSoC. [Thesis]. Linköping University; 2008. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15394

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

30. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 08, 2019. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 08 Dec 2019.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

.