subject:(Soft Error)

University of Waterloo

1. Ghaznavi, Solmaz. Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA.

Degree: 2011, University of Waterloo

► This thesis presents a new architecture for the reliable implementation of the symmetric-key algorithm Advanced Encryption Standard (AES) in Field Programmable Gate Arrays (FPGAs). Since… (more)

Subjects/Keywords: soft error; AES

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APA (6^th Edition):

Ghaznavi, S. (2011). Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/5792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ghaznavi, Solmaz. “Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA.” 2011. Thesis, University of Waterloo. Accessed April 11, 2021. http://hdl.handle.net/10012/5792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ghaznavi, Solmaz. “Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA.” 2011. Web. 11 Apr 2021.

Vancouver:

Ghaznavi S. Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA. [Internet] [Thesis]. University of Waterloo; 2011. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10012/5792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ghaznavi S. Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA. [Thesis]. University of Waterloo; 2011. Available from: http://hdl.handle.net/10012/5792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

2. Ossi, Edward John. Soft-error mitigation at the architecture-level using Berger codes for error detection.

Degree: ME, Electrical Engineering, 2011, Vanderbilt University

URL: http://hdl.handle.net/1803/15019

► Soft-error mitigation using design techniques at the architecture-level can overcome the limitations of process and circuit-level mitigation techniques in advanced technologies. This thesis presents two… (more)

Subjects/Keywords: berger code; architecture; soft error

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APA (6^th Edition):

Ossi, E. J. (2011). Soft-error mitigation at the architecture-level using Berger codes for error detection. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Thesis, Vanderbilt University. Accessed April 11, 2021. http://hdl.handle.net/1803/15019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Web. 11 Apr 2021.

Vancouver:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Internet] [Thesis]. Vanderbilt University; 2011. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1803/15019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Thesis]. Vanderbilt University; 2011. Available from: http://hdl.handle.net/1803/15019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Saskatchewan

3. Xie, Hao 1988-. Study of Single Event Transient Error Mitigation.

Degree: 2017, University of Saskatchewan

URL: http://hdl.handle.net/10388/8025

► Single Event Transient (SET) errors in ground-level electronic devices are a growing concern in the radiation hardening field. However, effective SET mitigation technologies which satisfy… (more)

▼ Single Event Transient (SET) errors in ground-level electronic devices are a growing concern in the radiation hardening field. However, effective SET mitigation technologies which satisfy ground-level demands such as generic, flexible, efficient, and fast, are limited. The classic Triple Modular Redundancy (TMR) method is the most well-known and popular technique in space and nuclear environment. But it leads to more than 200% area and power overheads, which is too costly to implement in ground-level applications. Meanwhile, the coding technique is extensively utilized to inhibit upset errors in storage cells, but the irregularity of combinatorial logics limits its use in SET mitigation. Therefore, SET mitigation techniques suitable for ground-level applications need to be addressed. Aware of the demands for SET mitigation techniques in ground-level applications, this thesis proposes two novel approaches based on the redundant wire and approximate logic techniques. The Redundant Wire is a SET mitigation technique. By selectively adding redundant wire connections, the technique can prohibit targeted transient faults from propagating on the fly. This thesis proposes a set of signature-based evaluation equations to efficiently estimate the protecting effect provided by each redundant wire candidates. Based on the estimated results, a greedy algorithm is used to insert the best candidate repeatedly. Simulation results substantiate that the evaluation equations can achieve up to 98% accuracy on average. Regarding protecting effects, the technique can mask 18.4% of the faults with a 4.3% area, 4.4% power, and 5.4% delay overhead on average. Overall, the quality of protecting results obtained are 2.8 times better than the previous work. Additionally, the impact of synthesis constraints and signature length are discussed. Approximate Logic is a partial TMR technique offering a trade-off between fault coverage and area overheads. The approximate logic consists of an under-approximate logic and an over-approximate logic. The under-approximate logic is a subset of the original min-terms and the over-approximate logic is a subset of the original max-terms. This thesis proposes a new algorithm for generating the two approximate logics. Through the generating process, the algorithm considers the intrinsic failure probabilities of each gate and utilizes a confidence interval estimate equation to minimize required computations. The technique is applied to two fault models, Stuck-at and SET, and the separate results are compared and discussed. The results show that the technique can reduce the error 75% with an area penalty of 46% on some circuits. The delay overheads of this technique are always two additional layers of logic. The two proposed SET mitigation techniques are both applicable to generic combinatorial logics and with high flexibility. The simulation shows promising SET mitigation ability. The proposed mitigation techniques provide designers more choices in developing reliable combinatorial logic in ground-level… Advisors/Committee Members: Chen, Li, Gokaraju, Ramakrishna, Yang, Qiaoqin, Bui, Francis.

Subjects/Keywords: Single Event Transient; Soft Error Mitigation

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APA (6^th Edition):

Xie, H. 1. (2017). Study of Single Event Transient Error Mitigation. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/8025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Xie, Hao 1988-. “Study of Single Event Transient Error Mitigation.” 2017. Thesis, University of Saskatchewan. Accessed April 11, 2021. http://hdl.handle.net/10388/8025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Xie, Hao 1988-. “Study of Single Event Transient Error Mitigation.” 2017. Web. 11 Apr 2021.

Vancouver:

Xie H1. Study of Single Event Transient Error Mitigation. [Internet] [Thesis]. University of Saskatchewan; 2017. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10388/8025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie H1. Study of Single Event Transient Error Mitigation. [Thesis]. University of Saskatchewan; 2017. Available from: http://hdl.handle.net/10388/8025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Penn State University

4. Bangalore Srinivasmurthy, Sowmyalatha. Impact of soft errors on scientific simulations .

Degree: 2011, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/12404

► The trends in computing processor technology are driving toward multicores through miniaturization that can pack many processors in a given chip area. This miniaturization has… (more)

Subjects/Keywords: sparse matrix; iterative linear solvers; soft error

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APA (6^th Edition):

Bangalore Srinivasmurthy, S. (2011). Impact of soft errors on scientific simulations . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Bangalore Srinivasmurthy, Sowmyalatha. “Impact of soft errors on scientific simulations .” 2011. Thesis, Penn State University. Accessed April 11, 2021. https://submit-etda.libraries.psu.edu/catalog/12404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Bangalore Srinivasmurthy, Sowmyalatha. “Impact of soft errors on scientific simulations .” 2011. Web. 11 Apr 2021.

Vancouver:

Bangalore Srinivasmurthy S. Impact of soft errors on scientific simulations . [Internet] [Thesis]. Penn State University; 2011. [cited 2021 Apr 11]. Available from: https://submit-etda.libraries.psu.edu/catalog/12404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bangalore Srinivasmurthy S. Impact of soft errors on scientific simulations . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Southern California

5. Suh, Jinho. Models for soft errors in low-level caches.

Degree: PhD, Computer Engineering, 2012, University of Southern California

URL: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/200536/rec/4161

► Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is critical to evaluate the relative merits of various… (more)

▼ Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is critical to evaluate the relative merits of various soft-error protection schemes available. Since protection has implications for power, energy and performance, it is desirable to avoid over provisioning. The semiconductor industry expects that one single event upset (SEU) will cause spatial multi-bit upsets (MBUs) more frequently in the near future so that, by the year 2016, all SEUs will likely to be spatial MBUs rather than single bit upsets (SBUs). This new trend contradicts what has been assumed until now for modeling, benchmarking and evaluating the soft-error reliability of memory structures. No existing framework can evaluate the realistic impact of multiple SBUs as well as spatial MBUs on memory structures. ❧ In this dissertation, we develop novel soft-error reliability benchmarking models and frameworks that address the complex scenarios produced collectively by SBUs and MBUs, in the context of large, low-level caches. First, we introduce a reliability benchmarking framework called PARMA (precise analytical reliability model for architecture). PARMA is a rigorous analytical framework that accurately accounts for multiple SBUs over time to measure the failure rate under any protection scheme. Second, we develop a reliability evaluation framework called MACAU (a Markov model for reliability evaluations of caches under single-bit and multi-bit upsets). MACAU addresses the overlapping effects of SBUs and spatial MBUs over time, to benchmark caches protected by various codes. Additionally MACAU is general enough to compute the intrinsic MTTFs (mean time to failure) of scrubbed caches. Finally, a novel reliability-aware sampling method to accelerate model-based reliability simulations is introduced and evaluated. This sampling technique solves the significant simulation slowdown that all model-based reliability benchmarking frameworks, including PARMA, MACAU, and AVF (Architectural Vulnerability Factor) analysis suffer from. The sampling accuracy is guaranteed by statistically controlling the FIT (Failures-In-Time) estimation error using a profiling technique. The PARMA or MACAU frameworks integrated with the reliability-aware sampling method are unique and invaluable tools for designers to evaluate and design reliable chips efficiently. Advisors/Committee Members: Dubois, Michel (Committee Chair), Annavaram, Murali (Committee Member), Golubchik, Leana (Committee Member).

Subjects/Keywords: cache; modeling; reliability; sampling; simulation; soft error

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APA (6^th Edition):

Suh, J. (2012). Models for soft errors in low-level caches. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/200536/rec/4161

Chicago Manual of Style (16^th Edition):

Suh, Jinho. “Models for soft errors in low-level caches.” 2012. Doctoral Dissertation, University of Southern California. Accessed April 11, 2021. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/200536/rec/4161.

MLA Handbook (7^th Edition):

Suh, Jinho. “Models for soft errors in low-level caches.” 2012. Web. 11 Apr 2021.

Vancouver:

Suh J. Models for soft errors in low-level caches. [Internet] [Doctoral dissertation]. University of Southern California; 2012. [cited 2021 Apr 11]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/200536/rec/4161.

Council of Science Editors:

Suh J. Models for soft errors in low-level caches. [Doctoral Dissertation]. University of Southern California; 2012. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/200536/rec/4161

Louisiana State University

6. Chen, Sui. Enhancing Program Soft Error Resilience through Algorithmic Approaches.

Degree: MSEE, Electrical and Computer Engineering, 2016, Louisiana State University

URL: etd-09262016-115601 ; https://digitalcommons.lsu.edu/gradschool_theses/4411

► The rising count and shrinking feature size of transistors within modern computers is making them increasingly vulnerable to various types of soft faults. This problem… (more)

Subjects/Keywords: Soft Error; Algorithmic Fault Resilience; Fault Injection

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APA (6^th Edition):

Chen, S. (2016). Enhancing Program Soft Error Resilience through Algorithmic Approaches. (Masters Thesis). Louisiana State University. Retrieved from etd-09262016-115601 ; https://digitalcommons.lsu.edu/gradschool_theses/4411

Chicago Manual of Style (16^th Edition):

Chen, Sui. “Enhancing Program Soft Error Resilience through Algorithmic Approaches.” 2016. Masters Thesis, Louisiana State University. Accessed April 11, 2021. etd-09262016-115601 ; https://digitalcommons.lsu.edu/gradschool_theses/4411.

MLA Handbook (7^th Edition):

Chen, Sui. “Enhancing Program Soft Error Resilience through Algorithmic Approaches.” 2016. Web. 11 Apr 2021.

Vancouver:

Chen S. Enhancing Program Soft Error Resilience through Algorithmic Approaches. [Internet] [Masters thesis]. Louisiana State University; 2016. [cited 2021 Apr 11]. Available from: etd-09262016-115601 ; https://digitalcommons.lsu.edu/gradschool_theses/4411.

Council of Science Editors:

Chen S. Enhancing Program Soft Error Resilience through Algorithmic Approaches. [Masters Thesis]. Louisiana State University; 2016. Available from: etd-09262016-115601 ; https://digitalcommons.lsu.edu/gradschool_theses/4411

7. Golnari, Pareesa Ameneh. Computing on Large, Sparse Datasets and Error-Prone Fabrics .

Degree: PhD, 2018, Princeton University

URL: http://arks.princeton.edu/ark:/88435/dsp01m039k7603

► In this dissertation we study problems arising from two trends: computation on large and sparse datasets and computing on error-prone fabrics. Every year the dataset… (more)

▼ In this dissertation we study problems arising from two trends: computation on large and sparse datasets and computing on error-prone fabrics. Every year the dataset sizes are growing. However, many of these large datasets are sparse, i.e., the majority of the data is zero. Therefore, skipping the zero elements can considerably accelerate computation on these datasets. We focus on accelerating a common kernel for sparse computation, sparse matrix-matrix multiplication (SpMM), and propose a high-performance and scalable systolic accelerator that minimizes the bandwidth-to-memory requirement and accelerates this operation 9-30 times compared to state-of-the-art. We also study sparse formats used to store sparse datasets. These formats help with reducing the required bandwidth and storage by storing only the non-zero elements. We modify the popular sparse format: CRS and propose the InCRS format that improves non-regular accesses. We show that this modification reduces the required memory accesses and consequently accelerates SpMM 5-12 times. As transistor scaling continues, devices are getting more unreliable and result in errors in the systems built out of them. We provide a framework that allows for comparing the error tolerance of different sparse data formats and choosing the most appropriate format for an arbitrary application. As case studies, we compare the performance of different formats for two machine learning applications, RBM and PCA, and a set of linear algebra operations. We also study error-tolerant processors built on error-prone fabrics that allow for errors in the architectural states. We formalize the minimal requirements for these processors to assure that they potentially provide useful results are progress, preventing the error effects to accumulate over time, and executing the essential parts of the program. We propose a framework to model the control flow of these processors, capturing the effects of errors and protection mechanisms, and to verify the reliability properties on them. As case studies, we verify these properties on two recent error-tolerant processors, PPU and ERSA, and propose modifications to these designs to satisfy the minimal reliability requirements. Advisors/Committee Members: Malik, Sharad (advisor).

Subjects/Keywords: crs; error-tolerant computing; reliability; soft error; sparse formats; spmm

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APA (6^th Edition):

Golnari, P. A. (2018). Computing on Large, Sparse Datasets and Error-Prone Fabrics . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01m039k7603

Chicago Manual of Style (16^th Edition):

Golnari, Pareesa Ameneh. “Computing on Large, Sparse Datasets and Error-Prone Fabrics .” 2018. Doctoral Dissertation, Princeton University. Accessed April 11, 2021. http://arks.princeton.edu/ark:/88435/dsp01m039k7603.

MLA Handbook (7^th Edition):

Golnari, Pareesa Ameneh. “Computing on Large, Sparse Datasets and Error-Prone Fabrics .” 2018. Web. 11 Apr 2021.

Vancouver:

Golnari PA. Computing on Large, Sparse Datasets and Error-Prone Fabrics . [Internet] [Doctoral dissertation]. Princeton University; 2018. [cited 2021 Apr 11]. Available from: http://arks.princeton.edu/ark:/88435/dsp01m039k7603.

Council of Science Editors:

Golnari PA. Computing on Large, Sparse Datasets and Error-Prone Fabrics . [Doctoral Dissertation]. Princeton University; 2018. Available from: http://arks.princeton.edu/ark:/88435/dsp01m039k7603

8. Batagin Armelin, Fábio. Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate.

Degree: Docteur es, Réseaux, information et communications, 2019, Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil)

URL: http://www.theses.fr/2019SACLT035

►

La vulnérabilité aux erreurs récupérables (SEV - Soft Error Vulnerability) est un paramètre estimé qui, associé aux caractéristiques de l’environnement de rayonnement, permet d’obtenir le… (more)

▼

La vulnérabilité aux erreurs récupérables (SEV - Soft Error Vulnerability) est un paramètre estimé qui, associé aux caractéristiques de l’environnement de rayonnement, permet d’obtenir le SER (Soft-Error Rate), une métrique couramment utilisée pour prédire le comportement des systèmes électroniques numériques exposés au rayonnement de particules. Actuellement, la méthode la plus précise pour l’estimation de SER est le test de rayonnement, car elle présente l’interaction réelle des particules avec le dispositif électronique. Cependant, ce test est coûteux et requiert le circuit qui, lui, n’est disponible qu’à la fin du cycle de développement. Cela a motivé le développement d'autres méthodes d'estimation de SER et de SEV, notamment des méthodes analytiques, des simulations électriques et logiques, ainsi que des approches basées sur l'émulation. Ces techniques incorporent généralement des effets de masquage logique, électrique ou temporel. Néanmoins, la plupart de ces techniques ne prennent pas en compte la susceptibilité aux événements singuliers transitoires (SET - Single Event Transient). Ce facteur est intrinsèque au test de radiation et représente la probabilité que le rayonnement ionisant produise une erreur `soft' à la sortie des portes logiques du circuit. Dans ce contexte, cette thèse propose une stratégie d’estimation de SEV basée sur les susceptibilités aux SET. Deux versions de cette stratégie sont considérées : la version simplifiée, où les susceptibilités SET prennent en compte seulement les effets de la topologie des portes logiques et la version complète, où les susceptibilités prennent en compte la topologie et le fonctionnement du circuit. La stratégie proposée a été évaluée avec une approche basée sur la simulation, estimant la SEV de 38 circuits de référence. Les résultats montrent que les deux versions de la stratégie entraînent une amélioration de la précision de l'estimation, la version complète présentant l'erreur d'estimation la plus faible. Enfin, la faisabilité de l’adoption de la stratégie proposée est démontrée avec approche basée sur l’émulation.

The Soft-Error Vulnerability (SEV) is an estimated parameter that, in conjunction with the characteristics of the radiation environment, is used to obtain the Soft-Error Rate (SER), that is a metric used to predict how digital systems will behave in this environment. Currently, the most confident method for SER estimation is the radiation test, since it has the actual interaction of the radiation with the electronic device. However, this test is expensive and requires the real device, that becomes available late on the design cycle. These restrictions motivated the development of other SER and SEV estimation methods, including analytical, electrical and logic simulations, and emulation-based approaches. These techniques usually incorporate the logical, electrical and latching-window masking effects into the estimation process. Nevertheless, most of them do not take into account a factor that is intrinsic to the radiation test: the probability of…

Advisors/Committee Members: Alves de Barros, Lirida (thesis director), D'Amore, Roberto (thesis director).

Subjects/Keywords: Taux d'erreur soft; Vulnérabilité aux erreurs soft; Injection de défauts; Transitoires d'événements uniques; FPGA; Soft error rate; Soft-Error Vulnerability; Fault injection; Single-Event Transient; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Batagin Armelin, F. (2019). Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate. (Doctoral Dissertation). Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil). Retrieved from http://www.theses.fr/2019SACLT035

Chicago Manual of Style (16^th Edition):

Batagin Armelin, Fábio. “Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate.” 2019. Doctoral Dissertation, Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil). Accessed April 11, 2021. http://www.theses.fr/2019SACLT035.

MLA Handbook (7^th Edition):

Batagin Armelin, Fábio. “Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate.” 2019. Web. 11 Apr 2021.

Vancouver:

Batagin Armelin F. Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate. [Internet] [Doctoral dissertation]. Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil); 2019. [cited 2021 Apr 11]. Available from: http://www.theses.fr/2019SACLT035.

Council of Science Editors:

Batagin Armelin F. Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate. [Doctoral Dissertation]. Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil); 2019. Available from: http://www.theses.fr/2019SACLT035

The Ohio State University

9. Liu, Jiaqi. Handling Soft and Hard Errors for Scientific Applications.

Degree: PhD, Computer Science and Engineering, 2017, The Ohio State University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067

► Due to the rapid decrease in Mean Time Between Failure (MTBF) in High Performance Computing, fault tolerance emerged as a critical topic to improve overall… (more)

▼ Due to the rapid decrease in Mean Time Between Failure (MTBF) in High Performance Computing, fault tolerance emerged as a critical topic to improve overall performance in the HPC community. In recent decades, along with the decrease in size of hardware, and the extensively used near-threshold computation for energy saving, the community is now facing more frequent soft errors than ever. Particularly, due to the difficulty in detecting soft errors, we are in urgent need for a general solution for these errors.Our work includes providing efficient and effective solution to handle soft and hard errors for parallel system. We start from solving the write bottleneck of the traditional checkpoint and restart. We exploit the communication structure to find locally finalized data, as well as each process's contribution to globally finalized data. We allow each node to take independent checkpoint using this information and therefore achieve uncoordinated checkpointing. We checkpoint asynchronously by overlapping the workload of checkpoint with computation, so that the system avoids write congestion. We discovered that the soft error impact in convergent iterative applications' output follows a pattern. We developed a signature analysis based detection with checkpointing based recovery, which is driven by the observation that high order bit flips can very negatively impact execution, but can also be easily detected. Specifically, we have developed signatures for this class of applications.For non-monotonically convergent applications, we observed that the signature of silent data corruption is specific to an application but independent of the input dataset size for the application. Based on this observation, we explored an approach that involves machine learning technique to detect soft errors. We use off-line training framework of machine learning, construct classifiers with representative inputs and periodically invoke the classifiers during execution to verify the status. Our work not only focuses on optimizing the existing fault tolerance solution to handle general case of faults, but also includes exploring new algorithms that detects and recovers from soft errors. We proposed an algorithm level fault tolerance solution for molecular dynamic applications to detect soft errors and recover from the error. We also developed an algorithm level recovery strategy, so that the applications do not need traditional checkpoint to back up the computation state. Finally, we supported in-situ analysis paradigm with fault resilience. We explored a Map-Reduce like platform for in-situ analysis and discovered the possibility of achieving runtime execution state by utilizing the redundant properties of reduction objects during computation. With the state stored in the shared locations among the nodes, we could maintain a checkpoint-restart like mechanism and the system could restart from any previous backup if any node fails. We were able to apply the approach both time-wise and space-wise for the Smart with reasonable extra overhead. Advisors/Committee Members: Agrawal, Gagan (Advisor).

Subjects/Keywords: Computer Engineering; Computer Science; hard error; soft error; scientific application; fault tolerance; resilience

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APA (6^th Edition):

Liu, J. (2017). Handling Soft and Hard Errors for Scientific Applications. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067

Chicago Manual of Style (16^th Edition):

Liu, Jiaqi. “Handling Soft and Hard Errors for Scientific Applications.” 2017. Doctoral Dissertation, The Ohio State University. Accessed April 11, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067.

MLA Handbook (7^th Edition):

Liu, Jiaqi. “Handling Soft and Hard Errors for Scientific Applications.” 2017. Web. 11 Apr 2021.

Vancouver:

Liu J. Handling Soft and Hard Errors for Scientific Applications. [Internet] [Doctoral dissertation]. The Ohio State University; 2017. [cited 2021 Apr 11]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067.

Council of Science Editors:

Liu J. Handling Soft and Hard Errors for Scientific Applications. [Doctoral Dissertation]. The Ohio State University; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067

NSYSU

10. Chih, Tsung-Liang. Design and Implementation of A Defect and Soft-Error Tolerable Cache.

Degree: Master, Electrical Engineering, 2015, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034

► When the feature size of transistors becomes smaller, chips are more sensitive to process defects and variation, which may result in low yield and reliability.… (more)

Subjects/Keywords: cache; performance degradation tolerance; performance degrading faults; defect; soft-error

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APA (6^th Edition):

Chih, T. (2015). Design and Implementation of A Defect and Soft-Error Tolerable Cache. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chih, Tsung-Liang. “Design and Implementation of A Defect and Soft-Error Tolerable Cache.” 2015. Thesis, NSYSU. Accessed April 11, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chih, Tsung-Liang. “Design and Implementation of A Defect and Soft-Error Tolerable Cache.” 2015. Web. 11 Apr 2021.

Vancouver:

Chih T. Design and Implementation of A Defect and Soft-Error Tolerable Cache. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Apr 11]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chih T. Design and Implementation of A Defect and Soft-Error Tolerable Cache. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

UCLA

11. Feng, Zhe. Logic Synthesis for FPGA Reliability.

Degree: Electrical Engineering, 2013, UCLA

URL: http://www.escholarship.org/uc/item/7w7602f5

► Logic synthesis is one of the key stages in the computer-aided design (CAD) flow for a field programmable gate array (FPGA) based design. It usually… (more)

Subjects/Keywords: Electrical engineering; FPGA; Logic synthesis; Reliability; Soft error

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APA (6^th Edition):

Feng, Z. (2013). Logic Synthesis for FPGA Reliability. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/7w7602f5

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Feng, Zhe. “Logic Synthesis for FPGA Reliability.” 2013. Thesis, UCLA. Accessed April 11, 2021. http://www.escholarship.org/uc/item/7w7602f5.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Feng, Zhe. “Logic Synthesis for FPGA Reliability.” 2013. Web. 11 Apr 2021.

Vancouver:

Feng Z. Logic Synthesis for FPGA Reliability. [Internet] [Thesis]. UCLA; 2013. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/7w7602f5.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Feng Z. Logic Synthesis for FPGA Reliability. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/7w7602f5

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

12. Sierawski, Brian David. The Role of Singly-Charged Particles in Microelectronics Reliability.

Degree: PhD, Electrical Engineering, 2011, Vanderbilt University

URL: http://hdl.handle.net/1803/14976

► Lightly ionizing particles in any radiation environment have the potential to induce single event upsets in scaled CMOS technologies. As microelectronic devices become smaller and… (more)

Subjects/Keywords: proton; muon; direct ionization; single event upset; soft error; memory

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APA (6^th Edition):

Sierawski, B. D. (2011). The Role of Singly-Charged Particles in Microelectronics Reliability. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14976

Chicago Manual of Style (16^th Edition):

Sierawski, Brian David. “The Role of Singly-Charged Particles in Microelectronics Reliability.” 2011. Doctoral Dissertation, Vanderbilt University. Accessed April 11, 2021. http://hdl.handle.net/1803/14976.

MLA Handbook (7^th Edition):

Sierawski, Brian David. “The Role of Singly-Charged Particles in Microelectronics Reliability.” 2011. Web. 11 Apr 2021.

Vancouver:

Sierawski BD. The Role of Singly-Charged Particles in Microelectronics Reliability. [Internet] [Doctoral dissertation]. Vanderbilt University; 2011. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1803/14976.

Council of Science Editors:

Sierawski BD. The Role of Singly-Charged Particles in Microelectronics Reliability. [Doctoral Dissertation]. Vanderbilt University; 2011. Available from: http://hdl.handle.net/1803/14976

Vanderbilt University

13. Gaspard, Nelson Joseph III. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

URL: http://hdl.handle.net/1803/10824

► Alpha, heavy-ion, neutron, and proton experimental results from 130-nm to 28-nm technology nodes are establish single-event upset cross section trends in soft and hardened flip-flop… (more)

Subjects/Keywords: single event upset; CMOS; flip-flop; soft error

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APA (6^th Edition):

Gaspard, N. J. I. (2017). Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10824

Chicago Manual of Style (16^th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed April 11, 2021. http://hdl.handle.net/1803/10824.

MLA Handbook (7^th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Web. 11 Apr 2021.

Vancouver:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1803/10824.

Council of Science Editors:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://hdl.handle.net/1803/10824

Penn State University

14. Barth, Michael Judson. SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES.

Degree: 2016, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/13195mjb590

► Antimonide based (Sb) compound semiconductors owing to their superior electron and hole transport properties over Si are an attractive option as a channel replacement material… (more)

▼ Antimonide based (Sb) compound semiconductors owing to their superior electron and hole transport properties over Si are an attractive option as a channel replacement material for the future generation of devices. Of the Sb materials p-channel InGaSb and n-channel InAsSb quantum wells (QWs) are particularly interesting due to their enhanced mobilities over silicon and their similar lattice constants. The similar lattice constants allows for a p and n channel all Sb-based alternative to Si CMOS technology to be grown on a common buffer layer. This integration advantages offered by a common buffer layer makes Sb-based devices applicable for use in future low power high-speed digital and millimeter wave applications. Important when evaluating any new technology is understanding its reliability. Radiation effects are important part of device reliability. Complex digital systems can be brought down by a vulnerability in one of its smallest subcomponents. For example an ionizing particle strikes a transistor or memory cell, the particle strike results in the generation of electron and hole pairs which can result the shift of critical transistor performance metrics such as threshold voltage (VT), or the corruption of a stored bit in the memory cell. This dissertation addresses the fabrication and integration challenges that were overcome to realize Sb-based QW-MOSFETs. Further this work investigates the radiation effects in p-channel InGaSb and n-channel InAsSb quantum well metal-oxide-semiconductor field effect transistors (QW-MOSFETs). Both p-channel InGaSb and n-channel InAsSb QW-MOSFETs are assessed for resilience to total ionizing dose (TID) effects and single event effects (SEE). A statistical analysis is presented to study the radiation induced effects. TCAD and SPICE simulations are utilized to detail the mechanisms behind the radiation induced effects, and assess their impact on circuit level implementations of Sb-based QW-MOSFETs. Advisors/Committee Members: Suman Datta, Dissertation Advisor/Co-Advisor, Jerzy Ruzyllo, Committee Chair/Co-Chair, Sumeet Kumar Gupta, Committee Member, Suman Datta, Committee Member, Roman Engel-Herbert, Outside Member.

Subjects/Keywords: InAsSb; GaSb; InGaSb; Soft Error; Heavy Ion; Atomic Layer Deposition

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Barth, M. J. (2016). SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/13195mjb590

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Barth, Michael Judson. “SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES.” 2016. Thesis, Penn State University. Accessed April 11, 2021. https://submit-etda.libraries.psu.edu/catalog/13195mjb590.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Barth, Michael Judson. “SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES.” 2016. Web. 11 Apr 2021.

Vancouver:

Barth MJ. SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES. [Internet] [Thesis]. Penn State University; 2016. [cited 2021 Apr 11]. Available from: https://submit-etda.libraries.psu.edu/catalog/13195mjb590.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Barth MJ. SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/13195mjb590

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

McMaster University

15. Zuzarte, Marvin. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.

Degree: MASc, 2014, McMaster University

URL: http://hdl.handle.net/11375/16500

►

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The… (more)

▼

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The use of field programmable gate arrays (FPGAs) within safety critical systems is becoming more prevalent due to the design and cost benefits their use provides. The effects of externally caused faults on these safety critical systems cannot be neglected. In particular, high energy particle striking a circuit can cause a voltage change in the circuit known as a soft error. The effects these soft errors will have on the circuit needs to be understood in order to ensure that the systems will function properly in the event soft errors do occur. In this thesis a tool is designed to facilitate the run-time injection of soft errors into a hardware circuit running on a FPGA. The tool allows for the control over the number of injections that can be performed and control over the rate that the injections will occur at. Additionally the tool records time stamps of when injections occur and time stamps of when errors are detected. This recorded data allows for the analysis of designs in conditions prone to soft errors. The implemented tool allows for design time parametrization and run time configuration, allowing a multitude of tests to be run for a single compiled design. The tool also eliminates the need for a host computer after configuration by generating the injection locations and times on the FPGA. Eliminating the host computer allows for faster testing when compared to other methods as data transfer times are greatly reduced. The implemented tool was run on classical examples of redundant structures, such as duplication with comparison and triple modular redundancy as well as a non-redundant structure to establish a baseline. The results of multiple tests run on each structure are analyzed to illustrate the uses of the tool and how the tool may be used to test other designs.

Thesis

Master of Applied Science (MASc)

Advisors/Committee Members: Lawford, Mark, Nicolici, Nicola, Software Engineering.

Subjects/Keywords: FPGA; Fault injection; Field programmable gate array; runtime; soft error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zuzarte, M. (2014). A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/16500

Chicago Manual of Style (16^th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Masters Thesis, McMaster University. Accessed April 11, 2021. http://hdl.handle.net/11375/16500.

MLA Handbook (7^th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Web. 11 Apr 2021.

Vancouver:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Internet] [Masters thesis]. McMaster University; 2014. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/11375/16500.

Council of Science Editors:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Masters Thesis]. McMaster University; 2014. Available from: http://hdl.handle.net/11375/16500

16. Zhang, Kuiyuan. A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究.

Degree: 博士（工学）, 2016, Kyoto Institute of Technology / 京都工芸繊維大学

URL: http://hdl.handle.net/10212/2312

► My thesis focuses on projection and evaluation for soft error tolerance in the radiation-hardened circuit by device and physics level simulations. The SERs of various… (more)

Subjects/Keywords: Soft Error; Radiation-hard; VLSI; Simulation; TCAD; PHITS

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APA (6^th Edition):

Zhang, K. (2016). A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究. (Thesis). Kyoto Institute of Technology / 京都工芸繊維大学. Retrieved from http://hdl.handle.net/10212/2312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zhang, Kuiyuan. “A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究.” 2016. Thesis, Kyoto Institute of Technology / 京都工芸繊維大学. Accessed April 11, 2021. http://hdl.handle.net/10212/2312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zhang, Kuiyuan. “A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究.” 2016. Web. 11 Apr 2021.

Vancouver:

Zhang K. A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究. [Internet] [Thesis]. Kyoto Institute of Technology / 京都工芸繊維大学; 2016. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10212/2312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang K. A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究. [Thesis]. Kyoto Institute of Technology / 京都工芸繊維大学; 2016. Available from: http://hdl.handle.net/10212/2312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Luong, Dinh Hung. Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ.

Degree: 博士(情報理工学), 2017, The University of Tokyo / 東京大学

URL: http://hdl.handle.net/2261/25849

► The problem of soft errors caused by radiation events are expected to get worse with technology scaling. This thesis focuses on mitigation of soft errors… (more)

Subjects/Keywords: soft error; defect; cache; reliability

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APA (6^th Edition):

Luong, D. H. (2017). Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ. (Thesis). The University of Tokyo / 東京大学. Retrieved from http://hdl.handle.net/2261/25849

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Luong, Dinh Hung. “Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ.” 2017. Thesis, The University of Tokyo / 東京大学. Accessed April 11, 2021. http://hdl.handle.net/2261/25849.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Luong, Dinh Hung. “Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ.” 2017. Web. 11 Apr 2021.

Vancouver:

Luong DH. Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ. [Internet] [Thesis]. The University of Tokyo / 東京大学; 2017. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2261/25849.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Luong DH. Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ. [Thesis]. The University of Tokyo / 東京大学; 2017. Available from: http://hdl.handle.net/2261/25849

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Arizona State University

18. Jeyapaul, Reiley. Smart Compilers for Reliable and Power-efficient Embedded Computing.

Degree: PhD, Computer Science, 2012, Arizona State University

URL: http://repository.asu.edu/items/14766

► Thanks to continuous technology scaling, intelligent, fast and smaller digital systems are now available at affordable costs. As a result, digital systems have found use… (more)

▼ Thanks to continuous technology scaling, intelligent, fast and smaller digital systems are now available at affordable costs. As a result, digital systems have found use in a wide range of application areas that were not even imagined before, including medical (e.g., MRI, remote or post-operative monitoring devices, etc.), automotive (e.g., adaptive cruise control, anti-lock brakes, etc.), security systems (e.g., residential security gateways, surveillance devices, etc.), and in- and out-of-body sensing (e.g., capsule swallowed by patients measuring digestive system pH, heart monitors, etc.). Such computing systems, which are completely embedded within the application, are called embedded systems, as opposed to general purpose computing systems. In the design of such embedded systems, power consumption and reliability are indispensable system requirements. In battery operated portable devices, the battery is the single largest factor contributing to device cost, weight, recharging time, frequency and ultimately its usability. For example, in the Apple iPhone 4 smart-phone, the battery is 40% of the device weight, occupies 36% of its volume and allows only 7 hours (over 3G) of talk time. As embedded systems find use in a range of sensitive applications, from bio-medical applications to safety and security systems, the reliability of the computations performed becomes a crucial factor. At our current technology-node, portable embedded systems are prone to expect failures due to soft errors at the rate of once-per-year; but with aggressive technology scaling, the rate is predicted to increase exponentially to once-per-hour. Over the years, researchers have been successful in developing techniques, implemented at different layers of the design-spectrum, to improve system power efficiency and reliability. Among the layers of design abstraction, I observe that the interface between the compiler and processor micro-architecture possesses a unique potential for efficient design optimizations. A compiler designer is able to observe and analyze the application software at a finer granularity; while the processor architect analyzes the system output (power, performance, etc.) for each executed instruction. At the compiler micro-architecture interface, if the system knowledge at the two design layers can be integrated, design optimizations at the two layers can be modified to efficiently utilize available resources and thereby achieve appreciable system-level benefits. To this effect, the thesis statement is that, ``by merging system design information at the compiler and micro-architecture design layers, smart compilers can be developed, that achieve reliable and power-efficient embedded computing through: i) Pure compiler techniques, ii) Hybrid compiler micro-architecture techniques, and iii) Compiler-aware architectures''. In this dissertation demonstrates, through contributions in each of the three compiler-based techniques, the effectiveness of smart compilers in achieving power-efficiency and reliability in…

Subjects/Keywords: Computer science; cgra; compiler; computer architecture; power efficiency; reliability; soft error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Jeyapaul, R. (2012). Smart Compilers for Reliable and Power-efficient Embedded Computing. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/14766

Chicago Manual of Style (16^th Edition):

Jeyapaul, Reiley. “Smart Compilers for Reliable and Power-efficient Embedded Computing.” 2012. Doctoral Dissertation, Arizona State University. Accessed April 11, 2021. http://repository.asu.edu/items/14766.

MLA Handbook (7^th Edition):

Jeyapaul, Reiley. “Smart Compilers for Reliable and Power-efficient Embedded Computing.” 2012. Web. 11 Apr 2021.

Vancouver:

Jeyapaul R. Smart Compilers for Reliable and Power-efficient Embedded Computing. [Internet] [Doctoral dissertation]. Arizona State University; 2012. [cited 2021 Apr 11]. Available from: http://repository.asu.edu/items/14766.

Council of Science Editors:

Jeyapaul R. Smart Compilers for Reliable and Power-efficient Embedded Computing. [Doctoral Dissertation]. Arizona State University; 2012. Available from: http://repository.asu.edu/items/14766

19. Isaza-González, José. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .

Degree: 2018, University of Alicante

URL: http://hdl.handle.net/10045/90359

► El funcionamiento correcto de un sistema electrónico, aún bajo perturbaciones y fallos causados por la radiación, ha sido siempre un factor crucial en aplicaciones aeroespaciales,… (more)

▼ El funcionamiento correcto de un sistema electrónico, aún bajo perturbaciones y fallos causados por la radiación, ha sido siempre un factor crucial en aplicaciones aeroespaciales, médicas, nucleares, de defensa, y de transporte. La tolerancia de estos sistemas, o de los componentes que los integran, a fallos de tipo Single Event Effects (SEEs), es un tema de investigación importante y una característica imprescindible de cualquier sistema utilizado, no solo en aplicaciones críticas, sino también en las aplicaciones del día a día. Por esta razón, las aplicaciones de estos sistemas requieren, cada vez más, herramientas, métricas y parámetros específicos que permitan evaluar la tolerancia a fallos; y a su vez, permitan guiar el proceso para aplicar de forma eficiente los mecanismos de protección utilizados para la mitigación de estos fallos. En este contexto, esta tesis doctoral presenta una herramienta de inyección de fallos y la metodología para la realización de campañas de inyección de fallos tipo Single Event upset (SEU) en procesadores Commercial Off-The-Shelf (COTS) y a través de plataformas de emulación/simulación. Esta herramienta aprovecha las ventajas que ofrecen las infraestructuras de depuración de hardware tales como On-Chip Debugging (OCD), y el depurador estándar de GNU (GDB) para la ejecución y depuración de los casos de estudio. También, se analiza la posibilidad de utilizar un modelo descrito en HDL (Hardware Description Language) del procesador MSP430 de Texas Instruments para estimar la fiabilidad de las aplicaciones al principio de la fase de desarrollo. Se utilizan diferentes métodos de inyección de fallos que muestran las ventajas que ofrece la emulación FPGA en comparación con las campañas de inyección llevadas a cabo en los dispositivos reales. La vulnerabilidad del banco de registros se compara y analiza por cada uno de sus registros. Por otro lado, esta memoria de tesis presenta una métrica para la aplicación eficiente del endurecimiento selectivo basada en software, que hemos llamado SHARC (Software based HARdening Criticality). Adicionalmente, también presenta un método para guiar el proceso de endurecimiento según la clasificación generada por la métrica SHARC. De esta forma, se logra proteger los recursos internos del procesador, obteniendo una cobertura máxima de fallos con los mínimos sobrecostes de protección (overheads). Esto permite diseñar sistemas confiables a bajo coste, logrando obtener un punto óptimo entre los requisitos de confiabilidad y las restricciones de diseño, evitando el uso excesivo de costosos mecanismos de protección (hardware y software). Advisors/Committee Members: Cuenca-Asensi, Sergio (advisor), Martínez-Álvarez, Antonio (advisor).

Subjects/Keywords: Microprocessor reliability; Fault injection; Soft error; Radiation effects fault tolerance

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APA (6^th Edition):

Isaza-González, J. (2018). Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . (Thesis). University of Alicante. Retrieved from http://hdl.handle.net/10045/90359

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Isaza-González, José. “Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .” 2018. Thesis, University of Alicante. Accessed April 11, 2021. http://hdl.handle.net/10045/90359.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Isaza-González, José. “Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .” 2018. Web. 11 Apr 2021.

Vancouver:

Isaza-González J. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . [Internet] [Thesis]. University of Alicante; 2018. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10045/90359.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Isaza-González J. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . [Thesis]. University of Alicante; 2018. Available from: http://hdl.handle.net/10045/90359

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Minnesota

20. Kumar, Saurabh. Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes.

Degree: PhD, Electrical Engineering, 2018, University of Minnesota

URL: http://hdl.handle.net/11299/215201

► Soft errors induced by particle strikes have been a major concern in reliability critical applications such as defense, space, medicine and finance etc. A number… (more)

▼ Soft errors induced by particle strikes have been a major concern in reliability critical applications such as defense, space, medicine and finance etc. A number of radiation particles present in the ambient environment can induce errors in circuits which can result in system failure. These can be charged particles such as alpha, electrons, protons or heavy ions or neutral particles like neutrons, laser etc. Radioactive impurities like Uranium and Thorium in chip and packaging materials emit alpha particles that contribute towards errors. Protons, electrons and neutrons are found in space and terrestrial environment that can induce soft errors. When these particles penetrate the silicon, electron hole pairs are generated along the tracks that may be collected by the p-n junctions via drift and diffusion mechanisms. If the collected charge is large enough, the logic state of the junction may change, resulting in what we refer to as a soft error. Continuous process scaling has resulted in shrinking of device features that results in smaller junction area and lower strike probability at or around the junction that can lead to an error induction. The transistors, therefore, have become more and more resilient towards radiation-induced strikes. Advent of FinFET technology has further increased the resilience of devices towards soft errors by employing narrow three dimensional source-drain features that inherently make it difficult for the charge to get collected quickly. However, with process scaling, device density per die has gone up exponentially which means more transistors can be packed in the same die area. This has resulted in a probable rise in overall soft error rate (SER) due to increased number of susceptible nodes. Hence although per device SER has gone down, chip-level SER still remains a critical reliability issue that needs to be dealt with. In order to come up with efficient circuit designs that are immune towards soft errors, it is necessary to accurately and efficiently characterize SER in the given process. In this work, novel circuits have been proposed that capture important circuit parameters impacting SER. First of these is the Back-Sampling Chain (BSC) circuit that employs highly sensitive detection chains with more than 9x sensitivity as compared to conventional circuits. Higher sensitivity is critical in SER characterization since it facilitates higher strike induction resulting in collection of large data in limited beam time. BSC chain is capable of detecting Single Event Transients (SETs), Single Event Upsets (SEUs) and Multi-Bit-Upsets (MBUs), with scalable architecture that can be scaled to millions of stages without compromising on the measurement accuracy. BSC circuit can measure the SET pulse parameters (width and amplitude) while sweeping the sensitivity points that helps in re-construction of individual strike pulses. This, to our knowledge, is the first work to show individual pulse re-construction. Secondly, we show the detailed analysis of neutron-induced soft errors measured from…

Subjects/Keywords: FinFET; MBU; Radiation strike; SET; SEU; Soft Error

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APA (6^th Edition):

Kumar, S. (2018). Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/215201

Chicago Manual of Style (16^th Edition):

Kumar, Saurabh. “Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes.” 2018. Doctoral Dissertation, University of Minnesota. Accessed April 11, 2021. http://hdl.handle.net/11299/215201.

MLA Handbook (7^th Edition):

Kumar, Saurabh. “Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes.” 2018. Web. 11 Apr 2021.

Vancouver:

Kumar S. Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes. [Internet] [Doctoral dissertation]. University of Minnesota; 2018. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/11299/215201.

Council of Science Editors:

Kumar S. Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes. [Doctoral Dissertation]. University of Minnesota; 2018. Available from: http://hdl.handle.net/11299/215201

Northeastern University

21. Shazli, Syed Zafar. High level modeling and mitigation of transient errors in nano-scale systems.

Degree: PhD, Department of Electrical and Computer Engineering, 2011, Northeastern University

URL: http://hdl.handle.net/2047/d20002793

► Soft errors, due to cosmic radiations, are a major reliability barrier for VLSI designs. The vulnerability of such systems to soft errors grows exponentially with… (more)

Subjects/Keywords: Error Recovery; Field Analysis; Online Error Detection; SER Estimation; Soft Errors; Transient Errors; Electrical and Computer Engineering; Engineering

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APA (6^th Edition):

Shazli, S. Z. (2011). High level modeling and mitigation of transient errors in nano-scale systems. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20002793

Chicago Manual of Style (16^th Edition):

Shazli, Syed Zafar. “High level modeling and mitigation of transient errors in nano-scale systems.” 2011. Doctoral Dissertation, Northeastern University. Accessed April 11, 2021. http://hdl.handle.net/2047/d20002793.

MLA Handbook (7^th Edition):

Shazli, Syed Zafar. “High level modeling and mitigation of transient errors in nano-scale systems.” 2011. Web. 11 Apr 2021.

Vancouver:

Shazli SZ. High level modeling and mitigation of transient errors in nano-scale systems. [Internet] [Doctoral dissertation]. Northeastern University; 2011. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2047/d20002793.

Council of Science Editors:

Shazli SZ. High level modeling and mitigation of transient errors in nano-scale systems. [Doctoral Dissertation]. Northeastern University; 2011. Available from: http://hdl.handle.net/2047/d20002793

22. Rhod, Eduardo Luis. Quaternary CLB a falul tolerant quaternary FPGA.

Degree: 2012, Brazil

URL: http://hdl.handle.net/10183/72925

►

A diminuição no tamanho dos transistores vem aumentando cada vez mais o número de funções que os dispositivos eletrônicos podem realizar. Apesar da diminuição do… (more)

▼

A diminuição no tamanho dos transistores vem aumentando cada vez mais o número de funções que os dispositivos eletrônicos podem realizar. Apesar da diminuição do tamanho mínimo dos transistores, a velocidade máxima dos circuitos não consegue seguir a mesma taxa de aumento. Um dos grandes culpados apontados pelos pesquisadores são as interconexões entre os transistores e também entre os componentes. O aumento no número de interconexões dos circuitos traz consigo um significativo aumento do cosumo de energia, aumento do atraso de propagação dos sinais, além de um aumento da complexidade e custo do projeto dos circuitos integrados. Como uma possível solução a este problema é proposta a utilização de lógica multivalorada, mais especificamente, a lógica quaternária. Os dispositivos FPGAs são caracterizados principalmente pela grande flexibilidade que oferecem aos projetistas de sistemas digitais. Entretanto, com o avanço nas tecnologias de fabricação de circuitos integrados e diminuição das dimensões de fabricação, os problemas relacionados ao grande número de interconexões são uma preocupação para as próximas tecnologias de FPGAs. As tecnologias menores que 90nm possuem um grande aumento na taxa de erros dos circuitos, na lógica combinacional e sequencial. Apesar de algumas potenciais soluções começara a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe o uso de circuitos quaternários com modificações para tolerar falhas provenientes de eventos transientes. Como principal contribuição deste trabalho destaca-se o desenvolvimento de uma CLB (do inglês Configurable Logic Block) quaternária capaz de suportar eventos transientes e, na possibilidade de um erro, evitá-lo ou corrigi-lo.

The decrease in transistor size is increasing the number of functions that can be performed by the electronic devices. Despite this reduction in the transistors minimum size, the circuit’s speed does not follow the same rate. One of the major reasons pointed out by researchers are the interconnections between the transistors and between the components. The increase in the number of circuit interconnections brings a significant increase in energy consumption, propagation delay of signals, and an increase in the complexity and cost of new technologies IC designs. As a possible solution to this problem the use of multivalued logic is being proposed, more specifically, the quaternary logic. FPGA devices are characterized mainly by offering greater flexibility to designers of digital systems. However, with the advance in IC manufacturing technologies and the reduced size of the minimum fabricated dimensions, the problems related to the large number of interconnections are a concern for future technologies of FPGAs. The sub 90nm technologies have a large increase in the error rate of its functions for the combinational and sequential logic. Although potential solutions are being investigated…

Advisors/Committee Members: Carro, Luigi.

Subjects/Keywords: Microeletrônica; Tolerancia : Falhas; Sistemas digitais; Fault tolerant architectures; Quaternary circuits; Error detection techniques; Soft error rate; FPGAs

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APA (6^th Edition):

Rhod, E. L. (2012). Quaternary CLB a falul tolerant quaternary FPGA. (Doctoral Dissertation). Brazil. Retrieved from http://hdl.handle.net/10183/72925

Chicago Manual of Style (16^th Edition):

Rhod, Eduardo Luis. “Quaternary CLB a falul tolerant quaternary FPGA.” 2012. Doctoral Dissertation, Brazil. Accessed April 11, 2021. http://hdl.handle.net/10183/72925.

MLA Handbook (7^th Edition):

Rhod, Eduardo Luis. “Quaternary CLB a falul tolerant quaternary FPGA.” 2012. Web. 11 Apr 2021.

Vancouver:

Rhod EL. Quaternary CLB a falul tolerant quaternary FPGA. [Internet] [Doctoral dissertation]. Brazil; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10183/72925.

Council of Science Editors:

Rhod EL. Quaternary CLB a falul tolerant quaternary FPGA. [Doctoral Dissertation]. Brazil; 2012. Available from: http://hdl.handle.net/10183/72925

23. Lackmann-Zimpeck, Alexandra. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET.

Degree: Docteur es, Micro et Nanosystèmes, 2019, Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil)

URL: http://www.theses.fr/2019ESAE0026

► Les contraintes imposées par la roadmap technologique nanométrique imposent aux fabricants de microélectronique une réduction de la variabilité de fabrication mais également de durcissement vis-à-vis… (more)

▼ Les contraintes imposées par la roadmap technologique nanométrique imposent aux fabricants de microélectronique une réduction de la variabilité de fabrication mais également de durcissement vis-à-vis des erreurs logiques induits par l’environnement radiatif naturel afin d’assurer un haut niveau de fiabilité. Certains travaux ont mis en évidence l'influence de la variabilité de fabrication et SET sur les circuits basés sur les technologies FinFET. Cependant jusqu’à lors, aucune approche pour les atténuer n’ont pu être présenté pour les technologies FinFET. Pour ces raisons, du point de vue de la conception, des efforts considérables doivent être déployés pour comprendre et réduire les impacts générés par ces deux problématiques de fiabilité. Dans ce contexte, les contributions principales de cette thèse sont: 1) étudier le comportement des cellules logiques FinFET en fonction des variations de fabrication et des effets de rayonnement; 2) évaluer quatre approches des durcissement au niveau du circuit afin de limiter les effets de variabilité (work-function fluctuation, WFF) de fabrication et des soft errors (SE); 3) fournir une comparaison entre toutes les techniques appliquées dans ce travail; 4) proposer le meilleur compromis entre performance, consommation, surface, et sensibilité aux corruptions de données et erreurs transitoires. Transistor reordering, decoupling cells, Schmitt Trigger, et sleep transistor sont quatre techniques prometteuses d’optimisation au niveau de circuit, explorées dans ce travail. Le potentiel de chacune d'elles pour rendre les cellules logiques plus robustes vis-à-vis variabilité de fabrication et de SE a été évalué. Cette thèse propose également une estimation des tendances comportementales en fonction du niveau de variabilité, des dimensionnements des transistors et des caractéristiques énergétique de particule ionisante comme transfert d'énergie linéaire. Lors de cette thèse, la variabilité de fabrication a été évaluée par des simulations Monte Carlo (MC) avec une WFF modélisé par une fonction Gaussienne utilisant le SPICE. La susceptibilité SE a été estimée à partir de d’outil de génération MC de radiations, MUSCA SEP3. Cet outil est basé sur des calculs MC afin de rendre compte des caractéristiques de l’environnement radiatif du design et des paramètres électriques des composants analysés. Les approches proposées par cette thèse améliorent l'état-de-l'art actuel en fournissant des options d’optimisation au niveau du circuit pour réduire les effets de variabilité de fabrication et la susceptibilité aux SE. La Transistor reordering peut augmenter la robustesse des cellules logiques pour une variabilité allant jusqu’à 8%, cependant cette approche n’est pas idéale pour la mitigation des SE. L’utilisation de decoupling cells permet de meilleurs résultats pour le contrôle de la variabilité de consommation avec des niveaux de variation supérieurs à 4%, et atténuant jusqu'à 10% la variabilité du délai pour la variabilité de fabrication de 3% de la WFF. D’un point de vue SE, cette technique… Advisors/Committee Members: Artola, Laurent (thesis director), Reis, Ricardo (thesis director).

Subjects/Keywords: Microélectronique; Design au niveau circuit; Variabilité de fabrication; Fiabilité; Soft error; FinFET; Microelectronics; Circuit-Level design; Process variability; Reliability; Soft error; FinFET

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lackmann-Zimpeck, A. (2019). Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. (Doctoral Dissertation). Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil). Retrieved from http://www.theses.fr/2019ESAE0026

Chicago Manual of Style (16^th Edition):

Lackmann-Zimpeck, Alexandra. “Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET.” 2019. Doctoral Dissertation, Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil). Accessed April 11, 2021. http://www.theses.fr/2019ESAE0026.

MLA Handbook (7^th Edition):

Lackmann-Zimpeck, Alexandra. “Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET.” 2019. Web. 11 Apr 2021.

Vancouver:

Lackmann-Zimpeck A. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. [Internet] [Doctoral dissertation]. Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil); 2019. [cited 2021 Apr 11]. Available from: http://www.theses.fr/2019ESAE0026.

Council of Science Editors:

Lackmann-Zimpeck A. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. [Doctoral Dissertation]. Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil); 2019. Available from: http://www.theses.fr/2019ESAE0026

Vanderbilt University

24. Jiang, Hui. Design of soft-error-aware sequential circuits with power and speed optimization.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

URL: http://hdl.handle.net/1803/10911

► A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology… (more)

▼ A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology scaling trends (smaller nodal capacitances) may result in dramatically increased sensitivity of the circuits to radiation. For this reason, SEE are especially considered challenges for low-power and high performance circuits. Hence, it is imperative to consider the SEE induced errors of the low power and high performance design when designing circuits for applications requiring high reliability. In this proposed research, a methodology to bridge the gap between experimental results and predictive models for SEE performance of sequential logic circuits have been developed. A study of the relationship between circuit SEE tolerance and power consumption is performed using this methodology. The purpose is to build a framework of designing soft-error-aware sequential circuits with power and speed optimization. A figure-of-merit (FOM) is provided for designers to make informed decisions on meeting power, speed, and SE specifications after the proposed framework. To comprehensively comment on the design parameters of different sequential logic circuits, a FOM is defined as the inverse of the product of power and SE cross-section (PCSP-1). Since minimization of power and SE cross-section is desirable, a lower PCSP value and thus a higher FOM value can be considered to be an indicator of an optimized design. This work focuses on the study of both power consumption and SEE tolerance at device and circuit-level. Sequential circuits are used as circuit examples in this proposed research. The ultimate goal of the work is to provide designers with capabilities and FOM to choose the suitable low power and SEE tolerance design for different targeted design specifications and operating environment. Advisors/Committee Members: Robinson H. William (committee member), Aniruddha Gokhale (committee member), Ronald D. Schrimpf (committee member), Lloyd Massengill (committee member), Bharat L. Bhuva (Committee Chair).

Subjects/Keywords: power optimization; sequential circuit; soft error rate; Single event effects; empirical model

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APA (6^th Edition):

Jiang, H. (2018). Design of soft-error-aware sequential circuits with power and speed optimization. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10911

Chicago Manual of Style (16^th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed April 11, 2021. http://hdl.handle.net/1803/10911.

MLA Handbook (7^th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Web. 11 Apr 2021.

Vancouver:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1803/10911.

Council of Science Editors:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://hdl.handle.net/1803/10911

Penn State University

25. Liu, Huichu. Device Circuit Interactions for Steep Switching Slope Devices.

Degree: 2015, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/23759

► Energy efficiency limit has becomes the main obstacle for the power-constrained applications using the conventional silicon complementary metal-oxide-semiconductor (CMOS) technology. In particular, the supply voltage… (more)

▼ Energy efficiency limit has becomes the main obstacle for the power-constrained applications using the conventional silicon complementary metal-oxide-semiconductor (CMOS) technology. In particular, the supply voltage scaling has slowed down in the past few technology generations due to the 60 mV/decade fundamental limit for on-off switching, which prevents the reduction of the energy per operation in today’s circuits and systems. To mitigate this challenge, tunneling-field-effect-transistor (TFET), as a viable alternative, has been proposed to achieve steep on-off switching at low supply voltages. Driven by the on-going progress of TFET prototype device development and its device characteristics applicable for different applications, co-design of TFET device-to-circuit is not only critical to transform the technology advantages into various application domains, but also important to evaluate its potential challenges. This dissertation has been dedicated to developing the simulation frameworks to model the III-V semiconductor material based TFETs from devices to circuits and system architectures. Based on the layers of abstractions, the impact of the steep sub-threshold slope, the asymmetrical source/drain, the uni-directional conduction as well as the digital and analog/RF metrics are explored for III-V TFETs. These unique device characteristics of TFETs are essential to enable the circuit design innovations and expand energy efficient application landscapes such as ultra-low power energy scavenging systems and body sensor nodes. Moreover, due to their low-voltage operation and the difference in the material systems and device designs, the reliability issues such as radiation induced single-event upsets, process variations as well as the parasitic effects of TFETs need to be evaluated from practical application perspectives, which are also addressed in this work. Advisors/Committee Members: Vijaykrishnan Narayanan, Committee Chair/Co-Chair, Suman Datta, Committee Chair/Co-Chair, Jerzy Ruzyllo, Committee Member, Joshua Alexander Robinson, Committee Member.

Subjects/Keywords: Tunneling-field-effect-transistor; device-circuit interaction; steep subthreshold slope; energy efficiency; soft error reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liu, H. (2015). Device Circuit Interactions for Steep Switching Slope Devices. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/23759

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liu, Huichu. “Device Circuit Interactions for Steep Switching Slope Devices.” 2015. Thesis, Penn State University. Accessed April 11, 2021. https://submit-etda.libraries.psu.edu/catalog/23759.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liu, Huichu. “Device Circuit Interactions for Steep Switching Slope Devices.” 2015. Web. 11 Apr 2021.

Vancouver:

Liu H. Device Circuit Interactions for Steep Switching Slope Devices. [Internet] [Thesis]. Penn State University; 2015. [cited 2021 Apr 11]. Available from: https://submit-etda.libraries.psu.edu/catalog/23759.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu H. Device Circuit Interactions for Steep Switching Slope Devices. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/23759

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Stellenbosch University

26. Babalola, Oluwaseyi Paul. Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation.

Degree: PhD, Electrical and Electronic Engineering, 2020, Stellenbosch University

URL: http://hdl.handle.net/10019.1/107932

► ENGLISH ABSTRACT: This thesis focuses on obtaining low complexity soft-decision (SD) decoding of binary cyclic codes with coding performance close to the optimal decoding algorithm.… (more)

▼ ENGLISH ABSTRACT: This thesis focuses on obtaining low complexity soft-decision (SD) decoding of binary cyclic codes with coding performance close to the optimal decoding algorithm. The belief propagation (BP) algorithm is commonly used to obtain near-optimal decoding but inappropriate for high-density parity-check (HDPC) codes. Therefore, alternative solutions such as the adaptive belief propagation (ABP) algorithm and the paritycheck transformation algorithm (PTA) have been proposed in the literature, based on matrix transformation, to effectively apply the BP decoding for HDPC codes. The extended parity-check transformation algorithm (EPTA) is introduced in this thesis to obtain a transformed parity-check matrix for the class of binary cyclic (BC) codes. The EPTA reduces the computational complexity of the known adaptive belief propagation (ABP) algorithm. However, it requires more iterative processes to attain comparable results to the ABP. Hence, a generalized parity-check transformation (GPT) algorithm for iterative SD decoding of the class of BC codes is developed. The proposed GPT algorithm is motivated by the EPTA and the belief propagation. The algorithm utilizes a new approach of matrix transformation to overcome the limitation with the BP algorithm for HDPC codes. The transformed matrix is obtained by permuting the columns of the initial parity-check matrix based on the reliability information received from the channel. Results show that the GPT offers a significant performance gain when compared with the hard decision Berlekamp-Massey (B-M) and belief propagation (BP) algorithms. It also produces a reasonable performance gain as compared with other iterative SD decoders. An important feature of the decoder is that it functions within a practical decoding time complexity and can be generally implemented for the class of linear block codes. Furthermore, a perfect knowledge model is developed to verify the optimality of all BP based algorithms for HDPC codes. The PKM computes a list of candidate matrices based on the prior knowledge of the transmitted codeword and it selects the best parity-check matrix according to a distance metric. The selected matrix is optimal since it minimizes the probability of error over various choices in the list. As a result, we show that for a given channel condition, the conventional transformed matrix, obtained by Gaussian reduction, is sub-optimal and will not necessarily contain unitary weighted columns at corresponding columns of the unreliable bits. Here, there exist specific scenarios where this matrix is not the same as the selected matrix from the PKM, giving room for improvement in the matrices of the BP in general. More so, the model can be used to verify performances of newly developed iterative SD decoders based on parity-check equations. In conclusion, the discovery of this thesis is important as it proposes a reduced computational time complexity soft-decision decoder for algebraic block codes. In view of some studies where the potentials of these… Advisors/Committee Members: Versfeld, Daniel Jaco J., Ogundile, Olayinka O., Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering..

Subjects/Keywords: Parity check; Digital communication; Error-correcting codes (Information theory); UCTD; Soft-decision decoding

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APA (6^th Edition):

Babalola, O. P. (2020). Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation. (Doctoral Dissertation). Stellenbosch University. Retrieved from http://hdl.handle.net/10019.1/107932

Chicago Manual of Style (16^th Edition):

Babalola, Oluwaseyi Paul. “Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation.” 2020. Doctoral Dissertation, Stellenbosch University. Accessed April 11, 2021. http://hdl.handle.net/10019.1/107932.

MLA Handbook (7^th Edition):

Babalola, Oluwaseyi Paul. “Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation.” 2020. Web. 11 Apr 2021.

Vancouver:

Babalola OP. Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation. [Internet] [Doctoral dissertation]. Stellenbosch University; 2020. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10019.1/107932.

Council of Science Editors:

Babalola OP. Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation. [Doctoral Dissertation]. Stellenbosch University; 2020. Available from: http://hdl.handle.net/10019.1/107932

University of Waterloo

27. Shah, Jaspal Singh. Low-Power Soft-Error-Robust Embedded SRAM.

Degree: 2013, University of Waterloo

URL: http://hdl.handle.net/10012/7186

► Soft errors are radiation-induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit… (more)

▼ Soft errors are radiation-induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit can always recover from such errors as the underlying semiconductor material is not damaged and hence, they are called soft errors. In nanometer technologies, the reduced node capacitance and supply voltage coupled with high packing density and lack of masking mechanisms are primarily responsible for the increased susceptibility of SRAMs towards soft errors. Coupled with these are the process variations (effective length, width, and threshold voltage), which are prominent in scaled-down technologies. Typically, SRAM constitutes up to 90% of the die in microprocessors and SoCs (System-on-Chip). Hence, the soft errors in SRAMs pose a potential threat to the reliable operation of the system. In this work, a soft-error-robust eight-transistor SRAM cell (8T) is proposed to establish a balance between low power consumption and soft error robustness. Using metrics like access time, leakage power, and sensitivity to single event transients (SET), the proposed approach is evaluated. For the purpose of analysis and comparisons the results of 8T cell are compared with a standard 6T SRAM cell and the state-of-the-art soft-error-robust SRAM cells. Based on simulation results in a 65-nm commercial CMOS process, the 8T cell demonstrates higher immunity to SETs along with smaller area and comparable leakage power. A 32-kb array of 8T cells was fabricated in silicon. After functional verification of the test chip, a radiation test was conducted to evaluate the soft error robustness. As SRAM cells are scaled aggressively to increase the overall packing density, the smaller transistors exhibit higher degrees of process variation and mismatch, leading to larger offset voltages. For SRAM sense amplifiers, higher offset voltages lead to an increased likelihood of an incorrect decision. To address this issue, a sense amplifier capable of cancelling the input offset voltage is presented. The simulated and measured results in 180-nm technology show that the sense amplifier is capable of detecting a 4 mV differential input signal under dc and transient conditions. The proposed sense amplifier, when compared with a conventional sense amplifier, has a similar die area and a greatly reduced offset voltage. Additionally, a dual-input sense amplifier architecture is proposed with corroborating silicon results to show that it requires smaller differential input to evaluate correctly.

Subjects/Keywords: VLSI; Embedded SRAM; Cache; Soft Error; Offset cancellation; Sense amplifier; Low Power

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APA (6^th Edition):

Shah, J. S. (2013). Low-Power Soft-Error-Robust Embedded SRAM. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/7186

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Shah, Jaspal Singh. “Low-Power Soft-Error-Robust Embedded SRAM.” 2013. Thesis, University of Waterloo. Accessed April 11, 2021. http://hdl.handle.net/10012/7186.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Shah, Jaspal Singh. “Low-Power Soft-Error-Robust Embedded SRAM.” 2013. Web. 11 Apr 2021.

Vancouver:

Shah JS. Low-Power Soft-Error-Robust Embedded SRAM. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10012/7186.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah JS. Low-Power Soft-Error-Robust Embedded SRAM. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/7186

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

28. Limbrick, Daniel Brian. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/14920

► Radiation-induced soft errors are becoming a dominant reliability-failure mechanism in modern CMOS technologies. In nanometer technologies, the effects are not limited to the storage elements… (more)

Subjects/Keywords: reliability-aware synthesis; single event transient; pulse width; combinational logic; soft error; logic synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Limbrick, D. B. (2012). Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14920

Chicago Manual of Style (16^th Edition):

Limbrick, Daniel Brian. “Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed April 11, 2021. http://hdl.handle.net/1803/14920.

MLA Handbook (7^th Edition):

Limbrick, Daniel Brian. “Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.” 2012. Web. 11 Apr 2021.

Vancouver:

Limbrick DB. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1803/14920.

Council of Science Editors:

Limbrick DB. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/14920

University of Texas – Austin

29. Mirkhani, Shahrzad. Statistical methods for rapid system evaluation under transient and permanent faults.

Degree: PhD, Electrical and Computer Engineering, 2014, University of Texas – Austin

URL: http://hdl.handle.net/2152/28393

► Traditional solutions for test and reliability do not scale well for modern designs with their size and complexity increasing with every technology generation. Therefore, in… (more)

Subjects/Keywords: Functional fault grading; VLSI testing; Fault coverage estimation; Soft error; Vulnerability factors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mirkhani, S. (2014). Statistical methods for rapid system evaluation under transient and permanent faults. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/28393

Chicago Manual of Style (16^th Edition):

Mirkhani, Shahrzad. “Statistical methods for rapid system evaluation under transient and permanent faults.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed April 11, 2021. http://hdl.handle.net/2152/28393.

MLA Handbook (7^th Edition):

Mirkhani, Shahrzad. “Statistical methods for rapid system evaluation under transient and permanent faults.” 2014. Web. 11 Apr 2021.

Vancouver:

Mirkhani S. Statistical methods for rapid system evaluation under transient and permanent faults. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2152/28393.

Council of Science Editors:

Mirkhani S. Statistical methods for rapid system evaluation under transient and permanent faults. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/28393

30. Zimpeck, Alexandra Lackmann. Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells.

Degree: 2019, Brazil

URL: http://hdl.handle.net/10183/201310

► A variabilidade de processo e a resistência a radiação são requisitos de confiabilidade relevantes à medida que a fabricação de chips avança mais a fundo… (more)

▼ A variabilidade de processo e a resistência a radiação são requisitos de confiabilidade relevantes à medida que a fabricação de chips avança mais a fundo no regime nanométrico. A perda de rendimento paramétrico e as falhas críticas no comportamento do sistema são as principais consequências destes problemas. Alguns trabalhos relacionados exploram a influência da variabilidade de processo e dos eventos transientes únicos (SET) nos circuitos projetados nas tecnologias FinFET, mas existe uma ausência de abordagens para mitigar eles. Por estas razões, do ponto de vista de projeto, esforços consideráveis devem ser feitos para entender e reduzir os impactos introduzidos pelos desafios de confiabilidade. Dessa forma, as principais contribuições desta tese de doutorado são: 1) investigar o comportamento de células lógicas FinFET sob variações de processo e efeitos de radiação; 2) avaliar quatro abordagens em nível de circuito para atenuar o impacto causado por flutuações na função trabalho (WFF) and soft errors (SE); 3) fornecer uma comparação global entre todas as técnicas aplicadas neste trabalho; 4) Traçar um balanceamento entre os ganhos e as penalidades de cada abordagem em relação ao desempenho, potência, área, seção transversal SET e largura de pulso SET. Reordenamento de transistores, e o uso de decoupling cells, Schmitt Triggers e sleep transistors são as quatro técnicas de mitigação em nível de circuito exploradas neste trabalho. O potencial de cada uma delas para tornar as células lógicas mais robustas à variabilidade de processo e aos soft errors induzidos pela radiação são avaliados comparando os resultados da versão padrão com o projeto usando cada uma das técnicas. Esta tese também estabelece a tendência de mitigação quando diferentes níveis de variação, dimensionamento de transistores e características das partículas de radiação, tais como a transferência linear de energia (LET), são aplicados no projeto com estas técnicas. A variabilidade de processo é avaliada através de simulações Monte Carlo (MC) com a WFF modelada como uma função Gaussiana usando simulações SPICE enquanto a susceptibilidade à SE é estimada usando a ferramenta gerado de eventos de radiação MUSCA SEP3 (desenvolvida na ONERA) também baseada em um método MC que lida com as características do ambiente de radiação, os recursos de leiaute e as propriedades elétricas dos dispositivos. De modo geral, as técnicas propostas melhoram o estado da arte, fornecendo opções à nível de circuito para reduzir os efeitos da variabilidade de processo e a susceptibilidade à SE, com menos penalidades e complexidade de projeto. A técnica de reordenamento de transistores pode aumentar a robustez das células lógicas sob variação de processo até 8%, mas este método não é favorável para a mitigação de SE. A inserção de decoupling cells mostra resultados interessantes para o controle da variabilidade de potência com níveis de variação acima de 4%, e esta técnica pode atenuar até 10% a variabilidade de atraso considerando um processo de manufatura com 3% de WFF.… Advisors/Committee Members: Reis, Ricardo Augusto da Luz, Hubert, Guillaume.

Subjects/Keywords: Microeletrônica; Circuitos digitais; circuit-level design; process variability; reliability; soft error; FinFET

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zimpeck, A. L. (2019). Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells. (Doctoral Dissertation). Brazil. Retrieved from http://hdl.handle.net/10183/201310

Chicago Manual of Style (16^th Edition):

Zimpeck, Alexandra Lackmann. “Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells.” 2019. Doctoral Dissertation, Brazil. Accessed April 11, 2021. http://hdl.handle.net/10183/201310.

MLA Handbook (7^th Edition):

Zimpeck, Alexandra Lackmann. “Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells.” 2019. Web. 11 Apr 2021.

Vancouver:

Zimpeck AL. Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells. [Internet] [Doctoral dissertation]. Brazil; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10183/201310.

Council of Science Editors:

Zimpeck AL. Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells. [Doctoral Dissertation]. Brazil; 2019. Available from: http://hdl.handle.net/10183/201310

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