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You searched for subject:(Single Event Upsets SEU ). Showing records 1 – 30 of 11266 total matches.

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Vanderbilt University

1. Chen, Yanran. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

 In deep sub-micron CMOS technologies, all-digital phase-locked loops (ADPLLs) are favored over conventional analog or mixed-signal phase-locked loops (A/MS) PLLs for providing the clock signals… (more)

Subjects/Keywords: Single-Event Upsets (SEU); All-digital Phase-locked Loops (ADPLLs); Single-Event Effects (SEE)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2017). Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;

Chicago Manual of Style (16th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed November 12, 2019. http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;.

MLA Handbook (7th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Web. 12 Nov 2019.

Vancouver:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2019 Nov 12]. Available from: http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;.

Council of Science Editors:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;


University of Southern California

2. Abramson, Jeremy D. Resiliency-aware scheduling.

Degree: PhD, Computer Science (High Performance Computing and Simulations), 2013, University of Southern California

 Hostile environments, shrinking feature sizes and processor aging elicit a need for resilient computing. Traditional course-grained approaches, such as software Checkpoint and Restart (C/R) and… (more)

Subjects/Keywords: resiliency; compilers; FPGA; reconfigurable; fault-tolerance; area consumption; SEU; errors; single-event upsets; scheduling; VLIW

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APA (6th Edition):

Abramson, J. D. (2013). Resiliency-aware scheduling. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/223327/rec/5547

Chicago Manual of Style (16th Edition):

Abramson, Jeremy D. “Resiliency-aware scheduling.” 2013. Doctoral Dissertation, University of Southern California. Accessed November 12, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/223327/rec/5547.

MLA Handbook (7th Edition):

Abramson, Jeremy D. “Resiliency-aware scheduling.” 2013. Web. 12 Nov 2019.

Vancouver:

Abramson JD. Resiliency-aware scheduling. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2019 Nov 12]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/223327/rec/5547.

Council of Science Editors:

Abramson JD. Resiliency-aware scheduling. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/223327/rec/5547


Virginia Tech

3. Arechiga, Austin Podoll. Sensitivity of Feedforward Neural Networks to Harsh Computing Environments.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Neural Networks have proven themselves very adept at solving a wide variety of problems, in particular they accel at image processing. However, it remains unknown… (more)

Subjects/Keywords: Machine Learning; Fault Tolerance; Single Event Upsets

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APA (6th Edition):

Arechiga, A. P. (2018). Sensitivity of Feedforward Neural Networks to Harsh Computing Environments. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84527

Chicago Manual of Style (16th Edition):

Arechiga, Austin Podoll. “Sensitivity of Feedforward Neural Networks to Harsh Computing Environments.” 2018. Masters Thesis, Virginia Tech. Accessed November 12, 2019. http://hdl.handle.net/10919/84527.

MLA Handbook (7th Edition):

Arechiga, Austin Podoll. “Sensitivity of Feedforward Neural Networks to Harsh Computing Environments.” 2018. Web. 12 Nov 2019.

Vancouver:

Arechiga AP. Sensitivity of Feedforward Neural Networks to Harsh Computing Environments. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/10919/84527.

Council of Science Editors:

Arechiga AP. Sensitivity of Feedforward Neural Networks to Harsh Computing Environments. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84527


Vanderbilt University

4. Kay, William Hunter. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

 The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme… (more)

Subjects/Keywords: flip flop; 20 nm; single event; SET; SEE; SEU

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APA (6th Edition):

Kay, W. H. (2015). Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;

Chicago Manual of Style (16th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Masters Thesis, Vanderbilt University. Accessed November 12, 2019. http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.

MLA Handbook (7th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Web. 12 Nov 2019.

Vancouver:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Internet] [Masters thesis]. Vanderbilt University; 2015. [cited 2019 Nov 12]. Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.

Council of Science Editors:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Masters Thesis]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;


Université de Grenoble

5. Mansour, Wassim. Méthodes et outils pour l'analyse tôt dans le flot de conception de la sensibilité aux soft-erreurs des applications et des circuits intégrés : Methods and tools for the early analysis in the design flow of the sensitivity to soft-errors of applications and integrated circuits.

Degree: Docteur es, Sciences et technologie industrielles, 2012, Université de Grenoble

La miniaturisation des gravures des transistors résulte en une augmentation de la sensibilité aux soft-erreurs des circuits intégrés face aux particules énergétiques présentes dans l’environnement… (more)

Subjects/Keywords: Environement spatial; Single event upsets; Injection des fautes; CEU; Architecture digitale; Spacial evironment; Single event upsets; Fault injection; Fault tolerance; CEU; Digital architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mansour, W. (2012). Méthodes et outils pour l'analyse tôt dans le flot de conception de la sensibilité aux soft-erreurs des applications et des circuits intégrés : Methods and tools for the early analysis in the design flow of the sensitivity to soft-errors of applications and integrated circuits. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2012GRENT055

Chicago Manual of Style (16th Edition):

Mansour, Wassim. “Méthodes et outils pour l'analyse tôt dans le flot de conception de la sensibilité aux soft-erreurs des applications et des circuits intégrés : Methods and tools for the early analysis in the design flow of the sensitivity to soft-errors of applications and integrated circuits.” 2012. Doctoral Dissertation, Université de Grenoble. Accessed November 12, 2019. http://www.theses.fr/2012GRENT055.

MLA Handbook (7th Edition):

Mansour, Wassim. “Méthodes et outils pour l'analyse tôt dans le flot de conception de la sensibilité aux soft-erreurs des applications et des circuits intégrés : Methods and tools for the early analysis in the design flow of the sensitivity to soft-errors of applications and integrated circuits.” 2012. Web. 12 Nov 2019.

Vancouver:

Mansour W. Méthodes et outils pour l'analyse tôt dans le flot de conception de la sensibilité aux soft-erreurs des applications et des circuits intégrés : Methods and tools for the early analysis in the design flow of the sensitivity to soft-errors of applications and integrated circuits. [Internet] [Doctoral dissertation]. Université de Grenoble; 2012. [cited 2019 Nov 12]. Available from: http://www.theses.fr/2012GRENT055.

Council of Science Editors:

Mansour W. Méthodes et outils pour l'analyse tôt dans le flot de conception de la sensibilité aux soft-erreurs des applications et des circuits intégrés : Methods and tools for the early analysis in the design flow of the sensitivity to soft-errors of applications and integrated circuits. [Doctoral Dissertation]. Université de Grenoble; 2012. Available from: http://www.theses.fr/2012GRENT055

6. Ramos Vargas, Pablo Francisco. Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors.

Degree: Docteur es, Nano electronique et nano technologies, 2017, Grenoble Alpes

La présente thèse vise à évaluer la sensibilité statique et dynamique face aux SEE de trois dispositifs COTS différents. Le premier est le processeur multi-cœurs… (more)

Subjects/Keywords: Fiabilité; Test; Injection de fautes; Processeurs many-Core; Single Event Upsets; Essai de radiation; Reliability; Testing; Fault injection; Many- core processors; Single Event Upsets; Radiation test; 600

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ramos Vargas, P. F. (2017). Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2017GREAT022

Chicago Manual of Style (16th Edition):

Ramos Vargas, Pablo Francisco. “Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors.” 2017. Doctoral Dissertation, Grenoble Alpes. Accessed November 12, 2019. http://www.theses.fr/2017GREAT022.

MLA Handbook (7th Edition):

Ramos Vargas, Pablo Francisco. “Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors.” 2017. Web. 12 Nov 2019.

Vancouver:

Ramos Vargas PF. Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2017. [cited 2019 Nov 12]. Available from: http://www.theses.fr/2017GREAT022.

Council of Science Editors:

Ramos Vargas PF. Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors. [Doctoral Dissertation]. Grenoble Alpes; 2017. Available from: http://www.theses.fr/2017GREAT022


Texas A&M University

7. Garg, Rajesh. Analysis and Design of Resilient VLSI Circuits.

Degree: 2010, Texas A&M University

 The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes,… (more)

Subjects/Keywords: Radiation Particle Strikes; Single Event Upsets (SEUs); Soft Errors; Single Event Transients; Design; Analysis; Modeling; DVS; Process Variations

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APA (6th Edition):

Garg, R. (2010). Analysis and Design of Resilient VLSI Circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-410

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Garg, Rajesh. “Analysis and Design of Resilient VLSI Circuits.” 2010. Thesis, Texas A&M University. Accessed November 12, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-410.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Garg, Rajesh. “Analysis and Design of Resilient VLSI Circuits.” 2010. Web. 12 Nov 2019.

Vancouver:

Garg R. Analysis and Design of Resilient VLSI Circuits. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-410.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Garg R. Analysis and Design of Resilient VLSI Circuits. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-410

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

8. Bennett, William Geoffrey. Single Event Upset Mechanisms in Emerging Memory Technologies.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

 The commercial memory industry, now more than ever, is looking at CMOS Flash alternatives to provide continued scaling of data storage elements. Meanwhile, radiation tolerant… (more)

Subjects/Keywords: single event upsets; multiple event upsets; RRAM; resistive random access memory; charge sharing; charge competition; multiple node charge collection; two photon absorption; heavy ion irradiation

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APA (6th Edition):

Bennett, W. G. (2014). Single Event Upset Mechanisms in Emerging Memory Technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-07082014-082801/ ;

Chicago Manual of Style (16th Edition):

Bennett, William Geoffrey. “Single Event Upset Mechanisms in Emerging Memory Technologies.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed November 12, 2019. http://etd.library.vanderbilt.edu/available/etd-07082014-082801/ ;.

MLA Handbook (7th Edition):

Bennett, William Geoffrey. “Single Event Upset Mechanisms in Emerging Memory Technologies.” 2014. Web. 12 Nov 2019.

Vancouver:

Bennett WG. Single Event Upset Mechanisms in Emerging Memory Technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2019 Nov 12]. Available from: http://etd.library.vanderbilt.edu/available/etd-07082014-082801/ ;.

Council of Science Editors:

Bennett WG. Single Event Upset Mechanisms in Emerging Memory Technologies. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-07082014-082801/ ;


Université de Grenoble

9. Evans, Adrian. Techniques d'abstraction pour l'analyse et la mitigation des effets dus à la radiation : Abstraction techniques for scalable soft error analysis and mitigation.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2014, Université de Grenoble

 Les effets dus à la radiation peuvent provoquer des pannes dans des circuits intégrés. Lorsqu'une particule subatomique, fait se déposer une charge dans les régions… (more)

Subjects/Keywords: Effets singuliers; Effets transitoires; Injection de fautes; Asic; Protection parité; Fiabilité; Single-event effects; Single-event upsets; Single-event transients; Reliable systems; Fault-injection; 620

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APA (6th Edition):

Evans, A. (2014). Techniques d'abstraction pour l'analyse et la mitigation des effets dus à la radiation : Abstraction techniques for scalable soft error analysis and mitigation. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2014GRENT035

Chicago Manual of Style (16th Edition):

Evans, Adrian. “Techniques d'abstraction pour l'analyse et la mitigation des effets dus à la radiation : Abstraction techniques for scalable soft error analysis and mitigation.” 2014. Doctoral Dissertation, Université de Grenoble. Accessed November 12, 2019. http://www.theses.fr/2014GRENT035.

MLA Handbook (7th Edition):

Evans, Adrian. “Techniques d'abstraction pour l'analyse et la mitigation des effets dus à la radiation : Abstraction techniques for scalable soft error analysis and mitigation.” 2014. Web. 12 Nov 2019.

Vancouver:

Evans A. Techniques d'abstraction pour l'analyse et la mitigation des effets dus à la radiation : Abstraction techniques for scalable soft error analysis and mitigation. [Internet] [Doctoral dissertation]. Université de Grenoble; 2014. [cited 2019 Nov 12]. Available from: http://www.theses.fr/2014GRENT035.

Council of Science Editors:

Evans A. Techniques d'abstraction pour l'analyse et la mitigation des effets dus à la radiation : Abstraction techniques for scalable soft error analysis and mitigation. [Doctoral Dissertation]. Université de Grenoble; 2014. Available from: http://www.theses.fr/2014GRENT035


Vanderbilt University

10. King, Michael Patrick. Energetic electron-induced single event upsets in static random access memory.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

  Energy deposition in ionizing radiation events can cause errors in static random access memories (SRAMs). The resulting errors can negatively impact nominal systems operation.… (more)

Subjects/Keywords: electron-induced SEU; energetic electron; static random access memory; single-event upset; error rate predictions

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APA (6th Edition):

King, M. P. (2014). Energetic electron-induced single event upsets in static random access memory. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03242014-131749/ ;

Chicago Manual of Style (16th Edition):

King, Michael Patrick. “Energetic electron-induced single event upsets in static random access memory.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed November 12, 2019. http://etd.library.vanderbilt.edu/available/etd-03242014-131749/ ;.

MLA Handbook (7th Edition):

King, Michael Patrick. “Energetic electron-induced single event upsets in static random access memory.” 2014. Web. 12 Nov 2019.

Vancouver:

King MP. Energetic electron-induced single event upsets in static random access memory. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2019 Nov 12]. Available from: http://etd.library.vanderbilt.edu/available/etd-03242014-131749/ ;.

Council of Science Editors:

King MP. Energetic electron-induced single event upsets in static random access memory. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-03242014-131749/ ;

11. Costenaro, Enrico. Techniques pour l'évaluation et l'amélioration du comportement des technologies émergentes face aux fautes aléatoires : Techniques for the evaluation and the improvement of emergent technologies’ behavior facing random errors.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2015, Grenoble Alpes

 L'objectif principal de cette thèse est de développer des techniques d'analyse et mitigation capables à contrer les effets des Evènements Singuliers (Single Event Effects) -… (more)

Subjects/Keywords: Événements singuliers; Événements singuliers upsets; Événements singuliers transitoire; Soft erreurs; Injection de fautes; Protection sélective; Single-event effects; Single-event upsets; Single-event transients; Soft errors; Fault-injection; Selective mitigation; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Costenaro, E. (2015). Techniques pour l'évaluation et l'amélioration du comportement des technologies émergentes face aux fautes aléatoires : Techniques for the evaluation and the improvement of emergent technologies’ behavior facing random errors. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2015GREAT137

Chicago Manual of Style (16th Edition):

Costenaro, Enrico. “Techniques pour l'évaluation et l'amélioration du comportement des technologies émergentes face aux fautes aléatoires : Techniques for the evaluation and the improvement of emergent technologies’ behavior facing random errors.” 2015. Doctoral Dissertation, Grenoble Alpes. Accessed November 12, 2019. http://www.theses.fr/2015GREAT137.

MLA Handbook (7th Edition):

Costenaro, Enrico. “Techniques pour l'évaluation et l'amélioration du comportement des technologies émergentes face aux fautes aléatoires : Techniques for the evaluation and the improvement of emergent technologies’ behavior facing random errors.” 2015. Web. 12 Nov 2019.

Vancouver:

Costenaro E. Techniques pour l'évaluation et l'amélioration du comportement des technologies émergentes face aux fautes aléatoires : Techniques for the evaluation and the improvement of emergent technologies’ behavior facing random errors. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2015. [cited 2019 Nov 12]. Available from: http://www.theses.fr/2015GREAT137.

Council of Science Editors:

Costenaro E. Techniques pour l'évaluation et l'amélioration du comportement des technologies émergentes face aux fautes aléatoires : Techniques for the evaluation and the improvement of emergent technologies’ behavior facing random errors. [Doctoral Dissertation]. Grenoble Alpes; 2015. Available from: http://www.theses.fr/2015GREAT137


Universidade do Rio Grande do Sul

12. Seclen, Jorge Lucio Tonfat. Frame-level redundancy scrubbing technique for SRAM-based FPGAs.

Degree: 2015, Universidade do Rio Grande do Sul

Reliability is an important design constraint for critical applications at ground-level and aerospace. SRAM-based FPGAs are attractive for critical applications due to their high performance… (more)

Subjects/Keywords: Microeletrônica; SRAM-based FPGA; Fpga; Soft error; Circuitos digitais; Memory scrubbing; Reliability; Single event upsets; Fault tolerance; Microelectronics

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APA (6th Edition):

Seclen, J. L. T. (2015). Frame-level redundancy scrubbing technique for SRAM-based FPGAs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/143194

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Seclen, Jorge Lucio Tonfat. “Frame-level redundancy scrubbing technique for SRAM-based FPGAs.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed November 12, 2019. http://hdl.handle.net/10183/143194.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Seclen, Jorge Lucio Tonfat. “Frame-level redundancy scrubbing technique for SRAM-based FPGAs.” 2015. Web. 12 Nov 2019.

Vancouver:

Seclen JLT. Frame-level redundancy scrubbing technique for SRAM-based FPGAs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/10183/143194.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Seclen JLT. Frame-level redundancy scrubbing technique for SRAM-based FPGAs. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/143194

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

13. Olson, Brian David. Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters.

Degree: PhD, Electrical Engineering, 2010, Vanderbilt University

 Analog-to-digital converters (ADCs) are necessary circuits in many space, military, and medical circuit applications. Intelligence, surveillance, reconnaissance, and communication missions all require high performance ADCs.… (more)

Subjects/Keywords: single-events; SEU; SEE; RHBD; radiation hardened by design; ADC; single-event effects; analog-to-digital converters

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APA (6th Edition):

Olson, B. D. (2010). Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;

Chicago Manual of Style (16th Edition):

Olson, Brian David. “Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters.” 2010. Doctoral Dissertation, Vanderbilt University. Accessed November 12, 2019. http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;.

MLA Handbook (7th Edition):

Olson, Brian David. “Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters.” 2010. Web. 12 Nov 2019.

Vancouver:

Olson BD. Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters. [Internet] [Doctoral dissertation]. Vanderbilt University; 2010. [cited 2019 Nov 12]. Available from: http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;.

Council of Science Editors:

Olson BD. Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters. [Doctoral Dissertation]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;


University of Kentucky

14. Ambat, Shadab Gopinath. SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS.

Degree: 2008, University of Kentucky

 The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset… (more)

Subjects/Keywords: Radiation; Geiger tube; Scintillator; Semiconductor Detector; Single Event Upset (SEU); Field Programmable Gate Array (FPGA); JTAG; JBits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ambat, S. G. (2008). SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/gradschool_theses/511

Chicago Manual of Style (16th Edition):

Ambat, Shadab Gopinath. “SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS.” 2008. Masters Thesis, University of Kentucky. Accessed November 12, 2019. http://uknowledge.uky.edu/gradschool_theses/511.

MLA Handbook (7th Edition):

Ambat, Shadab Gopinath. “SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS.” 2008. Web. 12 Nov 2019.

Vancouver:

Ambat SG. SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS. [Internet] [Masters thesis]. University of Kentucky; 2008. [cited 2019 Nov 12]. Available from: http://uknowledge.uky.edu/gradschool_theses/511.

Council of Science Editors:

Ambat SG. SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS. [Masters Thesis]. University of Kentucky; 2008. Available from: http://uknowledge.uky.edu/gradschool_theses/511


Universidade do Rio Grande do Sul

15. Santos, André Flores dos. Análise do uso de redundância em circuitos gerados por síntese de alto nível para FPGA programado por SRAM sob falhas transientes.

Degree: 2017, Universidade do Rio Grande do Sul

Este trabalho consiste no estudo e análise da suscetibilidade a efeitos da radiação em projetos de circuitos gerados por ferramenta de Síntese de Alto Nível… (more)

Subjects/Keywords: Field-Programable Gate Arrays (FPGAs); Microeletrônica; Fpga; Triple Modular Redundance (TMR); Single Event Upset (SEU); Single Event Effects (SEEs); System-on-Chips (SoCs)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Santos, A. F. d. (2017). Análise do uso de redundância em circuitos gerados por síntese de alto nível para FPGA programado por SRAM sob falhas transientes. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/178392

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Santos, André Flores dos. “Análise do uso de redundância em circuitos gerados por síntese de alto nível para FPGA programado por SRAM sob falhas transientes.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed November 12, 2019. http://hdl.handle.net/10183/178392.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Santos, André Flores dos. “Análise do uso de redundância em circuitos gerados por síntese de alto nível para FPGA programado por SRAM sob falhas transientes.” 2017. Web. 12 Nov 2019.

Vancouver:

Santos AFd. Análise do uso de redundância em circuitos gerados por síntese de alto nível para FPGA programado por SRAM sob falhas transientes. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/10183/178392.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santos AFd. Análise do uso de redundância em circuitos gerados por síntese de alto nível para FPGA programado por SRAM sob falhas transientes. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/178392

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

16. Degalahal, Vijay Sai. Soft Errors: Modeling And Interactions with Power Optimizations.

Degree: PhD, Computer Science and Engineering, 2005, Penn State University

 Soft errors are radiation induced ionization events that cause errors in circuits. The circuit always recovers from these errors as they do not damage the… (more)

Subjects/Keywords: reliability in DSM; Soft errors; Single event upsets; low power VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Degalahal, V. S. (2005). Soft Errors: Modeling And Interactions with Power Optimizations. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/6783

Chicago Manual of Style (16th Edition):

Degalahal, Vijay Sai. “Soft Errors: Modeling And Interactions with Power Optimizations.” 2005. Doctoral Dissertation, Penn State University. Accessed November 12, 2019. https://etda.libraries.psu.edu/catalog/6783.

MLA Handbook (7th Edition):

Degalahal, Vijay Sai. “Soft Errors: Modeling And Interactions with Power Optimizations.” 2005. Web. 12 Nov 2019.

Vancouver:

Degalahal VS. Soft Errors: Modeling And Interactions with Power Optimizations. [Internet] [Doctoral dissertation]. Penn State University; 2005. [cited 2019 Nov 12]. Available from: https://etda.libraries.psu.edu/catalog/6783.

Council of Science Editors:

Degalahal VS. Soft Errors: Modeling And Interactions with Power Optimizations. [Doctoral Dissertation]. Penn State University; 2005. Available from: https://etda.libraries.psu.edu/catalog/6783


Universidade do Rio Grande do Sul

17. Balen, Tiago Roberto. Efeitos da radiação em dispositivos analógicos programáveis (FPAAs) e técnicas de proteção.

Degree: 2010, Universidade do Rio Grande do Sul

 Este trabalho estuda os efeitos da radiação em dispositivos analógicos programáveis (FPAAs, do inglês, Field Programmable Analog Arrays) e técnicas de proteção que podem ser… (more)

Subjects/Keywords: Single event upset (SEU); Circuitos eletrônicos; Total ionizing dose (TID) Field programmable analog arrays (FPAAs); Efeitos da radiação; Radiation effects; Circuitos analógicos; Radiação : Proteção; Self-checking; Radiation hardening techniques

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Balen, T. R. (2010). Efeitos da radiação em dispositivos analógicos programáveis (FPAAs) e técnicas de proteção. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/27254

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Balen, Tiago Roberto. “Efeitos da radiação em dispositivos analógicos programáveis (FPAAs) e técnicas de proteção.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed November 12, 2019. http://hdl.handle.net/10183/27254.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Balen, Tiago Roberto. “Efeitos da radiação em dispositivos analógicos programáveis (FPAAs) e técnicas de proteção.” 2010. Web. 12 Nov 2019.

Vancouver:

Balen TR. Efeitos da radiação em dispositivos analógicos programáveis (FPAAs) e técnicas de proteção. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/10183/27254.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Balen TR. Efeitos da radiação em dispositivos analógicos programáveis (FPAAs) e técnicas de proteção. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/27254

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

18. Chielle, Eduardo. Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead.

Degree: 2016, Universidade do Rio Grande do Sul

Software-based fault tolerance techniques are a low-cost way to protect processors against soft errors. However, they introduce significant overheads to the execution time and code… (more)

Subjects/Keywords: SIHFT techniques; Microeletrônica; Tolerancia : Falhas : Software; Selective hardening; Transient faults; Processadores; Soft errors; Single event effects; SEU; SET; Processor; Reliability; Execution time; Code size; Energy consumption; Lower overheads

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chielle, E. (2016). Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/142568

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chielle, Eduardo. “Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed November 12, 2019. http://hdl.handle.net/10183/142568.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chielle, Eduardo. “Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead.” 2016. Web. 12 Nov 2019.

Vancouver:

Chielle E. Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/10183/142568.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chielle E. Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/142568

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

19. Jonsson, Per-Axel. Equipment for measuring cosmic-ray effects on DRAM.

Degree: Electrical Engineering, 2007, Linköping University

  Nuclear particles hitting the silicon in a electronic device can cause a change in the data in a memory bit cell or in a… (more)

Subjects/Keywords: DRAM; memory; SEU; single event upset; soft error; FPGA; cosmic radiation; Electronics; Elektronik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jonsson, P. (2007). Equipment for measuring cosmic-ray effects on DRAM. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jonsson, Per-Axel. “Equipment for measuring cosmic-ray effects on DRAM.” 2007. Thesis, Linköping University. Accessed November 12, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jonsson, Per-Axel. “Equipment for measuring cosmic-ray effects on DRAM.” 2007. Web. 12 Nov 2019.

Vancouver:

Jonsson P. Equipment for measuring cosmic-ray effects on DRAM. [Internet] [Thesis]. Linköping University; 2007. [cited 2019 Nov 12]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jonsson P. Equipment for measuring cosmic-ray effects on DRAM. [Thesis]. Linköping University; 2007. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Nsengiyumva, Patrick. INVESTIGATING THE EFFECTS OF SINGLE-EVENT UPSETS IN STATIC AND DYNAMIC REGISTERS.

Degree: MS, 2014, University of New Hampshire

 Radiation-induced single-event upsets (SEUs) pose a serious threat to the reliability of registers. The existing SEU analyses for static CMOS registers focus on the circuit-level… (more)

Subjects/Keywords: Critical Charge; Fault-Tolerance; Integrated Circuit Reliability; Radiation-Induced Effects; Selective Node Hardening (SNH); Single-Event Upset (SEU); Nuclear engineering; Computer engineering; Electrical engineering

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APA (6th Edition):

Nsengiyumva, P. (2014). INVESTIGATING THE EFFECTS OF SINGLE-EVENT UPSETS IN STATIC AND DYNAMIC REGISTERS. (Thesis). University of New Hampshire. Retrieved from https://scholars.unh.edu/thesis/984

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nsengiyumva, Patrick. “INVESTIGATING THE EFFECTS OF SINGLE-EVENT UPSETS IN STATIC AND DYNAMIC REGISTERS.” 2014. Thesis, University of New Hampshire. Accessed November 12, 2019. https://scholars.unh.edu/thesis/984.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nsengiyumva, Patrick. “INVESTIGATING THE EFFECTS OF SINGLE-EVENT UPSETS IN STATIC AND DYNAMIC REGISTERS.” 2014. Web. 12 Nov 2019.

Vancouver:

Nsengiyumva P. INVESTIGATING THE EFFECTS OF SINGLE-EVENT UPSETS IN STATIC AND DYNAMIC REGISTERS. [Internet] [Thesis]. University of New Hampshire; 2014. [cited 2019 Nov 12]. Available from: https://scholars.unh.edu/thesis/984.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nsengiyumva P. INVESTIGATING THE EFFECTS OF SINGLE-EVENT UPSETS IN STATIC AND DYNAMIC REGISTERS. [Thesis]. University of New Hampshire; 2014. Available from: https://scholars.unh.edu/thesis/984

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Peng, Chi-Chen. Setmap: a soft error tolerant mapping algorithm for FPGA designs with low power.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 Field programmable gate arrays (FPGAs) are widely used in VLSI applications due to their flexibility to implement logical functions, fast total turn-around time, and low… (more)

Subjects/Keywords: Field-Programmable Gate Array (FPGA); Single Event Upset (SEU)

…of enhancing SRAM for avoiding SEU. In terms of logic, one of the famous structures is… …combinational logic components. When one SEU occurs in one of the three combinational logic components… …x28;a) SEU in Combinational Logic 1 out Combinational Logic 2 Combinational Logic 3… …Then, it increases reliability through addition of single gates. In [6], three… …error for a cut itself. 4.2 Calculation of Cost Function for a Cut Itself SEU LUT A LUT B 1… 

Page 1 Page 2 Page 3 Page 4 Page 5 Sample image

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Peng, C. (2010). Setmap: a soft error tolerant mapping algorithm for FPGA designs with low power. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/16188

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Peng, Chi-Chen. “Setmap: a soft error tolerant mapping algorithm for FPGA designs with low power.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed November 12, 2019. http://hdl.handle.net/2142/16188.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Peng, Chi-Chen. “Setmap: a soft error tolerant mapping algorithm for FPGA designs with low power.” 2010. Web. 12 Nov 2019.

Vancouver:

Peng C. Setmap: a soft error tolerant mapping algorithm for FPGA designs with low power. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/2142/16188.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Peng C. Setmap: a soft error tolerant mapping algorithm for FPGA designs with low power. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/16188

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

22. Shambhulingaiah, Sandeep. Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation.

Degree: Electrical Engineering, 2015, Arizona State University

Subjects/Keywords: Electrical engineering; Flip-flop; Methodology; Multi node charge collection; Radiation hardening by design; Single Event Transient (SET); Single Event Upset (SEU)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shambhulingaiah, S. (2015). Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/29650

Chicago Manual of Style (16th Edition):

Shambhulingaiah, Sandeep. “Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation.” 2015. Doctoral Dissertation, Arizona State University. Accessed November 12, 2019. http://repository.asu.edu/items/29650.

MLA Handbook (7th Edition):

Shambhulingaiah, Sandeep. “Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation.” 2015. Web. 12 Nov 2019.

Vancouver:

Shambhulingaiah S. Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation. [Internet] [Doctoral dissertation]. Arizona State University; 2015. [cited 2019 Nov 12]. Available from: http://repository.asu.edu/items/29650.

Council of Science Editors:

Shambhulingaiah S. Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation. [Doctoral Dissertation]. Arizona State University; 2015. Available from: http://repository.asu.edu/items/29650


Linköping University

23. Dahlberg, Johan. Embedded Computer for Space Applications suitable for Linux.

Degree: Electrical Engineering, 2003, Linköping University

  This report briefly describes the special requirements for a computer board for use in space. In particular, component selection and ways of mitigating the… (more)

Subjects/Keywords: Datorteknik; Embedded computer; Space; Linux; Radiation; Single event upsets; Error correction; Hamming codes; Microprocessor; Memory; StrongARM; FPGA; Datorteknik; Computer Engineering; Datorteknik

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APA (6th Edition):

Dahlberg, J. (2003). Embedded Computer for Space Applications suitable for Linux. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2085

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dahlberg, Johan. “Embedded Computer for Space Applications suitable for Linux.” 2003. Thesis, Linköping University. Accessed November 12, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2085.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dahlberg, Johan. “Embedded Computer for Space Applications suitable for Linux.” 2003. Web. 12 Nov 2019.

Vancouver:

Dahlberg J. Embedded Computer for Space Applications suitable for Linux. [Internet] [Thesis]. Linköping University; 2003. [cited 2019 Nov 12]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2085.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dahlberg J. Embedded Computer for Space Applications suitable for Linux. [Thesis]. Linköping University; 2003. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2085

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of South Florida

24. Rejimon, Thara. Reliability-centric probabilistic analysis of VLSI circuits.

Degree: 2006, University of South Florida

 Reliability is one of the most serious issues confronted by microelectronics industry as feature sizes scale down from deep submicron to sub-100-nanometer and nanometer regime.… (more)

Subjects/Keywords: Single-event-upsets; Soft errors; Dynamic errors; Error modeling; Bayesian networks; American Studies; Arts and Humanities

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APA (6th Edition):

Rejimon, T. (2006). Reliability-centric probabilistic analysis of VLSI circuits. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/2670

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rejimon, Thara. “Reliability-centric probabilistic analysis of VLSI circuits.” 2006. Thesis, University of South Florida. Accessed November 12, 2019. https://scholarcommons.usf.edu/etd/2670.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rejimon, Thara. “Reliability-centric probabilistic analysis of VLSI circuits.” 2006. Web. 12 Nov 2019.

Vancouver:

Rejimon T. Reliability-centric probabilistic analysis of VLSI circuits. [Internet] [Thesis]. University of South Florida; 2006. [cited 2019 Nov 12]. Available from: https://scholarcommons.usf.edu/etd/2670.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rejimon T. Reliability-centric probabilistic analysis of VLSI circuits. [Thesis]. University of South Florida; 2006. Available from: https://scholarcommons.usf.edu/etd/2670

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

25. Nguyen, Tran Huu Nguyen. Repairing FPGA configuration memory errors using dynamic partial reconfiguration.

Degree: Faculty of Engineering, 2017, University of New South Wales

 The configuration memory of SRAM-based Field-Programmable Gate Arrays (FPGAs) is susceptible to radiation-induced Single Event Upsets (SEUs). This has limited their adoption for space applications… (more)

Subjects/Keywords: Triple modular redundancy; Field programmable gate arrays; Single event upsets; Module-based error recovery; Reliability; Dynamic partial reconfiguration; Reconfiguration control network; Voter scheduling engine (VSE); Variable rate voter checking (VRVC); Genetic algorithm

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APA (6th Edition):

Nguyen, T. H. N. (2017). Repairing FPGA configuration memory errors using dynamic partial reconfiguration. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/58878 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47876/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Nguyen, Tran Huu Nguyen. “Repairing FPGA configuration memory errors using dynamic partial reconfiguration.” 2017. Doctoral Dissertation, University of New South Wales. Accessed November 12, 2019. http://handle.unsw.edu.au/1959.4/58878 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47876/SOURCE02?view=true.

MLA Handbook (7th Edition):

Nguyen, Tran Huu Nguyen. “Repairing FPGA configuration memory errors using dynamic partial reconfiguration.” 2017. Web. 12 Nov 2019.

Vancouver:

Nguyen THN. Repairing FPGA configuration memory errors using dynamic partial reconfiguration. [Internet] [Doctoral dissertation]. University of New South Wales; 2017. [cited 2019 Nov 12]. Available from: http://handle.unsw.edu.au/1959.4/58878 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47876/SOURCE02?view=true.

Council of Science Editors:

Nguyen THN. Repairing FPGA configuration memory errors using dynamic partial reconfiguration. [Doctoral Dissertation]. University of New South Wales; 2017. Available from: http://handle.unsw.edu.au/1959.4/58878 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47876/SOURCE02?view=true


Rice University

26. Zhou, Quming. Reliability-driven circuit optimization and design.

Degree: PhD, Engineering, 2007, Rice University

Single-event upsets (SEUs) induced by high-energy neutrons and alpha particles have emerged as a key reliability threat to advanced commercial electronic components and systems. This… (more)

Subjects/Keywords: Electrical engineering; Applied sciences; Circuit design; Circuit optimization; Low-power; Reliability; Single-event upsets; Soft error

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APA (6th Edition):

Zhou, Q. (2007). Reliability-driven circuit optimization and design. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/103673

Chicago Manual of Style (16th Edition):

Zhou, Quming. “Reliability-driven circuit optimization and design.” 2007. Doctoral Dissertation, Rice University. Accessed November 12, 2019. http://hdl.handle.net/1911/103673.

MLA Handbook (7th Edition):

Zhou, Quming. “Reliability-driven circuit optimization and design.” 2007. Web. 12 Nov 2019.

Vancouver:

Zhou Q. Reliability-driven circuit optimization and design. [Internet] [Doctoral dissertation]. Rice University; 2007. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/1911/103673.

Council of Science Editors:

Zhou Q. Reliability-driven circuit optimization and design. [Doctoral Dissertation]. Rice University; 2007. Available from: http://hdl.handle.net/1911/103673


Vanderbilt University

27. Harrington, Rachel Christine. Models for Characterizing Single-Event Effects in Advanced Technology Circuits.

Degree: PhD, Electrical Engineering, 2019, Vanderbilt University

 At each emerging technology node, characterization of single-event transients and upsets is crucial to accurately predict soft error rates for circuits operating in radiation environments.… (more)

Subjects/Keywords: modeling; single-event transient; single-event upset; single-event effects

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Harrington, R. C. (2019). Models for Characterizing Single-Event Effects in Advanced Technology Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-05152019-100307/ ;

Chicago Manual of Style (16th Edition):

Harrington, Rachel Christine. “Models for Characterizing Single-Event Effects in Advanced Technology Circuits.” 2019. Doctoral Dissertation, Vanderbilt University. Accessed November 12, 2019. http://etd.library.vanderbilt.edu/available/etd-05152019-100307/ ;.

MLA Handbook (7th Edition):

Harrington, Rachel Christine. “Models for Characterizing Single-Event Effects in Advanced Technology Circuits.” 2019. Web. 12 Nov 2019.

Vancouver:

Harrington RC. Models for Characterizing Single-Event Effects in Advanced Technology Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2019. [cited 2019 Nov 12]. Available from: http://etd.library.vanderbilt.edu/available/etd-05152019-100307/ ;.

Council of Science Editors:

Harrington RC. Models for Characterizing Single-Event Effects in Advanced Technology Circuits. [Doctoral Dissertation]. Vanderbilt University; 2019. Available from: http://etd.library.vanderbilt.edu/available/etd-05152019-100307/ ;


Vanderbilt University

28. Narasimham, Balaji. On Chip Characterization of Single Event Transient Pulse Widths.

Degree: MS, Electrical Engineering, 2005, Vanderbilt University

 It is now well known to the radiation effects community that single event effects caused by energetic particles, particularly single event transients, will be among… (more)

Subjects/Keywords: transient pulse width; SET; SEU; single event; CMOS; RHBD; Radiation hardening; Integrated circuits  – Effect of radiation on  – Computer simulation

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APA (6th Edition):

Narasimham, B. (2005). On Chip Characterization of Single Event Transient Pulse Widths. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-11302005-010732/ ;

Chicago Manual of Style (16th Edition):

Narasimham, Balaji. “On Chip Characterization of Single Event Transient Pulse Widths.” 2005. Masters Thesis, Vanderbilt University. Accessed November 12, 2019. http://etd.library.vanderbilt.edu/available/etd-11302005-010732/ ;.

MLA Handbook (7th Edition):

Narasimham, Balaji. “On Chip Characterization of Single Event Transient Pulse Widths.” 2005. Web. 12 Nov 2019.

Vancouver:

Narasimham B. On Chip Characterization of Single Event Transient Pulse Widths. [Internet] [Masters thesis]. Vanderbilt University; 2005. [cited 2019 Nov 12]. Available from: http://etd.library.vanderbilt.edu/available/etd-11302005-010732/ ;.

Council of Science Editors:

Narasimham B. On Chip Characterization of Single Event Transient Pulse Widths. [Masters Thesis]. Vanderbilt University; 2005. Available from: http://etd.library.vanderbilt.edu/available/etd-11302005-010732/ ;


Vanderbilt University

29. Nsengiyumva, Patrick. Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 With technology scaling at 22 nm and beyond, the semiconductor industry has successfully transitioned to 3D multi-gate transistors (i.e., FinFETs) due to the excellent FinFET… (more)

Subjects/Keywords: RHBD; Charge Collection Mechanisms; Integrated Circuit; SEE Simulations; Soft Error Modes; Bulk Technologies; CMOS IC; Angular SEE Mechanisms; Rad-hard; Three-Dimensional Transistor; Multi-Gate Transistor; Planar Technologies; Radiation Effects; Single-Event Upset (SEU); Spatial and Temporal SEE Considerations; SET Pulse Width; Single-Event Transient (SET); FinFET Geometric and Orientation Dependence; FinFET Structure; Single-Event Effects (SEE); FinFET; Digital Circuits; Alpha Particle Data; Upset Cross-Section; Flip-flop; Heavy-Ion Data; TCAD; Advanced Technologies

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APA (6th Edition):

Nsengiyumva, P. (2018). Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03202018-160105/ ;

Chicago Manual of Style (16th Edition):

Nsengiyumva, Patrick. “Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed November 12, 2019. http://etd.library.vanderbilt.edu/available/etd-03202018-160105/ ;.

MLA Handbook (7th Edition):

Nsengiyumva, Patrick. “Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes.” 2018. Web. 12 Nov 2019.

Vancouver:

Nsengiyumva P. Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2019 Nov 12]. Available from: http://etd.library.vanderbilt.edu/available/etd-03202018-160105/ ;.

Council of Science Editors:

Nsengiyumva P. Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-03202018-160105/ ;


Vanderbilt University

30. Vibbert, Daniel Scott. An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes.

Degree: MS, Electrical Engineering, 2018, Vanderbilt University

 An enhancement to an existing radiation hardening by design (RHBD) technique is proposed. The technique, Sensitive Node Active Charge Cancellation (SNACC), protects sensitive A/MS circuit… (more)

Subjects/Keywords: single-event hardening; single-event transients; single-event effects; radiation hardening by design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vibbert, D. S. (2018). An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-08152018-130817/ ;

Chicago Manual of Style (16th Edition):

Vibbert, Daniel Scott. “An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes.” 2018. Masters Thesis, Vanderbilt University. Accessed November 12, 2019. http://etd.library.vanderbilt.edu/available/etd-08152018-130817/ ;.

MLA Handbook (7th Edition):

Vibbert, Daniel Scott. “An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes.” 2018. Web. 12 Nov 2019.

Vancouver:

Vibbert DS. An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes. [Internet] [Masters thesis]. Vanderbilt University; 2018. [cited 2019 Nov 12]. Available from: http://etd.library.vanderbilt.edu/available/etd-08152018-130817/ ;.

Council of Science Editors:

Vibbert DS. An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes. [Masters Thesis]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-08152018-130817/ ;

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