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You searched for subject:(Silvaco ATLAS). Showing records 1 – 6 of 6 total matches.

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1. Jrad, Abdelhak. Elaboration, characterization and design of ZnS thin films for optoelectronic applications : Synthèse et caractérisation de couches minces de sulfure de zinc : applications physiques et simulations numériques.

Degree: Docteur es, Chimie. Surface, Interface, Matériaux fonctionnels, 2017, Sorbonne Paris Cité; Université de Tunis El Manar

Le sulfure de zinc est l'un des premiers semiconducteurs découverts. Il a un grand potentiel d’applications grâces à ses propriétés physicochimiques. Il est intensément utilisé… (more)

Subjects/Keywords: Dépôt chimique en solution; Dopage; Silvaco ATLAS; Chemical Bath Deposition; Doping; Silvaco ATLAS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jrad, A. (2017). Elaboration, characterization and design of ZnS thin films for optoelectronic applications : Synthèse et caractérisation de couches minces de sulfure de zinc : applications physiques et simulations numériques. (Doctoral Dissertation). Sorbonne Paris Cité; Université de Tunis El Manar. Retrieved from http://www.theses.fr/2017USPCC074

Chicago Manual of Style (16th Edition):

Jrad, Abdelhak. “Elaboration, characterization and design of ZnS thin films for optoelectronic applications : Synthèse et caractérisation de couches minces de sulfure de zinc : applications physiques et simulations numériques.” 2017. Doctoral Dissertation, Sorbonne Paris Cité; Université de Tunis El Manar. Accessed October 18, 2019. http://www.theses.fr/2017USPCC074.

MLA Handbook (7th Edition):

Jrad, Abdelhak. “Elaboration, characterization and design of ZnS thin films for optoelectronic applications : Synthèse et caractérisation de couches minces de sulfure de zinc : applications physiques et simulations numériques.” 2017. Web. 18 Oct 2019.

Vancouver:

Jrad A. Elaboration, characterization and design of ZnS thin films for optoelectronic applications : Synthèse et caractérisation de couches minces de sulfure de zinc : applications physiques et simulations numériques. [Internet] [Doctoral dissertation]. Sorbonne Paris Cité; Université de Tunis El Manar; 2017. [cited 2019 Oct 18]. Available from: http://www.theses.fr/2017USPCC074.

Council of Science Editors:

Jrad A. Elaboration, characterization and design of ZnS thin films for optoelectronic applications : Synthèse et caractérisation de couches minces de sulfure de zinc : applications physiques et simulations numériques. [Doctoral Dissertation]. Sorbonne Paris Cité; Université de Tunis El Manar; 2017. Available from: http://www.theses.fr/2017USPCC074


University of Toledo

2. Jogi, Sreeram. Modelling of GaN Power Switches.

Degree: MS, Electrical Engineering, 2015, University of Toledo

 .The main goal of this work was to develop the necessary expertise and model various parameters and characteristics of gallium nitride power HEMT (High Electron… (more)

Subjects/Keywords: Electrical Engineering; AlGaN-GaN Modelling; Silvaco Atlas; HEMT

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APA (6th Edition):

Jogi, S. (2015). Modelling of GaN Power Switches. (Masters Thesis). University of Toledo. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=toledo1431717800

Chicago Manual of Style (16th Edition):

Jogi, Sreeram. “Modelling of GaN Power Switches.” 2015. Masters Thesis, University of Toledo. Accessed October 18, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1431717800.

MLA Handbook (7th Edition):

Jogi, Sreeram. “Modelling of GaN Power Switches.” 2015. Web. 18 Oct 2019.

Vancouver:

Jogi S. Modelling of GaN Power Switches. [Internet] [Masters thesis]. University of Toledo; 2015. [cited 2019 Oct 18]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=toledo1431717800.

Council of Science Editors:

Jogi S. Modelling of GaN Power Switches. [Masters Thesis]. University of Toledo; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=toledo1431717800


Arizona State University

3. Warren, Andrew. Simulation of GaN CAVETs in Silvaco Atlas.

Degree: Electrical Engineering, 2019, Arizona State University

Subjects/Keywords: Electrical engineering; Atlas; CAVET; GaN; Silvaco; Simulation

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APA (6th Edition):

Warren, A. (2019). Simulation of GaN CAVETs in Silvaco Atlas. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/53600

Chicago Manual of Style (16th Edition):

Warren, Andrew. “Simulation of GaN CAVETs in Silvaco Atlas.” 2019. Masters Thesis, Arizona State University. Accessed October 18, 2019. http://repository.asu.edu/items/53600.

MLA Handbook (7th Edition):

Warren, Andrew. “Simulation of GaN CAVETs in Silvaco Atlas.” 2019. Web. 18 Oct 2019.

Vancouver:

Warren A. Simulation of GaN CAVETs in Silvaco Atlas. [Internet] [Masters thesis]. Arizona State University; 2019. [cited 2019 Oct 18]. Available from: http://repository.asu.edu/items/53600.

Council of Science Editors:

Warren A. Simulation of GaN CAVETs in Silvaco Atlas. [Masters Thesis]. Arizona State University; 2019. Available from: http://repository.asu.edu/items/53600


Rochester Institute of Technology

4. Aguinaldo, Ryan. Modeling solutions and simulations for advanced III-V photovoltaics based on nanostructures.

Degree: Center for Materials Science and Engineering, 2008, Rochester Institute of Technology

 It is the purpose of the work to develop methods for and present on the computational analyses of advanced III-V photovoltaic devices and their enhancement… (more)

Subjects/Keywords: Detailed balance; Intermediate band solar Cell; Photovoltaics; Quantum dots; Silvaco ATLAS; Solar cells

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APA (6th Edition):

Aguinaldo, R. (2008). Modeling solutions and simulations for advanced III-V photovoltaics based on nanostructures. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/2756

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aguinaldo, Ryan. “Modeling solutions and simulations for advanced III-V photovoltaics based on nanostructures.” 2008. Thesis, Rochester Institute of Technology. Accessed October 18, 2019. https://scholarworks.rit.edu/theses/2756.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aguinaldo, Ryan. “Modeling solutions and simulations for advanced III-V photovoltaics based on nanostructures.” 2008. Web. 18 Oct 2019.

Vancouver:

Aguinaldo R. Modeling solutions and simulations for advanced III-V photovoltaics based on nanostructures. [Internet] [Thesis]. Rochester Institute of Technology; 2008. [cited 2019 Oct 18]. Available from: https://scholarworks.rit.edu/theses/2756.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aguinaldo R. Modeling solutions and simulations for advanced III-V photovoltaics based on nanostructures. [Thesis]. Rochester Institute of Technology; 2008. Available from: https://scholarworks.rit.edu/theses/2756

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

5. Pandit, Vedhas. Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology.

Degree: MS, Electrical Engineering, 2010, Arizona State University

 The thesis focuses on cost-efficient integration of the electro-chemical residue sensor (ECRS), a novel sensor developed for the in situ and real-time measurement of the… (more)

Subjects/Keywords: Electrical Engineering; amorphous silicon TFT; cost effective integration; device simulation modeling; in situ contamination measurement; silvaco atlas deckbuild; SOI device design fabrication

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pandit, V. (2010). Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/8800

Chicago Manual of Style (16th Edition):

Pandit, Vedhas. “Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology.” 2010. Masters Thesis, Arizona State University. Accessed October 18, 2019. http://repository.asu.edu/items/8800.

MLA Handbook (7th Edition):

Pandit, Vedhas. “Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology.” 2010. Web. 18 Oct 2019.

Vancouver:

Pandit V. Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology. [Internet] [Masters thesis]. Arizona State University; 2010. [cited 2019 Oct 18]. Available from: http://repository.asu.edu/items/8800.

Council of Science Editors:

Pandit V. Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology. [Masters Thesis]. Arizona State University; 2010. Available from: http://repository.asu.edu/items/8800


Brigham Young University

6. Cho, Hanho. Optically Powered Logic Transistor.

Degree: MS, 2008, Brigham Young University

 This thesis presents the modeling and fabrication of a new solid-state device meant to be used for digital logic circuits. Most current logic circuits are… (more)

Subjects/Keywords: MOSFET; PIN photodiode; silvaco; atlas; NAND; NOR; CMOS; etching; silicon; fabrication; circuit; photolithography; nMOS; pMOS; doping; optical; transistor; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cho, H. (2008). Optically Powered Logic Transistor. (Masters Thesis). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=2478&context=etd

Chicago Manual of Style (16th Edition):

Cho, Hanho. “Optically Powered Logic Transistor.” 2008. Masters Thesis, Brigham Young University. Accessed October 18, 2019. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=2478&context=etd.

MLA Handbook (7th Edition):

Cho, Hanho. “Optically Powered Logic Transistor.” 2008. Web. 18 Oct 2019.

Vancouver:

Cho H. Optically Powered Logic Transistor. [Internet] [Masters thesis]. Brigham Young University; 2008. [cited 2019 Oct 18]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=2478&context=etd.

Council of Science Editors:

Cho H. Optically Powered Logic Transistor. [Masters Thesis]. Brigham Young University; 2008. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=2478&context=etd

.