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You searched for subject:(Silent data corruption). Showing records 1 – 9 of 9 total matches.

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University of California – Riverside

1. Wu, Panruo. Silent Data Corruption Resilient Matrix Factorizations on Distributed Memory System.

Degree: Computer Science, 2016, University of California – Riverside

 The lack of efficient resilience solutions is expected to be a major problem for the coming exascale supercomputers, as the chance that a long running… (more)

Subjects/Keywords: Computer science; algorithm based fault tolerance; matrix factorization; parallel computing; scalapack; silent data corruption

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APA (6th Edition):

Wu, P. (2016). Silent Data Corruption Resilient Matrix Factorizations on Distributed Memory System. (Thesis). University of California – Riverside. Retrieved from http://www.escholarship.org/uc/item/22262301

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Panruo. “Silent Data Corruption Resilient Matrix Factorizations on Distributed Memory System.” 2016. Thesis, University of California – Riverside. Accessed March 02, 2021. http://www.escholarship.org/uc/item/22262301.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Panruo. “Silent Data Corruption Resilient Matrix Factorizations on Distributed Memory System.” 2016. Web. 02 Mar 2021.

Vancouver:

Wu P. Silent Data Corruption Resilient Matrix Factorizations on Distributed Memory System. [Internet] [Thesis]. University of California – Riverside; 2016. [cited 2021 Mar 02]. Available from: http://www.escholarship.org/uc/item/22262301.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu P. Silent Data Corruption Resilient Matrix Factorizations on Distributed Memory System. [Thesis]. University of California – Riverside; 2016. Available from: http://www.escholarship.org/uc/item/22262301

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

2. Chen, Chao. Compiler-Assisted Resilience Framework for Recovery from Transient Faults.

Degree: PhD, Computer Science, 2020, Georgia Tech

 Due to system scaling trends toward smaller transistor size, higher circuit density and the use of near-threshold voltage (NTV) techniques, transient hardware faults introduced by… (more)

Subjects/Keywords: Resilience; Compiler; HPC; High Performance Computing; Fault Tolerance; SDC; Silent Data Corruption; Transient Hardware Fault; Transient Fault; Soft Failure; Crash; Failure

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APA (6th Edition):

Chen, C. (2020). Compiler-Assisted Resilience Framework for Recovery from Transient Faults. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64214

Chicago Manual of Style (16th Edition):

Chen, Chao. “Compiler-Assisted Resilience Framework for Recovery from Transient Faults.” 2020. Doctoral Dissertation, Georgia Tech. Accessed March 02, 2021. http://hdl.handle.net/1853/64214.

MLA Handbook (7th Edition):

Chen, Chao. “Compiler-Assisted Resilience Framework for Recovery from Transient Faults.” 2020. Web. 02 Mar 2021.

Vancouver:

Chen C. Compiler-Assisted Resilience Framework for Recovery from Transient Faults. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1853/64214.

Council of Science Editors:

Chen C. Compiler-Assisted Resilience Framework for Recovery from Transient Faults. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64214

3. Moussa, Mohamad. Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption .

Degree: 2018, University of Arizona

 An error correcting code is a technique of adding extra information to a message such that it can be recovered even when some of its… (more)

Subjects/Keywords: erasure codes; error correcting codes; fault tolerance; RAID 6; reed solomon code; silent data corruption

…drives are in good conditions, what is called silent data corruption. This data corruption… …P 0 Q 6= Q0 Data drive corruption P 6= P 0 Q 6= Q0 (1.13) Finally, after the… …8 LIST OF TABLES 3.1 3.2 3.3 3.4 3.5 3 drives, one data and 2 parity at location k… …Systems of equations for recovery from a failure of 3 drives, two data and 1 parity at location… …are data errors and 1 is a parity error. The listing of conditions on the syndromes sj and… 

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APA (6th Edition):

Moussa, M. (2018). Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/631302

Chicago Manual of Style (16th Edition):

Moussa, Mohamad. “Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption .” 2018. Doctoral Dissertation, University of Arizona. Accessed March 02, 2021. http://hdl.handle.net/10150/631302.

MLA Handbook (7th Edition):

Moussa, Mohamad. “Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption .” 2018. Web. 02 Mar 2021.

Vancouver:

Moussa M. Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption . [Internet] [Doctoral dissertation]. University of Arizona; 2018. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10150/631302.

Council of Science Editors:

Moussa M. Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption . [Doctoral Dissertation]. University of Arizona; 2018. Available from: http://hdl.handle.net/10150/631302


Arizona State University

4. Lokam, Sai Ram Dheeraj. InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes.

Degree: Computer Science, 2016, Arizona State University

Subjects/Keywords: Computer engineering; Computer science; Electrical engineering; Algorithms; Checkpointing; Recovery; Reliability; Silent Data Corruption; Soft-Errors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lokam, S. R. D. (2016). InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/40720

Chicago Manual of Style (16th Edition):

Lokam, Sai Ram Dheeraj. “InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes.” 2016. Masters Thesis, Arizona State University. Accessed March 02, 2021. http://repository.asu.edu/items/40720.

MLA Handbook (7th Edition):

Lokam, Sai Ram Dheeraj. “InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes.” 2016. Web. 02 Mar 2021.

Vancouver:

Lokam SRD. InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes. [Internet] [Masters thesis]. Arizona State University; 2016. [cited 2021 Mar 02]. Available from: http://repository.asu.edu/items/40720.

Council of Science Editors:

Lokam SRD. InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes. [Masters Thesis]. Arizona State University; 2016. Available from: http://repository.asu.edu/items/40720


Arizona State University

5. Didehban, Moslem. Software Techniques For Dependable Execution.

Degree: Computer Engineering, 2018, Arizona State University

Subjects/Keywords: Computer engineering; Computer science; Compiler transfromation; Instruction Duplication; Redundancy; Reliability; Silent Data Corruption; Soft Error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Didehban, M. (2018). Software Techniques For Dependable Execution. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/51604

Chicago Manual of Style (16th Edition):

Didehban, Moslem. “Software Techniques For Dependable Execution.” 2018. Doctoral Dissertation, Arizona State University. Accessed March 02, 2021. http://repository.asu.edu/items/51604.

MLA Handbook (7th Edition):

Didehban, Moslem. “Software Techniques For Dependable Execution.” 2018. Web. 02 Mar 2021.

Vancouver:

Didehban M. Software Techniques For Dependable Execution. [Internet] [Doctoral dissertation]. Arizona State University; 2018. [cited 2021 Mar 02]. Available from: http://repository.asu.edu/items/51604.

Council of Science Editors:

Didehban M. Software Techniques For Dependable Execution. [Doctoral Dissertation]. Arizona State University; 2018. Available from: http://repository.asu.edu/items/51604

6. Ni, Xiang. Mitigation of failures in high performance computing via runtime techniques.

Degree: PhD, Computer Science, 2016, University of Illinois – Urbana-Champaign

 As machines increase in scale, it is predicted that failure rates of supercomputers will correspondingly increase. Even though the mean time to failure (MTTF) of… (more)

Subjects/Keywords: runtime system; fault tolerance; silent data corruption; hard error; soft error; solid state disk; high performance computing

…energy particle strikes. For example, silent data corruption (SDC) may occur due to… …insidious form of soft error is silent data corruption (SDC) [2]. For mission… …utilization and vulnerability to fail-stop failures and silent data corruptions with different sizes… …protect applications from silent data corruptions. In Figure 1.2, we model the system… …help protect applications from silent data corruptions. Thesis statement: We explore the… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ni, X. (2016). Mitigation of failures in high performance computing via runtime techniques. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/92798

Chicago Manual of Style (16th Edition):

Ni, Xiang. “Mitigation of failures in high performance computing via runtime techniques.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/92798.

MLA Handbook (7th Edition):

Ni, Xiang. “Mitigation of failures in high performance computing via runtime techniques.” 2016. Web. 02 Mar 2021.

Vancouver:

Ni X. Mitigation of failures in high performance computing via runtime techniques. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/92798.

Council of Science Editors:

Ni X. Mitigation of failures in high performance computing via runtime techniques. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/92798

7. Calhoun, Jon Cameron. From detection to optimization: impact of soft errors on high-performance computing applications.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

 As high-performance computing (HPC) continues to progress, constraints on HPC system design forces the handling of errors to higher levels in the software stack. Of… (more)

Subjects/Keywords: High-performance computing; Fault tolerance; Silent data corruption; Soft errors; Error detection; Error recovery; Fault injection; Error propagation; Lossy compression; Checkpoint-restart

…soft error that is propagated to other components and can lead to silent data corruption… …is important for AMG and other sparse, linear solvers. To motivate the need for silent data… …that an error has occurred. The other possible results from faults lead to silent data… …Average corruption in selected variables on rank 3 for Jacobi within 90% confidence… …Average corruption in selected variables on rank 3 for HPCCG within 90% confidence… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Calhoun, J. C. (2017). From detection to optimization: impact of soft errors on high-performance computing applications. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98379

Chicago Manual of Style (16th Edition):

Calhoun, Jon Cameron. “From detection to optimization: impact of soft errors on high-performance computing applications.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/98379.

MLA Handbook (7th Edition):

Calhoun, Jon Cameron. “From detection to optimization: impact of soft errors on high-performance computing applications.” 2017. Web. 02 Mar 2021.

Vancouver:

Calhoun JC. From detection to optimization: impact of soft errors on high-performance computing applications. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/98379.

Council of Science Editors:

Calhoun JC. From detection to optimization: impact of soft errors on high-performance computing applications. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98379

8. Campbell, Keith A. Low-cost error detection through high-level synthesis.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a… (more)

Subjects/Keywords: High-level synthesis; Automation; error detection; scheduling; binding; compiler transformation; compiler optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath, control logic; shadow logic; low cost; high performance; electrical bugs; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback; recovery; post-silicon validation; Accelerators; system on a chip; signature generation; execution signatures; execution hashing; logic bugs; nondeterministic bugs; masked errors; circuit reliability; hot spots; wear out; silent data corruption; observability; detection latency; mixed datapath; diversity; checkpoint corruption; error injection; error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); hybrid hardware/software; execution tracing; address conversion; undefined behavior; High-Level Synthesis (HLS) engine bugs; detection coverage

…elements, there can be a third “limbo” state known as silent data corruption. In this state, the… …stored in memory indefinitely, there is no limit to how long silent data corruption can last… …logic bug is a memory copy operation for input data that simultaneously (for faster… …elements may be read and outputted, in which case the error becomes unmasked. Since data can be… …coverage with minimum checker allocation; 2. Support for mixed arithmetic/non-arithmetic data… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2015). Low-cost error detection through high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Web. 02 Mar 2021.

Vancouver:

Campbell KA. Low-cost error detection through high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Campbell KA. Low-cost error detection through high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…languages SDC Silent Data Corruption SEC Statistical Error Compensation SEMU Single Event… …silent data corruption. In this state, the error has changed the internal behavior of the… …limit to how long silent data corruption can last. While unmasked errors are clearly the most… …deluge of data from an RTL-level value change dump. In Chapter 6, we propose the insertion of… …logic bug is a memory copy operation for input data that simultaneously (for faster… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 02 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

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