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You searched for subject:(Signal Integrity). Showing records 1 – 30 of 77 total matches.

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University of Cincinnati

1. ARUMUGAM, THIAGARAJAN. A heuristic approach for Capacitive Crosstalk Avoidance during Post Global Routing Crosstalk Synthesis for Deep Submicron Technologies.

Degree: MS, Engineering : Computer Engineering, 2008, University of Cincinnati

 With decreasing feature sizes, higher clock rates and increasing interconnect densities, crosstalk has become a major concern in Integrated Circuit (IC) design [1]. Crosstalk optimization… (more)

Subjects/Keywords: Crosstalk; Global Routing; Signal Integrity

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

ARUMUGAM, T. (2008). A heuristic approach for Capacitive Crosstalk Avoidance during Post Global Routing Crosstalk Synthesis for Deep Submicron Technologies. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1204214738

Chicago Manual of Style (16th Edition):

ARUMUGAM, THIAGARAJAN. “A heuristic approach for Capacitive Crosstalk Avoidance during Post Global Routing Crosstalk Synthesis for Deep Submicron Technologies.” 2008. Masters Thesis, University of Cincinnati. Accessed November 18, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1204214738.

MLA Handbook (7th Edition):

ARUMUGAM, THIAGARAJAN. “A heuristic approach for Capacitive Crosstalk Avoidance during Post Global Routing Crosstalk Synthesis for Deep Submicron Technologies.” 2008. Web. 18 Nov 2019.

Vancouver:

ARUMUGAM T. A heuristic approach for Capacitive Crosstalk Avoidance during Post Global Routing Crosstalk Synthesis for Deep Submicron Technologies. [Internet] [Masters thesis]. University of Cincinnati; 2008. [cited 2019 Nov 18]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1204214738.

Council of Science Editors:

ARUMUGAM T. A heuristic approach for Capacitive Crosstalk Avoidance during Post Global Routing Crosstalk Synthesis for Deep Submicron Technologies. [Masters Thesis]. University of Cincinnati; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1204214738


NSYSU

2. Huang, Sheng-Hua. Enhanced Signal and Power Integrity Using Open-Stub Structure.

Degree: Master, Electrical Engineering, 2014, NSYSU

 With the advance of IC manufacture process, operating speed of the circuit systems gets higher, so does the demand for data communication. This phenomenon will… (more)

Subjects/Keywords: open-stubs; signal integrity; power integrity; passive equalizer; electromagnetic band-gap

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APA (6th Edition):

Huang, S. (2014). Enhanced Signal and Power Integrity Using Open-Stub Structure. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706114-144044

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Sheng-Hua. “Enhanced Signal and Power Integrity Using Open-Stub Structure.” 2014. Thesis, NSYSU. Accessed November 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706114-144044.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Sheng-Hua. “Enhanced Signal and Power Integrity Using Open-Stub Structure.” 2014. Web. 18 Nov 2019.

Vancouver:

Huang S. Enhanced Signal and Power Integrity Using Open-Stub Structure. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Nov 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706114-144044.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang S. Enhanced Signal and Power Integrity Using Open-Stub Structure. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706114-144044

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

3. Peng, Yarui. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher device density without needs for technology scaling. However, designing reliable 3D IC… (more)

Subjects/Keywords: 3D IC; CAD; Methodology; Reliable; Power integrity; Signal integrity

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APA (6th Edition):

Peng, Y. (2016). CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56330

Chicago Manual of Style (16th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Doctoral Dissertation, Georgia Tech. Accessed November 18, 2019. http://hdl.handle.net/1853/56330.

MLA Handbook (7th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Web. 18 Nov 2019.

Vancouver:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/1853/56330.

Council of Science Editors:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56330


Georgia Tech

4. Zhang, David Chong. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 A power distribution network (PDN) is designed to provide clean power and facilitate high signal integrity in modern electronic systems. However, the design of a… (more)

Subjects/Keywords: Power delivery network; Power transmission line; Signal integrity; Power integrity; Return path discontinuity

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APA (6th Edition):

Zhang, D. C. (2016). Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56282

Chicago Manual of Style (16th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed November 18, 2019. http://hdl.handle.net/1853/56282.

MLA Handbook (7th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Web. 18 Nov 2019.

Vancouver:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/1853/56282.

Council of Science Editors:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56282


University of Hong Kong

5. Lei, Chi-un. VLSI macromodeling and signal integrity analysis via digital signal processing techniques.

Degree: PhD, 2011, University of Hong Kong

published_or_final_version

Electrical and Electronic Engineering

Doctoral

Doctor of Philosophy

Advisors/Committee Members: Wong, N, Ng, TS.

Subjects/Keywords: Signal processing - Digital techniques.; Integrated circuits - Very large scale integration - Mathematicalmodels.; Signal integrity (Electronics)

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APA (6th Edition):

Lei, C. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Doctoral Dissertation). University of Hong Kong. Retrieved from Lei, C. [李志遠]. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4570058 ; http://dx.doi.org/10.5353/th_b4570058 ; http://hdl.handle.net/10722/133220

Chicago Manual of Style (16th Edition):

Lei, Chi-un. “VLSI macromodeling and signal integrity analysis via digital signal processing techniques.” 2011. Doctoral Dissertation, University of Hong Kong. Accessed November 18, 2019. Lei, C. [李志遠]. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4570058 ; http://dx.doi.org/10.5353/th_b4570058 ; http://hdl.handle.net/10722/133220.

MLA Handbook (7th Edition):

Lei, Chi-un. “VLSI macromodeling and signal integrity analysis via digital signal processing techniques.” 2011. Web. 18 Nov 2019.

Vancouver:

Lei C. VLSI macromodeling and signal integrity analysis via digital signal processing techniques. [Internet] [Doctoral dissertation]. University of Hong Kong; 2011. [cited 2019 Nov 18]. Available from: Lei, C. [李志遠]. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4570058 ; http://dx.doi.org/10.5353/th_b4570058 ; http://hdl.handle.net/10722/133220.

Council of Science Editors:

Lei C. VLSI macromodeling and signal integrity analysis via digital signal processing techniques. [Doctoral Dissertation]. University of Hong Kong; 2011. Available from: Lei, C. [李志遠]. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4570058 ; http://dx.doi.org/10.5353/th_b4570058 ; http://hdl.handle.net/10722/133220


NSYSU

6. Su, Bo-Yin. Signal Integrity Analysis of a Hybrid Advanced Packaging Technology for 100Gbps Serdes Applications.

Degree: Master, Electrical Engineering, 2017, NSYSU

 The rapid development of high-speed digital circuits leads to high complexity of layout design and the accompanying signal integrity problems, and presents a very serious… (more)

Subjects/Keywords: Differential Signal; Discontinuity; Fan-Out Wafer Level Package; SERDES Interface; Signal Integrity

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APA (6th Edition):

Su, B. (2017). Signal Integrity Analysis of a Hybrid Advanced Packaging Technology for 100Gbps Serdes Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615117-230950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Su, Bo-Yin. “Signal Integrity Analysis of a Hybrid Advanced Packaging Technology for 100Gbps Serdes Applications.” 2017. Thesis, NSYSU. Accessed November 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615117-230950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Su, Bo-Yin. “Signal Integrity Analysis of a Hybrid Advanced Packaging Technology for 100Gbps Serdes Applications.” 2017. Web. 18 Nov 2019.

Vancouver:

Su B. Signal Integrity Analysis of a Hybrid Advanced Packaging Technology for 100Gbps Serdes Applications. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Nov 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615117-230950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Su B. Signal Integrity Analysis of a Hybrid Advanced Packaging Technology for 100Gbps Serdes Applications. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615117-230950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ITESO – Universidad Jesuita de Guadalajara

7. Robledo-Mariscal, Juan A. Frequency domain optimization based methodology to accelerate high speed digital interconnect design .

Degree: 2017, ITESO – Universidad Jesuita de Guadalajara

Subjects/Keywords: Optimization Methodologies; Signal Integrity

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APA (6th Edition):

Robledo-Mariscal, J. A. (2017). Frequency domain optimization based methodology to accelerate high speed digital interconnect design . (Thesis). ITESO – Universidad Jesuita de Guadalajara. Retrieved from http://hdl.handle.net/11117/4371

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Robledo-Mariscal, Juan A. “Frequency domain optimization based methodology to accelerate high speed digital interconnect design .” 2017. Thesis, ITESO – Universidad Jesuita de Guadalajara. Accessed November 18, 2019. http://hdl.handle.net/11117/4371.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Robledo-Mariscal, Juan A. “Frequency domain optimization based methodology to accelerate high speed digital interconnect design .” 2017. Web. 18 Nov 2019.

Vancouver:

Robledo-Mariscal JA. Frequency domain optimization based methodology to accelerate high speed digital interconnect design . [Internet] [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2017. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/11117/4371.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Robledo-Mariscal JA. Frequency domain optimization based methodology to accelerate high speed digital interconnect design . [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2017. Available from: http://hdl.handle.net/11117/4371

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Tai, Cheng-Han. Stub Alternated Microstrip Lines with Crosstalk Suppression for DDR System.

Degree: Master, Electrical Engineering, 2017, NSYSU

 For the past few years, the single-ended transmission line is still not entirely replaced by differential transmission line in the high speed circuit. Double Data… (more)

Subjects/Keywords: Stub alternated; Equivalent circuit; Crosstalk; Signal Integrity; Eye diagram

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APA (6th Edition):

Tai, C. (2017). Stub Alternated Microstrip Lines with Crosstalk Suppression for DDR System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628117-165615

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tai, Cheng-Han. “Stub Alternated Microstrip Lines with Crosstalk Suppression for DDR System.” 2017. Thesis, NSYSU. Accessed November 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628117-165615.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tai, Cheng-Han. “Stub Alternated Microstrip Lines with Crosstalk Suppression for DDR System.” 2017. Web. 18 Nov 2019.

Vancouver:

Tai C. Stub Alternated Microstrip Lines with Crosstalk Suppression for DDR System. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Nov 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628117-165615.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tai C. Stub Alternated Microstrip Lines with Crosstalk Suppression for DDR System. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628117-165615

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

9. Petroli, Lorenzo. Avaliação de um modelo para integridade de sinais em circuitos eletrônicos complexos.

Degree: 2012, Universidade do Rio Grande do Sul

Uma das características mais marcantes das gerações atuais é a necessidade por armazenar e acessar cada vez mais informação em dispositivos cada vez menores. O… (more)

Subjects/Keywords: Microeletrônica; Signal integrity; Processamento : Sinais; Electromagnetic interference; Transmission lines; RLCG model

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APA (6th Edition):

Petroli, L. (2012). Avaliação de um modelo para integridade de sinais em circuitos eletrônicos complexos. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/67847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Petroli, Lorenzo. “Avaliação de um modelo para integridade de sinais em circuitos eletrônicos complexos.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed November 18, 2019. http://hdl.handle.net/10183/67847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Petroli, Lorenzo. “Avaliação de um modelo para integridade de sinais em circuitos eletrônicos complexos.” 2012. Web. 18 Nov 2019.

Vancouver:

Petroli L. Avaliação de um modelo para integridade de sinais em circuitos eletrônicos complexos. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/10183/67847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Petroli L. Avaliação de um modelo para integridade de sinais em circuitos eletrônicos complexos. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/67847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Li, Chien-Jung. Research on Digitally Predistorted Power Amplifier and Injection-Pulled Oscillator for Wireless Communication System.

Degree: PhD, Electrical Engineering, 2009, NSYSU

 In a wireless communication system, the RF signal integrity is often deteriorated by power amplifier (PA) nonlinearity and local oscillator (LO) pulling. This dissertation attempts… (more)

Subjects/Keywords: highly efficient linear transmitter; sensing circuit; RF signal integrity

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APA (6th Edition):

Li, C. (2009). Research on Digitally Predistorted Power Amplifier and Injection-Pulled Oscillator for Wireless Communication System. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726109-131218

Chicago Manual of Style (16th Edition):

Li, Chien-Jung. “Research on Digitally Predistorted Power Amplifier and Injection-Pulled Oscillator for Wireless Communication System.” 2009. Doctoral Dissertation, NSYSU. Accessed November 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726109-131218.

MLA Handbook (7th Edition):

Li, Chien-Jung. “Research on Digitally Predistorted Power Amplifier and Injection-Pulled Oscillator for Wireless Communication System.” 2009. Web. 18 Nov 2019.

Vancouver:

Li C. Research on Digitally Predistorted Power Amplifier and Injection-Pulled Oscillator for Wireless Communication System. [Internet] [Doctoral dissertation]. NSYSU; 2009. [cited 2019 Nov 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726109-131218.

Council of Science Editors:

Li C. Research on Digitally Predistorted Power Amplifier and Injection-Pulled Oscillator for Wireless Communication System. [Doctoral Dissertation]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726109-131218


NSYSU

11. Wu, Po-I. A Study on Signal Integrity of Fine Lines in Package Substrate.

Degree: Master, Electrical Engineering, 2015, NSYSU

 With the advance of IC manufacturing process, the density of circuit gets higher year by year. In order to increase the amount of transmitted information… (more)

Subjects/Keywords: Common mode noise; Signal integrity; Roughness; Passive equalizer; Differential pair

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APA (6th Edition):

Wu, P. (2015). A Study on Signal Integrity of Fine Lines in Package Substrate. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726115-155146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Po-I. “A Study on Signal Integrity of Fine Lines in Package Substrate.” 2015. Thesis, NSYSU. Accessed November 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726115-155146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Po-I. “A Study on Signal Integrity of Fine Lines in Package Substrate.” 2015. Web. 18 Nov 2019.

Vancouver:

Wu P. A Study on Signal Integrity of Fine Lines in Package Substrate. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Nov 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726115-155146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu P. A Study on Signal Integrity of Fine Lines in Package Substrate. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726115-155146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rutgers University

12. Raman, Chandrasekharan. Relaying and scheduling in interference limited wireless networks.

Degree: PhD, Electrical and Computer Engineering, 2010, Rutgers University

In this dissertation, we address two issues related to communication in interference-limited wireless networks. In the first part of the thesis, we study benefits of… (more)

Subjects/Keywords: Wireless communication systems; Computer scheduling; Signal integrity (Electronics)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Raman, C. (2010). Relaying and scheduling in interference limited wireless networks. (Doctoral Dissertation). Rutgers University. Retrieved from http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000053152

Chicago Manual of Style (16th Edition):

Raman, Chandrasekharan. “Relaying and scheduling in interference limited wireless networks.” 2010. Doctoral Dissertation, Rutgers University. Accessed November 18, 2019. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000053152.

MLA Handbook (7th Edition):

Raman, Chandrasekharan. “Relaying and scheduling in interference limited wireless networks.” 2010. Web. 18 Nov 2019.

Vancouver:

Raman C. Relaying and scheduling in interference limited wireless networks. [Internet] [Doctoral dissertation]. Rutgers University; 2010. [cited 2019 Nov 18]. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000053152.

Council of Science Editors:

Raman C. Relaying and scheduling in interference limited wireless networks. [Doctoral Dissertation]. Rutgers University; 2010. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000053152


Rutgers University

13. Baid, Akash, 1987-. Multi-radio interference diagnosis in unlicensed bands using passive monitoring.

Degree: MS, Electrical and Computer Engineering, 2011, Rutgers University

 The increasing density and data rate of unlicensed band wireless devices has led to significant inter- and intra-radio interference problems. Multiple competing standards such as… (more)

Subjects/Keywords: Wireless communication systems; Signal integrity (Electronics); Radio – Interference

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APA (6th Edition):

Baid, Akash, 1. (2011). Multi-radio interference diagnosis in unlicensed bands using passive monitoring. (Masters Thesis). Rutgers University. Retrieved from http://hdl.rutgers.edu/1782.1/rucore10001600001.ETD.000060983

Chicago Manual of Style (16th Edition):

Baid, Akash, 1987-. “Multi-radio interference diagnosis in unlicensed bands using passive monitoring.” 2011. Masters Thesis, Rutgers University. Accessed November 18, 2019. http://hdl.rutgers.edu/1782.1/rucore10001600001.ETD.000060983.

MLA Handbook (7th Edition):

Baid, Akash, 1987-. “Multi-radio interference diagnosis in unlicensed bands using passive monitoring.” 2011. Web. 18 Nov 2019.

Vancouver:

Baid, Akash 1. Multi-radio interference diagnosis in unlicensed bands using passive monitoring. [Internet] [Masters thesis]. Rutgers University; 2011. [cited 2019 Nov 18]. Available from: http://hdl.rutgers.edu/1782.1/rucore10001600001.ETD.000060983.

Council of Science Editors:

Baid, Akash 1. Multi-radio interference diagnosis in unlicensed bands using passive monitoring. [Masters Thesis]. Rutgers University; 2011. Available from: http://hdl.rutgers.edu/1782.1/rucore10001600001.ETD.000060983


University of Illinois – Urbana-Champaign

14. Rajwardan, Ashwarya. Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology.

Degree: MS, Electrical & Computer Engr, 2019, University of Illinois – Urbana-Champaign

 This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented:… (more)

Subjects/Keywords: DFE; CTLE; Equalizer; Signal Integrity; High-speed serial link

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APA (6th Edition):

Rajwardan, A. (2019). Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104803

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rajwardan, Ashwarya. “Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology.” 2019. Thesis, University of Illinois – Urbana-Champaign. Accessed November 18, 2019. http://hdl.handle.net/2142/104803.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rajwardan, Ashwarya. “Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology.” 2019. Web. 18 Nov 2019.

Vancouver:

Rajwardan A. Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2019. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/2142/104803.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rajwardan A. Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology. [Thesis]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104803

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

15. Lee, Kil-Hoon. Design of signal integrity enhancement circuits.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 This dissertation is aimed at examining signal integrity degradation factors and realizing signal integrity enhancement circuits for both wired and wireless communication systems. For wired… (more)

Subjects/Keywords: Full-duplex system; Transmitter leakage cancellation; CMOS; Signal integrity; Optical coherent detection; Feedforward equalizer; Electronic dispersion compensator; Transmitter leakage; Wireless communication systems; Signal processing; Signal integrity (Electronics)

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APA (6th Edition):

Lee, K. (2010). Design of signal integrity enhancement circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37191

Chicago Manual of Style (16th Edition):

Lee, Kil-Hoon. “Design of signal integrity enhancement circuits.” 2010. Doctoral Dissertation, Georgia Tech. Accessed November 18, 2019. http://hdl.handle.net/1853/37191.

MLA Handbook (7th Edition):

Lee, Kil-Hoon. “Design of signal integrity enhancement circuits.” 2010. Web. 18 Nov 2019.

Vancouver:

Lee K. Design of signal integrity enhancement circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/1853/37191.

Council of Science Editors:

Lee K. Design of signal integrity enhancement circuits. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37191


University of Washington

16. Huang, Shaowu. Broadband Green's Function and Applications to Fast Electromagnetic Analysis of High-Speed Interconnects.

Degree: PhD, 2015, University of Washington

 This dissertation is focused on research and development of an innovative Broadband Green’s Function method and the applications to fast electromagnetic modeling and simulations of… (more)

Subjects/Keywords: broadband Green's function; electromagnetic compatibility; high-speed interconnect; power integrity; printed circuit board; signal integrity; Electrical engineering; Electromagnetics; engineering

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APA (6th Edition):

Huang, S. (2015). Broadband Green's Function and Applications to Fast Electromagnetic Analysis of High-Speed Interconnects. (Doctoral Dissertation). University of Washington. Retrieved from http://hdl.handle.net/1773/33464

Chicago Manual of Style (16th Edition):

Huang, Shaowu. “Broadband Green's Function and Applications to Fast Electromagnetic Analysis of High-Speed Interconnects.” 2015. Doctoral Dissertation, University of Washington. Accessed November 18, 2019. http://hdl.handle.net/1773/33464.

MLA Handbook (7th Edition):

Huang, Shaowu. “Broadband Green's Function and Applications to Fast Electromagnetic Analysis of High-Speed Interconnects.” 2015. Web. 18 Nov 2019.

Vancouver:

Huang S. Broadband Green's Function and Applications to Fast Electromagnetic Analysis of High-Speed Interconnects. [Internet] [Doctoral dissertation]. University of Washington; 2015. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/1773/33464.

Council of Science Editors:

Huang S. Broadband Green's Function and Applications to Fast Electromagnetic Analysis of High-Speed Interconnects. [Doctoral Dissertation]. University of Washington; 2015. Available from: http://hdl.handle.net/1773/33464

17. Goral, Benoit. Technique et Méthodologie de Conception du Réseau de Distribution d'Alimentation d'une Carte Electronique Rapide à Haute Densité d'Interconnexion : Design Techniques and Methodology for Power Delivery Network of a High Speed High Sensity Electronic Board.

Degree: Docteur es, Génie électrique, 2017, Paris Saclay

 Les contraintes économiques actuelles amènent les entreprises d'électronique non seulement à innover à un rythme très soutenu mais aussi à réduire le cycle de conception… (more)

Subjects/Keywords: Intégrité de Puissance; Intégrité de signal; Simulation; Mesures Electronique Rapide; Modélisation; Interconnexion; Power Integrity; Signal Integrity; Simulation; High Speed Measurement; Model; Interconnect

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APA (6th Edition):

Goral, B. (2017). Technique et Méthodologie de Conception du Réseau de Distribution d'Alimentation d'une Carte Electronique Rapide à Haute Densité d'Interconnexion : Design Techniques and Methodology for Power Delivery Network of a High Speed High Sensity Electronic Board. (Doctoral Dissertation). Paris Saclay. Retrieved from http://www.theses.fr/2017SACLN037

Chicago Manual of Style (16th Edition):

Goral, Benoit. “Technique et Méthodologie de Conception du Réseau de Distribution d'Alimentation d'une Carte Electronique Rapide à Haute Densité d'Interconnexion : Design Techniques and Methodology for Power Delivery Network of a High Speed High Sensity Electronic Board.” 2017. Doctoral Dissertation, Paris Saclay. Accessed November 18, 2019. http://www.theses.fr/2017SACLN037.

MLA Handbook (7th Edition):

Goral, Benoit. “Technique et Méthodologie de Conception du Réseau de Distribution d'Alimentation d'une Carte Electronique Rapide à Haute Densité d'Interconnexion : Design Techniques and Methodology for Power Delivery Network of a High Speed High Sensity Electronic Board.” 2017. Web. 18 Nov 2019.

Vancouver:

Goral B. Technique et Méthodologie de Conception du Réseau de Distribution d'Alimentation d'une Carte Electronique Rapide à Haute Densité d'Interconnexion : Design Techniques and Methodology for Power Delivery Network of a High Speed High Sensity Electronic Board. [Internet] [Doctoral dissertation]. Paris Saclay; 2017. [cited 2019 Nov 18]. Available from: http://www.theses.fr/2017SACLN037.

Council of Science Editors:

Goral B. Technique et Méthodologie de Conception du Réseau de Distribution d'Alimentation d'une Carte Electronique Rapide à Haute Densité d'Interconnexion : Design Techniques and Methodology for Power Delivery Network of a High Speed High Sensity Electronic Board. [Doctoral Dissertation]. Paris Saclay; 2017. Available from: http://www.theses.fr/2017SACLN037


University of Cincinnati

18. Liu, Jianxun. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects.

Degree: PhD, Engineering and Applied Science: Computer Science and Engineering, 2011, University of Cincinnati

 As technology approaches deep sub-micron and clock frequency approaches Giga Hertz, the signal integrity problem of high-speed interconnects is becoming a more and more serious… (more)

Subjects/Keywords: Computer Engineering; Interconnect Testing; Pseudo-Exhaustive Testing; PE-BIST; Signal Integrity; SoC; High Speed Interconnect

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APA (6th Edition):

Liu, J. (2011). Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248

Chicago Manual of Style (16th Edition):

Liu, Jianxun. “Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects.” 2011. Doctoral Dissertation, University of Cincinnati. Accessed November 18, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248.

MLA Handbook (7th Edition):

Liu, Jianxun. “Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects.” 2011. Web. 18 Nov 2019.

Vancouver:

Liu J. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. [Internet] [Doctoral dissertation]. University of Cincinnati; 2011. [cited 2019 Nov 18]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248.

Council of Science Editors:

Liu J. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. [Doctoral Dissertation]. University of Cincinnati; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248


NSYSU

19. Su, Hsin-Hsiang. A Novel Approach for Modeling Diodes Without Reducing the Time Step in the FDTD Method.

Degree: PhD, Electrical Engineering, 2013, NSYSU

 In a high-speed digital system, issues of the signal integrity (SI) associated with the high-speed circuit and printed circuit boards (PCB) become more important as… (more)

Subjects/Keywords: Lumped devices; Equivalent current source method; Multi-port circuits; Finite-difference time-domain; Signal integrity

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APA (6th Edition):

Su, H. (2013). A Novel Approach for Modeling Diodes Without Reducing the Time Step in the FDTD Method. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1104113-144454

Chicago Manual of Style (16th Edition):

Su, Hsin-Hsiang. “A Novel Approach for Modeling Diodes Without Reducing the Time Step in the FDTD Method.” 2013. Doctoral Dissertation, NSYSU. Accessed November 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1104113-144454.

MLA Handbook (7th Edition):

Su, Hsin-Hsiang. “A Novel Approach for Modeling Diodes Without Reducing the Time Step in the FDTD Method.” 2013. Web. 18 Nov 2019.

Vancouver:

Su H. A Novel Approach for Modeling Diodes Without Reducing the Time Step in the FDTD Method. [Internet] [Doctoral dissertation]. NSYSU; 2013. [cited 2019 Nov 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1104113-144454.

Council of Science Editors:

Su H. A Novel Approach for Modeling Diodes Without Reducing the Time Step in the FDTD Method. [Doctoral Dissertation]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1104113-144454


Penn State University

20. Eze, Melvin. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity.

Degree: PhD, Computer Science and Engineering, 2013, Penn State University

 The emergence of System-on-Chip as the dominant chip level architecture in the integrated Circuit industry, has been accompanied by a need to meet the considerable… (more)

Subjects/Keywords: Interconnect; Signal Integrity; Offset Switching; Variable Cycle Timing with Temporal Redundancy; NBTI

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APA (6th Edition):

Eze, M. (2013). Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/19916

Chicago Manual of Style (16th Edition):

Eze, Melvin. “Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity.” 2013. Doctoral Dissertation, Penn State University. Accessed November 18, 2019. https://etda.libraries.psu.edu/catalog/19916.

MLA Handbook (7th Edition):

Eze, Melvin. “Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity.” 2013. Web. 18 Nov 2019.

Vancouver:

Eze M. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity. [Internet] [Doctoral dissertation]. Penn State University; 2013. [cited 2019 Nov 18]. Available from: https://etda.libraries.psu.edu/catalog/19916.

Council of Science Editors:

Eze M. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity. [Doctoral Dissertation]. Penn State University; 2013. Available from: https://etda.libraries.psu.edu/catalog/19916


UCLA

21. Yao, Wei. Modeling and Optimization for High-speed Links and 3D IC.

Degree: Electrical Engineering, 2012, UCLA

 The advance of modern integrated circuit (IC) processes has supported increasing date rates on chip-to-chip communications in many consumer and professional applications, such as multimedia… (more)

Subjects/Keywords: Electrical engineering; 3D IC; circuit optimization; Interconnect modeling; signal integrity; through-silicon via

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APA (6th Edition):

Yao, W. (2012). Modeling and Optimization for High-speed Links and 3D IC. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/5f2003tx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yao, Wei. “Modeling and Optimization for High-speed Links and 3D IC.” 2012. Thesis, UCLA. Accessed November 18, 2019. http://www.escholarship.org/uc/item/5f2003tx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yao, Wei. “Modeling and Optimization for High-speed Links and 3D IC.” 2012. Web. 18 Nov 2019.

Vancouver:

Yao W. Modeling and Optimization for High-speed Links and 3D IC. [Internet] [Thesis]. UCLA; 2012. [cited 2019 Nov 18]. Available from: http://www.escholarship.org/uc/item/5f2003tx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yao W. Modeling and Optimization for High-speed Links and 3D IC. [Thesis]. UCLA; 2012. Available from: http://www.escholarship.org/uc/item/5f2003tx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Florida

22. Harb, Shadi. Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs.

Degree: PhD, Electrical and Computer Engineering, 2010, University of Florida

 3D Technology is emerging as an attractive way to sustain Moore s law, by making it possible for highly integrated, high performance, cost effective compact… (more)

Subjects/Keywords: 3d; bandgap; biasing; bist; crosstalk; delay; embedded; gtl; integrity; reference; signal; stacked; test; time; tsv

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APA (6th Edition):

Harb, S. (2010). Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0041423

Chicago Manual of Style (16th Edition):

Harb, Shadi. “Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs.” 2010. Doctoral Dissertation, University of Florida. Accessed November 18, 2019. http://ufdc.ufl.edu/UFE0041423.

MLA Handbook (7th Edition):

Harb, Shadi. “Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs.” 2010. Web. 18 Nov 2019.

Vancouver:

Harb S. Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs. [Internet] [Doctoral dissertation]. University of Florida; 2010. [cited 2019 Nov 18]. Available from: http://ufdc.ufl.edu/UFE0041423.

Council of Science Editors:

Harb S. Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs. [Doctoral Dissertation]. University of Florida; 2010. Available from: http://ufdc.ufl.edu/UFE0041423

23. Frejd, Andreas. Analysis and verification of routing effects on signal integrity for high-speed digital stripline interconnects in multi-layer PCB designs.

Degree: The Institute of Technology, 2010, Linköping UniversityLinköping University

  The way printed circuit board interconnects for high-speed digital signals are designed ultimately determines the performance that can be achieved for a certain interface,… (more)

Subjects/Keywords: Signal integrity; PCB; digital interconnect; high-speed; microwave probing; EM field solver

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APA (6th Edition):

Frejd, A. (2010). Analysis and verification of routing effects on signal integrity for high-speed digital stripline interconnects in multi-layer PCB designs. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-76899

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Frejd, Andreas. “Analysis and verification of routing effects on signal integrity for high-speed digital stripline interconnects in multi-layer PCB designs.” 2010. Thesis, Linköping UniversityLinköping University. Accessed November 18, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-76899.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Frejd, Andreas. “Analysis and verification of routing effects on signal integrity for high-speed digital stripline interconnects in multi-layer PCB designs.” 2010. Web. 18 Nov 2019.

Vancouver:

Frejd A. Analysis and verification of routing effects on signal integrity for high-speed digital stripline interconnects in multi-layer PCB designs. [Internet] [Thesis]. Linköping UniversityLinköping University; 2010. [cited 2019 Nov 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-76899.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Frejd A. Analysis and verification of routing effects on signal integrity for high-speed digital stripline interconnects in multi-layer PCB designs. [Thesis]. Linköping UniversityLinköping University; 2010. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-76899

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

24. Dahlen, Paul Eric. Enhancing signal Integrity design methodologies utilizing discrete frequency domain techniques.

Degree: PhD, Electrical Engineering, 2014, University of Minnesota

Signal integrity engineering involves the use of electrical models and time-domain simulation to predict signal waveform degradation as the signal propagates across interconnects. It is… (more)

Subjects/Keywords: Bilinear transform; Laplace transform; Matched-z transform; Rational function approximation; Signal integrity; z-domain

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APA (6th Edition):

Dahlen, P. E. (2014). Enhancing signal Integrity design methodologies utilizing discrete frequency domain techniques. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/163244

Chicago Manual of Style (16th Edition):

Dahlen, Paul Eric. “Enhancing signal Integrity design methodologies utilizing discrete frequency domain techniques.” 2014. Doctoral Dissertation, University of Minnesota. Accessed November 18, 2019. http://hdl.handle.net/11299/163244.

MLA Handbook (7th Edition):

Dahlen, Paul Eric. “Enhancing signal Integrity design methodologies utilizing discrete frequency domain techniques.” 2014. Web. 18 Nov 2019.

Vancouver:

Dahlen PE. Enhancing signal Integrity design methodologies utilizing discrete frequency domain techniques. [Internet] [Doctoral dissertation]. University of Minnesota; 2014. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/11299/163244.

Council of Science Editors:

Dahlen PE. Enhancing signal Integrity design methodologies utilizing discrete frequency domain techniques. [Doctoral Dissertation]. University of Minnesota; 2014. Available from: http://hdl.handle.net/11299/163244


University of Illinois – Urbana-Champaign

25. Lu, Tianjian. Signal integrity analysis of high-speed multilayer interconnects using the finite element method.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 Approaches of modeling high-speed interconnect generally fall into two categories: circuit models based on circuit-parameter extractions and full-wave methods based on solving Maxwell's equations. Even… (more)

Subjects/Keywords: Signal Integrity; Multilayer Interconnects; Full-Wave Analysis; Finite Element Method; Fast Frequency Sweep; Domain Decomposition

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APA (6th Edition):

Lu, T. (2013). Signal integrity analysis of high-speed multilayer interconnects using the finite element method. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Tianjian. “Signal integrity analysis of high-speed multilayer interconnects using the finite element method.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed November 18, 2019. http://hdl.handle.net/2142/42119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Tianjian. “Signal integrity analysis of high-speed multilayer interconnects using the finite element method.” 2013. Web. 18 Nov 2019.

Vancouver:

Lu T. Signal integrity analysis of high-speed multilayer interconnects using the finite element method. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/2142/42119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu T. Signal integrity analysis of high-speed multilayer interconnects using the finite element method. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Newell, Drew. Transistor level X-parameter simulations of equalization circuits.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 As frequencies have increased in circuits used for communication electronics, signal integrity concepts have become some of the foremost challenges that circuit designers must deal… (more)

Subjects/Keywords: signal integrity; x-parameter; ibis

…Figure 1.1: Eye diagram 1.2 Signal Integrity: Jitter and the Eye Diagram Dispersion… …complexity solves some signal integrity problems at the circuit level but presents greater… …form of jitter. Jitter is defined as the deviation of a signal timing event from its ideal… …properties have on bit streams. The output signal, Vo (t), is the result of the familiar… …Deserializer (SerDes) links. As discussed in Chapter 1, these added circuits and signal… 

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APA (6th Edition):

Newell, D. (2014). Transistor level X-parameter simulations of equalization circuits. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/49409

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Newell, Drew. “Transistor level X-parameter simulations of equalization circuits.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed November 18, 2019. http://hdl.handle.net/2142/49409.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Newell, Drew. “Transistor level X-parameter simulations of equalization circuits.” 2014. Web. 18 Nov 2019.

Vancouver:

Newell D. Transistor level X-parameter simulations of equalization circuits. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/2142/49409.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Newell D. Transistor level X-parameter simulations of equalization circuits. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/49409

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Colorado State University

27. Ahadi Dolatsara, Majid. Efficient multidimensional uncertainty quantification of high speed circuits using advanced polynomial chaos approaches.

Degree: MS(M.S.), Electrical and Computer Engineering, 2016, Colorado State University

 With the scaling of VLSI technology to sub-45 nm levels, uncertainty in the nanoscale manufacturing processes and operating conditions have been found to result in… (more)

Subjects/Keywords: High speed circuits; Polynomial chaos; Uncertainty quantification; linear regression; Computer aided design; Signal integrity

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APA (6th Edition):

Ahadi Dolatsara, M. (2016). Efficient multidimensional uncertainty quantification of high speed circuits using advanced polynomial chaos approaches. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/176722

Chicago Manual of Style (16th Edition):

Ahadi Dolatsara, Majid. “Efficient multidimensional uncertainty quantification of high speed circuits using advanced polynomial chaos approaches.” 2016. Masters Thesis, Colorado State University. Accessed November 18, 2019. http://hdl.handle.net/10217/176722.

MLA Handbook (7th Edition):

Ahadi Dolatsara, Majid. “Efficient multidimensional uncertainty quantification of high speed circuits using advanced polynomial chaos approaches.” 2016. Web. 18 Nov 2019.

Vancouver:

Ahadi Dolatsara M. Efficient multidimensional uncertainty quantification of high speed circuits using advanced polynomial chaos approaches. [Internet] [Masters thesis]. Colorado State University; 2016. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/10217/176722.

Council of Science Editors:

Ahadi Dolatsara M. Efficient multidimensional uncertainty quantification of high speed circuits using advanced polynomial chaos approaches. [Masters Thesis]. Colorado State University; 2016. Available from: http://hdl.handle.net/10217/176722


University of Arizona

28. Li, Qian. SIGNAL INTEGRITY ANALYSIS ON MATERIALS AND VIA STRUCTURES MODELING AND CHARACTERIZATION .

Degree: 2011, University of Arizona

 The development of modern digital communication systems has been entered a new era with faster signal transmission and processing capability, called high-speed circuit systems. As… (more)

Subjects/Keywords: Signal Integrity; Via modeling; Electrical & Computer Engineering; Material Characterization; on-wafer measurment

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, Q. (2011). SIGNAL INTEGRITY ANALYSIS ON MATERIALS AND VIA STRUCTURES MODELING AND CHARACTERIZATION . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/203472

Chicago Manual of Style (16th Edition):

Li, Qian. “SIGNAL INTEGRITY ANALYSIS ON MATERIALS AND VIA STRUCTURES MODELING AND CHARACTERIZATION .” 2011. Doctoral Dissertation, University of Arizona. Accessed November 18, 2019. http://hdl.handle.net/10150/203472.

MLA Handbook (7th Edition):

Li, Qian. “SIGNAL INTEGRITY ANALYSIS ON MATERIALS AND VIA STRUCTURES MODELING AND CHARACTERIZATION .” 2011. Web. 18 Nov 2019.

Vancouver:

Li Q. SIGNAL INTEGRITY ANALYSIS ON MATERIALS AND VIA STRUCTURES MODELING AND CHARACTERIZATION . [Internet] [Doctoral dissertation]. University of Arizona; 2011. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/10150/203472.

Council of Science Editors:

Li Q. SIGNAL INTEGRITY ANALYSIS ON MATERIALS AND VIA STRUCTURES MODELING AND CHARACTERIZATION . [Doctoral Dissertation]. University of Arizona; 2011. Available from: http://hdl.handle.net/10150/203472


North-West University

29. Hudson, Robert Dearn. Development of an integrated co-processor based power electronic drive / by Robert D. Hudson .

Degree: 2008, North-West University

 The McTronX research group at the North-West University is currently researching self-sensing techniques for Active Magnetic Bearings (AMB). The research is part of an ongoing… (more)

Subjects/Keywords: Active magnetic bearing; Co-processor; Digital signal processor; Field programmable gate array; Power amplifie; Pulse width modulation; Self-sensing; Signal integrity

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hudson, R. D. (2008). Development of an integrated co-processor based power electronic drive / by Robert D. Hudson . (Thesis). North-West University. Retrieved from http://hdl.handle.net/10394/3723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hudson, Robert Dearn. “Development of an integrated co-processor based power electronic drive / by Robert D. Hudson .” 2008. Thesis, North-West University. Accessed November 18, 2019. http://hdl.handle.net/10394/3723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hudson, Robert Dearn. “Development of an integrated co-processor based power electronic drive / by Robert D. Hudson .” 2008. Web. 18 Nov 2019.

Vancouver:

Hudson RD. Development of an integrated co-processor based power electronic drive / by Robert D. Hudson . [Internet] [Thesis]. North-West University; 2008. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/10394/3723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hudson RD. Development of an integrated co-processor based power electronic drive / by Robert D. Hudson . [Thesis]. North-West University; 2008. Available from: http://hdl.handle.net/10394/3723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Asokan, Anu. Signal Integrity - Aware Pattern Generation for Delay Testing : Signal Integrity - Aware Pattern Generation for Delay Testing.

Degree: Docteur es, Systèmes automatiques et microélectroniques, 2015, Montpellier

La miniaturisation des circuits intégrés permet d'avoir une intégration plus élevée dans une même puce. Cela, conduit a des problèmes de qualité dans les signaux… (more)

Subjects/Keywords: L'intégrité du signal; Test; Génération de configuration; Retard de trajet; Signal Integrity issues; Test; Design; Path delay

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Asokan, A. (2015). Signal Integrity - Aware Pattern Generation for Delay Testing : Signal Integrity - Aware Pattern Generation for Delay Testing. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2015MONTS206

Chicago Manual of Style (16th Edition):

Asokan, Anu. “Signal Integrity - Aware Pattern Generation for Delay Testing : Signal Integrity - Aware Pattern Generation for Delay Testing.” 2015. Doctoral Dissertation, Montpellier. Accessed November 18, 2019. http://www.theses.fr/2015MONTS206.

MLA Handbook (7th Edition):

Asokan, Anu. “Signal Integrity - Aware Pattern Generation for Delay Testing : Signal Integrity - Aware Pattern Generation for Delay Testing.” 2015. Web. 18 Nov 2019.

Vancouver:

Asokan A. Signal Integrity - Aware Pattern Generation for Delay Testing : Signal Integrity - Aware Pattern Generation for Delay Testing. [Internet] [Doctoral dissertation]. Montpellier; 2015. [cited 2019 Nov 18]. Available from: http://www.theses.fr/2015MONTS206.

Council of Science Editors:

Asokan A. Signal Integrity - Aware Pattern Generation for Delay Testing : Signal Integrity - Aware Pattern Generation for Delay Testing. [Doctoral Dissertation]. Montpellier; 2015. Available from: http://www.theses.fr/2015MONTS206

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