You searched for subject:(Side channel Attacks).
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Delft University of Technology
1.
van Tienen, Freek (author).
Far-field Correlation Electromagnetic Analysis attacks against AES in real world applications.
Degree: 2018, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:50d1a4f2-2458-47f5-a176-3439cefcc20b 
► In almost every device cryptographic functions are used to protect data and sensitive information from being intercepted. A commonly used encryption algorithm is the Advanced…
(more)
▼ In almost every device cryptographic functions are used to protect data and sensitive information from being intercepted. A commonly used encryption algorithm is the Advanced Encryption Standard (AES), which is a symmetric block cypher.
Side-
channel attacks against AES are well known and are often performed either directly on the surface of the integrated circuit or by attaching wires to the target device. These
attacks are more difficult for devices with tamper protection, which can detect such an attack because the device enclosure must be removed. This limits the attack possibilities of these
side-
channel attacks for these real-world applications.
Attacks using electromagnetic radiation from a further distance, called the far-field, can be used to prevent opening the enclosure. For these power based
side-
channel attacks against AES, power traces must be recorded with the exact timing before an encryption or decryption starts. This is used to align the recorded traces and perform statistical analysis to extract the secret key. In order to achieve this often an GPIO trigger is used to indicate the start of a new trace. When such an GPIO trigger is not available a smart trigger can be used, which uses a pattern to generate a trigger based on the measured power. This removes the need for making a connection with the target device. In this thesis an approach for performing non-invasive far-field
side-
channel attacks against multiple target devices is evaluated. For this approach near-field analysis is performed to analyse the target leakage, with the use of Test Vector Leakage Assessment. Then for each of these targets far-field
side-
channel attacks are attempted using a Software Defined Radio set-up and several smart triggers are tested in real-world scenarios. The results of these
attacks showed that far-field
side-
channel attacks without an artificial trigger are possible, and thus the enclosure of the target device can stay in tact and non-invasive
attacks can be performed. For the Microsemi SF2 Basic development kit
attacks up to a distance of 15 cm can be achieved in an office environment. This means that far-field
side-
channel attacks against AES are possible in real world applications, and when designing cryptographic devices precautions must be made to protect against these
attacks.
Advisors/Committee Members: van der Lubbe, Jan (mentor), Haesakkers, J. (graduation committee), Stoevelaar, G. (graduation committee), Boix Carpi, R. (graduation committee), Delft University of Technology (degree granting institution).
Subjects/Keywords: Side-Channel Attacks; AES; Electromagnetic
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APA (6th Edition):
van Tienen, F. (. (2018). Far-field Correlation Electromagnetic Analysis attacks against AES in real world applications. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:50d1a4f2-2458-47f5-a176-3439cefcc20b
Chicago Manual of Style (16th Edition):
van Tienen, Freek (author). “Far-field Correlation Electromagnetic Analysis attacks against AES in real world applications.” 2018. Masters Thesis, Delft University of Technology. Accessed March 02, 2021.
http://resolver.tudelft.nl/uuid:50d1a4f2-2458-47f5-a176-3439cefcc20b.
MLA Handbook (7th Edition):
van Tienen, Freek (author). “Far-field Correlation Electromagnetic Analysis attacks against AES in real world applications.” 2018. Web. 02 Mar 2021.
Vancouver:
van Tienen F(. Far-field Correlation Electromagnetic Analysis attacks against AES in real world applications. [Internet] [Masters thesis]. Delft University of Technology; 2018. [cited 2021 Mar 02].
Available from: http://resolver.tudelft.nl/uuid:50d1a4f2-2458-47f5-a176-3439cefcc20b.
Council of Science Editors:
van Tienen F(. Far-field Correlation Electromagnetic Analysis attacks against AES in real world applications. [Masters Thesis]. Delft University of Technology; 2018. Available from: http://resolver.tudelft.nl/uuid:50d1a4f2-2458-47f5-a176-3439cefcc20b
Georgia Tech
2.
Shih, Mingwei.
Securing Intel SGX against side-channel attacks via load-time synthesis.
Degree: PhD, Computer Science, 2019, Georgia Tech
URL: http://hdl.handle.net/1853/62337
► In response to the growing need for securing user data in the cloud, recent Intel processors have supported a new feature, Intel Software Guard Extensions…
(more)
▼ In response to the growing need for securing user data in the cloud, recent Intel processors have supported a new feature, Intel Software Guard Extensions (SGX). SGX allows a program to execute in isolation
from the rest of the underlying system. Thus, even after compromising the system, neither cloud providers nor attackers can gain access to data that the program processes. Unfortunately, recent studies have shown that such isolation is bypassable via
side-
channel attacks (SCAs). In particular, SCAs against SGX are more critical under the extreme assumption (i.e., attackers compromise the system), allowing attackers to infer fine-grained information from an SGX-protected program. Toward practical defenses against SCAs on SGX, the first part of the thesis presents two mitigation techniques, SGX-Armor and T-SGX, both of which require neither hardware- nor source-code-level modifications and incur moderate runtime overhead to the program. SGX-Armor is a general-purpose defense based on Address Space Layout Randomization (ASLR) that obfuscates the memory layout of the program, preventing attackers from interpreting
side-
channel information. Unlike traditional ASLR implementations, SGX-Armor incorporates a secure algorithm that shuffles memory layout without revealing the information of the layout through any of the known
side channels. T-SGX is a novel defense against controlled-
channel attacks that exploit page faults as a
side channel. By using Intel Transactional Synchronization Extensions (TSX) as a primitive that suppresses page faults, T-SGX automatically transfers a program into a protected one at compile time. The second part of the thesis presents Pridwen, a framework that addresses the challeenges of combining multiple mitigation techniques such as SGX-Armor and T-SGX, thereby providing a broader scope of protection against SCAs on SGX. Using load-time synthesis, Pridwen adaptively enforces mitigation schemes to a program in distinct cloud
environments. The prototype of Pridwen has supported four mitigation
schemes that secure SGX programs again various SCAs while minimizing the incurred runtime overhead according to the configuration of the
environment.
Advisors/Committee Members: Kim, Taesoo (advisor), Lee, Wenke (committee member), Peinado, Marcus (committee member), Steiner, Michael (committee member), Saltaformaggio, Brendan (committee member).
Subjects/Keywords: Intel SGX; Side-channel attacks
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APA (6th Edition):
Shih, M. (2019). Securing Intel SGX against side-channel attacks via load-time synthesis. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62337
Chicago Manual of Style (16th Edition):
Shih, Mingwei. “Securing Intel SGX against side-channel attacks via load-time synthesis.” 2019. Doctoral Dissertation, Georgia Tech. Accessed March 02, 2021.
http://hdl.handle.net/1853/62337.
MLA Handbook (7th Edition):
Shih, Mingwei. “Securing Intel SGX against side-channel attacks via load-time synthesis.” 2019. Web. 02 Mar 2021.
Vancouver:
Shih M. Securing Intel SGX against side-channel attacks via load-time synthesis. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/1853/62337.
Council of Science Editors:
Shih M. Securing Intel SGX against side-channel attacks via load-time synthesis. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62337
University of New South Wales
3.
Arora, Ankita.
Framework and countermeasures for cache and power based attacks.
Degree: Computer Science & Engineering, 2013, University of New South Wales
URL: http://handle.unsw.edu.au/1959.4/52952
;
https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11630/SOURCE01?view=true
► Advancements in technology, the need for automation and ease of manufacturability, have made embedded systems ubiquitous. One of the preeminent challenges in embedded systems is…
(more)
▼ Advancements in technology, the need for automation and ease of manufacturability, have made embedded systems ubiquitous. One of the preeminent challenges in embedded systems is maintaining the privacy of sensitive information being passed and keeping it secure. Security is taken care of by the deployment of state-of-the-art cryptographic algorithms to encrypt confidential data, which is then decrypted at the receiving end. Some embedded systems are increasingly attacked by adversaries for financial gain, or to obtain personal information. Internal computations are often revealed by external manifestations such as processing time~, power consumption~, electromagnetic emission~ and faults~. Such manifestations can be exploited by an adversary to obtain secret keys of cryptographic algorithms, and the process of obtaining secret keys using this mechanism is called a Side Channel Attack (SCA). SCAs~ are categorized based on the characteristics used for the attack. Two of the main side channel attacks are cache based attacks and power based attacks. Cache based side channel attacks are built using cache behavior of the system when data is exchanged between the processor and the main memory. A Cache is a smaller and faster memory placed between the processor and main memory and stores the information needed for computations in the processor to reduce memory transaction time. Cache based attacks are further classified as time-driven attacks~ and access-driven attacks~. Time-driven attacks use the encryption time during the execution of cryptographic algorithm in the processor while access-driven attacks are performed when the adversary gets access to the data stored in the cache. Power based attacks are mounted by measuring power variations during the encryption/decryption of a cryptographic algorithm. A successful recovery of the secret key allows the adversary to fake identities and gain benefits. Power based attacks are classified into Simple Power Analysis (SPA) and Differential Power Analysis (DPA) attacks. In SPA~, internal data is retrieved directly by analyzing the power magnitude, while in DPA~, much advanced statistical analysis is performed to predict the secret key. Several solutions exist to counter both cache based and power based side channel attacks. Cache attacks can be avoided by using architectural modifications~, time skewing~, cache warming~, use of maximum cache line size~,etc. The countermeasures used against power based attacks are masking~, sense amplifier based logic~, wave dynamic differential logic~, dual rail…
Subjects/Keywords: Side Channel Attacks; Cache Attacks; Countermeasure; Power Attacks
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APA (6th Edition):
Arora, A. (2013). Framework and countermeasures for cache and power based attacks. (Masters Thesis). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/52952 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11630/SOURCE01?view=true
Chicago Manual of Style (16th Edition):
Arora, Ankita. “Framework and countermeasures for cache and power based attacks.” 2013. Masters Thesis, University of New South Wales. Accessed March 02, 2021.
http://handle.unsw.edu.au/1959.4/52952 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11630/SOURCE01?view=true.
MLA Handbook (7th Edition):
Arora, Ankita. “Framework and countermeasures for cache and power based attacks.” 2013. Web. 02 Mar 2021.
Vancouver:
Arora A. Framework and countermeasures for cache and power based attacks. [Internet] [Masters thesis]. University of New South Wales; 2013. [cited 2021 Mar 02].
Available from: http://handle.unsw.edu.au/1959.4/52952 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11630/SOURCE01?view=true.
Council of Science Editors:
Arora A. Framework and countermeasures for cache and power based attacks. [Masters Thesis]. University of New South Wales; 2013. Available from: http://handle.unsw.edu.au/1959.4/52952 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11630/SOURCE01?view=true
University of New South Wales
4.
Jayasinghe, Jayasinghe A. D. Nayanajith.
Algorithmically Balanced Circuit to Mitigate Power and Fault Injection Based Side Channel Analysis Attacks.
Degree: Faculty of Engineering, 2017, University of New South Wales
URL: http://handle.unsw.edu.au/1959.4/58605
;
https://unsworks.unsw.edu.au/fapi/datastream/unsworks:46363/SOURCE02?view=true
► Cryptography algorithms, such as Advanced Encryption Standard (AES) algorithm, are responsible for keeping confidential and critical data secure using a secret key to access that…
(more)
▼ Cryptography algorithms, such as Advanced Encryption Standard (AES) algorithm, are responsible for keeping confidential and critical data secure using a secret key to access that data. Today, due to the integration of digital technology into all disciplines, personal information, government, financial, and military information is stored using cryptographic algorithms to prevent unauthorised access.When cryptographic algorithms are executed on either circuit based implementations or software based implementations, using non-computational emanated information, such as power dissipation, elapsed time, electromagnetic radiation, faulty ciphertext, and cache content (which are referred to as
side-channels) the secret key can be deduced. Such
attacks are referred to as
side-
channel attacks.Most devices, armed with cryptographic algorithms, use modes of operations to remove data dependencies. In this dissertation, first, the resistance of modes of operations of AES is tested against power based
side-
channel analysis
attacks. The minimal number of power traces to break each mode is calculated with a 99.99% confidence interval. This analysis is the first comprehensive analytical study of power based
side-
channel analysis resistance and the comparison of the levels of resistance offered by the differing modes of AES.In order to mitigate power based
side channel attacks, countermeasures must be deployed. Balancing bit flips has been shown to be an excellent solution against power analysis
attacks where the data and the complement of the data are processed simultaneously to cancel out (balance) the data dependent power dissipations.A novel algorithmic circuit balancing technique, QuadSeal, which balances both static power and the dynamic power is proposed as the main contribution of this thesis. QuadSeal uses four algorithmically modified circuits. The mathematical proof of the QuadSeal countermeasure is presented, and AES is balanced as an example with a random input swapping methodology to resist variability effects. Having a 6.5x area overhead and 4 × power overhead, QuadSeal-AES is the smallest complete balancing countermeasure against power based
side-
channel analysis
attacks. Unlike, all the circuitry balancing countermeasures proposed in the literature, QuadSeal can turn off additional circuitry to save power consumption or perform parallel encryptions to increase throughput when the security is not essential.Only a few countermeasures offer protection against multiple
side-
channel leakages. QuadSeal countermeasure was tested against fault injection
attacks. First, a mathematical proof of the fault injection attack resistance of QuadSeal is presented, and it is proven that QuadSeal offers protection against fault injection
attacks, but not detection. Therefore, a dual mode circuit (referred to as C-FIA circuit) which can detect and correct fault injections is proposed to hone the resistance against fault injection
attacks. The only possible way to break the security of C-FIA circuit is by injecting identical faults…
Advisors/Committee Members: Parameswaran, Sridevan, Faculty of Engineering, UNSW, Ignjatovic, Aleksandar, Faculty of Engineering, UNSW.
Subjects/Keywords: Differential Power analysis attacks; Side channel attacks; Power analysis attacks
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APA ·
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APA (6th Edition):
Jayasinghe, J. A. D. N. (2017). Algorithmically Balanced Circuit to Mitigate Power and Fault Injection Based Side Channel Analysis Attacks. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/58605 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:46363/SOURCE02?view=true
Chicago Manual of Style (16th Edition):
Jayasinghe, Jayasinghe A D Nayanajith. “Algorithmically Balanced Circuit to Mitigate Power and Fault Injection Based Side Channel Analysis Attacks.” 2017. Doctoral Dissertation, University of New South Wales. Accessed March 02, 2021.
http://handle.unsw.edu.au/1959.4/58605 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:46363/SOURCE02?view=true.
MLA Handbook (7th Edition):
Jayasinghe, Jayasinghe A D Nayanajith. “Algorithmically Balanced Circuit to Mitigate Power and Fault Injection Based Side Channel Analysis Attacks.” 2017. Web. 02 Mar 2021.
Vancouver:
Jayasinghe JADN. Algorithmically Balanced Circuit to Mitigate Power and Fault Injection Based Side Channel Analysis Attacks. [Internet] [Doctoral dissertation]. University of New South Wales; 2017. [cited 2021 Mar 02].
Available from: http://handle.unsw.edu.au/1959.4/58605 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:46363/SOURCE02?view=true.
Council of Science Editors:
Jayasinghe JADN. Algorithmically Balanced Circuit to Mitigate Power and Fault Injection Based Side Channel Analysis Attacks. [Doctoral Dissertation]. University of New South Wales; 2017. Available from: http://handle.unsw.edu.au/1959.4/58605 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:46363/SOURCE02?view=true
University of Texas – Austin
5.
-8281-6884.
Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems.
Degree: MSin Engineering, Electrical and Computer Engineering, 2017, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/2820
► Electromagnetic (EM) fields emanated due to switching currents in crypto-blocks can be an effective non-invasive channel for extracting secret keys. Accurate design-time simulation tools are…
(more)
▼ Electromagnetic (EM) fields emanated due to switching currents in crypto-blocks can be an effective non-invasive
channel for extracting secret keys. Accurate design-time simulation tools are needed to predict vulnerabilities and improve resilience of embedded systems to EM
side-
channel analysis
attacks. Modeling such
attacks is challenging, however, as it requires a multitude of expensive simulations across multiple circuit abstraction levels together with EM simulations. In this work, a simulation ow is developed to study the differential EM analysis (DEMA) attack on the Advanced Encryption System (AES) block cipher. The proposed ow enables design-time evaluation of realistic DEMA
attacks for the first time. The major challenge is accurately computing signals received by a nearby probe at various positions above the chip surface for a large number of AES encryptions. This requires rapidly generating spatial distribution and transient EM radiation of on-chip current waveforms. Commercial CAD tools are used to generate space-time samples of these waveforms and a custom EM simulator to radiate them. The computations are sped up by focusing on information-leaking time windows, performing hybrid gate- and transistor-level simulations, radiating only the currents on top metallization layers, and generating traces for different encryptions in parallel. These methods reduce simulation time to a manageable ~ 20 hrs wall-clock time/attack allowing a previously impossible level of vulnerability analysis. The proposed ow also allows pinpointing critical regions on the chip most susceptible to EM
attacks. We demonstrate that exploiting the spatial profile of circuit elements can reveal cryptographic keys with significantly fewer number of traces than DPA , guiding designers to the most critical areas of the layout. This enables targeted deployment of counter-measures to the highest information-leaking design components
Advisors/Committee Members: Orshansky, Michael (advisor).
Subjects/Keywords: Side channel attacks; Electromagnetic attacks; Differential attacks; Design for security
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APA ·
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APA (6th Edition):
-8281-6884. (2017). Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems. (Masters Thesis). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2820
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-8281-6884. “Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems.” 2017. Masters Thesis, University of Texas – Austin. Accessed March 02, 2021.
http://dx.doi.org/10.26153/tsw/2820.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-8281-6884. “Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems.” 2017. Web. 02 Mar 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-8281-6884. Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems. [Internet] [Masters thesis]. University of Texas – Austin; 2017. [cited 2021 Mar 02].
Available from: http://dx.doi.org/10.26153/tsw/2820.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-8281-6884. Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems. [Masters Thesis]. University of Texas – Austin; 2017. Available from: http://dx.doi.org/10.26153/tsw/2820
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Delft University of Technology
6.
Venkatachalam, Pradeep (author).
S-Net, A Neural Network Based Countermeasure for AES.
Degree: 2019, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:59001df2-9b47-47c2-bfbe-d1c016902795
► Hardware implementations of encryption schemes are unprotected against side-channel analysis techniques. Physical realizations of secure algorithms leak side-channel information through power, noise, time, sound and…
(more)
▼ Hardware implementations of encryption schemes are unprotected against
side-
channel analysis techniques. Physical realizations of secure algorithms leak
side-
channel information through power, noise, time, sound and electromagnetic radiation. Data-dependent correlations with this leakage are exploited to obtain secret information. Power analysis techniques are powerful, undetectable and non-intrusive
attacks that allow an adversary to extracts the secret key of the encryption scheme. These techniques rely on analyzing the power consumed by these physical realizations using leakage models and statistical techniques. Implementing a countermeasure against power analysis
attacks require a thorough understanding of the attack, encryption algorithm and it's implementation on hardware and software. Conventional countermeasures for AES against power analysis techniques minimize the
side-
channel information by implementing masking and hiding strategies at different abstraction levels. This thesis investigates a new class of countermeasures known as "breaking" through the implementation of the Substitution Box transformation using a neural network (S-Net). The inherent properties associated with the neural network architecture is expected to remove the correlation between the power consumed and the secret key used for encryption by breaking the linear power characteristics assumed by the leakage model. The proposed approach was implemented in software and an attack framework is used to run
side-
channel attacks and quantify information leakage. The effectiveness of the implemented countermeasure is measured by checking and quantifying it's security against Differential and Correlation Power Analysis, Template and Deep Learning based techniques. The results indicate that the implementation is secure against these
attacks.
Advisors/Committee Members: Taouil, Mottaqiallah (mentor), Hamdioui, Said (graduation committee), van Leuken, Rene (graduation committee), Delft University of Technology (degree granting institution).
Subjects/Keywords: Side-Channel Attacks; Hardware Security; Cryptography
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APA ·
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APA (6th Edition):
Venkatachalam, P. (. (2019). S-Net, A Neural Network Based Countermeasure for AES. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:59001df2-9b47-47c2-bfbe-d1c016902795
Chicago Manual of Style (16th Edition):
Venkatachalam, Pradeep (author). “S-Net, A Neural Network Based Countermeasure for AES.” 2019. Masters Thesis, Delft University of Technology. Accessed March 02, 2021.
http://resolver.tudelft.nl/uuid:59001df2-9b47-47c2-bfbe-d1c016902795.
MLA Handbook (7th Edition):
Venkatachalam, Pradeep (author). “S-Net, A Neural Network Based Countermeasure for AES.” 2019. Web. 02 Mar 2021.
Vancouver:
Venkatachalam P(. S-Net, A Neural Network Based Countermeasure for AES. [Internet] [Masters thesis]. Delft University of Technology; 2019. [cited 2021 Mar 02].
Available from: http://resolver.tudelft.nl/uuid:59001df2-9b47-47c2-bfbe-d1c016902795.
Council of Science Editors:
Venkatachalam P(. S-Net, A Neural Network Based Countermeasure for AES. [Masters Thesis]. Delft University of Technology; 2019. Available from: http://resolver.tudelft.nl/uuid:59001df2-9b47-47c2-bfbe-d1c016902795
Virginia Tech
7.
Patrick, Conor Persson.
Software Protection Against Fault and Side Channel Attacks.
Degree: MS, Computer Engineering, 2017, Virginia Tech
URL: http://hdl.handle.net/10919/78685
► Embedded systems are increasingly ubiquitous. Many of them have security requirements such as smart cards, mobile phones, and internet connected appliances. It can be a…
(more)
▼ Embedded systems are increasingly ubiquitous. Many of them have security
requirements such as smart cards, mobile phones, and internet connected
appliances. It can be a challenge to fulfill security requirements due to the
constrained nature of embedded devices. This security challenge is worsened by
the possibility of implementation
attacks. Despite well formulated
cryptosystems being used, the underlying hardware
can often undermine any security proven on paper.
If a secret key is at play, an adversary has a chance of revealing it by simply
looking at the power variation. Additionally, an adversary can tamper with an embedded
system's environment to get it to skip a security check or generate
side
channel information.
Any adversary with physical access to an embedded system can conduct such
implementation
attacks. It is the focus of this work to explore different
countermeasures against both
side channel and fault
attacks. A new
countermeasure call Intra-instruction Redundancy, based on bit-slicing, or
N-bit SIMD processing, is proposed. Another challenge with implementing
countermeasures against implementation
attacks, is that they need to be able to
be combined. Most proposed
side channel countermeasures do not prevent fault
injection and vice versa. Combining them is non-trivial as demonstrated with a
combined implementation attack.
Advisors/Committee Members: Schaumont, Patrick Robert (committeechair), Nazhandali, Leyla (committee member), Gerdes, Ryan M. (committee member).
Subjects/Keywords: Fault attacks; side channel analysis; countermeasure
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APA (6th Edition):
Patrick, C. P. (2017). Software Protection Against Fault and Side Channel Attacks. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78685
Chicago Manual of Style (16th Edition):
Patrick, Conor Persson. “Software Protection Against Fault and Side Channel Attacks.” 2017. Masters Thesis, Virginia Tech. Accessed March 02, 2021.
http://hdl.handle.net/10919/78685.
MLA Handbook (7th Edition):
Patrick, Conor Persson. “Software Protection Against Fault and Side Channel Attacks.” 2017. Web. 02 Mar 2021.
Vancouver:
Patrick CP. Software Protection Against Fault and Side Channel Attacks. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/10919/78685.
Council of Science Editors:
Patrick CP. Software Protection Against Fault and Side Channel Attacks. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78685
Delft University of Technology
8.
Arora, V. (author).
Side-channel leakages: from different target devices.
Degree: 2020, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:5566f6d5-2cee-4f5c-b047-7c8e36e8306f
► The advances in cryptography have enabled the features of confidentiality, security, and integrity in the digital space. The information about the working of the…
(more)
▼ The advances in cryptography have enabled the features of confidentiality, security, and integrity in the digital space. The information about the working of the digital system is used to perform side-channel attacks. These attacks exploit the physics of the system rather than targeting the mathematical complexity of algorithms. Side-channel attacks measure the variations in the system's physical characteristics to obtain information about the operations being performed along with the operand data. In this work, we evaluate how the choice of physical target device impacts the cryptographic implementation's security. A software implementation is flashed on devices from two different manufactures with the same instruction set, configured for identical execution. Power traces from different hardware devices are acquired and evaluated using leakage detection methodologies of TVLA, and KL-Divergence. Trace-sets are compared at the abstraction level of intra-board, inter-board, and inter-class to explore the information leaks. The performance of leakage detection methodologies in identifying leaks is evaluated using key-rank analysis and verified by profiling templates. Results show two classes of devices belonging to different manufacturers vary significantly in terms of the power profile yet show similarities in data leakage. Based on the source of leaks; micro-architecture leaks have minor differences at the inter-board level within boards of the same class, though the results of micro-architecture leaks are not comparable across boards of different classes. Data-overwrite leaks are specific to the instruction set and pipeline implementation and are observed for both classes of devices. This work provides a methodology for evaluating software implementations across different hardware.
Embedded Systems
Advisors/Committee Members: Picek, S. (mentor), Delft University of Technology (degree granting institution).
Subjects/Keywords: Side-channel analysis; template attacks; Portability
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APA (6th Edition):
Arora, V. (. (2020). Side-channel leakages: from different target devices. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:5566f6d5-2cee-4f5c-b047-7c8e36e8306f
Chicago Manual of Style (16th Edition):
Arora, V (author). “Side-channel leakages: from different target devices.” 2020. Masters Thesis, Delft University of Technology. Accessed March 02, 2021.
http://resolver.tudelft.nl/uuid:5566f6d5-2cee-4f5c-b047-7c8e36e8306f.
MLA Handbook (7th Edition):
Arora, V (author). “Side-channel leakages: from different target devices.” 2020. Web. 02 Mar 2021.
Vancouver:
Arora V(. Side-channel leakages: from different target devices. [Internet] [Masters thesis]. Delft University of Technology; 2020. [cited 2021 Mar 02].
Available from: http://resolver.tudelft.nl/uuid:5566f6d5-2cee-4f5c-b047-7c8e36e8306f.
Council of Science Editors:
Arora V(. Side-channel leakages: from different target devices. [Masters Thesis]. Delft University of Technology; 2020. Available from: http://resolver.tudelft.nl/uuid:5566f6d5-2cee-4f5c-b047-7c8e36e8306f
Virginia Tech
9.
Kathuria, Tarun.
Gate-level Leakage Assessment and Mitigation.
Degree: MS, Computer Engineering, 2019, Virginia Tech
URL: http://hdl.handle.net/10919/101862
► Side-channel leakage, caused by imperfect implementation of cryptographic algorithms in hardware, has become a serious security threat for connected devices that generate and process sensitive…
(more)
▼ Side-
channel leakage, caused by imperfect implementation of cryptographic algorithms in
hardware, has become a serious security threat for connected devices that generate and
process sensitive data. This
side-
channel leakage can divulge secret information in the form of
power consumption or electromagnetic emissions. The
side-
channel leakage of a crytographic
device is commonly assessed after tape-out on a physical prototype.
This thesis presents a methodology called Gate-level Leakage Assessment (GLA), which
evaluates the power-based
side-
channel leakage of an integrated circuit at design time. By
combining
side-
channel leakage assessment with power simulations on the gate-level netlist,
GLA is able to pinpoint the leakiest cells in the netlist in addition to assessing the overall
side-
channel vulnerability to
side-
channel leakage. As the power traces obtained from power
simulations are noiseless, GLA is able to precisely locate the sources of
side-
channel leakage
with fewer measurements than on a physical prototype. The thesis applies the methodology
on the design of a encryption co-processor to analyze sources of
side-
channel leakage.
Once the gate-level leakage sources are identified, this thesis presents a logic level replacement
strategy for the leakage sources that can thwart
side-
channel leakage. The countermeasures
presented selectively replaces gate-level cells with a secure logic style effectively removing
the
side-
channel leakage with minimal impact in area. The assessment methodology along
with the countermeasures demonstrated is a turnkey solution for IP module designers and
is also applicable to larger system level designs.
Advisors/Committee Members: Schaumont, Patrick Robert (committeechair), Patterson, Cameron D. (committee member), Jian, Xun (committee member).
Subjects/Keywords: Side-channel leakage; Countermeasures; Power analysis attacks
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APA (6th Edition):
Kathuria, T. (2019). Gate-level Leakage Assessment and Mitigation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/101862
Chicago Manual of Style (16th Edition):
Kathuria, Tarun. “Gate-level Leakage Assessment and Mitigation.” 2019. Masters Thesis, Virginia Tech. Accessed March 02, 2021.
http://hdl.handle.net/10919/101862.
MLA Handbook (7th Edition):
Kathuria, Tarun. “Gate-level Leakage Assessment and Mitigation.” 2019. Web. 02 Mar 2021.
Vancouver:
Kathuria T. Gate-level Leakage Assessment and Mitigation. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/10919/101862.
Council of Science Editors:
Kathuria T. Gate-level Leakage Assessment and Mitigation. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/101862
Université Catholique de Louvain
10.
Poussier, Romain.
Key enumeration, rank estimation and horizontal side-channel attacks.
Degree: 2018, Université Catholique de Louvain
URL: http://hdl.handle.net/2078.1/195707
► Since their discovery in the late 90's, side-channel attacks have been shown to be a great threat to the security of cryptographic implementations. In addition…
(more)
▼ Since their discovery in the late 90's, side-channel attacks have been shown to be a great threat to the security of cryptographic implementations. In addition to the standard inputs and outputs of an algorithm, these attacks exploit the leakages coming from its implementation. As this additional information was not taken into account during the design of the standard schemes, they have been broken. A wide range of countermeasures has then been developed to increase the resilience of cryptographic schemes against these attacks. However, these countermeasures do not prevent attacks, but rather make them more complex to perform. As a result, the actual security of a given implementation needs to be tested in practice. A way to assess the security of an algorithm is to actually attack it in two steps. The first one, that we denote by information extraction, focuses on the way to use the information arising from the leakages as optimally as possible. The second one, that we denote by information exploitation, focuses on the way to use computational power to mitigate the lack of side-channel information after its extraction. This thesis follows this strategy and tackles both of these problems in two parts. In the first one, we focus on the leakage exploitation in the case of block ciphers. In this respect, we present new key enumeration and rank estimation algorithms and study their applicability. In the second part, we focus on the leakage extraction against elliptic curve cryptography. In that purpose, we present a method to use most of the available information against scalar multiplication algorithms through horizontal differential power attacks.
(FSA - Sciences de l'ingénieur) – UCL, 2018
Advisors/Committee Members: UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique, UCL - Ecole Polytechnique de Louvain, Standaert, François-Xavier, Bol, David, Pereira, Olivier, Rivain, Matthieu, Dhem, Jean-François.
Subjects/Keywords: Cryptography; Side-Channel Attacks; Key Enumeration; Rank Estimation; Horizontal Attacks
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Manager
APA (6th Edition):
Poussier, R. (2018). Key enumeration, rank estimation and horizontal side-channel attacks. (Thesis). Université Catholique de Louvain. Retrieved from http://hdl.handle.net/2078.1/195707
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Poussier, Romain. “Key enumeration, rank estimation and horizontal side-channel attacks.” 2018. Thesis, Université Catholique de Louvain. Accessed March 02, 2021.
http://hdl.handle.net/2078.1/195707.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Poussier, Romain. “Key enumeration, rank estimation and horizontal side-channel attacks.” 2018. Web. 02 Mar 2021.
Vancouver:
Poussier R. Key enumeration, rank estimation and horizontal side-channel attacks. [Internet] [Thesis]. Université Catholique de Louvain; 2018. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/2078.1/195707.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Poussier R. Key enumeration, rank estimation and horizontal side-channel attacks. [Thesis]. Université Catholique de Louvain; 2018. Available from: http://hdl.handle.net/2078.1/195707
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Virginia Tech
11.
Kiaei, Pantea.
Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack.
Degree: MS, Computer Engineering, 2019, Virginia Tech
URL: http://hdl.handle.net/10919/93537
► Ciphers are algorithms designed by mathematicians. They protect data by encrypting them. In one of the main categories of these ciphers, called symmetric-key ciphers, a…
(more)
▼ Ciphers are algorithms designed by mathematicians. They protect data by encrypting them. In one of the main categories of these ciphers, called symmetric-key ciphers, a secret key is used to both encrypt and decrypt the data. Once the secret key of a cipher is retrieved, anyone can find the decoded data and thereby access the original data. Cryptographers traditionally sought to design ciphers in such a way that no adversary could reveal the secret key by finding holes in the algorithm. However, this has been shown insufficient for a specific implementation of a cryptographic algorithm to be considered as “unbreakable” since the physical properties of the implementation, can help an adversary find the secret key and break the encryption. Analyzing these physical properties can be either active; by making controlled changes in the normal progress of its execution, or passive; by merely measuring the physical properties during normal execution.
Designers try to take these analyses into account when implementing a cryptographic function and so, in this project, we aim to present architectural support for a combination of some of the countermeasures.
Advisors/Committee Members: Schaumont, Patrick R. (committeechair), Nazhandali, Leyla (committee member), Hsiao, Michael S. (committee member).
Subjects/Keywords: Side-channel attacks; Fault attacks; Custom-instruction extensions; Bitslicing; Software countermeasures
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Manager
APA (6th Edition):
Kiaei, P. (2019). Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/93537
Chicago Manual of Style (16th Edition):
Kiaei, Pantea. “Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack.” 2019. Masters Thesis, Virginia Tech. Accessed March 02, 2021.
http://hdl.handle.net/10919/93537.
MLA Handbook (7th Edition):
Kiaei, Pantea. “Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack.” 2019. Web. 02 Mar 2021.
Vancouver:
Kiaei P. Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/10919/93537.
Council of Science Editors:
Kiaei P. Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/93537
Delft University of Technology
12.
Frigo, Pietro (author).
Practical Microarchitectural Attacks from Integrated GPUs.
Degree: 2017, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:c0d3c629-4c67-4741-9776-05802d89872f
► Dark silicon is pushing processor vendors to add more specialized units such as accelerators to commodity processor chips. Unfortunately this is done without enough care…
(more)
▼ Dark silicon is pushing processor vendors to add more specialized units such as accelerators to commodity processor chips. Unfortunately this is done without enough care to security. In this paper we look at the security implications of integrated Graphical Processor Units (GPUs) found in almost all mobile processors. We demonstrate that GPUs, already widely employed to accelerate a variety of benign applications such as image rendering, can also be used to “accelerate” microarchitectural
attacks (i.e., making them more effective) on commodity platforms. In particular, we show that an attacker can build all the necessary primitives for performing effective GPU-based microarchitectural
attacks and that these primitives are all exposed to the web through standardized browser extensions, allowing
side-
channel and Rowhammer
attacks from JavaScript. These
attacks bypass state-of-the-art mitigations and advance existing CPU-based
attacks: we show the first end-to-end microarchitectural compromise of a browser running on a mobile phone by orchestrating our GPU primitives. While powerful, these GPU primitives are not easy to implement due to undocumented hardware features. We describe novel reverse engineering techniques for peeking into the previously unknown cache architecture and replacement policy of the Adreno 330, an integrated GPU found in many common mobile platforms. This information is necessary when building shader programs implementing our GPU primitives. We conclude by discussing mitigations against GPU-enabled attackers.
Advisors/Committee Members: Doerr, Christian (mentor), van der Lubbe, Jan (graduation committee), Wong, Stephan (graduation committee), Delft University of Technology (degree granting institution).
Subjects/Keywords: Microarchitectural Attacks; Integrated GPUs; Mobile Security; Side-Channel Attacks; Rowhammer Attacks; ARM
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APA ·
Chicago ·
MLA ·
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CSE |
Export
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Manager
APA (6th Edition):
Frigo, P. (. (2017). Practical Microarchitectural Attacks from Integrated GPUs. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c0d3c629-4c67-4741-9776-05802d89872f
Chicago Manual of Style (16th Edition):
Frigo, Pietro (author). “Practical Microarchitectural Attacks from Integrated GPUs.” 2017. Masters Thesis, Delft University of Technology. Accessed March 02, 2021.
http://resolver.tudelft.nl/uuid:c0d3c629-4c67-4741-9776-05802d89872f.
MLA Handbook (7th Edition):
Frigo, Pietro (author). “Practical Microarchitectural Attacks from Integrated GPUs.” 2017. Web. 02 Mar 2021.
Vancouver:
Frigo P(. Practical Microarchitectural Attacks from Integrated GPUs. [Internet] [Masters thesis]. Delft University of Technology; 2017. [cited 2021 Mar 02].
Available from: http://resolver.tudelft.nl/uuid:c0d3c629-4c67-4741-9776-05802d89872f.
Council of Science Editors:
Frigo P(. Practical Microarchitectural Attacks from Integrated GPUs. [Masters Thesis]. Delft University of Technology; 2017. Available from: http://resolver.tudelft.nl/uuid:c0d3c629-4c67-4741-9776-05802d89872f
Uppsala University
13.
Lindqvist, Maria.
Dynamic Eviction Set Algorithms and Their Applicability to Cache Characterisation.
Degree: Information Technology, 2020, Uppsala University
URL: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-420317
► Eviction sets are groups of memory addresses that map to the same cache set. They can be used to perform efficient information-leaking attacks against…
(more)
▼ Eviction sets are groups of memory addresses that map to the same cache set. They can be used to perform efficient information-leaking attacks against the cache memory, so-called cache side channel attacks. In this project, two different algorithms that find such sets are implemented and compared. The second of the algorithms improves on the first by using a concept called group testing. It is also evaluated if these algorithms can be used to analyse or reverse engineer the cache characteristics, which is a new area of application for this type of algorithms. The results show that the optimised algorithm performs significantly better than the previous state-of-the-art algorithm. This means that countermeasures developed against this type of attacks need to be designed with the possibility of faster attacks in mind. The results also shows, as a proof-of-concept, that it is possible to use these algorithms to create a tool for cache analysis.
Subjects/Keywords: microarchitectural attacks; cache attacks; side channel attacks; eviction set; cache memory; Computer Engineering; Datorteknik
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APA ·
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Manager
APA (6th Edition):
Lindqvist, M. (2020). Dynamic Eviction Set Algorithms and Their Applicability to Cache Characterisation. (Thesis). Uppsala University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-420317
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Lindqvist, Maria. “Dynamic Eviction Set Algorithms and Their Applicability to Cache Characterisation.” 2020. Thesis, Uppsala University. Accessed March 02, 2021.
http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-420317.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Lindqvist, Maria. “Dynamic Eviction Set Algorithms and Their Applicability to Cache Characterisation.” 2020. Web. 02 Mar 2021.
Vancouver:
Lindqvist M. Dynamic Eviction Set Algorithms and Their Applicability to Cache Characterisation. [Internet] [Thesis]. Uppsala University; 2020. [cited 2021 Mar 02].
Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-420317.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Lindqvist M. Dynamic Eviction Set Algorithms and Their Applicability to Cache Characterisation. [Thesis]. Uppsala University; 2020. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-420317
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
14.
Ordas, Sébastien.
Évaluation de méthodes faible consommation contre les attaques matérielles : Evaluation of low power methods against hardware attacks.
Degree: Docteur es, Systèmes automatiques et microélectroniques, 2015, Montpellier
URL: http://www.theses.fr/2015MONTS023
► La consommation des circuits intégrés n'a cessé d'augmenter cette dernière décennie. Avec l'augmentation du prix de l'énergie et la démocratisation des systèmes embarqués, des méthodes…
(more)
▼ La consommation des circuits intégrés n'a cessé d'augmenter cette dernière décennie. Avec l'augmentation du prix de l'énergie et la démocratisation des systèmes embarqués, des méthodes permettant de gérer le compromis consommation performance, comme la gestion dynamique de la fréquence et de la tension d'alimentation ou encore du potentiel de substrat, ont été élaborées. Ces méthodes, qui sont de plus en plus couramment mises en œuvre dans les systèmes intégrés, permettent de diminuer la consommation de ceux-ci, et mieux de gérer le compromis consommation performance. Certains de ces circuits, embarquant ces méthodes peuvent avoir à effectuer des opérations traitant des informations confidentielles. Il est donc nécessaire de s'interroger sur l'éventuel impact de ces sur la sécurité des systèmes intégrés. Dans ce contexte, les travaux de thèse reportés dans le présent document, ont eu pour objectif d'analyser la compatibilité de ces méthodes de gestion de la consommation avec la conception de circuits robustes aux attaques matérielles. Plus particulièrement, l'objectif a été de déterminer si ces techniques de conception faible consommation, constituent des obstacles réels ou bien facilitent les attaques matérielles par observation et perturbation exploitant le canal électromagnétique. Dans un premier temps, une étude sur l'efficacité des attaques par observation en présence de gestion aléatoire de la tension, de la fréquence et de la polarisation de substrat a été conduite. Dans un deuxième temps, l'impact de la gestion dynamique des tensions d'alimentation et de substrat sur la capacité à injecter des fautes par médium électromagnétique a été étudié. Ce document présente l'ensemble des résultats de ces analyses.Mots-clés : Attaques Matérielles, Attaques par Canaux Auxiliaires, Attaques par fautes, Canal électromagnétique, DVFS, Body-Biasing.
The consumption of integrated circuits has been increasing over the last decade. With the increase of energy prices and the democratization of embedded systems, methods to manage the consumption performance compromise, such as the dynamic management of the frequency and the supply voltage or the substrate potential, were developed. These methods, which are becoming more commonly implemented in integrated systems, allow to reduce the consumption of those latter, and to better manage the tradeoff between consumption and performance.Some of these circuits, embedding these methods, may have to perform some operations with confidential information. It is therefore necessary to consider the possible impact of these methods on the safety of the integrated systems. In this context, the work reported in this thesis aimed to analyze the compatibility of these methods of power management with the design of robust circuits to physical attacks.Specifically, the objective was to determine whether these low-power techniques constitute real obstacles or facilitate the attacks by observation or perturbation exploiting the electromagnetic channel. Initially, a study on the effectiveness of…
Advisors/Committee Members: Maurine, Philippe (thesis director).
Subjects/Keywords: Attaques; Side-Channel; Consommation; Injection de fautes; Attacks; Side-Channel; Power Consumption; Faults injection
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Ordas, S. (2015). Évaluation de méthodes faible consommation contre les attaques matérielles : Evaluation of low power methods against hardware attacks. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2015MONTS023
Chicago Manual of Style (16th Edition):
Ordas, Sébastien. “Évaluation de méthodes faible consommation contre les attaques matérielles : Evaluation of low power methods against hardware attacks.” 2015. Doctoral Dissertation, Montpellier. Accessed March 02, 2021.
http://www.theses.fr/2015MONTS023.
MLA Handbook (7th Edition):
Ordas, Sébastien. “Évaluation de méthodes faible consommation contre les attaques matérielles : Evaluation of low power methods against hardware attacks.” 2015. Web. 02 Mar 2021.
Vancouver:
Ordas S. Évaluation de méthodes faible consommation contre les attaques matérielles : Evaluation of low power methods against hardware attacks. [Internet] [Doctoral dissertation]. Montpellier; 2015. [cited 2021 Mar 02].
Available from: http://www.theses.fr/2015MONTS023.
Council of Science Editors:
Ordas S. Évaluation de méthodes faible consommation contre les attaques matérielles : Evaluation of low power methods against hardware attacks. [Doctoral Dissertation]. Montpellier; 2015. Available from: http://www.theses.fr/2015MONTS023
Delft University of Technology
15.
Tubbing, Rico (author).
An Analysis of Deep Learning Based Profiled Side-channel Attacks: Custom Deep Learning Layer, CNN Hyperparameters for Countermeasures, and Portability Settings.
Degree: 2019, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:a2179003-b00b-495e-8f2f-225562e65232
► A side-channel attack (SCA) recovers secret data from a device by exploiting unintended physical leakages such as power consumption. In a profiled SCA, we assume…
(more)
▼ A side-channel attack (SCA) recovers secret data from a device by exploiting unintended physical leakages such as power consumption. In a profiled SCA, we assume an adversary has control over a target and copy device. Using the copy device the adversary learns a profile of the device. With the profile, the adversary exploits the measurements from a target device and recovers the secret key. As SCAs have shown to be a realistic attack vector, countermeasures have been invented to harden these kinds of attacks. In the last few years, deep learning has been applied in a wide variety of domains. For example, convolutional neural networks have shown to be effective for object recognition in images and recurrent neural networks for text generation. In the side-channel analysis domain, deep learning has shown to be successful. Up until recently, no deep learning layer existed that was specifically designed for SCAs. In this work, we analyze this layer, called the spread layer, and demonstrate the flaws of this layer. We improve the flaws and show the spread layer does not enhance the performance of SCAs. Additionally, we show there is no need to develop a deep learning layer specifically for SCAs on unprotected implementations. For implementations where countermeasures are present, literature demonstrated that convolutional neural networks are the most successful. However, for both the masking and random delay countermeasure, little is known about the influence of the kernel size and depth of the network. In this work, we illustrate that increasing the kernel size and depth of the network both increase the attack efficiency for the random delay countermeasure. For the masking countermeasure, we demonstrate that higher kernel sizes and shallow networks perform the best. Additionally, in this work, we consider a portability setting where the probe position has been changed in between the measurements of the profiling and attack measurements. Here, we show that the probe position causes a typical deep learning SCA to be ineffective. We introduce a normalization method such that the attack becomes effective, and show this method enables the attack to perform as expected.
Computer Science
Advisors/Committee Members: Picek, Stjepan (mentor), Doerr, Christian (graduation committee), Murukannaiah, Pradeep (graduation committee), Delft University of Technology (degree granting institution).
Subjects/Keywords: Side-Channel Attacks; Deep Learning; Profiled Side-channel Attack; Convolutional Neural Networks; Spread; Portability
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APA ·
Chicago ·
MLA ·
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CSE |
Export
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Manager
APA (6th Edition):
Tubbing, R. (. (2019). An Analysis of Deep Learning Based Profiled Side-channel Attacks: Custom Deep Learning Layer, CNN Hyperparameters for Countermeasures, and Portability Settings. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:a2179003-b00b-495e-8f2f-225562e65232
Chicago Manual of Style (16th Edition):
Tubbing, Rico (author). “An Analysis of Deep Learning Based Profiled Side-channel Attacks: Custom Deep Learning Layer, CNN Hyperparameters for Countermeasures, and Portability Settings.” 2019. Masters Thesis, Delft University of Technology. Accessed March 02, 2021.
http://resolver.tudelft.nl/uuid:a2179003-b00b-495e-8f2f-225562e65232.
MLA Handbook (7th Edition):
Tubbing, Rico (author). “An Analysis of Deep Learning Based Profiled Side-channel Attacks: Custom Deep Learning Layer, CNN Hyperparameters for Countermeasures, and Portability Settings.” 2019. Web. 02 Mar 2021.
Vancouver:
Tubbing R(. An Analysis of Deep Learning Based Profiled Side-channel Attacks: Custom Deep Learning Layer, CNN Hyperparameters for Countermeasures, and Portability Settings. [Internet] [Masters thesis]. Delft University of Technology; 2019. [cited 2021 Mar 02].
Available from: http://resolver.tudelft.nl/uuid:a2179003-b00b-495e-8f2f-225562e65232.
Council of Science Editors:
Tubbing R(. An Analysis of Deep Learning Based Profiled Side-channel Attacks: Custom Deep Learning Layer, CNN Hyperparameters for Countermeasures, and Portability Settings. [Masters Thesis]. Delft University of Technology; 2019. Available from: http://resolver.tudelft.nl/uuid:a2179003-b00b-495e-8f2f-225562e65232
Virginia Tech
16.
Sinha, Ambuj Sudhir.
Design Techniques for Side-channel Resistant Embedded Software.
Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech
URL: http://hdl.handle.net/10919/34465
► Side Channel Attacks (SCA) are a class of passive attacks on cryptosystems that exploit implementation characteristics of the system. Currently, a lot of research is…
(more)
▼ Side Channel Attacks (SCA) are a class of passive
attacks on cryptosystems that exploit implementation characteristics of the system. Currently, a lot of research is focussed towards developing countermeasures to
side channel attacks. In this thesis, we address two challenges that are an inherent part of the efficient implementation of SCA countermeasures. While designing a system, design choices made for enhancing the efficiency or performance of the system can also affect the
side channel security of the system. The first challenge is that the effect of different design choices on the
side channel resistance of a system is currently not well understood. It is important to understand these effects in order to develop systems that are both secure and efficient. A second problem with incorporating SCA countermeasures is the increased design complexity. It is often difficult and time consuming to integrate an SCA countermeasure in a larger system.
In this thesis, we explore that above mentioned problems from the point of view of developing embedded software that is resistant to power based
side channel attacks. Our first work is an evaluation of different software AES implementations, from the perspective of
side channel resistance, that shows the effect of design choices on the security and performance of the implementation. Next we present work that identifies the problems that arise while designing software for a particular type of SCA resistant architecture - the Virtual Secure Circuit. We provide a solution in terms of a methodology that can be used for developing software for such a system - and also demonstrate that this methodology can be conveniently automated - leading to swifter and easier software development for
side channel resistant designs.
Advisors/Committee Members: Schaumont, Patrick Robert (committeechair), Shukla, Sandeep K. (committee member), Hsiao, Michael S. (committee member).
Subjects/Keywords: Bitslice Cryptography; Side Channel Attacks; Virtual Secure Circuit; Secure Embedded Systems; Side-channel Countermeasures
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APA (6th Edition):
Sinha, A. S. (2011). Design Techniques for Side-channel Resistant Embedded Software. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34465
Chicago Manual of Style (16th Edition):
Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Masters Thesis, Virginia Tech. Accessed March 02, 2021.
http://hdl.handle.net/10919/34465.
MLA Handbook (7th Edition):
Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Web. 02 Mar 2021.
Vancouver:
Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/10919/34465.
Council of Science Editors:
Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34465
University of California – Irvine
17.
Crane, Stephen.
Enhancing and Extending Software Diversity.
Degree: Computer Science, 2015, University of California – Irvine
URL: http://www.escholarship.org/uc/item/45w3n70k
► Software immunity through diversity is a promising research direction. Address Space Layout Randomization has been widely deployed to defend against code-reuse attacks and significantly raises…
(more)
▼ Software immunity through diversity is a promising research direction. Address Space Layout Randomization has been widely deployed to defend against code-reuse attacks and significantly raises the bar for attackers. However, automated software diversity is still exploitable by adroit and adaptable adversaries. Using powerful memory disclosure attacks, offensive researchers have demonstrated weaknesses in conventional randomization techniques. In addition, current defenses are largely passive and allow attackers to continuously brute-force randomized defenses with little impediment. Building on the foundation of automated software diversity, we propose novel techniques to strengthen the security and broaden the impact of code randomization. We first discuss software booby traps, a new active defense technique enabled by randomized program contents. We then propose, implement, and evaluate a comprehensive randomization-based system, Readactor++, which is resilient to all types of memory disclosure attacks. Readactor++ enforces execute-only memory protections on commodity x86 processors, thus preventing direct disclosure of randomized code. We also identify the indirect disclosure attack, a new class of code leakage via data disclosure, and mitigate this attack as well. By integrating booby traps into our system, we protect against brute-force memory disclosure attempts. In our evaluation we find that Readactor++ compares favorably to other memory-disclosure resilient code-reuse defenses and that it scales effectively to complex, real-world software. Finally, we propose a novel extension of code randomization to mitigate side-channel rather than code-reuse attacks. Using control-flow diversity, a novel control-flow transformation, we introduce dynamic behavior into program side effects with fast, static code. As an example, we apply this technique to mitigate an AES cache side-channel attack. With our techniques, software diversity can now be efficiently secured against advanced attacks, including memory disclosure and function table reuse, and is adaptable to combat new classes of threats, such as side-channel attacks.
Subjects/Keywords: Computer science; Code-reuse Attacks; Computer Security; Side-channel Attacks; Software Defenses; Software Diversity
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Manager
APA (6th Edition):
Crane, S. (2015). Enhancing and Extending Software Diversity. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/45w3n70k
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Crane, Stephen. “Enhancing and Extending Software Diversity.” 2015. Thesis, University of California – Irvine. Accessed March 02, 2021.
http://www.escholarship.org/uc/item/45w3n70k.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Crane, Stephen. “Enhancing and Extending Software Diversity.” 2015. Web. 02 Mar 2021.
Vancouver:
Crane S. Enhancing and Extending Software Diversity. [Internet] [Thesis]. University of California – Irvine; 2015. [cited 2021 Mar 02].
Available from: http://www.escholarship.org/uc/item/45w3n70k.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Crane S. Enhancing and Extending Software Diversity. [Thesis]. University of California – Irvine; 2015. Available from: http://www.escholarship.org/uc/item/45w3n70k
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Illinois – Urbana-Champaign
18.
Ahmad, Mohammad.
Cauldron: a framework to defend against cache-based side-channel attacks in clouds.
Degree: MS, Computer Science, 2016, University of Illinois – Urbana-Champaign
URL: http://hdl.handle.net/2142/90967
► Cache-based side-channel attacks have garnered much interest in recent literature. Such attacks are particularly relevant for cloud computing platforms due to high levels of multi-tenancy.…
(more)
▼ Cache-based
side-
channel attacks have garnered much interest in recent literature. Such
attacks are particularly relevant for cloud computing platforms due to high levels of multi-tenancy. In fact, there exists recent work that demonstrates such
attacks on real cloud platforms (e.g., DotCloud). In this thesis we present Cauldron, a framework to defend against such cache-based
side-
channel attacks. Cauldron uses a combination of smart scheduling techniques and microarchitectural mechanisms to achieve this goal. We are able to demonstrate improved defenses against both cross-core
side channel attacks that target shared caches as well as same-core
attacks. Furthermore, Cauldron is transparent to the user - requiring no modi cation (or even recompilation) of users' application binaries by integrating directly with the popular container runtime framework, Docker. Preliminary evaluation results show that the proposed approach is effective for cloud computing applications.
Advisors/Committee Members: Campbell, Roy H (advisor), Bobba, Rakesh B (advisor).
Subjects/Keywords: Cache-based side-channel attacks; Cloud computing; Containers; Virtualization; Docker
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Manager
APA (6th Edition):
Ahmad, M. (2016). Cauldron: a framework to defend against cache-based side-channel attacks in clouds. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90967
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Ahmad, Mohammad. “Cauldron: a framework to defend against cache-based side-channel attacks in clouds.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed March 02, 2021.
http://hdl.handle.net/2142/90967.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Ahmad, Mohammad. “Cauldron: a framework to defend against cache-based side-channel attacks in clouds.” 2016. Web. 02 Mar 2021.
Vancouver:
Ahmad M. Cauldron: a framework to defend against cache-based side-channel attacks in clouds. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/2142/90967.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Ahmad M. Cauldron: a framework to defend against cache-based side-channel attacks in clouds. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90967
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Illinois – Urbana-Champaign
19.
Wang, He.
Applying multimodal sensing to human location estimation.
Degree: PhD, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign
URL: http://hdl.handle.net/2142/92743
► Mobile devices like smartphones and smartwatches are beginning to "stick" to the human body. Given that these devices are equipped with a variety of sensors,…
(more)
▼ Mobile devices like smartphones and smartwatches are beginning to "stick" to the human body. Given that these devices are equipped with a variety of sensors, they are becoming a natural platform to understand various aspects of human behavior. This dissertation will focus on just one dimension of human behavior, namely "location". We will begin by discussing our research on localizing humans in indoor environments, a problem that requires precise tracking of human footsteps. We investigated the benefits of leveraging smartphone sensors (accelerometers, gyroscopes, magnetometers, etc.) into the indoor localization framework, which breaks away from pure radio frequency based localization (e.g., cellular, WiFi). Our research leveraged inherent properties of indoor environments to perform localization. We also designed additional solutions, where computer vision was integrated with sensor fusion to offer highly precise localization. We will close this thesis with micro-scale tracking of the human wrist and demonstrate how motion data processing is indeed a "double-edged sword", offering unprecedented utility on one hand while breaching privacy on the other.
Advisors/Committee Members: Roy Choudhury, Romit (advisor), Vaidya, Nitin (Committee Chair), Lymberopoulos, Dimitrios (committee member), Nahrstedt, Klara (committee member).
Subjects/Keywords: sensing; location; visual fingerprinting; motion leaks; side-channel attacks; security
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APA (6th Edition):
Wang, H. (2016). Applying multimodal sensing to human location estimation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/92743
Chicago Manual of Style (16th Edition):
Wang, He. “Applying multimodal sensing to human location estimation.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 02, 2021.
http://hdl.handle.net/2142/92743.
MLA Handbook (7th Edition):
Wang, He. “Applying multimodal sensing to human location estimation.” 2016. Web. 02 Mar 2021.
Vancouver:
Wang H. Applying multimodal sensing to human location estimation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/2142/92743.
Council of Science Editors:
Wang H. Applying multimodal sensing to human location estimation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/92743
Clemson University
20.
Janefalkar, Tushar.
TOWARDS SECURING VIRTUALIZATION USING A RECONFIGURABLE PLATFORM.
Degree: MS, Computer Engineering, 2011, Clemson University
URL: https://tigerprints.clemson.edu/all_theses/1063
► Virtualization is no longer limited to main stream processors and servers. Virtualization software for General Purpose Processors (GPP) that allow one Operating System (OS) to…
(more)
▼ Virtualization is no longer limited to main stream processors and servers. Virtualization software for General Purpose Processors (GPP) that allow one Operating System (OS) to run as an application in another OS have become commonplace. To exploit the full potential of the available hardware, virtualization is now prevalent across all systems big and small. Besides GPPs, state-of-the-art embedded processors are now capable of running rich operating systems and their virtualization is now a hot topic of research. However, this technological progress also opens doors for attackers to snoop on data that is not only confined to storage servers but also transferred to and used in important transactions on mobile platforms. This work focuses on
side channel attacks that arise due to hardware resource sharing between two concurrently running processes. These
attacks can be in the form of monitoring cache accesses of a process or monitoring the power consumption of the system to determine the operation being performed. These
attacks are seemingly harmless as the attacking process does not perform any illegal operations to snoop on the information available through
side channels.
Side channel attacks have been used to easily decipher encryption keys for AES and RSA algorithms that are the two most commonly used encryption techniques. Software based solutions against these
side channel attacks have been documented but do not guarantee a complete solution as they are either too specific to one aspect of an attack or demand changes to the Instruction Set Architecture (ISA) or static hardware designs. Implementation of such solutions is not always feasible. In this project, we explore the virtualization of a PowerPC processor embedded on a Field Programmable Gate Array (FPGA) using the Kernel-based Virtual Machine (KVM). Then, we propose solutions that make use of the surrounding FPGA fabric to implement security measures that would make execution of
side channel attacks difficult. Lastly, this work provides detailed discussion on how to setup a development platform for FPGA-enabled hardware security, which involves cross compilation.
Advisors/Committee Members: Smith, Melissa C, Brooks , Richard R, Birchfield , Stanley.
Subjects/Keywords: FPGA; Hardware security; Side-channel attacks; Virtualization; Computer Engineering
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APA (6th Edition):
Janefalkar, T. (2011). TOWARDS SECURING VIRTUALIZATION USING A RECONFIGURABLE PLATFORM. (Masters Thesis). Clemson University. Retrieved from https://tigerprints.clemson.edu/all_theses/1063
Chicago Manual of Style (16th Edition):
Janefalkar, Tushar. “TOWARDS SECURING VIRTUALIZATION USING A RECONFIGURABLE PLATFORM.” 2011. Masters Thesis, Clemson University. Accessed March 02, 2021.
https://tigerprints.clemson.edu/all_theses/1063.
MLA Handbook (7th Edition):
Janefalkar, Tushar. “TOWARDS SECURING VIRTUALIZATION USING A RECONFIGURABLE PLATFORM.” 2011. Web. 02 Mar 2021.
Vancouver:
Janefalkar T. TOWARDS SECURING VIRTUALIZATION USING A RECONFIGURABLE PLATFORM. [Internet] [Masters thesis]. Clemson University; 2011. [cited 2021 Mar 02].
Available from: https://tigerprints.clemson.edu/all_theses/1063.
Council of Science Editors:
Janefalkar T. TOWARDS SECURING VIRTUALIZATION USING A RECONFIGURABLE PLATFORM. [Masters Thesis]. Clemson University; 2011. Available from: https://tigerprints.clemson.edu/all_theses/1063
Princeton University
21.
Liu, Fangfei.
Cache Side Channel Attacks and Secure Cache Architectures
.
Degree: PhD, 2016, Princeton University
URL: http://arks.princeton.edu/ark:/88435/dsp01h415pd02s
► With the number of cyber attacks escalating, it is crucial to protect the confidentiality and integrity of data and programs in our networked computer systems.…
(more)
▼ With the number of cyber
attacks escalating, it is crucial to protect the confidentiality and integrity of data and programs in our networked computer systems. Although strong cryptography can be used to encrypt and authenticate data, it is rendered useless if the secret keys can be leaked out. It turns out that this can be done easily through cache
side channel attacks. Today, all processors with caches are susceptible to cache
side channel attacks – this enables attackers to compromise all computers from smartphones to cloud computers. The goal of this dissertation is to design secure caches with built-in resistance to cache
side channel attacks. The rest part of the dissertation focuses on designing secure L1 caches using a moving target defense strategy. We first systematically study the security, performance and physical characteristics of Newcache, which can randomize where a data is located in the cache. We show the feasibility of designing Newcache, with comparable performance and power consumption as conventional
set-associative caches of the same size. We find that Newcache can defeat contention based
attacks, but is still susceptible to some reuse based
attacks. We further propose a novel random fill cache architecture to defeat the reuse based
attacks. A random fill cache can randomize when data is fetched into the cache, which only requires small changes to the cache controller and is complementary to Newcache. We further study
attacks and defenses on the last-level caches (LLC). In cloud computing, LLC
attacks may be more pertinent to the virtual machine co-residency threats, since the LLC is shared by all the cores in a processor package, while the L1 and L2 caches are typically core-private. The dissertation demonstrates the first practical LLC
attacks that can leak a private key used in a co-resident virtual machine.
To defeat these LLC
attacks, we propose a system solution, which leverages the Intel Cache Allocation Technology (CAT). This is a hardware feature newly introduced in Intel processors which we use for security enhancement instead. Our solution creates finer grained secure partitions, and can provide a strong security guarantee with negligible performance degradation.
Advisors/Committee Members: Lee, Ruby B (advisor).
Subjects/Keywords: cache;
commputer architecture;
information leakage;
security;
side channel attacks
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Manager
APA (6th Edition):
Liu, F. (2016). Cache Side Channel Attacks and Secure Cache Architectures
. (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01h415pd02s
Chicago Manual of Style (16th Edition):
Liu, Fangfei. “Cache Side Channel Attacks and Secure Cache Architectures
.” 2016. Doctoral Dissertation, Princeton University. Accessed March 02, 2021.
http://arks.princeton.edu/ark:/88435/dsp01h415pd02s.
MLA Handbook (7th Edition):
Liu, Fangfei. “Cache Side Channel Attacks and Secure Cache Architectures
.” 2016. Web. 02 Mar 2021.
Vancouver:
Liu F. Cache Side Channel Attacks and Secure Cache Architectures
. [Internet] [Doctoral dissertation]. Princeton University; 2016. [cited 2021 Mar 02].
Available from: http://arks.princeton.edu/ark:/88435/dsp01h415pd02s.
Council of Science Editors:
Liu F. Cache Side Channel Attacks and Secure Cache Architectures
. [Doctoral Dissertation]. Princeton University; 2016. Available from: http://arks.princeton.edu/ark:/88435/dsp01h415pd02s
University of Cincinnati
22.
Gohil, Nikhil N.
Design of DPA-Resistant Integrated Circuits.
Degree: MS, Engineering and Applied Science: Electrical
Engineering, 2017, University of Cincinnati
URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541
► During the recent past, Integrated Circuit (IC) technology has grown by leaps and bounds, with modern circuits capable of performing tasks at an extremely efficient…
(more)
▼ During the recent past, Integrated Circuit (IC)
technology has grown by leaps and bounds, with modern circuits
capable of performing tasks at an extremely efficient rate. Along
with the increase in usage of IC’s there is a growing need to
safeguard important information that these circuits process. In
addition, cryptographic devices providing security-centric
functions are widely used in applications such as secure
communication (encrypted messaging) and identification (digital
signatures, smart- card authorization). Increased reliability on
such devices for important applications has led to a multitude of
attacks being developed to attack these IC’s. Although many
mathematically secure algorithms have been proposed, a device is
still vulnerable when implemented in hardware because of data
leakage through
side-channels such as power consumption, timing
delay etc.This thesis focuses on Differential Power Analysis (DPA)
attacks, a class of
attacks that exploit data dependent power
consumption of devices implemented using CMOS (Complimentary
Metal-Oxide-Semiconductor) logic. Several circuit level counterme-
asures have been proposed to increase resistance to DPA
attacks.
Secure Differential Multiplexer based Logic using Pass Transistors
(SDMLp) developed in the Digital Design Environments Lab at the
University of Cincinnati is one such alternative to CMOS
technology.In this thesis, we test several flip-flop styles to
gauge the impact of sequential elements of a circuit on DPA
attacks. We then propose a design flow using the tested flip-flops
and SDMLp to enable implementation of DPA resistant logic circuits.
We attack AES and DES implementations using both SDMLp and CMOS and
show that the SDMLp implementations are DPA
resistant.
Advisors/Committee Members: Vemuri, Ranganadha (Committee Chair).
Subjects/Keywords: Engineering; Hardware Security; SDMLp; DPA; Side Channel Attacks
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APA (6th Edition):
Gohil, N. N. (2017). Design of DPA-Resistant Integrated Circuits. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541
Chicago Manual of Style (16th Edition):
Gohil, Nikhil N. “Design of DPA-Resistant Integrated Circuits.” 2017. Masters Thesis, University of Cincinnati. Accessed March 02, 2021.
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541.
MLA Handbook (7th Edition):
Gohil, Nikhil N. “Design of DPA-Resistant Integrated Circuits.” 2017. Web. 02 Mar 2021.
Vancouver:
Gohil NN. Design of DPA-Resistant Integrated Circuits. [Internet] [Masters thesis]. University of Cincinnati; 2017. [cited 2021 Mar 02].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541.
Council of Science Editors:
Gohil NN. Design of DPA-Resistant Integrated Circuits. [Masters Thesis]. University of Cincinnati; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541
Université de Bordeaux I
23.
Andouard, Philippe.
Outils d'aide à la recherche de vulnérabilités dans l'implantation d'applications embarquées sur carte à puce : New generation of high dynamic range vision systems.
Degree: Docteur es, Informatique, 2009, Université de Bordeaux I
URL: http://www.theses.fr/2009BOR13958
► Les travaux présentés dans cette thèse ont pour objectif de faciliter les évaluations sécuritaires des logiciels embarqués dans les cartes à puce. En premier lieu,…
(more)
▼ Les travaux présentés dans cette thèse ont pour objectif de faciliter les évaluations sécuritaires des logiciels embarqués dans les cartes à puce. En premier lieu, nous avons mis au point un environnement logiciel dédié à l'analyse de la résistance d'implémentations d'algorithmes cryptographiques face à des attaques par analyse de la consommation de courant. Cet environnement doit être vu comme un outil pour rechercher des fuites d'information dans une implémentation en vue d'évaluer la faisabilité d'une attaque sur le produit réel. En second lieu, nous nous sommes intéressé à l'analyse de programmes écrits en langage d'assemblage AVR dans le but de vérifier s'ils sont vulnérables aux sl{timing attacks}. Nous avons donc développé un outil qui consiste à décrire des chemins du flot de contrôle d'un programme grâce à des expressions régulières qui seront par la suite interprétées par notre outil afin de donner leur temps exact d'exécution (en terme de cycles d'horloge). Enfin, nous avons étudié comment faciliter la compréhension de programmes écrits en langage C dans le but de vérifier si des politiques de sécurité sont correctement implémentées. D'une part, nous fournissons des assistants de navigation qui au travers d'informations concernant les variables et procédures rencontrées, facilitent la compréhension du programme. D'autre part, nous avons au point une manière de vérifier les politiques de sécurité sans modélisation préalable (e.g. avec un automate à états finis) au moyen de requêtes exprimées dans la logique CTL.
The work presented in this thesis aims at easing the evaluation process of smartcards embedded software. On one hand, we set up a software environment dedicated to analyze the implementation resistance of cryptographic to power analysis attacks. This environment must be seen as a tool that facilitates a real attack by giving a way to find information leakages in an implementation. On the other hand, we focused on analyzing program written in AVR assembly language in order to check whether they are vulnerable to timing attacks. To achieve this goal we have developed a tool that makes possible the description of a path in the control flow of the program thanks to regular expressions. Those regular expressions will be interpreted by our tool in order to give the exact execution timing (expressed in clock cycles). Finally, we studied how to ease the global comprehension of a program written in C language in order to check whether security policies are well implemented. First, we provide graphical navigation assisants that helps to understand the progam being analyzed by giving information on variables and procedures. Then, we provide a way to check the security policies through the use of requests expressed with the CTL logic. This approach does not need prior modelisation of the program.
Advisors/Committee Members: Ly, Olivier (thesis director), Mosbah, Mohamed (thesis director).
Subjects/Keywords: Carte à puce; Sécurité; Side channel attacks; Langage d'assemblage AVR; Langage C; Smartcard; Security; Microcontrollers; Side channel attacks; AVR assembly language; C language
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Manager
APA (6th Edition):
Andouard, P. (2009). Outils d'aide à la recherche de vulnérabilités dans l'implantation d'applications embarquées sur carte à puce : New generation of high dynamic range vision systems. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2009BOR13958
Chicago Manual of Style (16th Edition):
Andouard, Philippe. “Outils d'aide à la recherche de vulnérabilités dans l'implantation d'applications embarquées sur carte à puce : New generation of high dynamic range vision systems.” 2009. Doctoral Dissertation, Université de Bordeaux I. Accessed March 02, 2021.
http://www.theses.fr/2009BOR13958.
MLA Handbook (7th Edition):
Andouard, Philippe. “Outils d'aide à la recherche de vulnérabilités dans l'implantation d'applications embarquées sur carte à puce : New generation of high dynamic range vision systems.” 2009. Web. 02 Mar 2021.
Vancouver:
Andouard P. Outils d'aide à la recherche de vulnérabilités dans l'implantation d'applications embarquées sur carte à puce : New generation of high dynamic range vision systems. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2009. [cited 2021 Mar 02].
Available from: http://www.theses.fr/2009BOR13958.
Council of Science Editors:
Andouard P. Outils d'aide à la recherche de vulnérabilités dans l'implantation d'applications embarquées sur carte à puce : New generation of high dynamic range vision systems. [Doctoral Dissertation]. Université de Bordeaux I; 2009. Available from: http://www.theses.fr/2009BOR13958
University of Bristol
24.
Green, Joseph A. F.
A study of inference-based attacks with neural network classifiers.
Degree: PhD, 2019, University of Bristol
URL: http://hdl.handle.net/1983/de93265f-81c8-40e6-bbbc-b20514f8a47d
► Belief Propagation is a message-passing algorithm used to propagate information in probabilistic graphical models. In 2014 it was shown that, in theory, Belief Propagation can…
(more)
▼ Belief Propagation is a message-passing algorithm used to propagate information in probabilistic graphical models. In 2014 it was shown that, in theory, Belief Propagation can be applied to Side Channel Analysis through an approach in which one can recover information on the secret data of a cryptographic encryption algorithm by observing variations in power consumption or electromagnetic radiation. In this thesis we explore the viability of such an attack in a real-world scenario and devise implementations to make the approach tractable in terms of its algorithmic and data complexity. We explore the construction of a factor graph (a bipartite graphical representation) of the AES cryptographic algorithm, showing that not all leakage points are useful in an attack. We propose implementation improvements that significantly reduce its memory overhead. We also provide a method that guarantees convergence at the cost of a small amount of information loss. We demonstrate that a combination of these proposed methods yields a significantly improved attack in terms of memory complexity and practical runtime. Neural networks have been applied to assist profiled side channel attacks. We contribute a new application of neural networks for inference based attacks in which we train networks for the variable nodes existing in the factor graph representation of AES. We show that popular network structures do not guarantee positive results and demonstrate that choice of performance metrics is critical in order to obtain stable results. Our analysis indicates that there is no 'one size fits all' model. However, we produce a network that yields reasonable classification across all important intermediates. The results are compared to other profiling methods in two ways: through per-trace classification, and a combined approach using the Belief Propagation algorithm. We observe that the neural network assisted Belief Propagation attack outperforms classical profiling methods such as Gaussian Templating and Linear Discriminant Analysis.
Subjects/Keywords: 004; Belief Propagation; Cryptography; Python; Side Channel Attacks; Deep Learning; Machine Learning
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APA (6th Edition):
Green, J. A. F. (2019). A study of inference-based attacks with neural network classifiers. (Doctoral Dissertation). University of Bristol. Retrieved from http://hdl.handle.net/1983/de93265f-81c8-40e6-bbbc-b20514f8a47d
Chicago Manual of Style (16th Edition):
Green, Joseph A F. “A study of inference-based attacks with neural network classifiers.” 2019. Doctoral Dissertation, University of Bristol. Accessed March 02, 2021.
http://hdl.handle.net/1983/de93265f-81c8-40e6-bbbc-b20514f8a47d.
MLA Handbook (7th Edition):
Green, Joseph A F. “A study of inference-based attacks with neural network classifiers.” 2019. Web. 02 Mar 2021.
Vancouver:
Green JAF. A study of inference-based attacks with neural network classifiers. [Internet] [Doctoral dissertation]. University of Bristol; 2019. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/1983/de93265f-81c8-40e6-bbbc-b20514f8a47d.
Council of Science Editors:
Green JAF. A study of inference-based attacks with neural network classifiers. [Doctoral Dissertation]. University of Bristol; 2019. Available from: http://hdl.handle.net/1983/de93265f-81c8-40e6-bbbc-b20514f8a47d
25.
Αντωνόπουλος, Αλέξανδρος.
Παροχή ασφαλών υπηρεσιών με φερέγγυες υποδομές.
Degree: 2009, University of Patras
URL: http://hdl.handle.net/10889/6841
► H διατριβή αντιμετωπίζει το πρόβλημα της σχεδίασης ασφαλών υποσυστημάτων που μπορούν να υπάρξουν σε μη-εμπιστεύσιμα συστήματα διασφαλίζοντας τη δική τους ασφάλεια στο μεγαλύτερο δυνατό βαθμό.…
(more)
▼ H διατριβή αντιμετωπίζει το πρόβλημα της σχεδίασης ασφαλών υποσυστημάτων που μπορούν να υπάρξουν σε μη-εμπιστεύσιμα συστήματα διασφαλίζοντας τη δική τους ασφάλεια στο μεγαλύτερο δυνατό βαθμό. Στα πλαίσια της διατριβής προσεγγίστικε το πρόβλημα της ασφάλειας γενικά εντοπίζοντας παράλληλα περιοχές οι οποίες κρίθηκαν σημαντικές για περαιτέρω διερεύνηση.
Αρχικά παρουσιάζεται η μεθοδολογία που ακολουθήθηκε για το σχεδιασμό και την ανάπτυξη αρχιτεκτονικής ασφάλειας για ένα δικτυο-κεντρικό σύστημα.
Εστιάζοντας στα ενσωματωμένα συστήματα εξετάστηκαν θέματα απόδοσης κρυπτογραφίας μνήμης δεδομένου ότι η κρυπτογραφία μνήμης αποτελεί βασικό κομμάτι για την ασφάλεια ενός ενσωματωμένου συστήματος. Στη συνέχεια εξετάζεται ένα είδος επίθεσης πλαγίου καναλιού και εισάγεται μια μεθοδολογία προστασίας από μια τέτοια επίθεση.
Δεδομένου ότι θέματα ασφαλείας που υπάρχουν σε συστήματα γενικού σκοπού μπορούν να αποτελέσουν μελλοντικούς κινδύνους για συστήματα ενσωματωμένου σκοπού παράλληλα με την επίβλεψη/υποστήριξη διπλωματικών εργασιών αναπτύχθηκαν λύσεις για ασφαλή εκκίνηση όπως και για τον εντοπισμό και αφαίρεση rootkit.
Τέλος ως «τελευταίο» επίπεδο και δεδομένου ότι όλα τα συστήματα χρησιμοποιούνται για την ποιοτική και ασφαλή λειτουργία μιας υπηρεσίας, η διατριβή εστίασε σε θέματα ασφαλειας στο επίπεδο των εφαρμογών. Παρουσιάζεται μια μελέτη του Spam και μεθοδολογία καταπολέμησης του και τέλος επιθέσεις cross-scripting και εφαρμογή για την ανίχνευση μη επιθυμητών συναλλαγών που πραγματοποιούνται από κακόβουλες εφαρμογές.
This dissertation addresses the problem of designing secure subsystems that can exist in non-trusted infrastructures ensuring their own safety to the greatest extent possible. The problem of security was approached in a holistic view identifying areas important for further investigation.
Initially we present the methodology used for the design and development of the security architecture for a network-centric system.
Later we focus on embedded systems were the performance of memory encryption was examined, since memory encryption can be crucial for embedded system security. Side- channel attacks are also presented and a methodology for protection against such attacks is presented.
Keeping in mind that the increase in power in embedded systems makes even more complicated attacks possible solutions were developed for secure boot and for identifying and removing rootkit.
At last "last" and with the idea that all sub-systems are used for the qualitative and safe operation of a service, dissertation focused on security issues at the application level. A study of Spam is presented along with a fight-back methodology. Finally cross-scripting attacks are presented.
Advisors/Committee Members: Σερπάνος, Δημήτριος, Antonopoulos, Alexandros, Χούσος, Ευθύμιος, Θραμπουλίδης, Κλεάνθης, Κουμπιάς, Σταύρος, Γκούτης, Κωνσταντίνος, Καξίρας, Στέφανος, Γαροφαλάκης, Ιωάννης, Σερπάνος, Δημήτριος.
Subjects/Keywords: Ασφάλεια; Αρχιτεκτονική ασφαλείας; Επιθέσεις πλαγίου καναλιού; 005.8; Security; Security architecture; Side-channel attacks
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Αντωνόπουλος, . (2009). Παροχή ασφαλών υπηρεσιών με φερέγγυες υποδομές. (Doctoral Dissertation). University of Patras. Retrieved from http://hdl.handle.net/10889/6841
Chicago Manual of Style (16th Edition):
Αντωνόπουλος, Αλέξανδρος. “Παροχή ασφαλών υπηρεσιών με φερέγγυες υποδομές.” 2009. Doctoral Dissertation, University of Patras. Accessed March 02, 2021.
http://hdl.handle.net/10889/6841.
MLA Handbook (7th Edition):
Αντωνόπουλος, Αλέξανδρος. “Παροχή ασφαλών υπηρεσιών με φερέγγυες υποδομές.” 2009. Web. 02 Mar 2021.
Vancouver:
Αντωνόπουλος . Παροχή ασφαλών υπηρεσιών με φερέγγυες υποδομές. [Internet] [Doctoral dissertation]. University of Patras; 2009. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/10889/6841.
Council of Science Editors:
Αντωνόπουλος . Παροχή ασφαλών υπηρεσιών με φερέγγυες υποδομές. [Doctoral Dissertation]. University of Patras; 2009. Available from: http://hdl.handle.net/10889/6841
26.
Carmona, Manuel Bejarano.
A simple and low cost platform to perform Power Analysis Attacks.
Degree: 2012, , School of Engineering
URL: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5811
► Power Analysis Attacks use the fact that power consumption in modern microprocessors and cryptographic devices depends on the instructions executed on them and so,…
(more)
▼ Power Analysis Attacks use the fact that power consumption in modern microprocessors and cryptographic devices depends on the instructions executed on them and so, it varies with time. This leak- age is mainly used to deduce cryptographic keys as well as algorithms by direct observation of power traces. Power Analysis is a recent field of study that has been developed for the last decade. Since then, the techniques used have evolved into more complex forms, that some- times require a variety of skills that makes the subject difficult to start with. Nowadays it is changeling to tackle the problem without expen- sive equipment; what is more, the off-the-shelf solutions to do Power Analysis Attacks are rare and expensive. This thesis aim to provide a low cost and open platform as an entry point to Power Analysis for a price under 10 USD. Besides that, it is designed to be able to per- form Simple Power Analysis and Differential Power Analysis attacks to a 8 bit microcontroller, including the software needed to automate the process of taking the measurements. Finally, the platform can be extended to cover a wide range of microcontrollers, microprocessors and cryptographic devices by simple insertion in a bread board, which makes it the perfect device for new comers to the field.
Subjects/Keywords: power analysis side channel attacks spa dpa simple differential; Computer Sciences; Datavetenskap (datalogi); Telecommunications; Telekommunikation
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Export
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Manager
APA (6th Edition):
Carmona, M. B. (2012). A simple and low cost platform to perform Power Analysis Attacks. (Thesis). , School of Engineering. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5811
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Carmona, Manuel Bejarano. “A simple and low cost platform to perform Power Analysis Attacks.” 2012. Thesis, , School of Engineering. Accessed March 02, 2021.
http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5811.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Carmona, Manuel Bejarano. “A simple and low cost platform to perform Power Analysis Attacks.” 2012. Web. 02 Mar 2021.
Vancouver:
Carmona MB. A simple and low cost platform to perform Power Analysis Attacks. [Internet] [Thesis]. , School of Engineering; 2012. [cited 2021 Mar 02].
Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5811.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Carmona MB. A simple and low cost platform to perform Power Analysis Attacks. [Thesis]. , School of Engineering; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5811
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
27.
Jauvart, Damien.
Sécurisation des algorithmes de couplages contre les attaques physiques : Security of pairing algorithms against physical attacks.
Degree: Docteur es, Informatique, 2017, Université Paris-Saclay (ComUE)
URL: http://www.theses.fr/2017SACLV059
► Cette thèse est consacrée à l’étude de la sécurité physique des algorithmesde couplage. Les algorithmes de couplage sont depuis une quinzaine d’années utilisésà des fins…
(more)
▼ Cette thèse est consacrée à l’étude de la sécurité physique des algorithmesde couplage. Les algorithmes de couplage sont depuis une quinzaine d’années utilisésà des fins cryptographiques. D’une part, les systèmes d’information évoluent, et denouveaux besoins de sécurité apparaissent. Les couplages permettent des protocolesinnovants, tels que le chiffrement basé sur l’identité, les attributs et l’échange tripartien un tour. D’autre part, l’implémentation des algorithmes de couplages est devenueefficace, elle permet ainsi d’intégrer des solutions cryptographiques à base de couplagedans les systèmes embarqués.La problématique de l’implémentation sécurisée des couplages dans les systèmesembarqués va être étudiée ici. En effet, l’implémentation d’algorithmes dédiés à lacryptographie sur les systèmes embarqués soulève une problématique : la sécurité del’implémentation des couplages face aux attaques physiques. Les attaques par canauxauxiliaires, dites passives, contre les algorithmes de couplages sont connues depuisbientôt une dizaine d’années. Nous proposons des études pour valider l’efficacité desattaques en pratique et avec des atouts théoriques. De notre connaissance, il y a uneseule attaque pratique dans la littérature, nous l’optimisons d’un facteur dix en termesde nombres de traces. Nous proposons aussi une attaque horizontale, qui nous permetd’attaquer le couplage twisted Ate en une seule trace.Par ailleurs, les contre-mesures n’ont été que peu étudiées. Nous complétons cettepartie manquante de la littérature. Nous proposons de nouveaux modèles d’attaquessur la contre-mesure de randomisation des coordonnées. L’attaque en collision proposéepermet ainsi de donner une réévaluation de la contre-mesure ciblée. Ainsi nousproposons la combinaison de contre-mesures qui, à moindres coûts, protégerait de cesattaques.
This thesis focuses on the resistance of Pairing implementations againstside channel attacks. Pairings have been studied as a cryptographic tool for the pastfifteen years and have been of a growing interest lately. On one hand, Pairings allowthe implementation of innovative protocols such as identity based encryption, attributebased encryption or one round tripartite exchange to address the evolving needs ofinformation systems. On the other hand, the implementation of the pairings algorithmshave become more efficient, allowing their integration into embedded systems.Like for most cryptographic algorithms, side channel attack schemes have beenproposed against Pairing implementations. However most of the schemes describedin the literature so far have had very little validation in practice. In this thesis, westudy the practical feasibility of such attacks by proposing a technique for optimizingcorrelation power analysis on long precision numbers. We hence improve by a factorof 10 the number of side-channel leakage traces needed to recover a 256-bit secret keycompared to what is, to our best knowledge, one of the rare practical implementationsof side channel attacks published. We also propose a horizontal attack,…
Advisors/Committee Members: Goubin, Louis (thesis director), Fournier, Jacques J. A. (thesis director), El Mrabet, Nadia (thesis director).
Subjects/Keywords: Cryptographie; Couplages; Attaques par canaux auxiliaires; Contre-Mesures; Cryptography; Pairings; Side-Channel attacks; Countermeasures
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Export
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Manager
APA (6th Edition):
Jauvart, D. (2017). Sécurisation des algorithmes de couplages contre les attaques physiques : Security of pairing algorithms against physical attacks. (Doctoral Dissertation). Université Paris-Saclay (ComUE). Retrieved from http://www.theses.fr/2017SACLV059
Chicago Manual of Style (16th Edition):
Jauvart, Damien. “Sécurisation des algorithmes de couplages contre les attaques physiques : Security of pairing algorithms against physical attacks.” 2017. Doctoral Dissertation, Université Paris-Saclay (ComUE). Accessed March 02, 2021.
http://www.theses.fr/2017SACLV059.
MLA Handbook (7th Edition):
Jauvart, Damien. “Sécurisation des algorithmes de couplages contre les attaques physiques : Security of pairing algorithms against physical attacks.” 2017. Web. 02 Mar 2021.
Vancouver:
Jauvart D. Sécurisation des algorithmes de couplages contre les attaques physiques : Security of pairing algorithms against physical attacks. [Internet] [Doctoral dissertation]. Université Paris-Saclay (ComUE); 2017. [cited 2021 Mar 02].
Available from: http://www.theses.fr/2017SACLV059.
Council of Science Editors:
Jauvart D. Sécurisation des algorithmes de couplages contre les attaques physiques : Security of pairing algorithms against physical attacks. [Doctoral Dissertation]. Université Paris-Saclay (ComUE); 2017. Available from: http://www.theses.fr/2017SACLV059
Delft University of Technology
28.
Pop, Marius (author).
Interpreting Information of Deep Neural Networks for Profiled Side Channel Analysis.
Degree: 2019, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:f21cf646-fb91-4c2c-97bb-6bc6eb2f00c1
► Security has become ever more important in today's quickly growing digital world as the number of digital assets has quickly grown. Our thesis focuses on…
(more)
▼ Security has become ever more important in today's quickly growing digital world as the number of digital assets has quickly grown. Our thesis focuses on devices that compute a secure cryptographic operation such that information can be communicated or authenticated. The attack vector utilized is known as Profiled Side-Channel Analysis (SCA) which aims at extracting a cryptographic key from a device through unintended behavior expressed through power monitoring or electromagnetic radiation. Profiled SCA attacks assume the most powerful adversary and therefore allows us to make a sound security assessment of a device in this setting. Our utilized profiling technique includes deep neural networks such as the multi-layer perceptron and the convolutional neural network. As this adds a layer of complexity to our assessment, we must understand how the properties of the network consolidate our security assessment. Previous research has shown that classical neural network metrics such as accuracy does not correlate to how successful or efficient a side-channel analysis is, therefore, we have proposed a mutual information metric. We measure mutual information across each layer in the neural network such that the behavior of each layer in interpreting how each layer is benefiting our classification. We investigate if the mutual information measure can be used to make a beneficial architectural distinction of the neural network for our side-channel analysis problem. Finally, we show there is a relationship between the mutual information and the guessing entropy for our side-channel attack and that it can be used to confirm that the chosen model is fully optimized for the side-channel problem.
Cyber Security | Data science and technology
Advisors/Committee Members: Picek, Stjepan (mentor), Erkin, Zekeriya (graduation committee), Isufi, Elvin (graduation committee), Delft University of Technology (degree granting institution).
Subjects/Keywords: Side-Channel Attacks; Deep Learning; Mutual Information; Convolutional Neural Network; Neural Network; Machine Learning
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APA ·
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APA (6th Edition):
Pop, M. (. (2019). Interpreting Information of Deep Neural Networks for Profiled Side Channel Analysis. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f21cf646-fb91-4c2c-97bb-6bc6eb2f00c1
Chicago Manual of Style (16th Edition):
Pop, Marius (author). “Interpreting Information of Deep Neural Networks for Profiled Side Channel Analysis.” 2019. Masters Thesis, Delft University of Technology. Accessed March 02, 2021.
http://resolver.tudelft.nl/uuid:f21cf646-fb91-4c2c-97bb-6bc6eb2f00c1.
MLA Handbook (7th Edition):
Pop, Marius (author). “Interpreting Information of Deep Neural Networks for Profiled Side Channel Analysis.” 2019. Web. 02 Mar 2021.
Vancouver:
Pop M(. Interpreting Information of Deep Neural Networks for Profiled Side Channel Analysis. [Internet] [Masters thesis]. Delft University of Technology; 2019. [cited 2021 Mar 02].
Available from: http://resolver.tudelft.nl/uuid:f21cf646-fb91-4c2c-97bb-6bc6eb2f00c1.
Council of Science Editors:
Pop M(. Interpreting Information of Deep Neural Networks for Profiled Side Channel Analysis. [Masters Thesis]. Delft University of Technology; 2019. Available from: http://resolver.tudelft.nl/uuid:f21cf646-fb91-4c2c-97bb-6bc6eb2f00c1
Delft University of Technology
29.
Samiotis, Ioannis Petros (author).
Side-Channel Attacks using Convolutional Neural Networks: A Study on the performance of Convolutional Neural Networks on side-channel data.
Degree: 2018, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:2e203eee-4c38-4c86-a92a-db94d0ffc34c
► Side-Channel Attacks, are a prominent type of attacks, used to break cryptographic implementations on a computing system. They are based on information "leaked" by the…
(more)
▼ Side-
Channel Attacks, are a prominent type of
attacks, used to break cryptographic implementations on a computing system. They are based on information "leaked" by the hardware of a computing system, rather than the encryption algorithm itself. Recent studies showed that
Side-
Channel Attacks can be performed using Deep Learning models. In this study, we examine the performance of Convolutional Neural Networks, on four different datasets of
side-
channel data and we compare our models with conventional Machine Learning algorithms and a CNN model from literature. We found that CNNs have the potential to achieve high accuracy performance (99.8%), although their capacity is heavily influenced by the use case. We also found that certain Machine Learning algorithms can outperform CNNs in certain cases, leaving an open debate on the performance gains of the latter.
Advisors/Committee Members: Picek, Stjepan (mentor), van der Lubbe, Jan (graduation committee), Hanjalic, Alan (graduation committee), Delft University of Technology (degree granting institution).
Subjects/Keywords: Side-Channel Attacks; Deep Learning; Convolutional Neural Networks; Machine Learning; optimization algorithms; Classification; cybersecurity
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APA ·
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Export
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APA (6th Edition):
Samiotis, I. P. (. (2018). Side-Channel Attacks using Convolutional Neural Networks: A Study on the performance of Convolutional Neural Networks on side-channel data. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:2e203eee-4c38-4c86-a92a-db94d0ffc34c
Chicago Manual of Style (16th Edition):
Samiotis, Ioannis Petros (author). “Side-Channel Attacks using Convolutional Neural Networks: A Study on the performance of Convolutional Neural Networks on side-channel data.” 2018. Masters Thesis, Delft University of Technology. Accessed March 02, 2021.
http://resolver.tudelft.nl/uuid:2e203eee-4c38-4c86-a92a-db94d0ffc34c.
MLA Handbook (7th Edition):
Samiotis, Ioannis Petros (author). “Side-Channel Attacks using Convolutional Neural Networks: A Study on the performance of Convolutional Neural Networks on side-channel data.” 2018. Web. 02 Mar 2021.
Vancouver:
Samiotis IP(. Side-Channel Attacks using Convolutional Neural Networks: A Study on the performance of Convolutional Neural Networks on side-channel data. [Internet] [Masters thesis]. Delft University of Technology; 2018. [cited 2021 Mar 02].
Available from: http://resolver.tudelft.nl/uuid:2e203eee-4c38-4c86-a92a-db94d0ffc34c.
Council of Science Editors:
Samiotis IP(. Side-Channel Attacks using Convolutional Neural Networks: A Study on the performance of Convolutional Neural Networks on side-channel data. [Masters Thesis]. Delft University of Technology; 2018. Available from: http://resolver.tudelft.nl/uuid:2e203eee-4c38-4c86-a92a-db94d0ffc34c
30.
Bao, Chongxi.
Hardware Attacks and Mitigation Techniques.
Degree: Electrical Engineering, 2017, University of Maryland
URL: http://hdl.handle.net/1903/19399
► Today, electronic devices have been widely deployed in our daily lives, basic infrastructure such as financial and communication systems, and military systems. Over the past…
(more)
▼ Today, electronic devices have been widely deployed in our daily lives, basic infrastructure such as financial and communication systems, and military systems. Over the past decade, there have been a growing number of threats against them, posing great danger on these systems. Hardware-based countermeasures offer a low-performance overhead for building secure systems. In this work, we investigate what hardware-based
attacks are possible against modern computers and electronic devices. We then explore several design and verification techniques to enhance hardware security with primary focus on two areas: hardware Trojans and
side-
channel attacks.
Hardware Trojans are malicious modifications to the original integrated circuits (ICs). Due to the trend of outsourcing designs to foundries overseas, the threat of hardware Trojans is increasing. Researchers have proposed numerous detection methods, which either take place at test-time or monitor the IC for unexpected behavior at run-time. Most of these methods require the possession of a Trojan-free IC, which is hard to obtain. In this work, we propose an innovative way to detect Trojans using reverse-engineering. Our method eliminates the need for a Trojan-free IC. In addition, it avoids the costly and error-prone steps in the reverse-engineering process and achieves significantly good detection accuracy. We also notice that in the current literature, very little effort has been made to design-time strategies that help to make test-time or run-time detection of Trojans easier. To address this issue, we develop techniques that can improve the sensitivity of designs to test-time detection approaches. Experiments show that using our method, we could detect a lot more Trojans with very small power/area overhead and no timing violations.
Side-
channel attack (SCA) is another form of hardware attack in which the adversary measures some
side-
channel information such as power, temperature, timing, etc. and deduces some critical information about the underlying system. We first investigate countermeasures for timing SCAs on cache. These
attacks have been demonstrated to be able to successfully break many widely-used modern ciphers. Existing hardware countermeasures usually have heavy performance overhead. We innovatively apply 3D integration techniques to solve the problem. We investigate the implication of 3D integration on timing SCAs on cache and propose several countermeasures that utilize 3D integration techniques. Experimental results show that our countermeasures increase system security significantly while still achieving some performance gain over a 2D baseline system. We also investigate the security of Oblivious RAM (ORAM), which is a newly proposed hardware primitive to hide memory access patterns. We demonstrate both through simulations and on FPGA board that timing SCAs can break many ORAM protocols. Some general guidelines in secure ORAM implementations are also provided. We hope that our findings will motivate a new line of research in making ORAMs more secure.
Advisors/Committee Members: Srivastava, Ankur (advisor).
Subjects/Keywords: Computer engineering; hardware security; hardware Trojan; ORAM; reverse-engineering; side-channel attacks
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APA (6th Edition):
Bao, C. (2017). Hardware Attacks and Mitigation Techniques. (Thesis). University of Maryland. Retrieved from http://hdl.handle.net/1903/19399
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Bao, Chongxi. “Hardware Attacks and Mitigation Techniques.” 2017. Thesis, University of Maryland. Accessed March 02, 2021.
http://hdl.handle.net/1903/19399.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Bao, Chongxi. “Hardware Attacks and Mitigation Techniques.” 2017. Web. 02 Mar 2021.
Vancouver:
Bao C. Hardware Attacks and Mitigation Techniques. [Internet] [Thesis]. University of Maryland; 2017. [cited 2021 Mar 02].
Available from: http://hdl.handle.net/1903/19399.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Bao C. Hardware Attacks and Mitigation Techniques. [Thesis]. University of Maryland; 2017. Available from: http://hdl.handle.net/1903/19399
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
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