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You searched for subject:(Shallow trench isolation). Showing records 1 – 5 of 5 total matches.

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Université de Grenoble

1. Tavernier, Aurélien. Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées : Developpement of an innovative process for shallow trench isolation gap-filling of advanced CMOS technology nodes.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2014, Université de Grenoble

Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre… (more)

Subjects/Keywords: Microélectronique; Tranchées d'isolation; CVD; Gravure; Film mince; Caractérisation; Microelectronic; Shallow trench isolation; CVD; Etching; Thin film; Characterization; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tavernier, A. (2014). Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées : Developpement of an innovative process for shallow trench isolation gap-filling of advanced CMOS technology nodes. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2014GRENT005

Chicago Manual of Style (16th Edition):

Tavernier, Aurélien. “Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées : Developpement of an innovative process for shallow trench isolation gap-filling of advanced CMOS technology nodes.” 2014. Doctoral Dissertation, Université de Grenoble. Accessed December 14, 2019. http://www.theses.fr/2014GRENT005.

MLA Handbook (7th Edition):

Tavernier, Aurélien. “Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées : Developpement of an innovative process for shallow trench isolation gap-filling of advanced CMOS technology nodes.” 2014. Web. 14 Dec 2019.

Vancouver:

Tavernier A. Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées : Developpement of an innovative process for shallow trench isolation gap-filling of advanced CMOS technology nodes. [Internet] [Doctoral dissertation]. Université de Grenoble; 2014. [cited 2019 Dec 14]. Available from: http://www.theses.fr/2014GRENT005.

Council of Science Editors:

Tavernier A. Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées : Developpement of an innovative process for shallow trench isolation gap-filling of advanced CMOS technology nodes. [Doctoral Dissertation]. Université de Grenoble; 2014. Available from: http://www.theses.fr/2014GRENT005


University of Minnesota

2. Marella, Sravan. Performance variations due to layout-dependent stress in VLSI circuits.

Degree: PhD, Electrical Engineering, 2015, University of Minnesota

 Layout-dependent stress is a significant source of variability in advanced VLSI technologies that impacts circuit performance. Mechanical stress affects transistor electrical parameters mobility and threshold… (more)

Subjects/Keywords: 3D-IC; FinFET; Layout dependent mechanical stress; Shallow trench isolation; Static Timing Analysis; Through silicon via

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APA (6th Edition):

Marella, S. (2015). Performance variations due to layout-dependent stress in VLSI circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/175249

Chicago Manual of Style (16th Edition):

Marella, Sravan. “Performance variations due to layout-dependent stress in VLSI circuits.” 2015. Doctoral Dissertation, University of Minnesota. Accessed December 14, 2019. http://hdl.handle.net/11299/175249.

MLA Handbook (7th Edition):

Marella, Sravan. “Performance variations due to layout-dependent stress in VLSI circuits.” 2015. Web. 14 Dec 2019.

Vancouver:

Marella S. Performance variations due to layout-dependent stress in VLSI circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2015. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/11299/175249.

Council of Science Editors:

Marella S. Performance variations due to layout-dependent stress in VLSI circuits. [Doctoral Dissertation]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/175249

3. Yu ZHANG. Portability-Aware CMOS Mixed Signal VLSI Circuit Design Methodology : ポータビリティを意識したCMOSミックスドシグナルVLSI回路設計手法に関する研究.

Degree: 博士, 2014, The University of Kitakyushu / 北九州市立大学

本研究は、半導体上に集積されたアナログ・ディジタル・メモリ回路から構成されるミクストシグナルシステムを別の製造プロセスへ移行することをポーティングとして定義し、効率的なポーティングを行うための設計方式と自動回路合成アルゴリズムを提案し、いくつかの典型的な回路に対する設計事例を示し、提案手法の妥当性を立証している。

Subjects/Keywords: layout-dependent effects(LDE); shallow trench isolation(STI); well proximity effect(WPE); integrated circuit; VLSI; geometric programming(GP); delay locked loop circuit(DLL); standard cell; memory; parameterized cell

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APA (6th Edition):

ZHANG, Y. (2014). Portability-Aware CMOS Mixed Signal VLSI Circuit Design Methodology : ポータビリティを意識したCMOSミックスドシグナルVLSI回路設計手法に関する研究. (Thesis). The University of Kitakyushu / 北九州市立大学. Retrieved from http://id.nii.ac.jp/1077/00000369/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

ZHANG, Yu. “Portability-Aware CMOS Mixed Signal VLSI Circuit Design Methodology : ポータビリティを意識したCMOSミックスドシグナルVLSI回路設計手法に関する研究.” 2014. Thesis, The University of Kitakyushu / 北九州市立大学. Accessed December 14, 2019. http://id.nii.ac.jp/1077/00000369/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

ZHANG, Yu. “Portability-Aware CMOS Mixed Signal VLSI Circuit Design Methodology : ポータビリティを意識したCMOSミックスドシグナルVLSI回路設計手法に関する研究.” 2014. Web. 14 Dec 2019.

Vancouver:

ZHANG Y. Portability-Aware CMOS Mixed Signal VLSI Circuit Design Methodology : ポータビリティを意識したCMOSミックスドシグナルVLSI回路設計手法に関する研究. [Internet] [Thesis]. The University of Kitakyushu / 北九州市立大学; 2014. [cited 2019 Dec 14]. Available from: http://id.nii.ac.jp/1077/00000369/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

ZHANG Y. Portability-Aware CMOS Mixed Signal VLSI Circuit Design Methodology : ポータビリティを意識したCMOSミックスドシグナルVLSI回路設計手法に関する研究. [Thesis]. The University of Kitakyushu / 北九州市立大学; 2014. Available from: http://id.nii.ac.jp/1077/00000369/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Dobri, Adam. Mémoires embarquées non volatiles à grille flottante : challenges technologiques et physiques pour l’augmentation des performances vers le noeud 28nm : Embedded Non-volatile 1T floating-gate memories : technological and physical challenges for augmenting performance towards the 28 nm node.

Degree: Docteur es, Nano electronique et nano technologies, 2017, Grenoble Alpes

Les mémoires flash sont intégrées dans presque tous les aspects de la vie moderne car leurs uns et zéros représentent les données stockées sur les… (more)

Subjects/Keywords: Mémoires Flash; Intégration dielectric haute permitivité; Autoalignment des canaux isolants; Flash memory; High-K dielectric integration; Self-Aligned shallow trench isolation; 600

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APA (6th Edition):

Dobri, A. (2017). Mémoires embarquées non volatiles à grille flottante : challenges technologiques et physiques pour l’augmentation des performances vers le noeud 28nm : Embedded Non-volatile 1T floating-gate memories : technological and physical challenges for augmenting performance towards the 28 nm node. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2017GREAT030

Chicago Manual of Style (16th Edition):

Dobri, Adam. “Mémoires embarquées non volatiles à grille flottante : challenges technologiques et physiques pour l’augmentation des performances vers le noeud 28nm : Embedded Non-volatile 1T floating-gate memories : technological and physical challenges for augmenting performance towards the 28 nm node.” 2017. Doctoral Dissertation, Grenoble Alpes. Accessed December 14, 2019. http://www.theses.fr/2017GREAT030.

MLA Handbook (7th Edition):

Dobri, Adam. “Mémoires embarquées non volatiles à grille flottante : challenges technologiques et physiques pour l’augmentation des performances vers le noeud 28nm : Embedded Non-volatile 1T floating-gate memories : technological and physical challenges for augmenting performance towards the 28 nm node.” 2017. Web. 14 Dec 2019.

Vancouver:

Dobri A. Mémoires embarquées non volatiles à grille flottante : challenges technologiques et physiques pour l’augmentation des performances vers le noeud 28nm : Embedded Non-volatile 1T floating-gate memories : technological and physical challenges for augmenting performance towards the 28 nm node. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2017. [cited 2019 Dec 14]. Available from: http://www.theses.fr/2017GREAT030.

Council of Science Editors:

Dobri A. Mémoires embarquées non volatiles à grille flottante : challenges technologiques et physiques pour l’augmentation des performances vers le noeud 28nm : Embedded Non-volatile 1T floating-gate memories : technological and physical challenges for augmenting performance towards the 28 nm node. [Doctoral Dissertation]. Grenoble Alpes; 2017. Available from: http://www.theses.fr/2017GREAT030

5. Rezzak, Nadia. Total ionizing dose effects in advanced CMOS technologies.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

 Key aspects of the total-ionizing dose (TID) response of advanced complementary metalâoxideâsemiconductor (CMOS) technologies are examined. As technology scales down, stress can strongly affect radiation-induced… (more)

Subjects/Keywords: Fully depleted SOI; Partially depleted SOI; Variability; total ionizing dose (TID); sidewall doping; shallow trench isolation (STI); MOSFET off-state leakage current; mechanical stress; Active space distance

…with shallow-trench isolation (STI) for advanced submicron technologies due to… …11 Fig. 1.8. TEM of shallow trench isolation that is recessed below the silicon active… …the system. Shallow trench isolation (STI)-induced mechanical stress increases… …of features, including geometry and type of trench refill oxide. C. Shallow trench… …58 Fig. 5.1. The pre-irradiation off-state leakage current evolution with trench-recess… 

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APA (6th Edition):

Rezzak, N. (2012). Total ionizing dose effects in advanced CMOS technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12212012-123125/ ;

Chicago Manual of Style (16th Edition):

Rezzak, Nadia. “Total ionizing dose effects in advanced CMOS technologies.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed December 14, 2019. http://etd.library.vanderbilt.edu/available/etd-12212012-123125/ ;.

MLA Handbook (7th Edition):

Rezzak, Nadia. “Total ionizing dose effects in advanced CMOS technologies.” 2012. Web. 14 Dec 2019.

Vancouver:

Rezzak N. Total ionizing dose effects in advanced CMOS technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2019 Dec 14]. Available from: http://etd.library.vanderbilt.edu/available/etd-12212012-123125/ ;.

Council of Science Editors:

Rezzak N. Total ionizing dose effects in advanced CMOS technologies. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-12212012-123125/ ;

.