Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Scratchpad). Showing records 1 – 30 of 30 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


Arizona State University

1. Cai, Jian. Scratchpad Management in Software Managed Manycore Architectures.

Degree: Computer Science, 2017, Arizona State University

 Caches have long been used to reduce memory access latency. However, the increased complexity of cache coherence brings significant challenges in processor design as the… (more)

Subjects/Keywords: Computer science; compiler; multicore; scratchpad memory; SPM

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cai, J. (2017). Scratchpad Management in Software Managed Manycore Architectures. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/46214

Chicago Manual of Style (16th Edition):

Cai, Jian. “Scratchpad Management in Software Managed Manycore Architectures.” 2017. Doctoral Dissertation, Arizona State University. Accessed January 25, 2021. http://repository.asu.edu/items/46214.

MLA Handbook (7th Edition):

Cai, Jian. “Scratchpad Management in Software Managed Manycore Architectures.” 2017. Web. 25 Jan 2021.

Vancouver:

Cai J. Scratchpad Management in Software Managed Manycore Architectures. [Internet] [Doctoral dissertation]. Arizona State University; 2017. [cited 2021 Jan 25]. Available from: http://repository.asu.edu/items/46214.

Council of Science Editors:

Cai J. Scratchpad Management in Software Managed Manycore Architectures. [Doctoral Dissertation]. Arizona State University; 2017. Available from: http://repository.asu.edu/items/46214


University of Waterloo

2. Prakash, Aayush. An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.

Degree: 2012, University of Waterloo

 This work presents a static instruction allocation scheme for the precision timed architecture’s (PRET) scratchpad memory. Since PRET provides timing instructions to control the temporal… (more)

Subjects/Keywords: memory allocation; precision timed architecture; scratchpad memory

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prakash, A. (2012). An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/7159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prakash, Aayush. “An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.” 2012. Thesis, University of Waterloo. Accessed January 25, 2021. http://hdl.handle.net/10012/7159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prakash, Aayush. “An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.” 2012. Web. 25 Jan 2021.

Vancouver:

Prakash A. An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture. [Internet] [Thesis]. University of Waterloo; 2012. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/10012/7159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prakash A. An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture. [Thesis]. University of Waterloo; 2012. Available from: http://hdl.handle.net/10012/7159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

3. Peterson, Thomas. Dynamic Allocation for Embedded Heterogeneous Memory : An Empirical Study.

Degree: Electrical Engineering and Computer Science (EECS), 2018, KTH

Embedded systems are omnipresent and contribute to our lives in many ways by instantiating functionality in larger systems. To operate, embedded systems require well-functioning… (more)

Subjects/Keywords: Memory management; NVRAM; Scratchpad memory; Embedded systems; Minneshantering; NVRAM; Scratchpad minne; Inbyggda system; Information Systems; Systemvetenskap, informationssystem och informatik

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Peterson, T. (2018). Dynamic Allocation for Embedded Heterogeneous Memory : An Empirical Study. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223904

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Peterson, Thomas. “Dynamic Allocation for Embedded Heterogeneous Memory : An Empirical Study.” 2018. Thesis, KTH. Accessed January 25, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223904.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Peterson, Thomas. “Dynamic Allocation for Embedded Heterogeneous Memory : An Empirical Study.” 2018. Web. 25 Jan 2021.

Vancouver:

Peterson T. Dynamic Allocation for Embedded Heterogeneous Memory : An Empirical Study. [Internet] [Thesis]. KTH; 2018. [cited 2021 Jan 25]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223904.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Peterson T. Dynamic Allocation for Embedded Heterogeneous Memory : An Empirical Study. [Thesis]. KTH; 2018. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223904

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Wu, Cheng-Ying. A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

Scratchpad memory (SPM) is popular for real-time embedded systems. Whereas caches use a memory management unit (MMU) to control which data accesses go to the… (more)

Subjects/Keywords: memory allocation; WCET; ACET; scratchpad memory; real-time systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (2009). A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810109-230024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Cheng-Ying. “A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time.” 2009. Thesis, NSYSU. Accessed January 25, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810109-230024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Cheng-Ying. “A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time.” 2009. Web. 25 Jan 2021.

Vancouver:

Wu C. A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Jan 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810109-230024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810109-230024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

5. De Francis, Michael. Schedulability-driven scratchpad memory swapping for resource-constrained real-time embedded systems.

Degree: Computer Engineering, 2012, Rochester Institute of Technology

 In resource-constrained real-time embedded systems, scratchpad memory (SPM) is utilized in place of cache to increase performance and enforce consistent behavior of both hard and… (more)

Subjects/Keywords: Embedded systems; Real-time systems; Scratchpad memory; SDAWS; SPM

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

De Francis, M. (2012). Schedulability-driven scratchpad memory swapping for resource-constrained real-time embedded systems. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5473

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

De Francis, Michael. “Schedulability-driven scratchpad memory swapping for resource-constrained real-time embedded systems.” 2012. Thesis, Rochester Institute of Technology. Accessed January 25, 2021. https://scholarworks.rit.edu/theses/5473.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

De Francis, Michael. “Schedulability-driven scratchpad memory swapping for resource-constrained real-time embedded systems.” 2012. Web. 25 Jan 2021.

Vancouver:

De Francis M. Schedulability-driven scratchpad memory swapping for resource-constrained real-time embedded systems. [Internet] [Thesis]. Rochester Institute of Technology; 2012. [cited 2021 Jan 25]. Available from: https://scholarworks.rit.edu/theses/5473.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

De Francis M. Schedulability-driven scratchpad memory swapping for resource-constrained real-time embedded systems. [Thesis]. Rochester Institute of Technology; 2012. Available from: https://scholarworks.rit.edu/theses/5473

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

6. Soliman, Muhammad Refaat Sedky. Automated Compilation Framework for Scratchpad-based Real-Time Systems.

Degree: 2019, University of Waterloo

ScratchPad Memory (SPM) is highly adopted in real-time systems as it exhibits a predictable behaviour. SPM is software-managed by explicitly inserting instructions to move code… (more)

Subjects/Keywords: real-time; LLVM; scratchpad; compiler; PREM; segmentation; allocation; optimization

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Soliman, M. R. S. (2019). Automated Compilation Framework for Scratchpad-based Real-Time Systems. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Soliman, Muhammad Refaat Sedky. “Automated Compilation Framework for Scratchpad-based Real-Time Systems.” 2019. Thesis, University of Waterloo. Accessed January 25, 2021. http://hdl.handle.net/10012/14835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Soliman, Muhammad Refaat Sedky. “Automated Compilation Framework for Scratchpad-based Real-Time Systems.” 2019. Web. 25 Jan 2021.

Vancouver:

Soliman MRS. Automated Compilation Framework for Scratchpad-based Real-Time Systems. [Internet] [Thesis]. University of Waterloo; 2019. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/10012/14835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Soliman MRS. Automated Compilation Framework for Scratchpad-based Real-Time Systems. [Thesis]. University of Waterloo; 2019. Available from: http://hdl.handle.net/10012/14835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Chen, Hung-Lun. A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Embedded system plays an important role in modern computer architecture since it can provide reliable performance with lower cost and area compared to the general… (more)

Subjects/Keywords: Conflict Miss; Hot Cache Set; Scratchpad Memory; Cache

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, H. (2017). A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721117-173334

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Hung-Lun. “A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support.” 2017. Thesis, NSYSU. Accessed January 25, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721117-173334.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Hung-Lun. “A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support.” 2017. Web. 25 Jan 2021.

Vancouver:

Chen H. A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Jan 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721117-173334.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721117-173334

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

8. Ampntel-Kanter-Oikonomou, A.K. (author). Design space exploration for a Local Object Store.

Degree: 2015, Delft University of Technology

Nowadays, modern Integrated Circuit (IC) technology allows processor manufacturers to produce complex designs with up to a few billions of transistors.Technology limitations and the end… (more)

Subjects/Keywords: Local Object Store Design; scratchpad; cache memory; management unit cache

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ampntel-Kanter-Oikonomou, A. K. (. (2015). Design space exploration for a Local Object Store. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ff0d73fa-339b-46c2-930c-f0e7b58625b6

Chicago Manual of Style (16th Edition):

Ampntel-Kanter-Oikonomou, A K (author). “Design space exploration for a Local Object Store.” 2015. Masters Thesis, Delft University of Technology. Accessed January 25, 2021. http://resolver.tudelft.nl/uuid:ff0d73fa-339b-46c2-930c-f0e7b58625b6.

MLA Handbook (7th Edition):

Ampntel-Kanter-Oikonomou, A K (author). “Design space exploration for a Local Object Store.” 2015. Web. 25 Jan 2021.

Vancouver:

Ampntel-Kanter-Oikonomou AK(. Design space exploration for a Local Object Store. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2021 Jan 25]. Available from: http://resolver.tudelft.nl/uuid:ff0d73fa-339b-46c2-930c-f0e7b58625b6.

Council of Science Editors:

Ampntel-Kanter-Oikonomou AK(. Design space exploration for a Local Object Store. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:ff0d73fa-339b-46c2-930c-f0e7b58625b6


Arizona State University

9. Lin, Jinn-Pean. Optimizing Heap Data Management on Software Managed Manycore Architectures.

Degree: Computer Science, 2017, Arizona State University

 Caches pose a serious limitation in scaling many-core architectures since the demand of area and power for maintaining cache coherence increases rapidly with the number… (more)

Subjects/Keywords: Computer science; Computer engineering; Compiler; Heap; Memory; Scratchpad

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, J. (2017). Optimizing Heap Data Management on Software Managed Manycore Architectures. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/45507

Chicago Manual of Style (16th Edition):

Lin, Jinn-Pean. “Optimizing Heap Data Management on Software Managed Manycore Architectures.” 2017. Masters Thesis, Arizona State University. Accessed January 25, 2021. http://repository.asu.edu/items/45507.

MLA Handbook (7th Edition):

Lin, Jinn-Pean. “Optimizing Heap Data Management on Software Managed Manycore Architectures.” 2017. Web. 25 Jan 2021.

Vancouver:

Lin J. Optimizing Heap Data Management on Software Managed Manycore Architectures. [Internet] [Masters thesis]. Arizona State University; 2017. [cited 2021 Jan 25]. Available from: http://repository.asu.edu/items/45507.

Council of Science Editors:

Lin J. Optimizing Heap Data Management on Software Managed Manycore Architectures. [Masters Thesis]. Arizona State University; 2017. Available from: http://repository.asu.edu/items/45507


University of Illinois – Urbana-Champaign

10. Kim, Wooil. Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy.

Degree: PhD, Computer Science, 2015, University of Illinois – Urbana-Champaign

 New architectures for extreme-scale computing need to be designed for higher energy efficiency than current systems. The DOE-funded Traleika Glacier architecture is a recently-proposed extreme-scale… (more)

Subjects/Keywords: incoherent cache hierarchy; scratchpad hierarchy; compiler-directed coherence; Runnemede architecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, W. (2015). Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89128

Chicago Manual of Style (16th Edition):

Kim, Wooil. “Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 25, 2021. http://hdl.handle.net/2142/89128.

MLA Handbook (7th Edition):

Kim, Wooil. “Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy.” 2015. Web. 25 Jan 2021.

Vancouver:

Kim W. Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/2142/89128.

Council of Science Editors:

Kim W. Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89128


University of Illinois – Urbana-Champaign

11. Tabish, Rohan. A real-time scratchpad-centric OS for multi-core embedded systems.

Degree: MS, Computer Science, 2016, University of Illinois – Urbana-Champaign

 Multicore processors have been increasing in development by the industry to meet the ever-growing processing requirements of various applications because these processors offer benefits such… (more)

Subjects/Keywords: Real Time Systems; Real time operating systems (RTOS); Multicore; Scratchpad

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tabish, R. (2016). A real-time scratchpad-centric OS for multi-core embedded systems. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tabish, Rohan. “A real-time scratchpad-centric OS for multi-core embedded systems.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed January 25, 2021. http://hdl.handle.net/2142/95440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tabish, Rohan. “A real-time scratchpad-centric OS for multi-core embedded systems.” 2016. Web. 25 Jan 2021.

Vancouver:

Tabish R. A real-time scratchpad-centric OS for multi-core embedded systems. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/2142/95440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tabish R. A real-time scratchpad-centric OS for multi-core embedded systems. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Paris-Sud – Paris XI

12. Diouf, Boubacar. Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales.

Degree: Docteur es, Informatique, 2011, Université Paris-Sud – Paris XI

Malgré la hiérarchie mémoire utilisée dans les ordinateurs modernes, il convient toujours d'optimiser l'utilisation des registres du processeur et des mémoires locales gérées de manières… (more)

Subjects/Keywords: Compilation; Allocation de registres; Allocation de mémoire; Scratchpad; Coloration de graphes pondérés; Problème de submarine-building; Compilation; Register allocation; Memory allocations; Scratchpad; Weighted graphs coloring; Submarine-building problem

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Diouf, B. (2011). Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2011PA112349

Chicago Manual of Style (16th Edition):

Diouf, Boubacar. “Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales.” 2011. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed January 25, 2021. http://www.theses.fr/2011PA112349.

MLA Handbook (7th Edition):

Diouf, Boubacar. “Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales.” 2011. Web. 25 Jan 2021.

Vancouver:

Diouf B. Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2011. [cited 2021 Jan 25]. Available from: http://www.theses.fr/2011PA112349.

Council of Science Editors:

Diouf B. Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2011. Available from: http://www.theses.fr/2011PA112349

13. Wasly, Saud. A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems.

Degree: 2013, University of Waterloo

 Scratch-pad memory is a popular alternative to caches in real-time embedded systems due to its advantages in terms of timing predictability and power consumption. However,… (more)

Subjects/Keywords: Real-time; embedded systems; scratchpad

…9 2.4 Hardware extensions for scratchpad management:(left) original, (… …time Scratchpad Memory Unit (RSMU) structure . . . . . . . . . . . 26 6.1 An… …the scratchpad on schedulability . . . . . 49 8.5 The effect of increasing the set of the… …ScratchPad Memory (SPM [7]) is used in addition to a cache. Tasks are… …is very predictable as they run out of the SPM. The Real-time Scratchpad Memory management… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wasly, S. (2013). A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/7210

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wasly, Saud. “A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems.” 2013. Thesis, University of Waterloo. Accessed January 25, 2021. http://hdl.handle.net/10012/7210.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wasly, Saud. “A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems.” 2013. Web. 25 Jan 2021.

Vancouver:

Wasly S. A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/10012/7210.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wasly S. A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/7210

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Houston

14. Kazemi Alamouti, Zeinab 1990-. Timing Analysis of the Abort-and-Restart Paradigm on a Scratchpad Memory-based Execution Platform.

Degree: MS, Computer Science, 2015, University of Houston

 Priority-based Functional Reactive Programming (P-FRP) is a new variant of FRP to model reactive applications in real-time systems. In P-FRP, when the currently running task… (more)

Subjects/Keywords: P-FRP; Scratchpad Memory; Worst-case execution time (WCET); Worst-case response time (WCRT)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kazemi Alamouti, Z. 1. (2015). Timing Analysis of the Abort-and-Restart Paradigm on a Scratchpad Memory-based Execution Platform. (Masters Thesis). University of Houston. Retrieved from http://hdl.handle.net/10657/1941

Chicago Manual of Style (16th Edition):

Kazemi Alamouti, Zeinab 1990-. “Timing Analysis of the Abort-and-Restart Paradigm on a Scratchpad Memory-based Execution Platform.” 2015. Masters Thesis, University of Houston. Accessed January 25, 2021. http://hdl.handle.net/10657/1941.

MLA Handbook (7th Edition):

Kazemi Alamouti, Zeinab 1990-. “Timing Analysis of the Abort-and-Restart Paradigm on a Scratchpad Memory-based Execution Platform.” 2015. Web. 25 Jan 2021.

Vancouver:

Kazemi Alamouti Z1. Timing Analysis of the Abort-and-Restart Paradigm on a Scratchpad Memory-based Execution Platform. [Internet] [Masters thesis]. University of Houston; 2015. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/10657/1941.

Council of Science Editors:

Kazemi Alamouti Z1. Timing Analysis of the Abort-and-Restart Paradigm on a Scratchpad Memory-based Execution Platform. [Masters Thesis]. University of Houston; 2015. Available from: http://hdl.handle.net/10657/1941


Arizona State University

15. Kim, Yooseong. WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems.

Degree: Computer Science, 2017, Arizona State University

 Cyber-physical systems and hard real-time systems have strict timing constraints that specify deadlines until which tasks must finish their execution. Missing a deadline can cause… (more)

Subjects/Keywords: Computer science; Computer engineering; Compiler; Embedded Systems; Predictability; Real-time Systems; Scratchpad Memory; WCET

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, Y. (2017). WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/42053

Chicago Manual of Style (16th Edition):

Kim, Yooseong. “WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems.” 2017. Doctoral Dissertation, Arizona State University. Accessed January 25, 2021. http://repository.asu.edu/items/42053.

MLA Handbook (7th Edition):

Kim, Yooseong. “WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems.” 2017. Web. 25 Jan 2021.

Vancouver:

Kim Y. WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems. [Internet] [Doctoral dissertation]. Arizona State University; 2017. [cited 2021 Jan 25]. Available from: http://repository.asu.edu/items/42053.

Council of Science Editors:

Kim Y. WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems. [Doctoral Dissertation]. Arizona State University; 2017. Available from: http://repository.asu.edu/items/42053


University of Waterloo

16. Wasly, Saud. Scratchpad Memory Management For Multicore Real-Time Embedded Systems.

Degree: 2018, University of Waterloo

 Multicore systems will continue to spread in the domain of real-time embedded systems due to the increasing need for high-performance applications. This research discusses some… (more)

Subjects/Keywords: real-time; scratchpad memory; scheduling; real-time architecture; predictable communication; parallel tasks

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wasly, S. (2018). Scratchpad Memory Management For Multicore Real-Time Embedded Systems. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/13566

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wasly, Saud. “Scratchpad Memory Management For Multicore Real-Time Embedded Systems.” 2018. Thesis, University of Waterloo. Accessed January 25, 2021. http://hdl.handle.net/10012/13566.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wasly, Saud. “Scratchpad Memory Management For Multicore Real-Time Embedded Systems.” 2018. Web. 25 Jan 2021.

Vancouver:

Wasly S. Scratchpad Memory Management For Multicore Real-Time Embedded Systems. [Internet] [Thesis]. University of Waterloo; 2018. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/10012/13566.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wasly S. Scratchpad Memory Management For Multicore Real-Time Embedded Systems. [Thesis]. University of Waterloo; 2018. Available from: http://hdl.handle.net/10012/13566

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Holzkamp, Olivera. Memory-aware mapping strategies for heterogeneous MPSoC systems.

Degree: 2017, Technische Universität Dortmund

 Embedded systems, such as mobile phones, integrate more and more features, e.g. multiple cameras, GPS sensors and many other sensors and actuators. These kind of… (more)

Subjects/Keywords: Memory optimization; MPSoCs; Thread mapping; Scratchpad memories; Homogeneous; Heterogeneous; 004; System-on-Chip; Chip-Multiprozessor; Multithreading; Parallelisierung; Speicherverwaltung; Mehrkriterielle Optimierung

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Holzkamp, O. (2017). Memory-aware mapping strategies for heterogeneous MPSoC systems. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-17981

Chicago Manual of Style (16th Edition):

Holzkamp, Olivera. “Memory-aware mapping strategies for heterogeneous MPSoC systems.” 2017. Doctoral Dissertation, Technische Universität Dortmund. Accessed January 25, 2021. http://dx.doi.org/10.17877/DE290R-17981.

MLA Handbook (7th Edition):

Holzkamp, Olivera. “Memory-aware mapping strategies for heterogeneous MPSoC systems.” 2017. Web. 25 Jan 2021.

Vancouver:

Holzkamp O. Memory-aware mapping strategies for heterogeneous MPSoC systems. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2017. [cited 2021 Jan 25]. Available from: http://dx.doi.org/10.17877/DE290R-17981.

Council of Science Editors:

Holzkamp O. Memory-aware mapping strategies for heterogeneous MPSoC systems. [Doctoral Dissertation]. Technische Universität Dortmund; 2017. Available from: http://dx.doi.org/10.17877/DE290R-17981


University of Kentucky

18. Chen, Zhi. Power-Efficient and Low-Latency Memory Access for CMP Systems with Heterogeneous Scratchpad On-Chip Memory.

Degree: 2013, University of Kentucky

 The gradually widening speed disparity of between CPU and memory has become an overwhelming bottleneck for the development of Chip Multiprocessor (CMP) systems. In addition,… (more)

Subjects/Keywords: Heterogeneousmemory; magnetic randomaccess memory; MRAM; Zerocapacitor random access memory; Z-RAM; scratchpad memory; scheduling; Computer and Systems Architecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Z. (2013). Power-Efficient and Low-Latency Memory Access for CMP Systems with Heterogeneous Scratchpad On-Chip Memory. (Masters Thesis). University of Kentucky. Retrieved from https://uknowledge.uky.edu/ece_etds/25

Chicago Manual of Style (16th Edition):

Chen, Zhi. “Power-Efficient and Low-Latency Memory Access for CMP Systems with Heterogeneous Scratchpad On-Chip Memory.” 2013. Masters Thesis, University of Kentucky. Accessed January 25, 2021. https://uknowledge.uky.edu/ece_etds/25.

MLA Handbook (7th Edition):

Chen, Zhi. “Power-Efficient and Low-Latency Memory Access for CMP Systems with Heterogeneous Scratchpad On-Chip Memory.” 2013. Web. 25 Jan 2021.

Vancouver:

Chen Z. Power-Efficient and Low-Latency Memory Access for CMP Systems with Heterogeneous Scratchpad On-Chip Memory. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2021 Jan 25]. Available from: https://uknowledge.uky.edu/ece_etds/25.

Council of Science Editors:

Chen Z. Power-Efficient and Low-Latency Memory Access for CMP Systems with Heterogeneous Scratchpad On-Chip Memory. [Masters Thesis]. University of Kentucky; 2013. Available from: https://uknowledge.uky.edu/ece_etds/25


Penn State University

19. Cover, Bryan Alan. Analyzing the Benefits of Scratchpad Memories for Scientific Matrix Computations .

Degree: 2008, Penn State University

Scratchpad memories (SPMs) have been shown to be more energy efficient, have faster access times, and take up less area than traditional hardware-managed caches. This,… (more)

Subjects/Keywords: software-controlled; CMP; computer architecture; cache; scratchpad; memory; matrix multiplication

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cover, B. A. (2008). Analyzing the Benefits of Scratchpad Memories for Scientific Matrix Computations . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/8239

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cover, Bryan Alan. “Analyzing the Benefits of Scratchpad Memories for Scientific Matrix Computations .” 2008. Thesis, Penn State University. Accessed January 25, 2021. https://submit-etda.libraries.psu.edu/catalog/8239.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cover, Bryan Alan. “Analyzing the Benefits of Scratchpad Memories for Scientific Matrix Computations .” 2008. Web. 25 Jan 2021.

Vancouver:

Cover BA. Analyzing the Benefits of Scratchpad Memories for Scientific Matrix Computations . [Internet] [Thesis]. Penn State University; 2008. [cited 2021 Jan 25]. Available from: https://submit-etda.libraries.psu.edu/catalog/8239.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cover BA. Analyzing the Benefits of Scratchpad Memories for Scientific Matrix Computations . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/8239

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

20. Pereira de Azevedo Filho, A. Efficient Execution of Video Applications on Heterogeneous Multi- and Many-Core Processors.

Degree: 2011, Delft University of Technology

 In this dissertation we present methodologies and evaluations aiming at increasing the efficiency of video coding applications for heterogeneous many-core processors composed of SIMD-only, scratchpad(more)

Subjects/Keywords: Video Processing; Parallel Processing; Processor Architecture; Scratchpad Memory; Software Cache; SIMD Processing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pereira de Azevedo Filho, A. (2011). Efficient Execution of Video Applications on Heterogeneous Multi- and Many-Core Processors. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; urn:NBN:nl:ui:24-uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; urn:NBN:nl:ui:24-uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; http://resolver.tudelft.nl/uuid:09179df1-7418-4b33-8a75-e0c557c6079c

Chicago Manual of Style (16th Edition):

Pereira de Azevedo Filho, A. “Efficient Execution of Video Applications on Heterogeneous Multi- and Many-Core Processors.” 2011. Doctoral Dissertation, Delft University of Technology. Accessed January 25, 2021. http://resolver.tudelft.nl/uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; urn:NBN:nl:ui:24-uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; urn:NBN:nl:ui:24-uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; http://resolver.tudelft.nl/uuid:09179df1-7418-4b33-8a75-e0c557c6079c.

MLA Handbook (7th Edition):

Pereira de Azevedo Filho, A. “Efficient Execution of Video Applications on Heterogeneous Multi- and Many-Core Processors.” 2011. Web. 25 Jan 2021.

Vancouver:

Pereira de Azevedo Filho A. Efficient Execution of Video Applications on Heterogeneous Multi- and Many-Core Processors. [Internet] [Doctoral dissertation]. Delft University of Technology; 2011. [cited 2021 Jan 25]. Available from: http://resolver.tudelft.nl/uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; urn:NBN:nl:ui:24-uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; urn:NBN:nl:ui:24-uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; http://resolver.tudelft.nl/uuid:09179df1-7418-4b33-8a75-e0c557c6079c.

Council of Science Editors:

Pereira de Azevedo Filho A. Efficient Execution of Video Applications on Heterogeneous Multi- and Many-Core Processors. [Doctoral Dissertation]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; urn:NBN:nl:ui:24-uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; urn:NBN:nl:ui:24-uuid:09179df1-7418-4b33-8a75-e0c557c6079c ; http://resolver.tudelft.nl/uuid:09179df1-7418-4b33-8a75-e0c557c6079c

21. VIVY SUHENDRA. Memory Optimizations for Time-Predictable Embedded Software.

Degree: 2009, National University of Singapore

Subjects/Keywords: real-time; embedded systems; scratchpad memory; cache; WCET; performance optimization

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SUHENDRA, V. (2009). Memory Optimizations for Time-Predictable Embedded Software. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/16329

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

SUHENDRA, VIVY. “Memory Optimizations for Time-Predictable Embedded Software.” 2009. Thesis, National University of Singapore. Accessed January 25, 2021. http://scholarbank.nus.edu.sg/handle/10635/16329.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

SUHENDRA, VIVY. “Memory Optimizations for Time-Predictable Embedded Software.” 2009. Web. 25 Jan 2021.

Vancouver:

SUHENDRA V. Memory Optimizations for Time-Predictable Embedded Software. [Internet] [Thesis]. National University of Singapore; 2009. [cited 2021 Jan 25]. Available from: http://scholarbank.nus.edu.sg/handle/10635/16329.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

SUHENDRA V. Memory Optimizations for Time-Predictable Embedded Software. [Thesis]. National University of Singapore; 2009. Available from: http://scholarbank.nus.edu.sg/handle/10635/16329

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Che, Weijia. Compilation of Stream Programs onto Embedded Multicore Architectures.

Degree: PhD, Computer Science, 2012, Arizona State University

 In recent years, we have observed the prevalence of stream applications in many embedded domains. Stream programs distinguish themselves from traditional sequential programming languages through… (more)

Subjects/Keywords: Computer science; compilation; embedded; multicore; parallel; scratchpad; stream

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Che, W. (2012). Compilation of Stream Programs onto Embedded Multicore Architectures. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/15224

Chicago Manual of Style (16th Edition):

Che, Weijia. “Compilation of Stream Programs onto Embedded Multicore Architectures.” 2012. Doctoral Dissertation, Arizona State University. Accessed January 25, 2021. http://repository.asu.edu/items/15224.

MLA Handbook (7th Edition):

Che, Weijia. “Compilation of Stream Programs onto Embedded Multicore Architectures.” 2012. Web. 25 Jan 2021.

Vancouver:

Che W. Compilation of Stream Programs onto Embedded Multicore Architectures. [Internet] [Doctoral dissertation]. Arizona State University; 2012. [cited 2021 Jan 25]. Available from: http://repository.asu.edu/items/15224.

Council of Science Editors:

Che W. Compilation of Stream Programs onto Embedded Multicore Architectures. [Doctoral Dissertation]. Arizona State University; 2012. Available from: http://repository.asu.edu/items/15224

23. Bai, Ke. Compiler and Runtime for Memory Management on Software Managed Manycore Processors.

Degree: PhD, Computer Science, 2014, Arizona State University

 We are expecting hundreds of cores per chip in the near future. However, scaling the memory architecture in manycore architectures becomes a major challenge. Cache… (more)

Subjects/Keywords: Computer science; Code Generation; Compiler; Manycore; Memory; Scratchpad Memory

scratchpad space we manage them on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2… …6 1.5 Local scratchpad memory and the anatomy of the compiled program… …core with local scratchpad memory. The function frame sizes are shown in (b). (… …53 6.1 Code overlay on scratchpad memory - when task assigned to the execution core has… …memory and the local scratchpad memory of the core… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bai, K. (2014). Compiler and Runtime for Memory Management on Software Managed Manycore Processors. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/24758

Chicago Manual of Style (16th Edition):

Bai, Ke. “Compiler and Runtime for Memory Management on Software Managed Manycore Processors.” 2014. Doctoral Dissertation, Arizona State University. Accessed January 25, 2021. http://repository.asu.edu/items/24758.

MLA Handbook (7th Edition):

Bai, Ke. “Compiler and Runtime for Memory Management on Software Managed Manycore Processors.” 2014. Web. 25 Jan 2021.

Vancouver:

Bai K. Compiler and Runtime for Memory Management on Software Managed Manycore Processors. [Internet] [Doctoral dissertation]. Arizona State University; 2014. [cited 2021 Jan 25]. Available from: http://repository.asu.edu/items/24758.

Council of Science Editors:

Bai K. Compiler and Runtime for Memory Management on Software Managed Manycore Processors. [Doctoral Dissertation]. Arizona State University; 2014. Available from: http://repository.asu.edu/items/24758

24. Gao, Yang. Automated Scratchpad Mapping and Allocation for Embedded Processors.

Degree: PhD, Computer Science and Engineering, 2014, University of South Carolina

  Embedded system-on-chip processors such as the Texas Instruments C66 DSP and the IBM Cell provide the programmer with a software controlled on-chip memory to… (more)

Subjects/Keywords: Computer Engineering; Engineering; scratchpad mapping; automated mapping; allocation; embedded processors

…Introduction Scratchpad memory (SPM) was originally designed as a way to avoid the… …the relaunched memory access but also the bandwidth wastage. The scratchpad with low access… …portion or all of one or both level of caches can be used as a software controlled scratchpad… …or fully as a scratchpad memory (SPM) space, integrated DMA controller allows… …scratchpad and DRAM. 7 Data accessed irregularly in a data-dependent pattern can be cached in a… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gao, Y. (2014). Automated Scratchpad Mapping and Allocation for Embedded Processors. (Doctoral Dissertation). University of South Carolina. Retrieved from https://scholarcommons.sc.edu/etd/3026

Chicago Manual of Style (16th Edition):

Gao, Yang. “Automated Scratchpad Mapping and Allocation for Embedded Processors.” 2014. Doctoral Dissertation, University of South Carolina. Accessed January 25, 2021. https://scholarcommons.sc.edu/etd/3026.

MLA Handbook (7th Edition):

Gao, Yang. “Automated Scratchpad Mapping and Allocation for Embedded Processors.” 2014. Web. 25 Jan 2021.

Vancouver:

Gao Y. Automated Scratchpad Mapping and Allocation for Embedded Processors. [Internet] [Doctoral dissertation]. University of South Carolina; 2014. [cited 2021 Jan 25]. Available from: https://scholarcommons.sc.edu/etd/3026.

Council of Science Editors:

Gao Y. Automated Scratchpad Mapping and Allocation for Embedded Processors. [Doctoral Dissertation]. University of South Carolina; 2014. Available from: https://scholarcommons.sc.edu/etd/3026

25. Steinke, Stefan. Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik.

Degree: 2003, Universität Dortmund

 In der Arbeitswelt und in der Freizeit hat die Nutzung von mobilen elektronischen Geräten wie Handys oder PDAs in den letzten Jahren stark zugenommen. Die… (more)

Subjects/Keywords: codegeneration; Code-Generierung; compiler; Compiler; Eingebettete Systeme; Embedded Systems; Energieeinsparung; Energieoptimierung; energy optimization; energy reduction; Integer linear programming; integer linear programming; Optimierungstechniken; optimization techniques; RISC processor; RISC Prozessor; Scratchpad; scratchpad; 004

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Steinke, S. (2003). Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik. (Thesis). Universität Dortmund. Retrieved from http://hdl.handle.net/2003/2769

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Steinke, Stefan. “Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik.” 2003. Thesis, Universität Dortmund. Accessed January 25, 2021. http://hdl.handle.net/2003/2769.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Steinke, Stefan. “Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik.” 2003. Web. 25 Jan 2021.

Vancouver:

Steinke S. Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik. [Internet] [Thesis]. Universität Dortmund; 2003. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/2003/2769.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Steinke S. Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik. [Thesis]. Universität Dortmund; 2003. Available from: http://hdl.handle.net/2003/2769

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Steinke, Stefan. Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik.

Degree: 2003, Technische Universität Dortmund

 In der Arbeitswelt und in der Freizeit hat die Nutzung von mobilen elektronischen Geräten wie Handys oder PDAs in den letzten Jahren stark zugenommen. Die… (more)

Subjects/Keywords: Eingebettete Systeme; Compiler; Code-Generierung; Energieeinsparung; Scratchpad; Optimierungstechniken; Energieoptimierung; Integer linear programming; RISC Prozessor; Embedded Systems; compiler; codegeneration; energy reduction; scratchpad; optimization techniques; energy optimization; integer linear programming; RISC processor; 004

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Steinke, S. (2003). Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-14716

Chicago Manual of Style (16th Edition):

Steinke, Stefan. “Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik.” 2003. Doctoral Dissertation, Technische Universität Dortmund. Accessed January 25, 2021. http://dx.doi.org/10.17877/DE290R-14716.

MLA Handbook (7th Edition):

Steinke, Stefan. “Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik.” 2003. Web. 25 Jan 2021.

Vancouver:

Steinke S. Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2003. [cited 2021 Jan 25]. Available from: http://dx.doi.org/10.17877/DE290R-14716.

Council of Science Editors:

Steinke S. Untersuchung des Energieeinsparungspotenzials in eingebetteten Systemen durch energieoptimierende Compilertechnik. [Doctoral Dissertation]. Technische Universität Dortmund; 2003. Available from: http://dx.doi.org/10.17877/DE290R-14716

27. Καββαδίας, Σταμάτης. Direct communication and synchronization mechanisms in chip multiprocessors.

Degree: 2010, University of Crete (UOC); Πανεπιστήμιο Κρήτης

 The physical constraints of transistor integration have made chip multiprocessors (CMPs) a necessity, and increasing the number of cores (CPUs) the best approach, yet, for… (more)

Subjects/Keywords: Μηχανισμοί επικοινωνίας; Μηχανισμοί συγχρονισμού; Πολυεπεξεργαστές ψηφίδας; Κρυφές μνήμες; Πρόχειρες μνήμες; Communication mechanisms; Synchronization mechanisms; Chip multiprocessors; Cache memory; Scratchpad memory

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Καββαδίας, . . (2010). Direct communication and synchronization mechanisms in chip multiprocessors. (Thesis). University of Crete (UOC); Πανεπιστήμιο Κρήτης. Retrieved from http://hdl.handle.net/10442/hedi/22318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Καββαδίας, Σταμάτης. “Direct communication and synchronization mechanisms in chip multiprocessors.” 2010. Thesis, University of Crete (UOC); Πανεπιστήμιο Κρήτης. Accessed January 25, 2021. http://hdl.handle.net/10442/hedi/22318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Καββαδίας, Σταμάτης. “Direct communication and synchronization mechanisms in chip multiprocessors.” 2010. Web. 25 Jan 2021.

Vancouver:

Καββαδίας . Direct communication and synchronization mechanisms in chip multiprocessors. [Internet] [Thesis]. University of Crete (UOC); Πανεπιστήμιο Κρήτης; 2010. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/10442/hedi/22318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Καββαδίας . Direct communication and synchronization mechanisms in chip multiprocessors. [Thesis]. University of Crete (UOC); Πανεπιστήμιο Κρήτης; 2010. Available from: http://hdl.handle.net/10442/hedi/22318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Jang, Ganghee. Data Shepherding: Cache design for future large scale chips.

Degree: Electrical and Computer Engineering, 2016, University of California – Irvine

 The issue of the power wall has had a drastic impact on many aspects of system design. Even though frequency scaling is limited because Dennard… (more)

Subjects/Keywords: Computer engineering; Data Shepherding; dynamic mapping; large scale cache design; multi-bank cache design; power efficiency; scratchpad memory

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jang, G. (2016). Data Shepherding: Cache design for future large scale chips. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/4bq2t8q5

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jang, Ganghee. “Data Shepherding: Cache design for future large scale chips.” 2016. Thesis, University of California – Irvine. Accessed January 25, 2021. http://www.escholarship.org/uc/item/4bq2t8q5.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jang, Ganghee. “Data Shepherding: Cache design for future large scale chips.” 2016. Web. 25 Jan 2021.

Vancouver:

Jang G. Data Shepherding: Cache design for future large scale chips. [Internet] [Thesis]. University of California – Irvine; 2016. [cited 2021 Jan 25]. Available from: http://www.escholarship.org/uc/item/4bq2t8q5.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jang G. Data Shepherding: Cache design for future large scale chips. [Thesis]. University of California – Irvine; 2016. Available from: http://www.escholarship.org/uc/item/4bq2t8q5

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Mancuso, Renato. Next-generation safety-critical systems on multi-core platforms.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

 Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. In fact, multi-core platforms can deliver large computational power together… (more)

Subjects/Keywords: Real-time systems; Multi-core systems; Commercial-off-the-shelf (COTS); Single-core equivalence; Single-core equivalent; Hardware resource management; Operating system (OS); Real-time operating system (RTOS); Worst case execution time (WCET); Scheduling; Schedulability analysis; Multi-core real-time operating system (RTOS); Profiling; Avionics; Safety-critical; Cyber-physical systems (CPS); Memguard; Colored lockdown; Palloc; Kernel verification; Scratchpad-centric operating system (OS); Scratchpad memories operating system (SPM-OS); Scratchpad scheduling; Direct memory access (DMA) scheduling; Flow-shop task; Flow-shop scheduling; Hardware scheduler; Field-programmable gate array (FPGA) scheduler; Real-time Linux; Automotive; Smart manufacturing; Real-time networking; Embedded systems; Multi-core avionics; Multi-core automotive; Self-driving cars; Multi-core safety-critical; Many-core; Reconfigurable computing; Internet of things; Real-time cloud computing; Provably safe cyber-physical systems (CPS); Multi-core scheduling; Performance isolation; Real-time resource management; Real-time cache; Real-time dynamic random access memory (DRAM); P4080; MPC5777M; Inter-core interference; Interference channels; CAST32; CAST32A; Federal Aviation Administration (FAA); Minimal multicore avionics certification guidance; Multi-core automotive open system architecture (AUTOSAR); DO-178C; DO-178B; Resource partitioning; Multi-core resource partitioning; Predictable execution model (PREM); Multi-core predictable execution model (PREM)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mancuso, R. (2017). Next-generation safety-critical systems on multi-core platforms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97399

Chicago Manual of Style (16th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 25, 2021. http://hdl.handle.net/2142/97399.

MLA Handbook (7th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Web. 25 Jan 2021.

Vancouver:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Jan 25]. Available from: http://hdl.handle.net/2142/97399.

Council of Science Editors:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97399


Indian Institute of Science

30. Jindal, Prachee. Compiler Assisted Energy Management For Sensor Network Nodes.

Degree: MSc Engg, Faculty of Engineering, 2010, Indian Institute of Science

 Emerging low power, embedded, wireless sensor devices are useful for wide range of applications, yet have very limited processing storage and especially energy resources. Sensor… (more)

Subjects/Keywords: Sensor Networks - Data Processing; Electronic Detector Networks; Data Processing; Compilers (Computer Science); Dynamic Voltage Scaling; Energy Optimization; Scratchpad Memory; Sensor Node Architecture; Sensor Network Node; Node Architecture; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jindal, P. (2010). Compiler Assisted Energy Management For Sensor Network Nodes. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/819

Chicago Manual of Style (16th Edition):

Jindal, Prachee. “Compiler Assisted Energy Management For Sensor Network Nodes.” 2010. Masters Thesis, Indian Institute of Science. Accessed January 25, 2021. http://etd.iisc.ac.in/handle/2005/819.

MLA Handbook (7th Edition):

Jindal, Prachee. “Compiler Assisted Energy Management For Sensor Network Nodes.” 2010. Web. 25 Jan 2021.

Vancouver:

Jindal P. Compiler Assisted Energy Management For Sensor Network Nodes. [Internet] [Masters thesis]. Indian Institute of Science; 2010. [cited 2021 Jan 25]. Available from: http://etd.iisc.ac.in/handle/2005/819.

Council of Science Editors:

Jindal P. Compiler Assisted Energy Management For Sensor Network Nodes. [Masters Thesis]. Indian Institute of Science; 2010. Available from: http://etd.iisc.ac.in/handle/2005/819

.