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You searched for subject:(STT MRAM). Showing records 1 – 26 of 26 total matches.

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Texas A&M University

1. Vikram Kulkarni, Nikhil. STT-MRAM Based NoC Buffer Design.

Degree: 2012, Texas A&M University

 As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory… (more)

Subjects/Keywords: STT-MRAM; Noc; Buffer

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APA (6th Edition):

Vikram Kulkarni, N. (2012). STT-MRAM Based NoC Buffer Design. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikram Kulkarni, Nikhil. “STT-MRAM Based NoC Buffer Design.” 2012. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikram Kulkarni, Nikhil. “STT-MRAM Based NoC Buffer Design.” 2012. Web. 24 Jan 2020.

Vancouver:

Vikram Kulkarni N. STT-MRAM Based NoC Buffer Design. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikram Kulkarni N. STT-MRAM Based NoC Buffer Design. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

2. Chintaluri, Ashwin K. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology that has gained immense interest in recent years due to its… (more)

Subjects/Keywords: STT-MRAM; Variation; Faults

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APA (6th Edition):

Chintaluri, A. K. (2016). Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55060

Chicago Manual of Style (16th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Masters Thesis, Georgia Tech. Accessed January 24, 2020. http://hdl.handle.net/1853/55060.

MLA Handbook (7th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Web. 24 Jan 2020.

Vancouver:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1853/55060.

Council of Science Editors:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55060


Université Montpellier II

3. Brum, Raphael Martins. Conception hybride CMOS et mémoires magnétiques : applications aux architectures programmables : On the design of hybrid CMOS and magnetic memories, with applications to reconfigurable architectures.

Degree: Docteur es, Systèmes automatiques et microélectroniques, 2014, Université Montpellier II

Avec la réduction continue des dimensions des transistors CMOS, le développement des mémoires statiques du type SRAM énergétiquement efficientes et de hautes densités devient de… (more)

Subjects/Keywords: Mram; Non-Volatilité; Fpga; Processeurs; Stt-Mram; Tas-Mram; Mram; Non-Volatility; Fpga; Processors; Stt-Mram; Tas-Mram

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APA (6th Edition):

Brum, R. M. (2014). Conception hybride CMOS et mémoires magnétiques : applications aux architectures programmables : On the design of hybrid CMOS and magnetic memories, with applications to reconfigurable architectures. (Doctoral Dissertation). Université Montpellier II. Retrieved from http://www.theses.fr/2014MON20141

Chicago Manual of Style (16th Edition):

Brum, Raphael Martins. “Conception hybride CMOS et mémoires magnétiques : applications aux architectures programmables : On the design of hybrid CMOS and magnetic memories, with applications to reconfigurable architectures.” 2014. Doctoral Dissertation, Université Montpellier II. Accessed January 24, 2020. http://www.theses.fr/2014MON20141.

MLA Handbook (7th Edition):

Brum, Raphael Martins. “Conception hybride CMOS et mémoires magnétiques : applications aux architectures programmables : On the design of hybrid CMOS and magnetic memories, with applications to reconfigurable architectures.” 2014. Web. 24 Jan 2020.

Vancouver:

Brum RM. Conception hybride CMOS et mémoires magnétiques : applications aux architectures programmables : On the design of hybrid CMOS and magnetic memories, with applications to reconfigurable architectures. [Internet] [Doctoral dissertation]. Université Montpellier II; 2014. [cited 2020 Jan 24]. Available from: http://www.theses.fr/2014MON20141.

Council of Science Editors:

Brum RM. Conception hybride CMOS et mémoires magnétiques : applications aux architectures programmables : On the design of hybrid CMOS and magnetic memories, with applications to reconfigurable architectures. [Doctoral Dissertation]. Université Montpellier II; 2014. Available from: http://www.theses.fr/2014MON20141


Texas A&M University

4. Kansal, Rohan. A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects.

Degree: 2013, Texas A&M University

 Network-on-Chip (NoC) is a de facto inter-core communication infrastructure for future Chip Multiprocessors (CMPs). NoC should be designed to provide both low latency and high… (more)

Subjects/Keywords: STT-MRAM; Network on Chips; Buffer design

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APA (6th Edition):

Kansal, R. (2013). A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/151161

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kansal, Rohan. “A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects.” 2013. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/151161.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kansal, Rohan. “A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects.” 2013. Web. 24 Jan 2020.

Vancouver:

Kansal R. A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/151161.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kansal R. A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/151161

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

5. Kim, Jongyeon. Spin-Based Logic and Memory Technologies for Low-Power Systems.

Degree: PhD, Electrical Engineering, 2016, University of Minnesota

 As the end draws near for Moore’s law, the search for low-power alternatives to CMOS technology is intensifying. Among the various post-CMOS candidates, spintronic devices… (more)

Subjects/Keywords: Circuit; Spin logic; Spintronics; STT-MRAM

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APA (6th Edition):

Kim, J. (2016). Spin-Based Logic and Memory Technologies for Low-Power Systems. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/178949

Chicago Manual of Style (16th Edition):

Kim, Jongyeon. “Spin-Based Logic and Memory Technologies for Low-Power Systems.” 2016. Doctoral Dissertation, University of Minnesota. Accessed January 24, 2020. http://hdl.handle.net/11299/178949.

MLA Handbook (7th Edition):

Kim, Jongyeon. “Spin-Based Logic and Memory Technologies for Low-Power Systems.” 2016. Web. 24 Jan 2020.

Vancouver:

Kim J. Spin-Based Logic and Memory Technologies for Low-Power Systems. [Internet] [Doctoral dissertation]. University of Minnesota; 2016. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/11299/178949.

Council of Science Editors:

Kim J. Spin-Based Logic and Memory Technologies for Low-Power Systems. [Doctoral Dissertation]. University of Minnesota; 2016. Available from: http://hdl.handle.net/11299/178949


University of Florida

6. Zeng, Qi. Content-Aware Spin-Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM) Cache Designs.

Degree: PhD, Computer Science - Computer and Information Science and Engineering, 2017, University of Florida

 As the speed gap between the processor cores and the memory subsystem has been continuously widening in this multi-core era, designers usually use larger caches… (more)

Subjects/Keywords: cache  – compression  – endurance  – energy  – replacement  – stt-mram

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APA (6th Edition):

Zeng, Q. (2017). Content-Aware Spin-Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM) Cache Designs. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0051762

Chicago Manual of Style (16th Edition):

Zeng, Qi. “Content-Aware Spin-Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM) Cache Designs.” 2017. Doctoral Dissertation, University of Florida. Accessed January 24, 2020. http://ufdc.ufl.edu/UFE0051762.

MLA Handbook (7th Edition):

Zeng, Qi. “Content-Aware Spin-Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM) Cache Designs.” 2017. Web. 24 Jan 2020.

Vancouver:

Zeng Q. Content-Aware Spin-Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM) Cache Designs. [Internet] [Doctoral dissertation]. University of Florida; 2017. [cited 2020 Jan 24]. Available from: http://ufdc.ufl.edu/UFE0051762.

Council of Science Editors:

Zeng Q. Content-Aware Spin-Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM) Cache Designs. [Doctoral Dissertation]. University of Florida; 2017. Available from: http://ufdc.ufl.edu/UFE0051762

7. Perrissin fabert, Nicolas. Miniaturisation extrême de mémoires STT-MRAM : couche de stockage à anisotropie de forme perpendiculaire : Ultimate scalability of STT MRAM : storage layer with perpendicular shape anisotropy.

Degree: Docteur es, Nano electronique et nano technologies, 2018, Grenoble Alpes

La plupart des efforts de développements actuels des STT-MRAM est centrée sur des jonctions tunnels magnétiques à aimantation hors du plan. Les derniers empilements mis… (more)

Subjects/Keywords: Stt-Mram; Anisotropie de forme perpendiculaire; Miniaturisation; Stt mram; Perpendicular shape anisotropy; Ultimate scalability; 540

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APA (6th Edition):

Perrissin fabert, N. (2018). Miniaturisation extrême de mémoires STT-MRAM : couche de stockage à anisotropie de forme perpendiculaire : Ultimate scalability of STT MRAM : storage layer with perpendicular shape anisotropy. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAT054

Chicago Manual of Style (16th Edition):

Perrissin fabert, Nicolas. “Miniaturisation extrême de mémoires STT-MRAM : couche de stockage à anisotropie de forme perpendiculaire : Ultimate scalability of STT MRAM : storage layer with perpendicular shape anisotropy.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed January 24, 2020. http://www.theses.fr/2018GREAT054.

MLA Handbook (7th Edition):

Perrissin fabert, Nicolas. “Miniaturisation extrême de mémoires STT-MRAM : couche de stockage à anisotropie de forme perpendiculaire : Ultimate scalability of STT MRAM : storage layer with perpendicular shape anisotropy.” 2018. Web. 24 Jan 2020.

Vancouver:

Perrissin fabert N. Miniaturisation extrême de mémoires STT-MRAM : couche de stockage à anisotropie de forme perpendiculaire : Ultimate scalability of STT MRAM : storage layer with perpendicular shape anisotropy. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2020 Jan 24]. Available from: http://www.theses.fr/2018GREAT054.

Council of Science Editors:

Perrissin fabert N. Miniaturisation extrême de mémoires STT-MRAM : couche de stockage à anisotropie de forme perpendiculaire : Ultimate scalability of STT MRAM : storage layer with perpendicular shape anisotropy. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAT054

8. Péneau, Pierre-Yves. Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency.

Degree: Docteur es, Systèmes automatiques et micro-électroniques, 2018, Montpellier

De nos jours, des efforts majeurs pour la conception de systèmes sur puces performants et efficaces énergétiquement sont en cours. Le déclin de la loi… (more)

Subjects/Keywords: Efficacité énergétique; Stt-Mram; Hiérarchie mémoire; Caches; Llc; Energy-Efficiency; Stt-Mram; Memory hierarchy; Caches; Llc

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APA (6th Edition):

Péneau, P. (2018). Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2018MONTS108

Chicago Manual of Style (16th Edition):

Péneau, Pierre-Yves. “Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency.” 2018. Doctoral Dissertation, Montpellier. Accessed January 24, 2020. http://www.theses.fr/2018MONTS108.

MLA Handbook (7th Edition):

Péneau, Pierre-Yves. “Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency.” 2018. Web. 24 Jan 2020.

Vancouver:

Péneau P. Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency. [Internet] [Doctoral dissertation]. Montpellier; 2018. [cited 2020 Jan 24]. Available from: http://www.theses.fr/2018MONTS108.

Council of Science Editors:

Péneau P. Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency. [Doctoral Dissertation]. Montpellier; 2018. Available from: http://www.theses.fr/2018MONTS108


Texas A&M University

9. Boyapati, Rahul. Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems.

Degree: 2017, Texas A&M University

 With advances in technology, future multicore systems scaled to 100s and 1000s of cores/accelerators are being touted as an effective solution for extracting huge performance… (more)

Subjects/Keywords: Networks-On-Chip; Power efficient Designs; Approximate Computing; STT-MRAM technology

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APA (6th Edition):

Boyapati, R. (2017). Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/161506

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Boyapati, Rahul. “Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems.” 2017. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/161506.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Boyapati, Rahul. “Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems.” 2017. Web. 24 Jan 2020.

Vancouver:

Boyapati R. Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems. [Internet] [Thesis]. Texas A&M University; 2017. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/161506.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Boyapati R. Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems. [Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/161506

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

10. Narayana, Sagar 1986-. Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.

Degree: 2012, Texas A&M University

 As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient… (more)

Subjects/Keywords: input buffer; router; STT-MRAM; Network-on-Chip

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APA (6th Edition):

Narayana, S. 1. (2012). Throughput-Efficient Network-on-Chip Router Design with STT-MRAM. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Narayana, Sagar 1986-. “Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.” 2012. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/148157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Narayana, Sagar 1986-. “Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.” 2012. Web. 24 Jan 2020.

Vancouver:

Narayana S1. Throughput-Efficient Network-on-Chip Router Design with STT-MRAM. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/148157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Narayana S1. Throughput-Efficient Network-on-Chip Router Design with STT-MRAM. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

11. Chun, Ki Chul. Design techniques for dense embedded memory in advanced CMOS technologies.

Degree: PhD, Electrical Engineering, 2012, University of Minnesota

 On-die cache memory is a key component in advanced processors since it can boost micro-architectural level performance at a moderate power penalty. Demand for denser… (more)

Subjects/Keywords: 2T DRAM; 3T DRAM; Cache; Embedded memory; Microprocessor; STT-MRAM

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APA (6th Edition):

Chun, K. C. (2012). Design techniques for dense embedded memory in advanced CMOS technologies. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/162804

Chicago Manual of Style (16th Edition):

Chun, Ki Chul. “Design techniques for dense embedded memory in advanced CMOS technologies.” 2012. Doctoral Dissertation, University of Minnesota. Accessed January 24, 2020. http://hdl.handle.net/11299/162804.

MLA Handbook (7th Edition):

Chun, Ki Chul. “Design techniques for dense embedded memory in advanced CMOS technologies.” 2012. Web. 24 Jan 2020.

Vancouver:

Chun KC. Design techniques for dense embedded memory in advanced CMOS technologies. [Internet] [Doctoral dissertation]. University of Minnesota; 2012. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/11299/162804.

Council of Science Editors:

Chun KC. Design techniques for dense embedded memory in advanced CMOS technologies. [Doctoral Dissertation]. University of Minnesota; 2012. Available from: http://hdl.handle.net/11299/162804


University of Minnesota

12. Nandkar, Pushkar Shridhar. Allocation policy analysis for cache coherence protocols for STT-MRAM-based caches.

Degree: MS, Electrical Engineering, 2014, University of Minnesota

 Spintronic devices have demonstrated promising results to replace the traditional CMOS devices in Last Level Caches. Recent research have focussed on STT-CMOS hybrid caches and… (more)

Subjects/Keywords: Allocation policy; Cache coherence; Hybrid; STT-MRAM; Write energy; Electrical engineering

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APA (6th Edition):

Nandkar, P. S. (2014). Allocation policy analysis for cache coherence protocols for STT-MRAM-based caches. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/169362

Chicago Manual of Style (16th Edition):

Nandkar, Pushkar Shridhar. “Allocation policy analysis for cache coherence protocols for STT-MRAM-based caches.” 2014. Masters Thesis, University of Minnesota. Accessed January 24, 2020. http://hdl.handle.net/11299/169362.

MLA Handbook (7th Edition):

Nandkar, Pushkar Shridhar. “Allocation policy analysis for cache coherence protocols for STT-MRAM-based caches.” 2014. Web. 24 Jan 2020.

Vancouver:

Nandkar PS. Allocation policy analysis for cache coherence protocols for STT-MRAM-based caches. [Internet] [Masters thesis]. University of Minnesota; 2014. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/11299/169362.

Council of Science Editors:

Nandkar PS. Allocation policy analysis for cache coherence protocols for STT-MRAM-based caches. [Masters Thesis]. University of Minnesota; 2014. Available from: http://hdl.handle.net/11299/169362


University of Rochester

13. Patel, Ravi (1986 - ). Memristive circuits for on-chip memories.

Degree: PhD, 2016, University of Rochester

 In less then a decade, memristors have evolved from an emerging device technology, to a promising circuit concept, and now a commercial product. This accelerated… (more)

Subjects/Keywords: CMOS; Memories; Memristors; Resistive Memories; RRAM; STT-MRAM; VLSI

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APA (6th Edition):

Patel, R. (. -. ). (2016). Memristive circuits for on-chip memories. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/30636

Chicago Manual of Style (16th Edition):

Patel, Ravi (1986 - ). “Memristive circuits for on-chip memories.” 2016. Doctoral Dissertation, University of Rochester. Accessed January 24, 2020. http://hdl.handle.net/1802/30636.

MLA Handbook (7th Edition):

Patel, Ravi (1986 - ). “Memristive circuits for on-chip memories.” 2016. Web. 24 Jan 2020.

Vancouver:

Patel R(-). Memristive circuits for on-chip memories. [Internet] [Doctoral dissertation]. University of Rochester; 2016. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1802/30636.

Council of Science Editors:

Patel R(-). Memristive circuits for on-chip memories. [Doctoral Dissertation]. University of Rochester; 2016. Available from: http://hdl.handle.net/1802/30636


University of California – Irvine

14. Dill, Joshua. Characterization of Magnetic Tunnel Junctions For Spin Transfer Torque Magnetic Random Access Memory.

Degree: Chemical and Material Physics, 2014, University of California – Irvine

 This thesis details two experimental methods for quantifying magnetic tunnel junction behavior, namely write error rates and field modulated spin-torque ferromagnetic resonance. The former examines… (more)

Subjects/Keywords: Physics; Magnetic Tunnel Junction; Spin Transfer Torque; STT-MRAM

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APA (6th Edition):

Dill, J. (2014). Characterization of Magnetic Tunnel Junctions For Spin Transfer Torque Magnetic Random Access Memory. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/4c03d1rm

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dill, Joshua. “Characterization of Magnetic Tunnel Junctions For Spin Transfer Torque Magnetic Random Access Memory.” 2014. Thesis, University of California – Irvine. Accessed January 24, 2020. http://www.escholarship.org/uc/item/4c03d1rm.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dill, Joshua. “Characterization of Magnetic Tunnel Junctions For Spin Transfer Torque Magnetic Random Access Memory.” 2014. Web. 24 Jan 2020.

Vancouver:

Dill J. Characterization of Magnetic Tunnel Junctions For Spin Transfer Torque Magnetic Random Access Memory. [Internet] [Thesis]. University of California – Irvine; 2014. [cited 2020 Jan 24]. Available from: http://www.escholarship.org/uc/item/4c03d1rm.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dill J. Characterization of Magnetic Tunnel Junctions For Spin Transfer Torque Magnetic Random Access Memory. [Thesis]. University of California – Irvine; 2014. Available from: http://www.escholarship.org/uc/item/4c03d1rm

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

15. Ma, Cong. The Design of Spintronic-based Circuitry for Memory and Logic Units in Computer Systems.

Degree: PhD, Electrical Engineering, 2018, University of Minnesota

 As CMOS technology starts to face serious scaling and power consumption issues, emerging beyond-CMOS technologies draw substantial attention in recent years. Spintronic device, one of… (more)

Subjects/Keywords: Cache Hierarchy; Computer Architecture; Spintronic device; Stochastic computing; STT-MRAM

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APA (6th Edition):

Ma, C. (2018). The Design of Spintronic-based Circuitry for Memory and Logic Units in Computer Systems. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/201684

Chicago Manual of Style (16th Edition):

Ma, Cong. “The Design of Spintronic-based Circuitry for Memory and Logic Units in Computer Systems.” 2018. Doctoral Dissertation, University of Minnesota. Accessed January 24, 2020. http://hdl.handle.net/11299/201684.

MLA Handbook (7th Edition):

Ma, Cong. “The Design of Spintronic-based Circuitry for Memory and Logic Units in Computer Systems.” 2018. Web. 24 Jan 2020.

Vancouver:

Ma C. The Design of Spintronic-based Circuitry for Memory and Logic Units in Computer Systems. [Internet] [Doctoral dissertation]. University of Minnesota; 2018. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/11299/201684.

Council of Science Editors:

Ma C. The Design of Spintronic-based Circuitry for Memory and Logic Units in Computer Systems. [Doctoral Dissertation]. University of Minnesota; 2018. Available from: http://hdl.handle.net/11299/201684


Northeastern University

16. KANG, DAE IN. Analysis Of Mtj Based Stt-mrams Cell Modeling And Design Perspective.

Degree: MS, Department of Electrical and Computer Engineering, 2016, Northeastern University

 As the memory market becomes more diverse, the conventional memory hierarchies composed of Flash memory, DRAM and SRAM are now being asked to have various… (more)

Subjects/Keywords: magnetic Tunnel Junction; Model; STT-MRAM; Electrical engineering; Engineering

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APA (6th Edition):

KANG, D. I. (2016). Analysis Of Mtj Based Stt-mrams Cell Modeling And Design Perspective. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20327427

Chicago Manual of Style (16th Edition):

KANG, DAE IN. “Analysis Of Mtj Based Stt-mrams Cell Modeling And Design Perspective.” 2016. Masters Thesis, Northeastern University. Accessed January 24, 2020. http://hdl.handle.net/2047/D20327427.

MLA Handbook (7th Edition):

KANG, DAE IN. “Analysis Of Mtj Based Stt-mrams Cell Modeling And Design Perspective.” 2016. Web. 24 Jan 2020.

Vancouver:

KANG DI. Analysis Of Mtj Based Stt-mrams Cell Modeling And Design Perspective. [Internet] [Masters thesis]. Northeastern University; 2016. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/2047/D20327427.

Council of Science Editors:

KANG DI. Analysis Of Mtj Based Stt-mrams Cell Modeling And Design Perspective. [Masters Thesis]. Northeastern University; 2016. Available from: http://hdl.handle.net/2047/D20327427


University of Rochester

17. Guo, Xiaochen. Energy-efficient architectures based on STT-MRAM.

Degree: PhD, 2015, University of Rochester

 As CMOS technology scales to smaller dimensions, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional… (more)

Subjects/Keywords: Computer architectures; Energy-efficiency; Memory systems; Non-volatile memories; Reliability; STT-MRAM

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APA (6th Edition):

Guo, X. (2015). Energy-efficient architectures based on STT-MRAM. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/30309

Chicago Manual of Style (16th Edition):

Guo, Xiaochen. “Energy-efficient architectures based on STT-MRAM.” 2015. Doctoral Dissertation, University of Rochester. Accessed January 24, 2020. http://hdl.handle.net/1802/30309.

MLA Handbook (7th Edition):

Guo, Xiaochen. “Energy-efficient architectures based on STT-MRAM.” 2015. Web. 24 Jan 2020.

Vancouver:

Guo X. Energy-efficient architectures based on STT-MRAM. [Internet] [Doctoral dissertation]. University of Rochester; 2015. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1802/30309.

Council of Science Editors:

Guo X. Energy-efficient architectures based on STT-MRAM. [Doctoral Dissertation]. University of Rochester; 2015. Available from: http://hdl.handle.net/1802/30309


Universidade do Rio Grande do Norte

18. Souza, Rafaela Medeiros de. Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos .

Degree: 2015, Universidade do Rio Grande do Norte

 The discovery that a spin-polarized current is capable of exerting a torque in a ferromagnetic material, through spin transfer, might provide the development of new… (more)

Subjects/Keywords: Reversão da magnetização; Torque por transferência de spin; Densidade de corrente crítica; Memória magnética; STT; MRAM

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APA (6th Edition):

Souza, R. M. d. (2015). Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/19789

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Souza, Rafaela Medeiros de. “Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos .” 2015. Thesis, Universidade do Rio Grande do Norte. Accessed January 24, 2020. http://repositorio.ufrn.br/handle/123456789/19789.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Souza, Rafaela Medeiros de. “Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos .” 2015. Web. 24 Jan 2020.

Vancouver:

Souza RMd. Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2015. [cited 2020 Jan 24]. Available from: http://repositorio.ufrn.br/handle/123456789/19789.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Souza RMd. Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos . [Thesis]. Universidade do Rio Grande do Norte; 2015. Available from: http://repositorio.ufrn.br/handle/123456789/19789

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

19. Souza, Rafaela Medeiros de. Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos .

Degree: 2015, Universidade do Rio Grande do Norte

 The discovery that a spin-polarized current is capable of exerting a torque in a ferromagnetic material, through spin transfer, might provide the development of new… (more)

Subjects/Keywords: Reversão da magnetização; Torque por transferência de spin; Densidade de corrente crítica; Memória magnética; STT; MRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Souza, R. M. d. (2015). Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/19789

Chicago Manual of Style (16th Edition):

Souza, Rafaela Medeiros de. “Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos .” 2015. Masters Thesis, Universidade do Rio Grande do Norte. Accessed January 24, 2020. http://repositorio.ufrn.br/handle/123456789/19789.

MLA Handbook (7th Edition):

Souza, Rafaela Medeiros de. “Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos .” 2015. Web. 24 Jan 2020.

Vancouver:

Souza RMd. Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2015. [cited 2020 Jan 24]. Available from: http://repositorio.ufrn.br/handle/123456789/19789.

Council of Science Editors:

Souza RMd. Estudo da densidade de corrente crítica para reversão da magnetização de nanoelementos ferromagnéticos . [Masters Thesis]. Universidade do Rio Grande do Norte; 2015. Available from: http://repositorio.ufrn.br/handle/123456789/19789


University of Minnesota

20. Borse, Nishant Ashok. Exploring a multiprocessor design space to analyze the impact of using STT-RAM in the memory hierarchy.

Degree: MS, Electrical Engineering, 2014, University of Minnesota

 Spin-tronic memory is a promising technology and offers advantages due to its non-volatility and higher density. At the same time, based on device properties, there… (more)

Subjects/Keywords: Design space exploration; New memory technology; Plackett and Burman; Sensitivity analysis; Spintronics; STT MRAM; Electrical engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Borse, N. A. (2014). Exploring a multiprocessor design space to analyze the impact of using STT-RAM in the memory hierarchy. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/167286

Chicago Manual of Style (16th Edition):

Borse, Nishant Ashok. “Exploring a multiprocessor design space to analyze the impact of using STT-RAM in the memory hierarchy.” 2014. Masters Thesis, University of Minnesota. Accessed January 24, 2020. http://hdl.handle.net/11299/167286.

MLA Handbook (7th Edition):

Borse, Nishant Ashok. “Exploring a multiprocessor design space to analyze the impact of using STT-RAM in the memory hierarchy.” 2014. Web. 24 Jan 2020.

Vancouver:

Borse NA. Exploring a multiprocessor design space to analyze the impact of using STT-RAM in the memory hierarchy. [Internet] [Masters thesis]. University of Minnesota; 2014. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/11299/167286.

Council of Science Editors:

Borse NA. Exploring a multiprocessor design space to analyze the impact of using STT-RAM in the memory hierarchy. [Masters Thesis]. University of Minnesota; 2014. Available from: http://hdl.handle.net/11299/167286


University of Toronto

21. Song, Hui William. A Spin-torque Transfer MRAM in 90nm CMOS.

Degree: 2011, University of Toronto

This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different… (more)

Subjects/Keywords: Spintronics; Solid-state memory; Non-volatile; MRAM; STT; MTJ; High-speed read-access; 2T1MTJ cell; 0544

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APA (6th Edition):

Song, H. W. (2011). A Spin-torque Transfer MRAM in 90nm CMOS. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/29628

Chicago Manual of Style (16th Edition):

Song, Hui William. “A Spin-torque Transfer MRAM in 90nm CMOS.” 2011. Masters Thesis, University of Toronto. Accessed January 24, 2020. http://hdl.handle.net/1807/29628.

MLA Handbook (7th Edition):

Song, Hui William. “A Spin-torque Transfer MRAM in 90nm CMOS.” 2011. Web. 24 Jan 2020.

Vancouver:

Song HW. A Spin-torque Transfer MRAM in 90nm CMOS. [Internet] [Masters thesis]. University of Toronto; 2011. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1807/29628.

Council of Science Editors:

Song HW. A Spin-torque Transfer MRAM in 90nm CMOS. [Masters Thesis]. University of Toronto; 2011. Available from: http://hdl.handle.net/1807/29628

22. KARIM ALI ABDELTAWWAB AHMED. ENERGY AND AREA EFFICIENT MAGNETIC TUNNEL JUNCTION BASED NON-VOLATILE MEMORY AND LOGIC.

Degree: 2019, National University of Singapore

Subjects/Keywords: MTJ; SOT; STT; MRAM; non-volatile; NVFF

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APA (6th Edition):

AHMED, K. A. A. (2019). ENERGY AND AREA EFFICIENT MAGNETIC TUNNEL JUNCTION BASED NON-VOLATILE MEMORY AND LOGIC. (Thesis). National University of Singapore. Retrieved from https://scholarbank.nus.edu.sg/handle/10635/156075

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

AHMED, KARIM ALI ABDELTAWWAB. “ENERGY AND AREA EFFICIENT MAGNETIC TUNNEL JUNCTION BASED NON-VOLATILE MEMORY AND LOGIC.” 2019. Thesis, National University of Singapore. Accessed January 24, 2020. https://scholarbank.nus.edu.sg/handle/10635/156075.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

AHMED, KARIM ALI ABDELTAWWAB. “ENERGY AND AREA EFFICIENT MAGNETIC TUNNEL JUNCTION BASED NON-VOLATILE MEMORY AND LOGIC.” 2019. Web. 24 Jan 2020.

Vancouver:

AHMED KAA. ENERGY AND AREA EFFICIENT MAGNETIC TUNNEL JUNCTION BASED NON-VOLATILE MEMORY AND LOGIC. [Internet] [Thesis]. National University of Singapore; 2019. [cited 2020 Jan 24]. Available from: https://scholarbank.nus.edu.sg/handle/10635/156075.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

AHMED KAA. ENERGY AND AREA EFFICIENT MAGNETIC TUNNEL JUNCTION BASED NON-VOLATILE MEMORY AND LOGIC. [Thesis]. National University of Singapore; 2019. Available from: https://scholarbank.nus.edu.sg/handle/10635/156075

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. TRINH QUANG KIEN. STT-MRAMS CIRCUIT TECHNIQUES FOR ENHANCED ROBUSTNESS IN LOW POWER EMBEDDED APPLICATIONS.

Degree: 2017, National University of Singapore

Subjects/Keywords: STT-MRAM; sensing margin; dynamic voltage scaling; variations; read robustness; spintronics

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APA (6th Edition):

KIEN, T. Q. (2017). STT-MRAMS CIRCUIT TECHNIQUES FOR ENHANCED ROBUSTNESS IN LOW POWER EMBEDDED APPLICATIONS. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/141255

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

KIEN, TRINH QUANG. “STT-MRAMS CIRCUIT TECHNIQUES FOR ENHANCED ROBUSTNESS IN LOW POWER EMBEDDED APPLICATIONS.” 2017. Thesis, National University of Singapore. Accessed January 24, 2020. http://scholarbank.nus.edu.sg/handle/10635/141255.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

KIEN, TRINH QUANG. “STT-MRAMS CIRCUIT TECHNIQUES FOR ENHANCED ROBUSTNESS IN LOW POWER EMBEDDED APPLICATIONS.” 2017. Web. 24 Jan 2020.

Vancouver:

KIEN TQ. STT-MRAMS CIRCUIT TECHNIQUES FOR ENHANCED ROBUSTNESS IN LOW POWER EMBEDDED APPLICATIONS. [Internet] [Thesis]. National University of Singapore; 2017. [cited 2020 Jan 24]. Available from: http://scholarbank.nus.edu.sg/handle/10635/141255.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

KIEN TQ. STT-MRAMS CIRCUIT TECHNIQUES FOR ENHANCED ROBUSTNESS IN LOW POWER EMBEDDED APPLICATIONS. [Thesis]. National University of Singapore; 2017. Available from: http://scholarbank.nus.edu.sg/handle/10635/141255

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Vinella, Paolo. A study of using STT-MRAM as Memory PUF: Design, Modeling and Quality Evaluation.

Degree: 2015, University of Illinois – Chicago

 The contribution of the present thesis work is to offer an extensive analysis and new methodologies and guidelines on the use of Magnetic Memory (MRAM),… (more)

Subjects/Keywords: Physical Unclonable Function; PUF; Strong PUF; Weak PUF; Hardware Security; Magnetic Memory; STT-MRAM; Spin-Torque Transfer; MRAM

…PUF generated by means of STT-MRAM . . . . . . . . . . . . . . . . . . . 98 STT-MRAM as… …digital implementation of STT-MRAM as Strong PUF. A Decoder is needed for each memory cell… …x29;, in its most advanced, recent and performing flavor (STT-MRAM) as a tool to… …bit-error rate; 5. Augmenting the proposed PUF model for Hardware Security: STT-MRAM not… …devices. Its most recent flavor, p-STT-MRAM, promises to become a unique, universal, fast memory… 

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APA (6th Edition):

Vinella, P. (2015). A study of using STT-MRAM as Memory PUF: Design, Modeling and Quality Evaluation. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/19674

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vinella, Paolo. “A study of using STT-MRAM as Memory PUF: Design, Modeling and Quality Evaluation.” 2015. Thesis, University of Illinois – Chicago. Accessed January 24, 2020. http://hdl.handle.net/10027/19674.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vinella, Paolo. “A study of using STT-MRAM as Memory PUF: Design, Modeling and Quality Evaluation.” 2015. Web. 24 Jan 2020.

Vancouver:

Vinella P. A study of using STT-MRAM as Memory PUF: Design, Modeling and Quality Evaluation. [Internet] [Thesis]. University of Illinois – Chicago; 2015. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/10027/19674.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vinella P. A study of using STT-MRAM as Memory PUF: Design, Modeling and Quality Evaluation. [Thesis]. University of Illinois – Chicago; 2015. Available from: http://hdl.handle.net/10027/19674

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. TAIEBEH TAHMASEBI. Perpendicular magnetic anisotropy materials for magnetic random access memory applications.

Degree: 2012, National University of Singapore

Subjects/Keywords: magnetic random access memory; STT-MRAM; perpendicular magnetic anisotropy; PMA; L10 FePt; Co/Pd multilayers; CoFeB with PMA; MTJ stack; pMTJ

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APA (6th Edition):

TAHMASEBI, T. (2012). Perpendicular magnetic anisotropy materials for magnetic random access memory applications. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/37907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

TAHMASEBI, TAIEBEH. “Perpendicular magnetic anisotropy materials for magnetic random access memory applications.” 2012. Thesis, National University of Singapore. Accessed January 24, 2020. http://scholarbank.nus.edu.sg/handle/10635/37907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

TAHMASEBI, TAIEBEH. “Perpendicular magnetic anisotropy materials for magnetic random access memory applications.” 2012. Web. 24 Jan 2020.

Vancouver:

TAHMASEBI T. Perpendicular magnetic anisotropy materials for magnetic random access memory applications. [Internet] [Thesis]. National University of Singapore; 2012. [cited 2020 Jan 24]. Available from: http://scholarbank.nus.edu.sg/handle/10635/37907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

TAHMASEBI T. Perpendicular magnetic anisotropy materials for magnetic random access memory applications. [Thesis]. National University of Singapore; 2012. Available from: http://scholarbank.nus.edu.sg/handle/10635/37907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Yoon, Insik. Post-CMOS memory technologies and their applications in emerging computing models.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The objective of this proposed research is to take a holistic approach to the post-CMOS in/near-memory processing system design for machine learning and optimizations. We… (more)

Subjects/Keywords: Post-CMOS memory; STT-MRAM; Ferroelectric FET; Reinforcement learning; In-memory computing; Convex optimization

…LIST OF TABLES 1.1 Comparison between STT-MRAM [7][5] and competing… …PCRAM[13][14] . . . . . . . . . . . . . . . . 3 1.2 STT-MRAM array… …Physical dimensions of MTJ in STT-MRAM bit-cells across technology generations… …hyper parameters for training . . . . . . . . . . . . . . . . . . . . . 97 5.2 STT-MRAM[… …5.18 : Energy dissipation from DRAM-based HBM and STT-MRAM memory stack (off-chip)… 

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APA (6th Edition):

Yoon, I. (2019). Post-CMOS memory technologies and their applications in emerging computing models. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61768

Chicago Manual of Style (16th Edition):

Yoon, Insik. “Post-CMOS memory technologies and their applications in emerging computing models.” 2019. Doctoral Dissertation, Georgia Tech. Accessed January 24, 2020. http://hdl.handle.net/1853/61768.

MLA Handbook (7th Edition):

Yoon, Insik. “Post-CMOS memory technologies and their applications in emerging computing models.” 2019. Web. 24 Jan 2020.

Vancouver:

Yoon I. Post-CMOS memory technologies and their applications in emerging computing models. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1853/61768.

Council of Science Editors:

Yoon I. Post-CMOS memory technologies and their applications in emerging computing models. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61768

.