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Delft University of Technology

1. Nigam, A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.

Degree: 2010, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78

► As we are moving toward nanometre technology, the variability in the circuit parameters and operating environment (Process, Voltage and Temperature (PVT)) are increasing, causing uncertainty…
(more)

Subjects/Keywords: STA; SSTA; digital circuit; timing analysis; EDA; PVT; variation; Monte Carlo; 45nm; methodology; simulation; MODERN

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Nigam, A. (2010). Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78

Chicago Manual of Style (16^{th} Edition):

Nigam, A. “Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.” 2010. Masters Thesis, Delft University of Technology. Accessed April 04, 2020. http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78.

MLA Handbook (7^{th} Edition):

Nigam, A. “Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.” 2010. Web. 04 Apr 2020.

Vancouver:

Nigam A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 Apr 04]. Available from: http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78.

Council of Science Editors:

Nigam A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78

Indian Institute of Science

2. Das, Bishnu Prasad. Random Local Delay Variability : On-chip Measurement And Modeling.

Degree: 2009, Indian Institute of Science

URL: http://hdl.handle.net/2005/1008

► This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in…
(more)

Subjects/Keywords: Electronic Gates - Design; On-chip Management And Construction; Electronic Gate Delay - Modeling; Random Local Delay Variation; On-chip Gate Delay Measurement; Process Voltage And Temperature Gate Delay Model; Electronic Gate Delay - Measurement; Statistical Static Timing Analysis (SSTA); Gate Delay Variability Measurement; Delay Variability; On-chip Measurement; Gate Delay Models; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Das, B. P. (2009). Random Local Delay Variability : On-chip Measurement And Modeling. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Thesis, Indian Institute of Science. Accessed April 04, 2020. http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Web. 04 Apr 2020.

Vancouver:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1008

Not specified: Masters Thesis or Doctoral Dissertation

3. Tang, Aoxiang. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .

Degree: PhD, 2015, Princeton University

URL: http://arks.princeton.edu/ark:/88435/dsp01z890rw568

► Technology scaling has been one of the most fundamental ways to improve chip performance and reduce power consumption. However, as the industry dives deeper into…
(more)

Subjects/Keywords: delay modeling; FinFET; genetic algorithm; power modeling; PVT variation; SSTA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Tang, A. (2015). Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01z890rw568

Chicago Manual of Style (16^{th} Edition):

Tang, Aoxiang. “Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .” 2015. Doctoral Dissertation, Princeton University. Accessed April 04, 2020. http://arks.princeton.edu/ark:/88435/dsp01z890rw568.

MLA Handbook (7^{th} Edition):

Tang, Aoxiang. “Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .” 2015. Web. 04 Apr 2020.

Vancouver:

Tang A. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . [Internet] [Doctoral dissertation]. Princeton University; 2015. [cited 2020 Apr 04]. Available from: http://arks.princeton.edu/ark:/88435/dsp01z890rw568.

Council of Science Editors:

Tang A. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . [Doctoral Dissertation]. Princeton University; 2015. Available from: http://arks.princeton.edu/ark:/88435/dsp01z890rw568

4. Pendela Venkata Ramanjuneya, Suryanarayana. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits.

Degree: MS, Engineering : Computer Engineering, 2010, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324

► Much of the Semiconductor Industry’s success can be attributed to Moore’s law whichstates that the number of transistors on an integrated circuit would double approximatelyevery…
(more)

Subjects/Keywords: Electrical Engineering; sta; timing; process variations; ssta; static timing analysis; standard cell

…a new class of STA called Statistical Static Timing Analysis
(*SSTA*). Another… …Analysis (*SSTA*). As described before, the
24
…

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Pendela Venkata Ramanjuneya, S. (2010). Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324

Chicago Manual of Style (16^{th} Edition):

Pendela Venkata Ramanjuneya, Suryanarayana. “Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits.” 2010. Masters Thesis, University of Cincinnati. Accessed April 04, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324.

MLA Handbook (7^{th} Edition):

Pendela Venkata Ramanjuneya, Suryanarayana. “Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits.” 2010. Web. 04 Apr 2020.

Vancouver:

Pendela Venkata Ramanjuneya S. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. [Internet] [Masters thesis]. University of Cincinnati; 2010. [cited 2020 Apr 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324.

Council of Science Editors:

Pendela Venkata Ramanjuneya S. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. [Masters Thesis]. University of Cincinnati; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324

University of Illinois – Urbana-Champaign

5. Chilstedt, Scott E. Architecture and CAD for carbon nanomaterial integrated circuits.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/15969

► The ITRS (International Technology Roadmap for Semiconductors) has recommended that carbon-based transistors be given further study as a potential ???Beyond CMOS??? technology. Unlike traditional devices…
(more)

Subjects/Keywords: Carbon Nanotubes; Graphene Nanoribbons; Carbon Nanomaterial Transistors; Nanoelectronic Architectures; Field programmable carbon nanotube array (FPCNA); Variation-Aware CAD; Discretized statistical static timing analysis (SSTA)

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Chilstedt, S. E. (2010). Architecture and CAD for carbon nanomaterial integrated circuits. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/15969

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Chilstedt, Scott E. “Architecture and CAD for carbon nanomaterial integrated circuits.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed April 04, 2020. http://hdl.handle.net/2142/15969.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Chilstedt, Scott E. “Architecture and CAD for carbon nanomaterial integrated circuits.” 2010. Web. 04 Apr 2020.

Vancouver:

Chilstedt SE. Architecture and CAD for carbon nanomaterial integrated circuits. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2142/15969.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chilstedt SE. Architecture and CAD for carbon nanomaterial integrated circuits. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/15969

Not specified: Masters Thesis or Doctoral Dissertation

University of Minnesota

6. Liu, Qunzeng. Statistical analysis techniques for logic and memory circuits.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

URL: http://purl.umn.edu/95019

► Process variations have become increasingly important as feature sizes enter the sub- 100nm regime and continue to shrink. Both logic and memory circuits have seen…
(more)

Subjects/Keywords: Embedded DRAM; Post-silicon optimization; SSTA; Statistical analysis; Electrical Engineering

Record Details Similar Records

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Liu, Q. (2010). Statistical analysis techniques for logic and memory circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/95019

Chicago Manual of Style (16^{th} Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Doctoral Dissertation, University of Minnesota. Accessed April 04, 2020. http://purl.umn.edu/95019.

MLA Handbook (7^{th} Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Web. 04 Apr 2020.

Vancouver:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2020 Apr 04]. Available from: http://purl.umn.edu/95019.

Council of Science Editors:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://purl.umn.edu/95019