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You searched for subject:(SRAM). Showing records 1 – 30 of 197 total matches.

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Delft University of Technology

1. Khawar Sarfraz, K.S. (author). SRAM power reduction: An ultra-low-power SRAM architecture in 45nm technology.

Degree: 2009, Delft University of Technology

Circuits and Systems

Electrical Engineering, Mathematics and Computer Science

Advisors/Committee Members: Doorn, T.S. (mentor), Van der Meijs, N.P. (mentor).

Subjects/Keywords: SRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khawar Sarfraz, K. S. (. (2009). SRAM power reduction: An ultra-low-power SRAM architecture in 45nm technology. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6bf48a02-371d-47fe-b642-a88f5c917a1d

Chicago Manual of Style (16th Edition):

Khawar Sarfraz, K S (author). “SRAM power reduction: An ultra-low-power SRAM architecture in 45nm technology.” 2009. Masters Thesis, Delft University of Technology. Accessed April 22, 2021. http://resolver.tudelft.nl/uuid:6bf48a02-371d-47fe-b642-a88f5c917a1d.

MLA Handbook (7th Edition):

Khawar Sarfraz, K S (author). “SRAM power reduction: An ultra-low-power SRAM architecture in 45nm technology.” 2009. Web. 22 Apr 2021.

Vancouver:

Khawar Sarfraz KS(. SRAM power reduction: An ultra-low-power SRAM architecture in 45nm technology. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2021 Apr 22]. Available from: http://resolver.tudelft.nl/uuid:6bf48a02-371d-47fe-b642-a88f5c917a1d.

Council of Science Editors:

Khawar Sarfraz KS(. SRAM power reduction: An ultra-low-power SRAM architecture in 45nm technology. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:6bf48a02-371d-47fe-b642-a88f5c917a1d


Texas Tech University

2. Pemberton, Lacey D. Optimizing cycle time through SRAM repairs.

Degree: Electrical and Computer Engineering, 2006, Texas Tech University

 This thesis describes a project on large microprocessor integrated circuits using very large scale integration (VLSI) technologies. This project will serve to confirm the hypothesis… (more)

Subjects/Keywords: SRAM

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APA (6th Edition):

Pemberton, L. D. (2006). Optimizing cycle time through SRAM repairs. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/17251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pemberton, Lacey D. “Optimizing cycle time through SRAM repairs.” 2006. Thesis, Texas Tech University. Accessed April 22, 2021. http://hdl.handle.net/2346/17251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pemberton, Lacey D. “Optimizing cycle time through SRAM repairs.” 2006. Web. 22 Apr 2021.

Vancouver:

Pemberton LD. Optimizing cycle time through SRAM repairs. [Internet] [Thesis]. Texas Tech University; 2006. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/2346/17251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pemberton LD. Optimizing cycle time through SRAM repairs. [Thesis]. Texas Tech University; 2006. Available from: http://hdl.handle.net/2346/17251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

3. Keerthi, Rajasekhar. STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY.

Degree: MSEgr, Electrical Engineering, 2007, Wright State University

 The transistor mismatch can be described as two closely placed identical transistors have important differences in their electrical parameters as threshold voltage, body factor and… (more)

Subjects/Keywords: sram; 7T SRAM; 6T SRAM

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APA (6th Edition):

Keerthi, R. (2007). STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1195600920

Chicago Manual of Style (16th Edition):

Keerthi, Rajasekhar. “STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY.” 2007. Masters Thesis, Wright State University. Accessed April 22, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1195600920.

MLA Handbook (7th Edition):

Keerthi, Rajasekhar. “STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY.” 2007. Web. 22 Apr 2021.

Vancouver:

Keerthi R. STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY. [Internet] [Masters thesis]. Wright State University; 2007. [cited 2021 Apr 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1195600920.

Council of Science Editors:

Keerthi R. STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY. [Masters Thesis]. Wright State University; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1195600920


University of Saskatchewan

4. Tian, Haonan. Study of Radiation-Tolerant SRAM Design.

Degree: 2019, University of Saskatchewan

 Static Random Access Memories (SRAMs) are important storage components and widely used in digital systems. Meanwhile, with the continuous development and progress of aerospace technologies,… (more)

Subjects/Keywords: SRAM; Single Event; Sense Amplifier

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APA (6th Edition):

Tian, H. (2019). Study of Radiation-Tolerant SRAM Design. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/11863

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tian, Haonan. “Study of Radiation-Tolerant SRAM Design.” 2019. Thesis, University of Saskatchewan. Accessed April 22, 2021. http://hdl.handle.net/10388/11863.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tian, Haonan. “Study of Radiation-Tolerant SRAM Design.” 2019. Web. 22 Apr 2021.

Vancouver:

Tian H. Study of Radiation-Tolerant SRAM Design. [Internet] [Thesis]. University of Saskatchewan; 2019. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/10388/11863.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tian H. Study of Radiation-Tolerant SRAM Design. [Thesis]. University of Saskatchewan; 2019. Available from: http://hdl.handle.net/10388/11863

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

5. Srinath, Vinayak Bhargav. Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing.

Degree: MS, Electrical Engineering, 2015, University of Minnesota

 A processor's power consumption can be most efficiently reduced by lowering the supply voltage. But with reduced voltage levels comes the major concern of failure… (more)

Subjects/Keywords: Approximate; Cache; Energy reduction; SRAM

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APA (6th Edition):

Srinath, V. B. (2015). Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/174718

Chicago Manual of Style (16th Edition):

Srinath, Vinayak Bhargav. “Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing.” 2015. Masters Thesis, University of Minnesota. Accessed April 22, 2021. http://hdl.handle.net/11299/174718.

MLA Handbook (7th Edition):

Srinath, Vinayak Bhargav. “Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing.” 2015. Web. 22 Apr 2021.

Vancouver:

Srinath VB. Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing. [Internet] [Masters thesis]. University of Minnesota; 2015. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/11299/174718.

Council of Science Editors:

Srinath VB. Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing. [Masters Thesis]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/174718


Georgia Tech

6. Kim, Woongrae. Design and test methodologies with statistical analysis for reliable memory and processor implementations.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of the proposed research is to develop comprehensive methodologies, including circuit design, new test methodologies, and statistical failure analysis, to implement reliable microprocessor… (more)

Subjects/Keywords: Reliability; SRAM; DRAM; Processor

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APA (6th Edition):

Kim, W. (2016). Design and test methodologies with statistical analysis for reliable memory and processor implementations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59737

Chicago Manual of Style (16th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 22, 2021. http://hdl.handle.net/1853/59737.

MLA Handbook (7th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Web. 22 Apr 2021.

Vancouver:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/1853/59737.

Council of Science Editors:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59737


University of Waterloo

7. Neale, Adam. Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation.

Degree: 2010, University of Waterloo

 Embedded SRAMs can occupy the majority of the chip area in SOCs. The increase in process variation and aging degradation due to technology scaling can… (more)

Subjects/Keywords: SRAM; variability

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APA (6th Edition):

Neale, A. (2010). Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/5355

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Neale, Adam. “Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation.” 2010. Thesis, University of Waterloo. Accessed April 22, 2021. http://hdl.handle.net/10012/5355.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Neale, Adam. “Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation.” 2010. Web. 22 Apr 2021.

Vancouver:

Neale A. Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation. [Internet] [Thesis]. University of Waterloo; 2010. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/10012/5355.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Neale A. Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation. [Thesis]. University of Waterloo; 2010. Available from: http://hdl.handle.net/10012/5355

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

8. Ahrabi, Nina. Low Leakage Asymmetric Stacked Sram Cell.

Degree: 2014, University of North Texas

 Memory is an important part of any digital processing system. On-chip SRAM can be found in various levels of the memory hierarchy in a processor… (more)

Subjects/Keywords: SRAM; stacking; leakage power

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APA (6th Edition):

Ahrabi, N. (2014). Low Leakage Asymmetric Stacked Sram Cell. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc500021/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ahrabi, Nina. “Low Leakage Asymmetric Stacked Sram Cell.” 2014. Thesis, University of North Texas. Accessed April 22, 2021. https://digital.library.unt.edu/ark:/67531/metadc500021/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ahrabi, Nina. “Low Leakage Asymmetric Stacked Sram Cell.” 2014. Web. 22 Apr 2021.

Vancouver:

Ahrabi N. Low Leakage Asymmetric Stacked Sram Cell. [Internet] [Thesis]. University of North Texas; 2014. [cited 2021 Apr 22]. Available from: https://digital.library.unt.edu/ark:/67531/metadc500021/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahrabi N. Low Leakage Asymmetric Stacked Sram Cell. [Thesis]. University of North Texas; 2014. Available from: https://digital.library.unt.edu/ark:/67531/metadc500021/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rice University

9. Cherivirala, Yaswanth Kumar. Design of CMOS based High Temperature sensor with integrated memory.

Degree: MS, Engineering, 2018, Rice University

 Recent advances in various fields like high speed wireless communication links, big data processing etc., has enabled the implementation of large distributed sensor systems. And… (more)

Subjects/Keywords: CMOS Sensors; SRAM; High Temperature

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APA (6th Edition):

Cherivirala, Y. K. (2018). Design of CMOS based High Temperature sensor with integrated memory. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/105612

Chicago Manual of Style (16th Edition):

Cherivirala, Yaswanth Kumar. “Design of CMOS based High Temperature sensor with integrated memory.” 2018. Masters Thesis, Rice University. Accessed April 22, 2021. http://hdl.handle.net/1911/105612.

MLA Handbook (7th Edition):

Cherivirala, Yaswanth Kumar. “Design of CMOS based High Temperature sensor with integrated memory.” 2018. Web. 22 Apr 2021.

Vancouver:

Cherivirala YK. Design of CMOS based High Temperature sensor with integrated memory. [Internet] [Masters thesis]. Rice University; 2018. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/1911/105612.

Council of Science Editors:

Cherivirala YK. Design of CMOS based High Temperature sensor with integrated memory. [Masters Thesis]. Rice University; 2018. Available from: http://hdl.handle.net/1911/105612


Delft University of Technology

10. Jain, V.R. (author). Hierarchical Memory Diagnosis Approach.

Degree: 2011, Delft University of Technology

Semiconductor memories are an inherent part of many modern electronic systems. Due to the fast development of memory process technology and the escalating computing speeds,… (more)

Subjects/Keywords: diagnosis; DfD; March tests; memory; SRAM; SRAM simulation

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APA (6th Edition):

Jain, V. R. (. (2011). Hierarchical Memory Diagnosis Approach. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:3f677e31-aa91-4641-a7a2-db8295ffa5fd

Chicago Manual of Style (16th Edition):

Jain, V R (author). “Hierarchical Memory Diagnosis Approach.” 2011. Masters Thesis, Delft University of Technology. Accessed April 22, 2021. http://resolver.tudelft.nl/uuid:3f677e31-aa91-4641-a7a2-db8295ffa5fd.

MLA Handbook (7th Edition):

Jain, V R (author). “Hierarchical Memory Diagnosis Approach.” 2011. Web. 22 Apr 2021.

Vancouver:

Jain VR(. Hierarchical Memory Diagnosis Approach. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2021 Apr 22]. Available from: http://resolver.tudelft.nl/uuid:3f677e31-aa91-4641-a7a2-db8295ffa5fd.

Council of Science Editors:

Jain VR(. Hierarchical Memory Diagnosis Approach. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:3f677e31-aa91-4641-a7a2-db8295ffa5fd


NSYSU

11. Liao, Chiang-Hsiang. Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation.

Degree: Master, Electrical Engineering, 2014, NSYSU

 This thesis is composed of a biomedical sensing system design and a novel circuit design of 5T SRAM (static random access memory, SRAM). The first… (more)

Subjects/Keywords: leakage current sensor; SRAM; readout circuit

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APA (6th Edition):

Liao, C. (2014). Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Chiang-Hsiang. “Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation.” 2014. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Chiang-Hsiang. “Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation.” 2014. Web. 22 Apr 2021.

Vancouver:

Liao C. Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao C. Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

12. Shi, Kejian. A Comparative Analysis of SRAM Sense Amplifiers.

Degree: Electrical Engineering, 2017, UCLA

 The operation of the voltage-mode and current-mode sense amplifiers (VSA and CSA) is explained in detail. Analytical expressions for offset arising from random FET mismatch… (more)

Subjects/Keywords: Electrical engineering; Latch; Sense Amplifier; SRAM

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APA (6th Edition):

Shi, K. (2017). A Comparative Analysis of SRAM Sense Amplifiers. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/0xn2r2wx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shi, Kejian. “A Comparative Analysis of SRAM Sense Amplifiers.” 2017. Thesis, UCLA. Accessed April 22, 2021. http://www.escholarship.org/uc/item/0xn2r2wx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shi, Kejian. “A Comparative Analysis of SRAM Sense Amplifiers.” 2017. Web. 22 Apr 2021.

Vancouver:

Shi K. A Comparative Analysis of SRAM Sense Amplifiers. [Internet] [Thesis]. UCLA; 2017. [cited 2021 Apr 22]. Available from: http://www.escholarship.org/uc/item/0xn2r2wx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shi K. A Comparative Analysis of SRAM Sense Amplifiers. [Thesis]. UCLA; 2017. Available from: http://www.escholarship.org/uc/item/0xn2r2wx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

13. Zimmer, Brian Matthew. Resilient Design Techniques for Improving Cache Energy Efficiency.

Degree: Electrical Engineering & Computer Sciences, 2015, University of California – Berkeley

 Improving energy efficiency is critical to increasing computing capability, from mobile devices operating with limited battery capacity to servers operating under thermal constraints. The widely… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Computer science; sram

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APA (6th Edition):

Zimmer, B. M. (2015). Resilient Design Techniques for Improving Cache Energy Efficiency. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/0qd1w5tr

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zimmer, Brian Matthew. “Resilient Design Techniques for Improving Cache Energy Efficiency.” 2015. Thesis, University of California – Berkeley. Accessed April 22, 2021. http://www.escholarship.org/uc/item/0qd1w5tr.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zimmer, Brian Matthew. “Resilient Design Techniques for Improving Cache Energy Efficiency.” 2015. Web. 22 Apr 2021.

Vancouver:

Zimmer BM. Resilient Design Techniques for Improving Cache Energy Efficiency. [Internet] [Thesis]. University of California – Berkeley; 2015. [cited 2021 Apr 22]. Available from: http://www.escholarship.org/uc/item/0qd1w5tr.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zimmer BM. Resilient Design Techniques for Improving Cache Energy Efficiency. [Thesis]. University of California – Berkeley; 2015. Available from: http://www.escholarship.org/uc/item/0qd1w5tr

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

14. Shin, Changhwan. Advanced MOSFET Designs and Implications for SRAM Scaling.

Degree: Electrical Engineering & Computer Sciences, 2011, University of California – Berkeley

 Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of… (more)

Subjects/Keywords: Electrical engineering; Devices; MOSFET; SRAM; Variability

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APA (6th Edition):

Shin, C. (2011). Advanced MOSFET Designs and Implications for SRAM Scaling. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/2nt3f2dn

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shin, Changhwan. “Advanced MOSFET Designs and Implications for SRAM Scaling.” 2011. Thesis, University of California – Berkeley. Accessed April 22, 2021. http://www.escholarship.org/uc/item/2nt3f2dn.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shin, Changhwan. “Advanced MOSFET Designs and Implications for SRAM Scaling.” 2011. Web. 22 Apr 2021.

Vancouver:

Shin C. Advanced MOSFET Designs and Implications for SRAM Scaling. [Internet] [Thesis]. University of California – Berkeley; 2011. [cited 2021 Apr 22]. Available from: http://www.escholarship.org/uc/item/2nt3f2dn.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shin C. Advanced MOSFET Designs and Implications for SRAM Scaling. [Thesis]. University of California – Berkeley; 2011. Available from: http://www.escholarship.org/uc/item/2nt3f2dn

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

15. Ho, Yenpo. Dynamic Modeling and Analysis for Design of Memristive and Static Random Access Memories.

Degree: PhD, Electrical Engineering, 2014, Texas A&M University

 Nowadays, the trend of modern memory technology is going towards the following directions: (1) look for new nonvolatile devices; (2) keep scaling down the existing… (more)

Subjects/Keywords: Memristor; nonvolatile memory; SRAM; volatile memory

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APA (6th Edition):

Ho, Y. (2014). Dynamic Modeling and Analysis for Design of Memristive and Static Random Access Memories. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/153637

Chicago Manual of Style (16th Edition):

Ho, Yenpo. “Dynamic Modeling and Analysis for Design of Memristive and Static Random Access Memories.” 2014. Doctoral Dissertation, Texas A&M University. Accessed April 22, 2021. http://hdl.handle.net/1969.1/153637.

MLA Handbook (7th Edition):

Ho, Yenpo. “Dynamic Modeling and Analysis for Design of Memristive and Static Random Access Memories.” 2014. Web. 22 Apr 2021.

Vancouver:

Ho Y. Dynamic Modeling and Analysis for Design of Memristive and Static Random Access Memories. [Internet] [Doctoral dissertation]. Texas A&M University; 2014. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/1969.1/153637.

Council of Science Editors:

Ho Y. Dynamic Modeling and Analysis for Design of Memristive and Static Random Access Memories. [Doctoral Dissertation]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/153637


University of Notre Dame

16. Kamal M Karda. Low Power Bistable-Body Tunnel SRAM</h1>.

Degree: Electrical Engineering, 2009, University of Notre Dame

  A bistable-body tunnel SRAM is proposed and validated using simulations. This cell, using one transistor and two tunnel diodes, is a high speed, low… (more)

Subjects/Keywords: SRAM; low power

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APA (6th Edition):

Karda, K. M. (2009). Low Power Bistable-Body Tunnel SRAM</h1>. (Thesis). University of Notre Dame. Retrieved from https://curate.nd.edu/show/6395w66534w

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Karda, Kamal M. “Low Power Bistable-Body Tunnel SRAM</h1>.” 2009. Thesis, University of Notre Dame. Accessed April 22, 2021. https://curate.nd.edu/show/6395w66534w.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Karda, Kamal M. “Low Power Bistable-Body Tunnel SRAM</h1>.” 2009. Web. 22 Apr 2021.

Vancouver:

Karda KM. Low Power Bistable-Body Tunnel SRAM</h1>. [Internet] [Thesis]. University of Notre Dame; 2009. [cited 2021 Apr 22]. Available from: https://curate.nd.edu/show/6395w66534w.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Karda KM. Low Power Bistable-Body Tunnel SRAM</h1>. [Thesis]. University of Notre Dame; 2009. Available from: https://curate.nd.edu/show/6395w66534w

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

17. Yueh, Wen. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The multi-chip integration in an advanced packaging has made the multi-physics interactions increasingly important. The objective of this research is to address the thermal coupling… (more)

Subjects/Keywords: Cooling; VLSI; SRAM; EDRAM; 3D IC; Packaging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yueh, W. (2015). Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56171

Chicago Manual of Style (16th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Doctoral Dissertation, Georgia Tech. Accessed April 22, 2021. http://hdl.handle.net/1853/56171.

MLA Handbook (7th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Web. 22 Apr 2021.

Vancouver:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/1853/56171.

Council of Science Editors:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56171


University of Waterloo

18. Gupta, Vasudha. Variability-Aware Design of Static Random Access Memory Bit-Cell.

Degree: 2008, University of Waterloo

 The increasing integration of functional blocks in today's integrated circuit designs necessitates a large embedded memory for data manipulation and storage. The most often used… (more)

Subjects/Keywords: SRAM; technology scaling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gupta, V. (2008). Variability-Aware Design of Static Random Access Memory Bit-Cell. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/3812

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gupta, Vasudha. “Variability-Aware Design of Static Random Access Memory Bit-Cell.” 2008. Thesis, University of Waterloo. Accessed April 22, 2021. http://hdl.handle.net/10012/3812.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gupta, Vasudha. “Variability-Aware Design of Static Random Access Memory Bit-Cell.” 2008. Web. 22 Apr 2021.

Vancouver:

Gupta V. Variability-Aware Design of Static Random Access Memory Bit-Cell. [Internet] [Thesis]. University of Waterloo; 2008. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/10012/3812.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gupta V. Variability-Aware Design of Static Random Access Memory Bit-Cell. [Thesis]. University of Waterloo; 2008. Available from: http://hdl.handle.net/10012/3812

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

19. Shakir, Tahseen. Low-Power, Low-Voltage SRAM Circuits Design For Nanometric CMOS Technologies.

Degree: 2011, University of Waterloo

 Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays.… (more)

Subjects/Keywords: SRAM; stability; sense amplifier; wordline boost techniques

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APA (6th Edition):

Shakir, T. (2011). Low-Power, Low-Voltage SRAM Circuits Design For Nanometric CMOS Technologies. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/6167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shakir, Tahseen. “Low-Power, Low-Voltage SRAM Circuits Design For Nanometric CMOS Technologies.” 2011. Thesis, University of Waterloo. Accessed April 22, 2021. http://hdl.handle.net/10012/6167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shakir, Tahseen. “Low-Power, Low-Voltage SRAM Circuits Design For Nanometric CMOS Technologies.” 2011. Web. 22 Apr 2021.

Vancouver:

Shakir T. Low-Power, Low-Voltage SRAM Circuits Design For Nanometric CMOS Technologies. [Internet] [Thesis]. University of Waterloo; 2011. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/10012/6167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shakir T. Low-Power, Low-Voltage SRAM Circuits Design For Nanometric CMOS Technologies. [Thesis]. University of Waterloo; 2011. Available from: http://hdl.handle.net/10012/6167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Sacramento

20. Shroff, Hardikkumar H. Embedded design of data storage and transfer using PIC18F4550.

Degree: MS, Electrical and Electronic Engineering, 2010, California State University – Sacramento

 Microcontroller is a system, which contains processor, memory, and peripherals. Microcontroller is a basic building block for embedded systems like automobiles, home appliances, and peripherals… (more)

Subjects/Keywords: PIC; SRAM; EEPROM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shroff, H. H. (2010). Embedded design of data storage and transfer using PIC18F4550. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/850

Chicago Manual of Style (16th Edition):

Shroff, Hardikkumar H. “Embedded design of data storage and transfer using PIC18F4550.” 2010. Masters Thesis, California State University – Sacramento. Accessed April 22, 2021. http://hdl.handle.net/10211.9/850.

MLA Handbook (7th Edition):

Shroff, Hardikkumar H. “Embedded design of data storage and transfer using PIC18F4550.” 2010. Web. 22 Apr 2021.

Vancouver:

Shroff HH. Embedded design of data storage and transfer using PIC18F4550. [Internet] [Masters thesis]. California State University – Sacramento; 2010. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/10211.9/850.

Council of Science Editors:

Shroff HH. Embedded design of data storage and transfer using PIC18F4550. [Masters Thesis]. California State University – Sacramento; 2010. Available from: http://hdl.handle.net/10211.9/850


Wright State University

21. Pusapati, A. V. Rama Raju. A Robust Low Power Static Random Access Memory Cell Design.

Degree: MSEE, Electrical Engineering, 2018, Wright State University

 Stability of a Static Random Access Memory (SRAM) cell is an important factor when considering an SRAM cell for any application. The Static Noise Margin… (more)

Subjects/Keywords: Electrical Engineering; Static RAM; SRAM; Memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pusapati, A. V. R. R. (2018). A Robust Low Power Static Random Access Memory Cell Design. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1535035549954703

Chicago Manual of Style (16th Edition):

Pusapati, A V Rama Raju. “A Robust Low Power Static Random Access Memory Cell Design.” 2018. Masters Thesis, Wright State University. Accessed April 22, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1535035549954703.

MLA Handbook (7th Edition):

Pusapati, A V Rama Raju. “A Robust Low Power Static Random Access Memory Cell Design.” 2018. Web. 22 Apr 2021.

Vancouver:

Pusapati AVRR. A Robust Low Power Static Random Access Memory Cell Design. [Internet] [Masters thesis]. Wright State University; 2018. [cited 2021 Apr 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1535035549954703.

Council of Science Editors:

Pusapati AVRR. A Robust Low Power Static Random Access Memory Cell Design. [Masters Thesis]. Wright State University; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1535035549954703


Delft University of Technology

22. Hamburger, Rens (author). BTI in SRAM: Mitigation for BTI ageing in SRAM memories.

Degree: 2020, Delft University of Technology

 The aggressive downscaling of the transistor has led to gigantic improvements in the performance and func- tionality of electronics. As a result, electronics have become… (more)

Subjects/Keywords: bti; sram; hardware mitigation; Software mitigation; ageing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hamburger, R. (. (2020). BTI in SRAM: Mitigation for BTI ageing in SRAM memories. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:b837d6b4-896e-41c0-91e6-b9737249c545

Chicago Manual of Style (16th Edition):

Hamburger, Rens (author). “BTI in SRAM: Mitigation for BTI ageing in SRAM memories.” 2020. Masters Thesis, Delft University of Technology. Accessed April 22, 2021. http://resolver.tudelft.nl/uuid:b837d6b4-896e-41c0-91e6-b9737249c545.

MLA Handbook (7th Edition):

Hamburger, Rens (author). “BTI in SRAM: Mitigation for BTI ageing in SRAM memories.” 2020. Web. 22 Apr 2021.

Vancouver:

Hamburger R(. BTI in SRAM: Mitigation for BTI ageing in SRAM memories. [Internet] [Masters thesis]. Delft University of Technology; 2020. [cited 2021 Apr 22]. Available from: http://resolver.tudelft.nl/uuid:b837d6b4-896e-41c0-91e6-b9737249c545.

Council of Science Editors:

Hamburger R(. BTI in SRAM: Mitigation for BTI ageing in SRAM memories. [Masters Thesis]. Delft University of Technology; 2020. Available from: http://resolver.tudelft.nl/uuid:b837d6b4-896e-41c0-91e6-b9737249c545


Université de Grenoble

23. Ben Jirad, Mohamed. Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection.

Degree: Docteur es, Sciences et technologie industrielles, 2013, Université de Grenoble

Cette thèse s'intéresse en premier lieu à l'évaluation des effets fonctionnels des erreurs survenant dans la mémoire SRAM de configuration de certains FPGAs. La famille… (more)

Subjects/Keywords: FPGA à base de SRAM; Robustesse; Injection de fautes; SRAM-based FPGAs; Robustness; Fault injection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ben Jirad, M. (2013). Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2013GRENT035

Chicago Manual of Style (16th Edition):

Ben Jirad, Mohamed. “Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection.” 2013. Doctoral Dissertation, Université de Grenoble. Accessed April 22, 2021. http://www.theses.fr/2013GRENT035.

MLA Handbook (7th Edition):

Ben Jirad, Mohamed. “Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection.” 2013. Web. 22 Apr 2021.

Vancouver:

Ben Jirad M. Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection. [Internet] [Doctoral dissertation]. Université de Grenoble; 2013. [cited 2021 Apr 22]. Available from: http://www.theses.fr/2013GRENT035.

Council of Science Editors:

Ben Jirad M. Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection. [Doctoral Dissertation]. Université de Grenoble; 2013. Available from: http://www.theses.fr/2013GRENT035


Brno University of Technology

24. Sedlář, Jan. Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test.

Degree: 2019, Brno University of Technology

 The project deals with the testing of SRAM memories using method MBIST with the utilisation of sofware tool Tessent Memory BIST. The main purpose is… (more)

Subjects/Keywords: SRAM; Tessent; MBIST; Test paměti; JTAG; Čip; SRAM; Tessent; MBIST; Memory test; JTAG; Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sedlář, J. (2019). Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/80934

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sedlář, Jan. “Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test.” 2019. Thesis, Brno University of Technology. Accessed April 22, 2021. http://hdl.handle.net/11012/80934.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sedlář, Jan. “Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test.” 2019. Web. 22 Apr 2021.

Vancouver:

Sedlář J. Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/11012/80934.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sedlář J. Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/80934

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Rodriguez, Axel. Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment.

Degree: Docteur es, Électronique, 2017, Montpellier

Les résultats de différentes expériences du CNES (Centre National d’Études Spatiales) embarquées sur satellites montrent que des composants SRAM et SDRAM subissent des erreurs atypiques,… (more)

Subjects/Keywords: Sram; Dram; Tcad; Test; Proton; Neutron; Sram; Dram; Tcad; Testing; Proton; Neutron

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APA (6th Edition):

Rodriguez, A. (2017). Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2017MONTS032

Chicago Manual of Style (16th Edition):

Rodriguez, Axel. “Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment.” 2017. Doctoral Dissertation, Montpellier. Accessed April 22, 2021. http://www.theses.fr/2017MONTS032.

MLA Handbook (7th Edition):

Rodriguez, Axel. “Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment.” 2017. Web. 22 Apr 2021.

Vancouver:

Rodriguez A. Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment. [Internet] [Doctoral dissertation]. Montpellier; 2017. [cited 2021 Apr 22]. Available from: http://www.theses.fr/2017MONTS032.

Council of Science Editors:

Rodriguez A. Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment. [Doctoral Dissertation]. Montpellier; 2017. Available from: http://www.theses.fr/2017MONTS032

26. Farjallah, Emna. Monitoring of temperature effects on CMOS memories : Monitoring des effets de la température sur les mémoires CMOS.

Degree: Docteur es, Systèmes automatiques et micro-électroniques, 2018, Montpellier

La complexité des systèmes électroniques ne cesse d’augmenter, tout comme la tendance actuelle de miniaturisation des transistors. La fiabilité est ainsi devenue un continuel défi.… (more)

Subjects/Keywords: Fiabilité; Monitoring; Température; Mémoires Flash; Mémoires SRAM; Rétention; Reliability; Monitoring; Temperature; Flash Memories; Sram; Retention

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Farjallah, E. (2018). Monitoring of temperature effects on CMOS memories : Monitoring des effets de la température sur les mémoires CMOS. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2018MONTS091

Chicago Manual of Style (16th Edition):

Farjallah, Emna. “Monitoring of temperature effects on CMOS memories : Monitoring des effets de la température sur les mémoires CMOS.” 2018. Doctoral Dissertation, Montpellier. Accessed April 22, 2021. http://www.theses.fr/2018MONTS091.

MLA Handbook (7th Edition):

Farjallah, Emna. “Monitoring of temperature effects on CMOS memories : Monitoring des effets de la température sur les mémoires CMOS.” 2018. Web. 22 Apr 2021.

Vancouver:

Farjallah E. Monitoring of temperature effects on CMOS memories : Monitoring des effets de la température sur les mémoires CMOS. [Internet] [Doctoral dissertation]. Montpellier; 2018. [cited 2021 Apr 22]. Available from: http://www.theses.fr/2018MONTS091.

Council of Science Editors:

Farjallah E. Monitoring of temperature effects on CMOS memories : Monitoring des effets de la température sur les mémoires CMOS. [Doctoral Dissertation]. Montpellier; 2018. Available from: http://www.theses.fr/2018MONTS091


Université de Grenoble

27. Akyel, Kaya Can. Statistical methodologies for modelling the impact of process variability in ultra-deep-submicron SRAMs : Méthodologie statistique de modélisation pour l'optimisation de l'offre SRAM 'basse puissance'.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2014, Université de Grenoble

La miniaturisation des transistors vers ses ultimes limites physiques a exacerbé les effets négatifs qui sont liées à la granularité de la matière. Plusieurs nouvelles… (more)

Subjects/Keywords: SRAM; Variabilité; RTS; Modélisation statistique; SRAM; Minimum operating voltage; Variability; RTS; Modelling; Variability-aware design; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Akyel, K. C. (2014). Statistical methodologies for modelling the impact of process variability in ultra-deep-submicron SRAMs : Méthodologie statistique de modélisation pour l'optimisation de l'offre SRAM 'basse puissance'. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2014GRENT080

Chicago Manual of Style (16th Edition):

Akyel, Kaya Can. “Statistical methodologies for modelling the impact of process variability in ultra-deep-submicron SRAMs : Méthodologie statistique de modélisation pour l'optimisation de l'offre SRAM 'basse puissance'.” 2014. Doctoral Dissertation, Université de Grenoble. Accessed April 22, 2021. http://www.theses.fr/2014GRENT080.

MLA Handbook (7th Edition):

Akyel, Kaya Can. “Statistical methodologies for modelling the impact of process variability in ultra-deep-submicron SRAMs : Méthodologie statistique de modélisation pour l'optimisation de l'offre SRAM 'basse puissance'.” 2014. Web. 22 Apr 2021.

Vancouver:

Akyel KC. Statistical methodologies for modelling the impact of process variability in ultra-deep-submicron SRAMs : Méthodologie statistique de modélisation pour l'optimisation de l'offre SRAM 'basse puissance'. [Internet] [Doctoral dissertation]. Université de Grenoble; 2014. [cited 2021 Apr 22]. Available from: http://www.theses.fr/2014GRENT080.

Council of Science Editors:

Akyel KC. Statistical methodologies for modelling the impact of process variability in ultra-deep-submicron SRAMs : Méthodologie statistique de modélisation pour l'optimisation de l'offre SRAM 'basse puissance'. [Doctoral Dissertation]. Université de Grenoble; 2014. Available from: http://www.theses.fr/2014GRENT080


University of Michigan

28. Wang, Jingcheng. Interconnect and Memory Design for Intelligent Mobile System.

Degree: PhD, Electrical and Computer Engineering, 2020, University of Michigan

 Technology scaling has driven the transistor to a smaller area, higher performance and lower power consuming which leads us into the mobile and edge computing… (more)

Subjects/Keywords: interconnect; low power SRAM; Compute-In-Memory; Neural Network Accelerator; low leakage SRAM; energy-efficient digital circuit; Electrical Engineering; Engineering

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APA (6th Edition):

Wang, J. (2020). Interconnect and Memory Design for Intelligent Mobile System. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/155232

Chicago Manual of Style (16th Edition):

Wang, Jingcheng. “Interconnect and Memory Design for Intelligent Mobile System.” 2020. Doctoral Dissertation, University of Michigan. Accessed April 22, 2021. http://hdl.handle.net/2027.42/155232.

MLA Handbook (7th Edition):

Wang, Jingcheng. “Interconnect and Memory Design for Intelligent Mobile System.” 2020. Web. 22 Apr 2021.

Vancouver:

Wang J. Interconnect and Memory Design for Intelligent Mobile System. [Internet] [Doctoral dissertation]. University of Michigan; 2020. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/2027.42/155232.

Council of Science Editors:

Wang J. Interconnect and Memory Design for Intelligent Mobile System. [Doctoral Dissertation]. University of Michigan; 2020. Available from: http://hdl.handle.net/2027.42/155232

29. Dounavi, Eleni - Maria. Self-healing integrated circuits/systems in semiconductor nanometer technologies.

Degree: 2020, University of Ioannina; Πανεπιστήμιο Ιωαννίνων

 The evolution of CMOS technology over the years has allowed the presence of billions of transistors in an integrated circuit. As the size of the… (more)

Subjects/Keywords: Αυτο-ίαση; Ανίχνευση γήρανσης; Μνήμες SRAM; Αξιοπιστία; Πρόβλεψη αστοχιών; Self-healing; Aging monitoring; SRAM memories; Reliability; Failure prediction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dounavi, E. -. M. (2020). Self-healing integrated circuits/systems in semiconductor nanometer technologies. (Thesis). University of Ioannina; Πανεπιστήμιο Ιωαννίνων. Retrieved from http://hdl.handle.net/10442/hedi/47477

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dounavi, Eleni - Maria. “Self-healing integrated circuits/systems in semiconductor nanometer technologies.” 2020. Thesis, University of Ioannina; Πανεπιστήμιο Ιωαννίνων. Accessed April 22, 2021. http://hdl.handle.net/10442/hedi/47477.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dounavi, Eleni - Maria. “Self-healing integrated circuits/systems in semiconductor nanometer technologies.” 2020. Web. 22 Apr 2021.

Vancouver:

Dounavi E-M. Self-healing integrated circuits/systems in semiconductor nanometer technologies. [Internet] [Thesis]. University of Ioannina; Πανεπιστήμιο Ιωαννίνων; 2020. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/10442/hedi/47477.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dounavi E-M. Self-healing integrated circuits/systems in semiconductor nanometer technologies. [Thesis]. University of Ioannina; Πανεπιστήμιο Ιωαννίνων; 2020. Available from: http://hdl.handle.net/10442/hedi/47477

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Washington State University

30. [No author]. Design Techniques and Tradeoffs of FinFET SRAM Memories .

Degree: 2013, Washington State University

 Nine novel eight-transistor (8T) FinFET SRAM cell schemes using different shorted gate (SG) or low power (LP) FinFET configurations are studied and evaluated comprehensively in… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; 6T SRAM; 8T SRAM; FinFET; High Performance; Low Leakage Current; Near-Threshold Operation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2013). Design Techniques and Tradeoffs of FinFET SRAM Memories . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/4752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “Design Techniques and Tradeoffs of FinFET SRAM Memories .” 2013. Thesis, Washington State University. Accessed April 22, 2021. http://hdl.handle.net/2376/4752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “Design Techniques and Tradeoffs of FinFET SRAM Memories .” 2013. Web. 22 Apr 2021.

Vancouver:

author] [. Design Techniques and Tradeoffs of FinFET SRAM Memories . [Internet] [Thesis]. Washington State University; 2013. [cited 2021 Apr 22]. Available from: http://hdl.handle.net/2376/4752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Design Techniques and Tradeoffs of FinFET SRAM Memories . [Thesis]. Washington State University; 2013. Available from: http://hdl.handle.net/2376/4752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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