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You searched for subject:(SOC). Showing records 1 – 30 of 562 total matches.

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1. Yu, Thomas Edison Chua. Studies on power-aware wrapper design for multi-clock domain cores using clock domain partitioning : マルチクロックドメインコアに対するクロックドメイン分割と消費電力を考慮したラッパー設計に関する研究; マルチクロックドメインコア ニ タイスル クロックドメイン ブンカツ ト ショウヒ デンリョク オ コウリョシタ ラッパーセッケイ ニ カンスル ケンキュウ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: SoC

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yu, T. E. C. (n.d.). Studies on power-aware wrapper design for multi-clock domain cores using clock domain partitioning : マルチクロックドメインコアに対するクロックドメイン分割と消費電力を考慮したラッパー設計に関する研究; マルチクロックドメインコア ニ タイスル クロックドメイン ブンカツ ト ショウヒ デンリョク オ コウリョシタ ラッパーセッケイ ニ カンスル ケンキュウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/4261

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yu, Thomas Edison Chua. “Studies on power-aware wrapper design for multi-clock domain cores using clock domain partitioning : マルチクロックドメインコアに対するクロックドメイン分割と消費電力を考慮したラッパー設計に関する研究; マルチクロックドメインコア ニ タイスル クロックドメイン ブンカツ ト ショウヒ デンリョク オ コウリョシタ ラッパーセッケイ ニ カンスル ケンキュウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 11, 2021. http://hdl.handle.net/10061/4261.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yu, Thomas Edison Chua. “Studies on power-aware wrapper design for multi-clock domain cores using clock domain partitioning : マルチクロックドメインコアに対するクロックドメイン分割と消費電力を考慮したラッパー設計に関する研究; マルチクロックドメインコア ニ タイスル クロックドメイン ブンカツ ト ショウヒ デンリョク オ コウリョシタ ラッパーセッケイ ニ カンスル ケンキュウ.” Web. 11 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Yu TEC. Studies on power-aware wrapper design for multi-clock domain cores using clock domain partitioning : マルチクロックドメインコアに対するクロックドメイン分割と消費電力を考慮したラッパー設計に関する研究; マルチクロックドメインコア ニ タイスル クロックドメイン ブンカツ ト ショウヒ デンリョク オ コウリョシタ ラッパーセッケイ ニ カンスル ケンキュウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10061/4261.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Yu TEC. Studies on power-aware wrapper design for multi-clock domain cores using clock domain partitioning : マルチクロックドメインコアに対するクロックドメイン分割と消費電力を考慮したラッパー設計に関する研究; マルチクロックドメインコア ニ タイスル クロックドメイン ブンカツ ト ショウヒ デンリョク オ コウリョシタ ラッパーセッケイ ニ カンスル ケンキュウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/4261

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

2. Miyazaki, Masahide. Studies on DFT for reducing its area and test application time of system-on-a-chip : システムオンチップのテスト回路面積とテスト実行時間を低減するテスト容易化設計法に関する研究; システムオンチップ ノ テスト カイロ メンセキ ト テスト ジッコウ ジカン オ テイゲンスル テスト ヨウイカ セッケイホウ ニ カンスル ケンキュウ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: SoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Miyazaki, M. (n.d.). Studies on DFT for reducing its area and test application time of system-on-a-chip : システムオンチップのテスト回路面積とテスト実行時間を低減するテスト容易化設計法に関する研究; システムオンチップ ノ テスト カイロ メンセキ ト テスト ジッコウ ジカン オ テイゲンスル テスト ヨウイカ セッケイホウ ニ カンスル ケンキュウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/2892

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Miyazaki, Masahide. “Studies on DFT for reducing its area and test application time of system-on-a-chip : システムオンチップのテスト回路面積とテスト実行時間を低減するテスト容易化設計法に関する研究; システムオンチップ ノ テスト カイロ メンセキ ト テスト ジッコウ ジカン オ テイゲンスル テスト ヨウイカ セッケイホウ ニ カンスル ケンキュウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 11, 2021. http://hdl.handle.net/10061/2892.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Miyazaki, Masahide. “Studies on DFT for reducing its area and test application time of system-on-a-chip : システムオンチップのテスト回路面積とテスト実行時間を低減するテスト容易化設計法に関する研究; システムオンチップ ノ テスト カイロ メンセキ ト テスト ジッコウ ジカン オ テイゲンスル テスト ヨウイカ セッケイホウ ニ カンスル ケンキュウ.” Web. 11 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Miyazaki M. Studies on DFT for reducing its area and test application time of system-on-a-chip : システムオンチップのテスト回路面積とテスト実行時間を低減するテスト容易化設計法に関する研究; システムオンチップ ノ テスト カイロ メンセキ ト テスト ジッコウ ジカン オ テイゲンスル テスト ヨウイカ セッケイホウ ニ カンスル ケンキュウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10061/2892.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Miyazaki M. Studies on DFT for reducing its area and test application time of system-on-a-chip : システムオンチップのテスト回路面積とテスト実行時間を低減するテスト容易化設計法に関する研究; システムオンチップ ノ テスト カイロ メンセキ ト テスト ジッコウ ジカン オ テイゲンスル テスト ヨウイカ セッケイホウ ニ カンスル ケンキュウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/2892

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

3. Yu, Thomas Edison Chua. Studies on Power, Thermal & False-path Aware Test Techniques for Modern System-on-Chips : 電力、温度およびフォールスパスを考慮したシステムオンチップのテスト技術に関する研究; デンリョク オンド オヨビ フォールスパス オ コウリョシタ システム オンチップ ノ テスト ギジュツ ニ カンスル ケンキュウ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: SoC

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yu, T. E. C. (n.d.). Studies on Power, Thermal & False-path Aware Test Techniques for Modern System-on-Chips : 電力、温度およびフォールスパスを考慮したシステムオンチップのテスト技術に関する研究; デンリョク オンド オヨビ フォールスパス オ コウリョシタ システム オンチップ ノ テスト ギジュツ ニ カンスル ケンキュウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/5203

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yu, Thomas Edison Chua. “Studies on Power, Thermal & False-path Aware Test Techniques for Modern System-on-Chips : 電力、温度およびフォールスパスを考慮したシステムオンチップのテスト技術に関する研究; デンリョク オンド オヨビ フォールスパス オ コウリョシタ システム オンチップ ノ テスト ギジュツ ニ カンスル ケンキュウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 11, 2021. http://hdl.handle.net/10061/5203.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yu, Thomas Edison Chua. “Studies on Power, Thermal & False-path Aware Test Techniques for Modern System-on-Chips : 電力、温度およびフォールスパスを考慮したシステムオンチップのテスト技術に関する研究; デンリョク オンド オヨビ フォールスパス オ コウリョシタ システム オンチップ ノ テスト ギジュツ ニ カンスル ケンキュウ.” Web. 11 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Yu TEC. Studies on Power, Thermal & False-path Aware Test Techniques for Modern System-on-Chips : 電力、温度およびフォールスパスを考慮したシステムオンチップのテスト技術に関する研究; デンリョク オンド オヨビ フォールスパス オ コウリョシタ システム オンチップ ノ テスト ギジュツ ニ カンスル ケンキュウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10061/5203.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Yu TEC. Studies on Power, Thermal & False-path Aware Test Techniques for Modern System-on-Chips : 電力、温度およびフォールスパスを考慮したシステムオンチップのテスト技術に関する研究; デンリョク オンド オヨビ フォールスパス オ コウリョシタ システム オンチップ ノ テスト ギジュツ ニ カンスル ケンキュウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/5203

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


AUT University

4. Xu, Stephen Sheng. System on Chip (SoC): a real time touch screen system on programmable chip .

Degree: 2012, AUT University

 This thesis is involved with the investigation, implementation, verification, validation and optimization of a purpose built on-chip solution customized for a real world touch screen… (more)

Subjects/Keywords: SoC; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xu, S. S. (2012). System on Chip (SoC): a real time touch screen system on programmable chip . (Thesis). AUT University. Retrieved from http://hdl.handle.net/10292/4412

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Stephen Sheng. “System on Chip (SoC): a real time touch screen system on programmable chip .” 2012. Thesis, AUT University. Accessed April 11, 2021. http://hdl.handle.net/10292/4412.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Stephen Sheng. “System on Chip (SoC): a real time touch screen system on programmable chip .” 2012. Web. 11 Apr 2021.

Vancouver:

Xu SS. System on Chip (SoC): a real time touch screen system on programmable chip . [Internet] [Thesis]. AUT University; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10292/4412.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu SS. System on Chip (SoC): a real time touch screen system on programmable chip . [Thesis]. AUT University; 2012. Available from: http://hdl.handle.net/10292/4412

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Oklahoma

5. Suarez, Hernan. REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS.

Degree: PhD, 2015, University of Oklahoma

 New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has… (more)

Subjects/Keywords: APC; SoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Suarez, H. (2015). REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS. (Doctoral Dissertation). University of Oklahoma. Retrieved from http://hdl.handle.net/11244/23338

Chicago Manual of Style (16th Edition):

Suarez, Hernan. “REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS.” 2015. Doctoral Dissertation, University of Oklahoma. Accessed April 11, 2021. http://hdl.handle.net/11244/23338.

MLA Handbook (7th Edition):

Suarez, Hernan. “REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS.” 2015. Web. 11 Apr 2021.

Vancouver:

Suarez H. REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS. [Internet] [Doctoral dissertation]. University of Oklahoma; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/11244/23338.

Council of Science Editors:

Suarez H. REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS. [Doctoral Dissertation]. University of Oklahoma; 2015. Available from: http://hdl.handle.net/11244/23338


NSYSU

6. Huang, Ming-Siang. Acceleration strategies for SystemC kernel.

Degree: Master, Institute Of Computer Science And Engineering, 2018, NSYSU

 Many manufacturers integrate several modules in the chip to enhance production efficiency in response to the increasing consumersâ needs, which elevates the complexity of chips.… (more)

Subjects/Keywords: SystemC; SoC; OSCI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, M. (2018). Acceleration strategies for SystemC kernel. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0527118-144248

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Ming-Siang. “Acceleration strategies for SystemC kernel.” 2018. Thesis, NSYSU. Accessed April 11, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0527118-144248.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Ming-Siang. “Acceleration strategies for SystemC kernel.” 2018. Web. 11 Apr 2021.

Vancouver:

Huang M. Acceleration strategies for SystemC kernel. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Apr 11]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0527118-144248.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang M. Acceleration strategies for SystemC kernel. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0527118-144248

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Kuo, Kuan-Fu. OCP-AHB Bus Interface for SoC Integration.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 A reliable scheme to reuse IP (Intellectual Property) cores became an important issue to accelerate the development of embedded systems. Unfortunately the diverse characteristic of… (more)

Subjects/Keywords: Interface; Bus; SoC; OCP; Integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kuo, K. (2011). OCP-AHB Bus Interface for SoC Integration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818111-151445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kuo, Kuan-Fu. “OCP-AHB Bus Interface for SoC Integration.” 2011. Thesis, NSYSU. Accessed April 11, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818111-151445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kuo, Kuan-Fu. “OCP-AHB Bus Interface for SoC Integration.” 2011. Web. 11 Apr 2021.

Vancouver:

Kuo K. OCP-AHB Bus Interface for SoC Integration. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Apr 11]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818111-151445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kuo K. OCP-AHB Bus Interface for SoC Integration. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818111-151445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. 増田, 公彦. 消費電力を考慮したマルチクロックドメインSoCのテストスケジューリングに関する研究 : Studies on Test Scheduling for Multi-Clock Domain SoCs with power constrraints; ショウヒ デンリョク オ コウリョシタ マルチ クロック ドメイン SoC ノ テスト スケジューリング ニ カンスル ケンキュウ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: マルチクロックドメインSoC

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

増田, . (n.d.). 消費電力を考慮したマルチクロックドメインSoCのテストスケジューリングに関する研究 : Studies on Test Scheduling for Multi-Clock Domain SoCs with power constrraints; ショウヒ デンリョク オ コウリョシタ マルチ クロック ドメイン SoC ノ テスト スケジューリング ニ カンスル ケンキュウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1699

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

増田, 公彦. “消費電力を考慮したマルチクロックドメインSoCのテストスケジューリングに関する研究 : Studies on Test Scheduling for Multi-Clock Domain SoCs with power constrraints; ショウヒ デンリョク オ コウリョシタ マルチ クロック ドメイン SoC ノ テスト スケジューリング ニ カンスル ケンキュウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 11, 2021. http://hdl.handle.net/10061/1699.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

増田, 公彦. “消費電力を考慮したマルチクロックドメインSoCのテストスケジューリングに関する研究 : Studies on Test Scheduling for Multi-Clock Domain SoCs with power constrraints; ショウヒ デンリョク オ コウリョシタ マルチ クロック ドメイン SoC ノ テスト スケジューリング ニ カンスル ケンキュウ.” Web. 11 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

増田 . 消費電力を考慮したマルチクロックドメインSoCのテストスケジューリングに関する研究 : Studies on Test Scheduling for Multi-Clock Domain SoCs with power constrraints; ショウヒ デンリョク オ コウリョシタ マルチ クロック ドメイン SoC ノ テスト スケジューリング ニ カンスル ケンキュウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10061/1699.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

増田 . 消費電力を考慮したマルチクロックドメインSoCのテストスケジューリングに関する研究 : Studies on Test Scheduling for Multi-Clock Domain SoCs with power constrraints; ショウヒ デンリョク オ コウリョシタ マルチ クロック ドメイン SoC ノ テスト スケジューリング ニ カンスル ケンキュウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1699

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

9. 吉田, 宜司. 再構成可能ラッパーを用いたマルチクロック・ドメイン・コアのテスト時間最適化 : Test Time Optimization for Multi-Clock Domain Cores using Reconfigurable Wrappers; サイコウセイ カノウ ラッパー オ モチイタ マルチ クロック ドメイン コア ノ テスト ジカン サイテキカ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: SoC テスト

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

吉田, . (n.d.). 再構成可能ラッパーを用いたマルチクロック・ドメイン・コアのテスト時間最適化 : Test Time Optimization for Multi-Clock Domain Cores using Reconfigurable Wrappers; サイコウセイ カノウ ラッパー オ モチイタ マルチ クロック ドメイン コア ノ テスト ジカン サイテキカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/5106

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

吉田, 宜司. “再構成可能ラッパーを用いたマルチクロック・ドメイン・コアのテスト時間最適化 : Test Time Optimization for Multi-Clock Domain Cores using Reconfigurable Wrappers; サイコウセイ カノウ ラッパー オ モチイタ マルチ クロック ドメイン コア ノ テスト ジカン サイテキカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 11, 2021. http://hdl.handle.net/10061/5106.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

吉田, 宜司. “再構成可能ラッパーを用いたマルチクロック・ドメイン・コアのテスト時間最適化 : Test Time Optimization for Multi-Clock Domain Cores using Reconfigurable Wrappers; サイコウセイ カノウ ラッパー オ モチイタ マルチ クロック ドメイン コア ノ テスト ジカン サイテキカ.” Web. 11 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

吉田 . 再構成可能ラッパーを用いたマルチクロック・ドメイン・コアのテスト時間最適化 : Test Time Optimization for Multi-Clock Domain Cores using Reconfigurable Wrappers; サイコウセイ カノウ ラッパー オ モチイタ マルチ クロック ドメイン コア ノ テスト ジカン サイテキカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10061/5106.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

吉田 . 再構成可能ラッパーを用いたマルチクロック・ドメイン・コアのテスト時間最適化 : Test Time Optimization for Multi-Clock Domain Cores using Reconfigurable Wrappers; サイコウセイ カノウ ラッパー オ モチイタ マルチ クロック ドメイン コア ノ テスト ジカン サイテキカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/5106

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Penn State University

10. Yedlapalli, Praveen. A Study of Parallelism-locality Tradeoffs across Memory Hierarchy.

Degree: 2015, Penn State University

 As the number of cores on a chip increases, the memory bandwidth requirements become a scalability issue. Current CMPs incorporate multiple resources both on-chip and… (more)

Subjects/Keywords: Memory; SOC; parallelism; locality

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yedlapalli, P. (2015). A Study of Parallelism-locality Tradeoffs across Memory Hierarchy. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/26536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yedlapalli, Praveen. “A Study of Parallelism-locality Tradeoffs across Memory Hierarchy.” 2015. Thesis, Penn State University. Accessed April 11, 2021. https://submit-etda.libraries.psu.edu/catalog/26536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yedlapalli, Praveen. “A Study of Parallelism-locality Tradeoffs across Memory Hierarchy.” 2015. Web. 11 Apr 2021.

Vancouver:

Yedlapalli P. A Study of Parallelism-locality Tradeoffs across Memory Hierarchy. [Internet] [Thesis]. Penn State University; 2015. [cited 2021 Apr 11]. Available from: https://submit-etda.libraries.psu.edu/catalog/26536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yedlapalli P. A Study of Parallelism-locality Tradeoffs across Memory Hierarchy. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/26536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

11. Luo, Chenjie. Smart Healthcare Device With IoT and Cloud Computing.

Degree: MS, Electrical Engineering, 2019, Texas A&M University

 Internet of Things (IoT) is a system of interrelated digital devices such as home appliances which could connect, communicate and exchange data with each other.… (more)

Subjects/Keywords: IoT; Healthcare; Mobile Communication; SoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Luo, C. (2019). Smart Healthcare Device With IoT and Cloud Computing. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/188768

Chicago Manual of Style (16th Edition):

Luo, Chenjie. “Smart Healthcare Device With IoT and Cloud Computing.” 2019. Masters Thesis, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/188768.

MLA Handbook (7th Edition):

Luo, Chenjie. “Smart Healthcare Device With IoT and Cloud Computing.” 2019. Web. 11 Apr 2021.

Vancouver:

Luo C. Smart Healthcare Device With IoT and Cloud Computing. [Internet] [Masters thesis]. Texas A&M University; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/188768.

Council of Science Editors:

Luo C. Smart Healthcare Device With IoT and Cloud Computing. [Masters Thesis]. Texas A&M University; 2019. Available from: http://hdl.handle.net/1969.1/188768


Karlstad University

12. Lindström, Björn. Metodik för analys av batteriets laddningscykel i entreprenadmaskiner : Prototypbyggnad och teori.

Degree: Engineering and Physics, 2015, Karlstad University

Volvo Construction Equipment AB, Volvo CE, är en global tillverkare av entreprenadmaskiner. Detta exjobb fokuserar på batterierna i dessa entreprenadmaskiner som försörjer maskinens elsystem… (more)

Subjects/Keywords: Batterier; dimensionering; SOC; SOH; Entreprenadmaskiner

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lindström, B. (2015). Metodik för analys av batteriets laddningscykel i entreprenadmaskiner : Prototypbyggnad och teori. (Thesis). Karlstad University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-36685

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lindström, Björn. “Metodik för analys av batteriets laddningscykel i entreprenadmaskiner : Prototypbyggnad och teori.” 2015. Thesis, Karlstad University. Accessed April 11, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-36685.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lindström, Björn. “Metodik för analys av batteriets laddningscykel i entreprenadmaskiner : Prototypbyggnad och teori.” 2015. Web. 11 Apr 2021.

Vancouver:

Lindström B. Metodik för analys av batteriets laddningscykel i entreprenadmaskiner : Prototypbyggnad och teori. [Internet] [Thesis]. Karlstad University; 2015. [cited 2021 Apr 11]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-36685.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lindström B. Metodik för analys av batteriets laddningscykel i entreprenadmaskiner : Prototypbyggnad och teori. [Thesis]. Karlstad University; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-36685

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rice University

13. Xu, Chao. Automated OS-level Device Runtime Power Management.

Degree: MS, Engineering, 2014, Rice University

 Hardware devices on a modern System-on-Chip (SoC), ranging from accelerators to IO controllers, usually account for the largest portion of the chip area. It is… (more)

Subjects/Keywords: Runtime power management; SoC; OS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xu, C. (2014). Automated OS-level Device Runtime Power Management. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/87791

Chicago Manual of Style (16th Edition):

Xu, Chao. “Automated OS-level Device Runtime Power Management.” 2014. Masters Thesis, Rice University. Accessed April 11, 2021. http://hdl.handle.net/1911/87791.

MLA Handbook (7th Edition):

Xu, Chao. “Automated OS-level Device Runtime Power Management.” 2014. Web. 11 Apr 2021.

Vancouver:

Xu C. Automated OS-level Device Runtime Power Management. [Internet] [Masters thesis]. Rice University; 2014. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1911/87791.

Council of Science Editors:

Xu C. Automated OS-level Device Runtime Power Management. [Masters Thesis]. Rice University; 2014. Available from: http://hdl.handle.net/1911/87791


Brno University of Technology

14. Kremel, Bruno. Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips.

Degree: 2019, Brno University of Technology

 This work reviews the development frameworks available for the Altera System-On-Chip solutions. These solutions are then compared to solutions available on the Xilinx platform. The… (more)

Subjects/Keywords: SoC; FPGA; Altera; Cyclone V SoC; Zynq; RSoC; SoC; FPGA; Altera; Cyclone V SoC; Zynq; RSoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kremel, B. (2019). Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/64072

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kremel, Bruno. “Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips.” 2019. Thesis, Brno University of Technology. Accessed April 11, 2021. http://hdl.handle.net/11012/64072.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kremel, Bruno. “Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips.” 2019. Web. 11 Apr 2021.

Vancouver:

Kremel B. Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/11012/64072.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kremel B. Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/64072

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boise State University

15. Austreng, Andrew Connor. The Carbon Budget Impact of Sagebrush Degradation.

Degree: 2012, Boise State University

 More than 20,000 km2 of sagebrush (Artemesia spp.) ecosystems within the Great Basin have been replaced, often following wildfire, by the nonnative winter annual cheatgrass… (more)

Subjects/Keywords: SOC; sagebrush; carbon; cheatgrass; Biogeochemistry

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Austreng, A. C. (2012). The Carbon Budget Impact of Sagebrush Degradation. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/268

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Austreng, Andrew Connor. “The Carbon Budget Impact of Sagebrush Degradation.” 2012. Thesis, Boise State University. Accessed April 11, 2021. https://scholarworks.boisestate.edu/td/268.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Austreng, Andrew Connor. “The Carbon Budget Impact of Sagebrush Degradation.” 2012. Web. 11 Apr 2021.

Vancouver:

Austreng AC. The Carbon Budget Impact of Sagebrush Degradation. [Internet] [Thesis]. Boise State University; 2012. [cited 2021 Apr 11]. Available from: https://scholarworks.boisestate.edu/td/268.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Austreng AC. The Carbon Budget Impact of Sagebrush Degradation. [Thesis]. Boise State University; 2012. Available from: https://scholarworks.boisestate.edu/td/268

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southampton

16. Gonciari, Paul Theo. Low cost test for core-based system-on-a-chip.

Degree: PhD, 2003, University of Southampton

 The availability of high level integration leads to building of millions of gates systemson- a-chip (SOC). Due to the high complexity of SOCs, testing them… (more)

Subjects/Keywords: 621; SOC

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APA (6th Edition):

Gonciari, P. T. (2003). Low cost test for core-based system-on-a-chip. (Doctoral Dissertation). University of Southampton. Retrieved from https://eprints.soton.ac.uk/257354/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.273845

Chicago Manual of Style (16th Edition):

Gonciari, Paul Theo. “Low cost test for core-based system-on-a-chip.” 2003. Doctoral Dissertation, University of Southampton. Accessed April 11, 2021. https://eprints.soton.ac.uk/257354/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.273845.

MLA Handbook (7th Edition):

Gonciari, Paul Theo. “Low cost test for core-based system-on-a-chip.” 2003. Web. 11 Apr 2021.

Vancouver:

Gonciari PT. Low cost test for core-based system-on-a-chip. [Internet] [Doctoral dissertation]. University of Southampton; 2003. [cited 2021 Apr 11]. Available from: https://eprints.soton.ac.uk/257354/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.273845.

Council of Science Editors:

Gonciari PT. Low cost test for core-based system-on-a-chip. [Doctoral Dissertation]. University of Southampton; 2003. Available from: https://eprints.soton.ac.uk/257354/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.273845


UCLA

17. Jia, Zhuo. Experimental Validation of Voltage-Based State-of-Charge Algorithm for Power Batteries.

Degree: Electrical Engineering, 2013, UCLA

 State-of-Charge (SOC) is a key to modeling and managing the battery system. Several algorithms have been developed to calculate the OCV (open-circuit voltage) based on… (more)

Subjects/Keywords: Electrical engineering; Power battery; SOC algorithm; Validation; Voltage based SOC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jia, Z. (2013). Experimental Validation of Voltage-Based State-of-Charge Algorithm for Power Batteries. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/1bj8j8tt

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jia, Zhuo. “Experimental Validation of Voltage-Based State-of-Charge Algorithm for Power Batteries.” 2013. Thesis, UCLA. Accessed April 11, 2021. http://www.escholarship.org/uc/item/1bj8j8tt.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jia, Zhuo. “Experimental Validation of Voltage-Based State-of-Charge Algorithm for Power Batteries.” 2013. Web. 11 Apr 2021.

Vancouver:

Jia Z. Experimental Validation of Voltage-Based State-of-Charge Algorithm for Power Batteries. [Internet] [Thesis]. UCLA; 2013. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/1bj8j8tt.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jia Z. Experimental Validation of Voltage-Based State-of-Charge Algorithm for Power Batteries. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/1bj8j8tt

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Marcelo Daniel Berejuck. Rede intra-chip com qualidade de serviços para uso em telecomunicações.

Degree: 2009, Universidade do Vale do Itajaí

O crescente aumento na densidade dos circuitos integrados tem permitido aos projetistas implementar múltiplos processadores de diferentes tipos em um mesmo chip. São sistemas completos… (more)

Subjects/Keywords: SoC; NoC; PABX; CIENCIA DA COMPUTACAO; SoC; NoC; PABX

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Berejuck, M. D. (2009). Rede intra-chip com qualidade de serviços para uso em telecomunicações. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Berejuck, Marcelo Daniel. “Rede intra-chip com qualidade de serviços para uso em telecomunicações.” 2009. Thesis, Universidade do Vale do Itajaí. Accessed April 11, 2021. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Berejuck, Marcelo Daniel. “Rede intra-chip com qualidade de serviços para uso em telecomunicações.” 2009. Web. 11 Apr 2021.

Vancouver:

Berejuck MD. Rede intra-chip com qualidade de serviços para uso em telecomunicações. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2009. [cited 2021 Apr 11]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Berejuck MD. Rede intra-chip com qualidade de serviços para uso em telecomunicações. [Thesis]. Universidade do Vale do Itajaí; 2009. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Grenoble

19. Faravelon, Aurélien. Une démarche de conception et d'implémentation de la protection de la vie privée basée sur le contrôle d'accès appliquée aux compositions de services : Design and Implementation of privacy in service compositions.

Degree: Docteur es, Informatique, 2013, Université de Grenoble

 La vie privée et sa protection sont aujourd'hui largement discutées. Membres de la société civile, juristes ou encore techniciens, nous sommes tous appelés à nous… (more)

Subjects/Keywords: SOC; SOA; Vie privée; SOC; SOA; Privacy; 004

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APA (6th Edition):

Faravelon, A. (2013). Une démarche de conception et d'implémentation de la protection de la vie privée basée sur le contrôle d'accès appliquée aux compositions de services : Design and Implementation of privacy in service compositions. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2013GRENM036

Chicago Manual of Style (16th Edition):

Faravelon, Aurélien. “Une démarche de conception et d'implémentation de la protection de la vie privée basée sur le contrôle d'accès appliquée aux compositions de services : Design and Implementation of privacy in service compositions.” 2013. Doctoral Dissertation, Université de Grenoble. Accessed April 11, 2021. http://www.theses.fr/2013GRENM036.

MLA Handbook (7th Edition):

Faravelon, Aurélien. “Une démarche de conception et d'implémentation de la protection de la vie privée basée sur le contrôle d'accès appliquée aux compositions de services : Design and Implementation of privacy in service compositions.” 2013. Web. 11 Apr 2021.

Vancouver:

Faravelon A. Une démarche de conception et d'implémentation de la protection de la vie privée basée sur le contrôle d'accès appliquée aux compositions de services : Design and Implementation of privacy in service compositions. [Internet] [Doctoral dissertation]. Université de Grenoble; 2013. [cited 2021 Apr 11]. Available from: http://www.theses.fr/2013GRENM036.

Council of Science Editors:

Faravelon A. Une démarche de conception et d'implémentation de la protection de la vie privée basée sur le contrôle d'accès appliquée aux compositions de services : Design and Implementation of privacy in service compositions. [Doctoral Dissertation]. Université de Grenoble; 2013. Available from: http://www.theses.fr/2013GRENM036


NSYSU

20. Kao, Chung-Fu. Exploration of Multiple ICEâs for Embedded Microprocessor Cores in an SOC.

Degree: Master, Computer Science and Engineering, 2000, NSYSU

SOC (System-On-Chip) designs are more and more popular, concurrently, more and more new challenges system integrators will meet. One out of these challenges is testing… (more)

Subjects/Keywords: SOC; IP; ICE

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kao, C. (2000). Exploration of Multiple ICEâs for Embedded Microprocessor Cores in an SOC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0821100-150631

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kao, Chung-Fu. “Exploration of Multiple ICEâs for Embedded Microprocessor Cores in an SOC.” 2000. Thesis, NSYSU. Accessed April 11, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0821100-150631.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kao, Chung-Fu. “Exploration of Multiple ICEâs for Embedded Microprocessor Cores in an SOC.” 2000. Web. 11 Apr 2021.

Vancouver:

Kao C. Exploration of Multiple ICEâs for Embedded Microprocessor Cores in an SOC. [Internet] [Thesis]. NSYSU; 2000. [cited 2021 Apr 11]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0821100-150631.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kao C. Exploration of Multiple ICEâs for Embedded Microprocessor Cores in an SOC. [Thesis]. NSYSU; 2000. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0821100-150631

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Chen, Li-Yao. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations… (more)

Subjects/Keywords: Integration; SOC; Programmable; SIMD; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, L. (2010). Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Thesis, NSYSU. Accessed April 11, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Web. 11 Apr 2021.

Vancouver:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Apr 11]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Yang, Fu-Ching. SYS-SIP SoC Development Infrastructure.

Degree: PhD, Computer Science and Engineering, 2009, NSYSU

 System-on-a-Chip (SoC) is a trend to achieve high performance, low cost, and low power in modern electronic devices. As the demand of functionality and performance… (more)

Subjects/Keywords: SoC development; Debug; Verification; Monitoring; External interrupt

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, F. (2009). SYS-SIP SoC Development Infrastructure. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012109-151215

Chicago Manual of Style (16th Edition):

Yang, Fu-Ching. “SYS-SIP SoC Development Infrastructure.” 2009. Doctoral Dissertation, NSYSU. Accessed April 11, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012109-151215.

MLA Handbook (7th Edition):

Yang, Fu-Ching. “SYS-SIP SoC Development Infrastructure.” 2009. Web. 11 Apr 2021.

Vancouver:

Yang F. SYS-SIP SoC Development Infrastructure. [Internet] [Doctoral dissertation]. NSYSU; 2009. [cited 2021 Apr 11]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012109-151215.

Council of Science Editors:

Yang F. SYS-SIP SoC Development Infrastructure. [Doctoral Dissertation]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012109-151215


NSYSU

23. Huang, Tzu-Ming. SoC Integration and Verification of a 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 While consumer demand for electronic equipment and more mature systems integration capabilities, it makes the system complexity of chip design increasing significantly. Also accompany an… (more)

Subjects/Keywords: Verification; Bus Bridge; SoC; 3D Graphics; Integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, T. (2011). SoC Integration and Verification of a 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Tzu-Ming. “SoC Integration and Verification of a 3D Graphics SoC.” 2011. Thesis, NSYSU. Accessed April 11, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Tzu-Ming. “SoC Integration and Verification of a 3D Graphics SoC.” 2011. Web. 11 Apr 2021.

Vancouver:

Huang T. SoC Integration and Verification of a 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Apr 11]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang T. SoC Integration and Verification of a 3D Graphics SoC. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Porto

24. Alves, Pedro Miguel Ferreira. Programmable flexible cores for SoC applications.

Degree: 2009, Universidade do Porto

Tese de mestrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 2009 Advisors/Committee Members: Ferreira, João Paulo de Castro Canas, Universidade do Porto. Faculdade de Engenharia.

Subjects/Keywords: Blocos digitais; Blocos lógicos programáveis; SoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alves, P. M. F. (2009). Programmable flexible cores for SoC applications. (Thesis). Universidade do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/58731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alves, Pedro Miguel Ferreira. “Programmable flexible cores for SoC applications.” 2009. Thesis, Universidade do Porto. Accessed April 11, 2021. http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/58731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alves, Pedro Miguel Ferreira. “Programmable flexible cores for SoC applications.” 2009. Web. 11 Apr 2021.

Vancouver:

Alves PMF. Programmable flexible cores for SoC applications. [Internet] [Thesis]. Universidade do Porto; 2009. [cited 2021 Apr 11]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/58731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alves PMF. Programmable flexible cores for SoC applications. [Thesis]. Universidade do Porto; 2009. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/58731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tasmania

25. de Deuge, JK. Exploratory study of factors that influence parental adaptation during the autism spectrum disorder diagnostic process.

Degree: 2015, University of Tasmania

 Due to the complexity of diagnosing Autism Spectrum Disorder (ASD) a multidisciplinary diagnostic approach represents best practice quality care. This process can however be time… (more)

Subjects/Keywords: ASD; social-support; SOC; multidisciplinary diagnosis

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APA (6th Edition):

de Deuge, J. (2015). Exploratory study of factors that influence parental adaptation during the autism spectrum disorder diagnostic process. (Thesis). University of Tasmania. Retrieved from https://eprints.utas.edu.au/23567/1/de_Deuge_whole_thesis.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

de Deuge, JK. “Exploratory study of factors that influence parental adaptation during the autism spectrum disorder diagnostic process.” 2015. Thesis, University of Tasmania. Accessed April 11, 2021. https://eprints.utas.edu.au/23567/1/de_Deuge_whole_thesis.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

de Deuge, JK. “Exploratory study of factors that influence parental adaptation during the autism spectrum disorder diagnostic process.” 2015. Web. 11 Apr 2021.

Vancouver:

de Deuge J. Exploratory study of factors that influence parental adaptation during the autism spectrum disorder diagnostic process. [Internet] [Thesis]. University of Tasmania; 2015. [cited 2021 Apr 11]. Available from: https://eprints.utas.edu.au/23567/1/de_Deuge_whole_thesis.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

de Deuge J. Exploratory study of factors that influence parental adaptation during the autism spectrum disorder diagnostic process. [Thesis]. University of Tasmania; 2015. Available from: https://eprints.utas.edu.au/23567/1/de_Deuge_whole_thesis.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Colorado State University

26. Bahirat, Shirish. Design and synthesis of hybrid nanophotonic-electric network-on-chip architectures.

Degree: PhD, Electrical and Computer Engineering, 2014, Colorado State University

 With increasing application complexity and improvements in CMOS process technology, chip multiprocessors (CMPs) with tens to hundreds of cores on a chip are today becoming… (more)

Subjects/Keywords: CMP; hybrid nanophotonics; MPSOC; NOC; photonics; SOC

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APA (6th Edition):

Bahirat, S. (2014). Design and synthesis of hybrid nanophotonic-electric network-on-chip architectures. (Doctoral Dissertation). Colorado State University. Retrieved from http://hdl.handle.net/10217/82580

Chicago Manual of Style (16th Edition):

Bahirat, Shirish. “Design and synthesis of hybrid nanophotonic-electric network-on-chip architectures.” 2014. Doctoral Dissertation, Colorado State University. Accessed April 11, 2021. http://hdl.handle.net/10217/82580.

MLA Handbook (7th Edition):

Bahirat, Shirish. “Design and synthesis of hybrid nanophotonic-electric network-on-chip architectures.” 2014. Web. 11 Apr 2021.

Vancouver:

Bahirat S. Design and synthesis of hybrid nanophotonic-electric network-on-chip architectures. [Internet] [Doctoral dissertation]. Colorado State University; 2014. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10217/82580.

Council of Science Editors:

Bahirat S. Design and synthesis of hybrid nanophotonic-electric network-on-chip architectures. [Doctoral Dissertation]. Colorado State University; 2014. Available from: http://hdl.handle.net/10217/82580


Jönköping University

27. Johansson, Louise. Att leva med depression : En analys av självbiografier.

Degree: Dep. of Nursing Science, 2016, Jönköping University

Bakgrund: Depression är en sjukdom som kännetecknas av bland annat nedstämdhet, orkeslöshet och känslor av meningslöshet som skiljer sig från vanliga stämningssvackor. Depression beräknas… (more)

Subjects/Keywords: Experience; nursing; SOC; KASAM; omvårdnad; upplevelse

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Johansson, L. (2016). Att leva med depression : En analys av självbiografier. (Thesis). Jönköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-30366

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Johansson, Louise. “Att leva med depression : En analys av självbiografier.” 2016. Thesis, Jönköping University. Accessed April 11, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-30366.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Johansson, Louise. “Att leva med depression : En analys av självbiografier.” 2016. Web. 11 Apr 2021.

Vancouver:

Johansson L. Att leva med depression : En analys av självbiografier. [Internet] [Thesis]. Jönköping University; 2016. [cited 2021 Apr 11]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-30366.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Johansson L. Att leva med depression : En analys av självbiografier. [Thesis]. Jönköping University; 2016. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-30366

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Karlsson, Malin. Det räcker inte att laga bron över livsfloden, man måste även lära barnen att simma! : En kvalitativ studie för att få en djupare förståelse om socialarbetare upplever att barn som deltar i Trappan-insatsen får en känsla av sammanhang?.

Degree: Social Work, 2014, Dalarna University

  The aim of this qualitative study was to get a deeper understanding of social workers experience that children who participate in the Trappan-insatsen get… (more)

Subjects/Keywords: Children; Domestic Violence; treatment; SOC; Trappan-samtal

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Karlsson, M. (2014). Det räcker inte att laga bron över livsfloden, man måste även lära barnen att simma! : En kvalitativ studie för att få en djupare förståelse om socialarbetare upplever att barn som deltar i Trappan-insatsen får en känsla av sammanhang?. (Thesis). Dalarna University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:du-17081

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Karlsson, Malin. “Det räcker inte att laga bron över livsfloden, man måste även lära barnen att simma! : En kvalitativ studie för att få en djupare förståelse om socialarbetare upplever att barn som deltar i Trappan-insatsen får en känsla av sammanhang?.” 2014. Thesis, Dalarna University. Accessed April 11, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:du-17081.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Karlsson, Malin. “Det räcker inte att laga bron över livsfloden, man måste även lära barnen att simma! : En kvalitativ studie för att få en djupare förståelse om socialarbetare upplever att barn som deltar i Trappan-insatsen får en känsla av sammanhang?.” 2014. Web. 11 Apr 2021.

Vancouver:

Karlsson M. Det räcker inte att laga bron över livsfloden, man måste även lära barnen att simma! : En kvalitativ studie för att få en djupare förståelse om socialarbetare upplever att barn som deltar i Trappan-insatsen får en känsla av sammanhang?. [Internet] [Thesis]. Dalarna University; 2014. [cited 2021 Apr 11]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:du-17081.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Karlsson M. Det räcker inte att laga bron över livsfloden, man måste även lära barnen att simma! : En kvalitativ studie för att få en djupare förståelse om socialarbetare upplever att barn som deltar i Trappan-insatsen får en känsla av sammanhang?. [Thesis]. Dalarna University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:du-17081

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

29. Stekas, N. (author). FPGA accelerated Facial Recognition.

Degree: 2016, Delft University of Technology

The ability to recognize faces is highly important in many areas of development. Though the years, the evolving technologies, enabled this process to be adapted… (more)

Subjects/Keywords: FPGA; SoC; face regcognition; real-time

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Stekas, N. (. (2016). FPGA accelerated Facial Recognition. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:359825f9-ed16-43f4-a998-d2028a6c3204

Chicago Manual of Style (16th Edition):

Stekas, N (author). “FPGA accelerated Facial Recognition.” 2016. Masters Thesis, Delft University of Technology. Accessed April 11, 2021. http://resolver.tudelft.nl/uuid:359825f9-ed16-43f4-a998-d2028a6c3204.

MLA Handbook (7th Edition):

Stekas, N (author). “FPGA accelerated Facial Recognition.” 2016. Web. 11 Apr 2021.

Vancouver:

Stekas N(. FPGA accelerated Facial Recognition. [Internet] [Masters thesis]. Delft University of Technology; 2016. [cited 2021 Apr 11]. Available from: http://resolver.tudelft.nl/uuid:359825f9-ed16-43f4-a998-d2028a6c3204.

Council of Science Editors:

Stekas N(. FPGA accelerated Facial Recognition. [Masters Thesis]. Delft University of Technology; 2016. Available from: http://resolver.tudelft.nl/uuid:359825f9-ed16-43f4-a998-d2028a6c3204


Princeton University

30. Davies, Gregory. Characterization of batteries using ultrasound: applications for battery management and structural determination .

Degree: PhD, 2018, Princeton University

 Ultrasound has been an invaluable and widely used tool in the medical and non-destructive testing (NDT) sectors. Much of its success is attributable to its… (more)

Subjects/Keywords: Batteries; Inversions; SOC; SOH; Ultrasound; XRD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Davies, G. (2018). Characterization of batteries using ultrasound: applications for battery management and structural determination . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01cn69m683b

Chicago Manual of Style (16th Edition):

Davies, Gregory. “Characterization of batteries using ultrasound: applications for battery management and structural determination .” 2018. Doctoral Dissertation, Princeton University. Accessed April 11, 2021. http://arks.princeton.edu/ark:/88435/dsp01cn69m683b.

MLA Handbook (7th Edition):

Davies, Gregory. “Characterization of batteries using ultrasound: applications for battery management and structural determination .” 2018. Web. 11 Apr 2021.

Vancouver:

Davies G. Characterization of batteries using ultrasound: applications for battery management and structural determination . [Internet] [Doctoral dissertation]. Princeton University; 2018. [cited 2021 Apr 11]. Available from: http://arks.princeton.edu/ark:/88435/dsp01cn69m683b.

Council of Science Editors:

Davies G. Characterization of batteries using ultrasound: applications for battery management and structural determination . [Doctoral Dissertation]. Princeton University; 2018. Available from: http://arks.princeton.edu/ark:/88435/dsp01cn69m683b

[1] [2] [3] [4] [5] … [19]

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