subject:(SIMD)

Rochester Institute of Technology

1. Mazza, James P. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.

Degree: MS, Electrical Engineering, 2014, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/8604

► Data parallel image processing algorithms have numerous uses in many real time applications. Depending on the complexity of the computations involved, these algorithms may… (more)

Subjects/Keywords: FPGA; Hardward; SIMD

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APA (6^th Edition):

Mazza, J. P. (2014). Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8604

Chicago Manual of Style (16^th Edition):

Mazza, James P. “Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.” 2014. Masters Thesis, Rochester Institute of Technology. Accessed July 23, 2019. https://scholarworks.rit.edu/theses/8604.

MLA Handbook (7^th Edition):

Mazza, James P. “Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.” 2014. Web. 23 Jul 2019.

Vancouver:

Mazza JP. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. [Internet] [Masters thesis]. Rochester Institute of Technology; 2014. [cited 2019 Jul 23]. Available from: https://scholarworks.rit.edu/theses/8604.

Council of Science Editors:

Mazza JP. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. [Masters Thesis]. Rochester Institute of Technology; 2014. Available from: https://scholarworks.rit.edu/theses/8604

NSYSU

2. Huang, Kuan-min. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

► 3D graphics pipeline can be divided into two subsystems: geometry subsystem and rendering subsystem. Hardware implementation of the transformation and lighting in the geometric subsystem… (more)

Subjects/Keywords: Vertex Shader; SIMD; Programmable

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APA (6^th Edition):

Huang, K. (2009). Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Thesis, NSYSU. Accessed July 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Web. 23 Jul 2019.

Vancouver:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Jul 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

3. Pan, Po-Hsun. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.

Degree: Master, Electrical Engineering, 2011, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

► In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. To identify human behavior which achieve… (more)

▼ In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. To identify human behavior which achieve the surveillance has great help by video automation in aspect of home caring, personal property and homeland security. To achieve action recognition, there are many factors to be considered, primarily the accuracy and real-time. If we can parallelize the action recognition algorithm, it will be a greatly improvement to the real-time processing capability of the algorithm. To achieve real-time demand, we study how to implement action recognition algorithm parallelization in the CELL B.E. platform. The action recognition algorithm with our design is faster than the original algorithm; it has 231 times speed up. We found that in the action recognition algorithm, there are many repeated operation between blocks, it can be parallelize by using single-instruction multiple-data architecture. In the action recognition algorithms, there are four major algorithms, DMASKS, HMHHb, MGD, SVM. The SIMD instructions in CELL B.E. platform can compute 128 bits data at once. While doing DMASKS, SIMD parallelism can reach 16 times, HMHHb parallelism up to 128 times, MGD parallelism up to 8 times, and SVM can reach 4 times. Based on CELL B.E. acceleration mechanism, we achieve high-performance computing models with multi-threading and multiple streaming. Our study showed that the action recognition algorithm is very suitable for multi-core system with parallel processing SIMD architecture. The parallelization for action recognition algorithm will have more immediate response in identifying human action. With the advantages of real-time, it can be expected to include more complex algorithms for the accuracy of algorithm in the future, to achieve both immediacy and accuracy. Advisors/Committee Members: Wann-Yun Shieh (chair), Chung-Ping Chung (chair), Jih-Ching Chiu (committee member), Chia-Hung Yeh (chair).

Subjects/Keywords: action recognition; SIMD; CELL; parallelize

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APA (6^th Edition):

Pan, P. (2011). The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pan, Po-Hsun. “The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.” 2011. Thesis, NSYSU. Accessed July 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pan, Po-Hsun. “The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.” 2011. Web. 23 Jul 2019.

Vancouver:

Pan P. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. [Internet] [Thesis]. NSYSU; 2011. [cited 2019 Jul 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pan P. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. 松本, 剛英. 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

URL: http://hdl.handle.net/10061/1770

Subjects/Keywords: プロセッサ; SIMD

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APA (6^th Edition):

松本, �. (n.d.). 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1770

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

松本, 剛英. “組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed July 23, 2019. http://hdl.handle.net/10061/1770.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

松本, 剛英. “組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ.” Web. 23 Jul 2019.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

松本 �. 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2019 Jul 23]. Available from: http://hdl.handle.net/10061/1770.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

松本 �. 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1770

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Linköping University

5. Chan, Chun-Jung. Investigation of NoGap : SIMD Datapath Implementation.

Degree: Electrical Engineering, 2011, Linköping University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131

► Nowadays, many ASIP systems with high computational capabilities are designed in order to fulfill the increasing demands of technical applications. However, the design of… (more)

Subjects/Keywords: ASIP; NoGap; ePUMA; Sleipnir; SIMD

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APA (6^th Edition):

Chan, C. (2011). Investigation of NoGap : SIMD Datapath Implementation. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chan, Chun-Jung. “Investigation of NoGap : SIMD Datapath Implementation.” 2011. Thesis, Linköping University. Accessed July 23, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chan, Chun-Jung. “Investigation of NoGap : SIMD Datapath Implementation.” 2011. Web. 23 Jul 2019.

Vancouver:

Chan C. Investigation of NoGap : SIMD Datapath Implementation. [Internet] [Thesis]. Linköping University; 2011. [cited 2019 Jul 23]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chan C. Investigation of NoGap : SIMD Datapath Implementation. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Delft University of Technology

6. De Smalen, S. A solution to misaligned data access in a vectorizing compiler framework:.

Degree: 2009, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f

► Vectorizing code for short vector architectures as employed by today’s multimedia extensions comes with a number of issues. The responsibilities of these issues are moved… (more)

Subjects/Keywords: SIMD; vectorization; compiler; alignment

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APA (6^th Edition):

De Smalen, S. (2009). A solution to misaligned data access in a vectorizing compiler framework:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f

Chicago Manual of Style (16^th Edition):

De Smalen, S. “A solution to misaligned data access in a vectorizing compiler framework:.” 2009. Masters Thesis, Delft University of Technology. Accessed July 23, 2019. http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f.

MLA Handbook (7^th Edition):

De Smalen, S. “A solution to misaligned data access in a vectorizing compiler framework:.” 2009. Web. 23 Jul 2019.

Vancouver:

De Smalen S. A solution to misaligned data access in a vectorizing compiler framework:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2019 Jul 23]. Available from: http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f.

Council of Science Editors:

De Smalen S. A solution to misaligned data access in a vectorizing compiler framework:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f

NSYSU

7. Chang, Hsin-Tzu. Study on LTE MIMO System in SIMD Architecture.

Degree: Master, Communications Engineering, 2018, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738

► In order to increase the spectral efficiency under limited bandwidth, the main technology Long Term Evolution (LTE) of the Fourth Generation of Mobile Phone Mobile… (more)

Subjects/Keywords: MKL; MIMO; SIMD; OFDM; LTE

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APA (6^th Edition):

Chang, H. (2018). Study on LTE MIMO System in SIMD Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chang, Hsin-Tzu. “Study on LTE MIMO System in SIMD Architecture.” 2018. Thesis, NSYSU. Accessed July 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chang, Hsin-Tzu. “Study on LTE MIMO System in SIMD Architecture.” 2018. Web. 23 Jul 2019.

Vancouver:

Chang H. Study on LTE MIMO System in SIMD Architecture. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Jul 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang H. Study on LTE MIMO System in SIMD Architecture. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of New South Wales

8. Zhang, Feng. Accelerating Tree-Based Irregular Applications by Exploiting SIMD Parallelism.

Degree: Computer Science & Engineering, 2018, University of New South Wales

URL: http://handle.unsw.edu.au/1959.4/60429

► Tree structures are one of the most pervasive data structures. Many tree-based applications feature abundant amount of data level parallelism (DLP), and modern SIMD architectures,… (more)

▼ Tree structures are one of the most pervasive data structures. Many tree-based applications feature abundant amount of data level parallelism (DLP), and modern SIMD architectures, such as GPUs and the SIMD instruction extension to CPUs, appear well-suited. However, due to the high irregularity in control flow and data accesses of these applications, exploiting DLP on SIMD architectures is difficult and transforming the SIMD resources into real performance is challenging.This thesis focuses on two such irregular applications: intensive tree search and repeated tree traversals, and proposes two corresponding approaches on CPUs and GPUs.The first proposed approach is Poker, a permutation-based SIMD approach for vectorizing intensive search queries over B+-trees on the SIMD instruction extension to CPUs. B+-trees are popular indexing structures in read-mostly in-memory database systems, in which they are repeatedly searched by numerous independent queries but remain unchanged for a long period. The vectorization of queries in such a problem is hampered by irregular memory accesses. The key insight is to combine vector loads and path-encoding-based permutations to alleviate memory latency while keeping the number of key comparisons required for a query to a minimum. Implemented as a C++ template library, Poker represents a general-purpose solution for vectorizing such an intensive tree search problem on multi-core CPU processors equipped with SIMD units.The next proposed approach is RegTT, a new parallelization approach that orchestrates an efficient execution of a repeated tree traversal algorithm on GPUs. Unlike intensive tree search, repeated tree traversals allow a query to visit each tree node exactly once unless truncated otherwise. Given abundant queries, their efficient parallelization on GPUs is hindered by branch divergence, load imbalance and memory access irregularity, as the nodes and their visitation orders differ significantly under different queries. Based on a key insight into several truncation-induced tree traversal regularities, RegTT employs a new traversal algorithm by beginning with breadth-first traversal, then reordering the queries being processed (based on their truncation histories) and finally switching to depth-first traversal. This enables as many threads as possible in the same warp to visit the same node simultaneously, enhancing both GPU resource utilization and memory coalescing.Both Poker and RegTT are evaluated on representative benchmarks, and their advantages are demonstrated with significant speedups over state-of-the-art works. Advisors/Committee Members: Xue, Jingling, Computer Science & Engineering, Faculty of Engineering, UNSW.

Subjects/Keywords: SIMD; Tree structures; Irregular applications

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhang, F. (2018). Accelerating Tree-Based Irregular Applications by Exploiting SIMD Parallelism. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60429

Chicago Manual of Style (16^th Edition):

Zhang, Feng. “Accelerating Tree-Based Irregular Applications by Exploiting SIMD Parallelism.” 2018. Doctoral Dissertation, University of New South Wales. Accessed July 23, 2019. http://handle.unsw.edu.au/1959.4/60429.

MLA Handbook (7^th Edition):

Zhang, Feng. “Accelerating Tree-Based Irregular Applications by Exploiting SIMD Parallelism.” 2018. Web. 23 Jul 2019.

Vancouver:

Zhang F. Accelerating Tree-Based Irregular Applications by Exploiting SIMD Parallelism. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2019 Jul 23]. Available from: http://handle.unsw.edu.au/1959.4/60429.

Council of Science Editors:

Zhang F. Accelerating Tree-Based Irregular Applications by Exploiting SIMD Parallelism. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60429

Brno University of Technology

9. Benna, Filip. Optimalizace procesorového jádra pro knihovnu OpenCV .

Degree: 2015, Brno University of Technology

URL: http://hdl.handle.net/11012/52377

► Tato bakalářská práce se zabývá překladem knihovny OpenCV pro procesorové jádro Codix RISC a následnou optimalizací vybraných aplikací implementovaných s použitím této knihovny. Optimalizace je… (more)

Subjects/Keywords: OpenCV; Codix RISC; SIMD; optimalizace; OpenCV; Codix RISC; SIMD; optimization

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APA (6^th Edition):

Benna, F. (2015). Optimalizace procesorového jádra pro knihovnu OpenCV . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/52377

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Benna, Filip. “Optimalizace procesorového jádra pro knihovnu OpenCV .” 2015. Thesis, Brno University of Technology. Accessed July 23, 2019. http://hdl.handle.net/11012/52377.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Benna, Filip. “Optimalizace procesorového jádra pro knihovnu OpenCV .” 2015. Web. 23 Jul 2019.

Vancouver:

Benna F. Optimalizace procesorového jádra pro knihovnu OpenCV . [Internet] [Thesis]. Brno University of Technology; 2015. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/11012/52377.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Benna F. Optimalizace procesorového jádra pro knihovnu OpenCV . [Thesis]. Brno University of Technology; 2015. Available from: http://hdl.handle.net/11012/52377

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

10. Šnobl, Pavel. Překlad OpenCL aplikací pro vestavěné systémy .

Degree: 2016, Brno University of Technology

URL: http://hdl.handle.net/11012/61853

► Tato diplomová práce se zabývá podporou pro překlad a spouštění programů napsaných pomocí OpenCL frameworku na vestavěných systémech. OpenCL je systém pro programování heterogenních systémů,… (more)

▼ Tato diplomová práce se zabývá podporou pro překlad a spouštění programů napsaných pomocí OpenCL frameworku na vestavěných systémech. OpenCL je systém pro programování heterogenních systémů, složených z procesorů, grafických akcelerátorů a dalších výpočetních zařízení. Využití má ovšem i na systémech skládajících se pouze z jedné výpočetní jednotky, kde umožňuje zápis paralelních programů (funkční a datový paralelismus) a práci s hierarchickým systémem pamětí. V rámci této práce jsou porovnány jednotlivé dostupné open source implementace OpenCL a následně je jedna vybraná integrována s překladačem LLVM. Tento překladač je generován v rámci sady nástrojů poskytovaných vývojovým prostředím pro tvorbu procesorů s aplikačně specifickou instrukční sadou zvaným Codasip Studio. Dále jsou navrženy a implementovány optimalizace pro architektury se SIMD instrukcemi a architektury typu VLIW. Výsledek je otestován a demonstrován na sadě testovacích aplikací.; This master's thesis deals with the support for compilation and execution of programs written using OpenCL framework on embedded systems. OpenCL is a system for programming heterogeneous systems comprising processors, graphic accelerators and other computing devices. But it also finds usage on systems composed of just one computing unit, where it allows to write parallel programs (task and data parallelism) and work with hierarchical system of memories. In this thesis, various available open source OpenCL implementations are compared and one selected is then integrated into LLVM compiler infrastructure. This compiler is generated as a part of toolchain provided by application specific instruction set architecture processor developement environment called Codasip Studio. Designed and implemented are also optimizations for architectures with SIMD instructions and VLIW architectures. The result is tested and demonstrated on a set of testing applications. Advisors/Committee Members: Hruška, Tomáš (advisor).

Subjects/Keywords: OpenCL; LLVM; Codasip; SIMD; VLIW; OpenCL; LLVM; Codasip; SIMD; VLIW

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APA (6^th Edition):

Šnobl, P. (2016). Překlad OpenCL aplikací pro vestavěné systémy . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy .” 2016. Thesis, Brno University of Technology. Accessed July 23, 2019. http://hdl.handle.net/11012/61853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy .” 2016. Web. 23 Jul 2019.

Vancouver:

Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy . [Internet] [Thesis]. Brno University of Technology; 2016. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/11012/61853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy . [Thesis]. Brno University of Technology; 2016. Available from: http://hdl.handle.net/11012/61853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

11. Šnobl, Pavel. Podpora SIMD instrukcí v překladači LLVM .

Degree: 2014, Brno University of Technology

URL: http://hdl.handle.net/11012/56572

► Tato bakalářská práce se zabývá podporou automatické vektorizace kódu v kompilačním frameworku LLVM a rozšířením modelu procesoru Codix o SIMD instrukce. Výsledkem je schopnost LLVM… (more)

Subjects/Keywords: SIMD; LLVM; Codix; CodAL; autovektorizace; SIMD; LLVM; Codix; CodAL; Auto-Vectorization

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APA (6^th Edition):

Šnobl, P. (2014). Podpora SIMD instrukcí v překladači LLVM . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/56572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Šnobl, Pavel. “Podpora SIMD instrukcí v překladači LLVM .” 2014. Thesis, Brno University of Technology. Accessed July 23, 2019. http://hdl.handle.net/11012/56572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Šnobl, Pavel. “Podpora SIMD instrukcí v překladači LLVM .” 2014. Web. 23 Jul 2019.

Vancouver:

Šnobl P. Podpora SIMD instrukcí v překladači LLVM . [Internet] [Thesis]. Brno University of Technology; 2014. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/11012/56572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šnobl P. Podpora SIMD instrukcí v překladači LLVM . [Thesis]. Brno University of Technology; 2014. Available from: http://hdl.handle.net/11012/56572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

12. Chen, Li-Yao. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

► OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations… (more)

Subjects/Keywords: Integration; SOC; Programmable; SIMD; Vertex Shader

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APA (6^th Edition):

Chen, L. (2010). Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Thesis, NSYSU. Accessed July 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Web. 23 Jul 2019.

Vancouver:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Jul 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

13. Li, Shang-Yu. Design and Implementation of a Vision Processor Based on the OpenVX Specification.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

► Embedded computer vision applications emphasizes fast and real-time processing speed with low power consumption. To face these challenge, we need more suitable hardware accelerator for… (more)

Subjects/Keywords: Computer vision applications; OpenVX; SIMD; Vision Processor

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APA (6^th Edition):

Li, S. (2016). Design and Implementation of a Vision Processor Based on the OpenVX Specification. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Thesis, NSYSU. Accessed July 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Web. 23 Jul 2019.

Vancouver:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Internet] [Thesis]. NSYSU; 2016. [cited 2019 Jul 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

14. Hsieh, Cheng-han. Study on Real-Time Software Architecture for LTE MIMO System.

Degree: Master, Communications Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659

► Long-term-evolution (LTE) and LTE-Advance are undoubtedly the most successful mobile broadband technologies in the fourth generation (4G) wireless system. LTE employs orthogonal frequency division multiplexing… (more)

Subjects/Keywords: MKL; parallel processing; MIMO; OFDM; LTE; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hsieh, C. (2017). Study on Real-Time Software Architecture for LTE MIMO System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hsieh, Cheng-han. “Study on Real-Time Software Architecture for LTE MIMO System.” 2017. Thesis, NSYSU. Accessed July 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hsieh, Cheng-han. “Study on Real-Time Software Architecture for LTE MIMO System.” 2017. Web. 23 Jul 2019.

Vancouver:

Hsieh C. Study on Real-Time Software Architecture for LTE MIMO System. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Jul 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh C. Study on Real-Time Software Architecture for LTE MIMO System. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Texas – Austin

15. Krimer, Evgeni. Improving energy efficiency of reliable massively-parallel architectures.

Degree: Electrical and Computer Engineering, 2012, University of Texas – Austin

URL: http://hdl.handle.net/2152/ETD-UT-2012-05-5473

► While transistor size continues to shrink every technology generation increasing the amount of transistors on a die, the reduction in energy consumption is less significant.… (more)

▼ While transistor size continues to shrink every technology generation increasing the amount of transistors on a die, the reduction in energy consumption is less significant. Furthermore, newer technologies induce fabrication challenges resulting in uncertainties in transistor and wire properties. Therefore to ensure correctness, design margins are introduced resulting in significantly sub-optimal energy efficiency. While increasing parallelism and the use of gating methods contribute to energy consumption reduction, ultimately, more radical changes to the architecture and better integration of architectural and circuit techniques will be necessary. This dissertation explores one such approach, combining a highly-efficient massively-parallel processor architecture with a design methodology that reduces energy by trimming design margins. Using a massively-parallel GPU-like (graphics processing unit) base- line architecture, we discuss the different components of process variation and design microarchitectural approaches supporting efficient margins reduction. We evaluate our design using a cycle-based GPU simulator, describe the conditions where efficiency improvements can be obtained, and explore the benefits of decoupling across a wide range of parameters. We architect a test-chip that was fabricated and show these mechanisms to work. We also discuss why previously developed related approaches fall short when process variation is very large, such as in low-voltage operation or as expected for future VLSI technology. We therefore develop and evaluate a new approach specifically for high-variation scenarios. To summarize, in this work, we address the emerging challenges of modern massively parallel architectures including energy efficient, reliable operation and high process variation. We believe that the results of this work are essential for breaking through the energy wall, continuing to improve the efficiency of future generations of the massively parallel architectures. Advisors/Committee Members: Erez, Mattan (advisor), John, Lizy K. (committee member), Orshansky, Michael (committee member), Gerstlauer, Andreas (committee member), Sentis, Luis (committee member).

Subjects/Keywords: SIMD; Energy-efficiency; Process variation; GPU; GPGPU

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APA (6^th Edition):

Krimer, E. (2012). Improving energy efficiency of reliable massively-parallel architectures. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2012-05-5473

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Krimer, Evgeni. “Improving energy efficiency of reliable massively-parallel architectures.” 2012. Thesis, University of Texas – Austin. Accessed July 23, 2019. http://hdl.handle.net/2152/ETD-UT-2012-05-5473.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Krimer, Evgeni. “Improving energy efficiency of reliable massively-parallel architectures.” 2012. Web. 23 Jul 2019.

Vancouver:

Krimer E. Improving energy efficiency of reliable massively-parallel architectures. [Internet] [Thesis]. University of Texas – Austin; 2012. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5473.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Krimer E. Improving energy efficiency of reliable massively-parallel architectures. [Thesis]. University of Texas – Austin; 2012. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5473

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of New South Wales

16. Zhou, Hao. Compiler techniques for improving SIMD parallelism.

Degree: Computer Science & Engineering, 2016, University of New South Wales

URL: http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true

► Modern CPUs are equipped with Single Instruction Multiple Data (SIMD) engines operating on short vectors, in order to meet the growing demands of accelerating multimedia… (more)

▼ Modern CPUs are equipped with Single Instruction Multiple Data (SIMD) engines operating on short vectors, in order to meet the growing demands of accelerating multimedia and scientific applications. Automatic simdization performed by the compiler, as a convenient way of utilizing the SIMD ISA extensions, however, faces challenges of translating SIMD resource into actual performance. Despite the fact that discovering SIMD parallelism is sometimes difficult due to the imprecise dependence analysis, for some SIMD parallelism that can be identified, current vectorization techniques are ineffective. In this thesis, we examine mixed SIMD parallelism and partial SIMD parallelism, which are both poorly exploited by the existing approaches. Two new vectorization techniques, i.e., Loop-Mix and Paver, are proposed, to tackle themrespectively. Existing loop vectorization techniques exploit either intra- or inter-iteration SIMD parallelism alone in a code region, if one part of the region vectorized for one type of parallelism has data dependences (called mixed-parallelism-inhibitingdependences) on the other part of the region vectorized for the other type of parallelism. We consider a class of loops that exhibit both types of parallelism in its code regions that contain mixed-parallelism-inhibiting data dependences (i.e.,mixed SIMD parallelism). We present a new compiler approach Loop-Mix for exploiting such mixed SIMD parallelism effectively by reducing the data reorganization overhead incurred when one type of parallelism is switched to the other. Additionally, existing loop vectorization techniques are ineffective for loops that exhibit little loop-level parallelism but some limited superword-level parallelism (SLP), where the SIMD parallelism is insufficient to fulfil the SIMD datapath (i.e., partial SIMD parallelism). We show that effectively vectorizing such loops requires partial vector operations to be executed correctly and efficiently. We present a simple yet effective SLP compiler technique, called Paver (PArtial VEctorizeR), formulated as a generalization of the traditional SLP algorithm, to optimize such partially vectorizable loops. The key idea is to maximize SIMD utilization by widening vector instructions used while minimizing the overheads caused by memory access, packing/unpacking, and/or masking operations, without introducing new memory errors or new numeric exceptions. Both Loop-Mix and Paver are simple and have been implemented in LLVM. We evaluate them with several real-world programs containing mixed or partial SIMD parallelism and demonstrate their performance advantages over the state-of-the-art. Advisors/Committee Members: Xue, Jingling, Computer Science & Engineering, Faculty of Engineering, UNSW.

Subjects/Keywords: Compiler; Vectorization; SIMD; Loop Vectorizer; SLP; Simdization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhou, H. (2016). Compiler techniques for improving SIMD parallelism. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true

Chicago Manual of Style (16^th Edition):

Zhou, Hao. “Compiler techniques for improving SIMD parallelism.” 2016. Doctoral Dissertation, University of New South Wales. Accessed July 23, 2019. http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true.

MLA Handbook (7^th Edition):

Zhou, Hao. “Compiler techniques for improving SIMD parallelism.” 2016. Web. 23 Jul 2019.

Vancouver:

Zhou H. Compiler techniques for improving SIMD parallelism. [Internet] [Doctoral dissertation]. University of New South Wales; 2016. [cited 2019 Jul 23]. Available from: http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true.

Council of Science Editors:

Zhou H. Compiler techniques for improving SIMD parallelism. [Doctoral Dissertation]. University of New South Wales; 2016. Available from: http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true

Northeastern University

17. Yilmazer, Ayse. Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS.

Degree: PhD, Department of Electrical and Computer Engineering, 2013, Northeastern University

URL: http://hdl.handle.net/2047/d20004880

► GPUs dedicate a majority of their transistor budgets to compute units rather than control logic. As a result, they can achieve excellent data-parallel power/performance. Given… (more)

▼ GPUs dedicate a majority of their transistor budgets to compute units rather than control logic. As a result, they can achieve excellent data-parallel power/performance. Given the continual demands for performance and power eefficiency, GPUs have become today's compute accelerators for many application domains.; The general purpose community has been focusing on developing strategies to move a broader class of applications to these powerful devices. The underlying GPU architecture has been adapted to run a limited class of general purpose computations present across a range of applications. Many applications have already been ported to GPU platforms to take advantage of the potential data-parallel performance that GPUs afford. But there still remain barriers to migrating a broader class of applications onto GPUs.; Being originally designed to run 3-D graphics, GPUs are highly optimized for graphics workloads. Graphics workloads possess a high degree of uniformity in their execution. Therefore, GPU architectures are optimized for efficient uniform execution. GPUs achieve high performance with data-parallel applications possessing regular control flow (i.e., predictable loops) and data access patterns that can effectively exploit high o-chip memory bandwidth. However, many general-purpose real world applications differ from graphics workloads-they come with large input sets exhibiting irregular access and synchronization patterns, and they possess varying computational granularity and irregular control flow. The current requirements for uniformity and predictability present barriers to moving a broader range of applications to GPUs. We believe if GPUs are going to become a mainstream computing device that it is necessary to relax some of these constraints. Only then can a wider variety of applications exploit the computational power of GPUs.; One critical barrier present in non-uniform data-parallel applications is the need to synchronize between threads. Fine-grained synchronization is needed to support shared data access, especially when faced with irregular access and communication patterns. This dissertation presents a new approach to enhance the efficiency and scalability of GPU synchronization. The proposed scheme can enable applications that work on shared data to effectively communicate at finer levels of granularity.; To achieve this ambitious goal, we propose a new synchronization approach called Hierarchical Queuing Locks (HQL). HQL is a novel hardware-based synchronization mechanism which provides efficient use of resources through execution blocking and hierarchical queuing. To provide a queue-based locking mechanism, HQL extends current GPU L1 and L2 cache management protocols by adding a synchronization protocol. Integration of HQL's synchronization protocol simplies the synchronization, but adds a level of complexity to the cache management protocol. Given this added complexity to the cache management scheme, as part of this dissertation we provide a formal verication of the proposed HQL synchronization…

Subjects/Keywords: GPU; SIMD Execution; Synchronization; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yilmazer, A. (2013). Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20004880

Chicago Manual of Style (16^th Edition):

Yilmazer, Ayse. “Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS.” 2013. Doctoral Dissertation, Northeastern University. Accessed July 23, 2019. http://hdl.handle.net/2047/d20004880.

MLA Handbook (7^th Edition):

Yilmazer, Ayse. “Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS.” 2013. Web. 23 Jul 2019.

Vancouver:

Yilmazer A. Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS. [Internet] [Doctoral dissertation]. Northeastern University; 2013. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/2047/d20004880.

Council of Science Editors:

Yilmazer A. Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS. [Doctoral Dissertation]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20004880

18. Winberg, Olov. Parallell beräkning av omslutande volymer.

Degree: Design and Engineering, 2010, Mälardalen University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-9439

► This paper presents techniques for speeding up commonly used algorithms forbounding volume (BV) computation, such as the AABB, sphere and k-DOP. Byexploiting the possibilities… (more)

Subjects/Keywords: Bounding volume; SIMD; parallel; k-DOP; AABB; Omslutande Volymer; SIMD; parallell; k-DOP; AABB

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Winberg, O. (2010). Parallell beräkning av omslutande volymer. (Thesis). Mälardalen University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-9439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Winberg, Olov. “Parallell beräkning av omslutande volymer.” 2010. Thesis, Mälardalen University. Accessed July 23, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-9439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Winberg, Olov. “Parallell beräkning av omslutande volymer.” 2010. Web. 23 Jul 2019.

Vancouver:

Winberg O. Parallell beräkning av omslutande volymer. [Internet] [Thesis]. Mälardalen University; 2010. [cited 2019 Jul 23]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-9439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Winberg O. Parallell beräkning av omslutande volymer. [Thesis]. Mälardalen University; 2010. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-9439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Bergach, Mohamed Amine. Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture.

Degree: Docteur es, Informatique, 2015, Nice

URL: http://www.theses.fr/2015NICE4060

►

Les architectures multi-cœurs Intel Core (IvyBridge, Haswell,...) contiennent à la fois des cœurs CPU généralistes (4), mais aussi des cœurs dédiés GPU embarqués sur cette… (more)

▼

Les architectures multi-cœurs Intel Core (IvyBridge, Haswell,...) contiennent à la fois des cœurs CPU généralistes (4), mais aussi des cœurs dédiés GPU embarqués sur cette même puce (16 et 40 respectivement). Dans le cadre de l'activité de la société Kontron (qui participe à ce financement de nature CIFRE) un objectif important est de calculer efficacement sur cette architecture des tableaux et séquences de transformées de Fourier rapides (FFT), comme par exemple on en trouve dans des applications radar. Alors que des bibliothèques natives (mais propriétaires) existent chez Intel pour les CPU, rien de tel n'est actuellement disponible pour la partie GPU. L'objectif de la thèse était donc de définir le placement efficace de modules FFT, en étudiant au niveau théorique la forme optimale permettant de regrouper des étages de calcul d'une telle FFT en fonction de la localité des données sur un cœur de calcul unique. Ce choix a priori permet d'espérer une efficacité des traitements, en ajustant la taille de la mémoire disponible à celles des données nécessaires. Ensuite la multiplicité des cœurs reste exploitable pour disposer plusieurs FFT calculées en parallèle, sans interférence (sauf contention du bus entre CPU et GPU). Nous avons obtenu des résultats significatifs, tant au niveau de l'implantation d'une FFT (1024 points) sur un cœur CPU SIMD, exprimée en langage C, que pour l'implantation d'une FFT de même taille sur un cœur GPU SIMT, exprimée alors en OpenCL. De plus nos résultats permettent de définir des règles pour synthétiser automatiquement de telles solutions, en fonction uniquement de la taille de la FFT son nombre d'étages plus précisément), et de la taille de la mémoire locale pour un coeur de calcul donné. Les performances obtenues sont supérieures à celles de la bibliothèque native Intel pour CPU), et démontrent un gain important de consommation sur GPU. Tous ces points sont détaillés dans le document de thèse. Ces résultats devraient donner lieu à exploitation au sein de la société Kontron.

Multicore architectures Intel Core (IvyBridge, Haswell…) contain both general purpose CPU cores (4) and dedicated GPU cores embedded on the same chip (16 and 40 respectively). As part of the activity of Kontron (the company partially funding this CIFRE scholarship), an important objective is to efficiently compute arrays and sequences of fast Fourier transforms (FFT) such as one finds in radar applications, on this architecture. While native (but proprietary) libraries exist for Intel CPU, nothing is currently available for the GPU part.The aim of the thesis was to define the efficient placement of FFT modules, and to study theoretically the optimal form for grouping computing stages of such FFT according to data locality on a single computing core. This choice should allow processing efficiency, by adjusting the memory size available to the required application data size. Then the multiplicity of cores is exploitable to compute several FFT in parallel, without interference (except for possible bus contention…

Advisors/Committee Members: Simone, Robert de (thesis director).

Subjects/Keywords: FFT; OpenCL; GPGPU; CPU; SIMD; SIMT; AAA; FFT; OpenCL; GPGPU; CPU; SIMD; SIMT; AAA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bergach, M. A. (2015). Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture. (Doctoral Dissertation). Nice. Retrieved from http://www.theses.fr/2015NICE4060

Chicago Manual of Style (16^th Edition):

Bergach, Mohamed Amine. “Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture.” 2015. Doctoral Dissertation, Nice. Accessed July 23, 2019. http://www.theses.fr/2015NICE4060.

MLA Handbook (7^th Edition):

Bergach, Mohamed Amine. “Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture.” 2015. Web. 23 Jul 2019.

Vancouver:

Bergach MA. Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture. [Internet] [Doctoral dissertation]. Nice; 2015. [cited 2019 Jul 23]. Available from: http://www.theses.fr/2015NICE4060.

Council of Science Editors:

Bergach MA. Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture. [Doctoral Dissertation]. Nice; 2015. Available from: http://www.theses.fr/2015NICE4060

20. Kalathingal, Sajith. Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread.

Degree: Docteur es, Informatique, 2016, Rennes 1

URL: http://www.theses.fr/2016REN1S133

►

De nombreux microprocesseurs modernes mettent en œuvre le multi-threading simultané (SMT) pour améliorer l'efficacité globale des processeurs superscalaires. SMT masque les opérations à longue latence… (more)

▼

De nombreux microprocesseurs modernes mettent en œuvre le multi-threading simultané (SMT) pour améliorer l'efficacité globale des processeurs superscalaires. SMT masque les opérations à longue latence en exécutant les instructions de plusieurs threads simultanément. Lorsque les threads exécutent le même programme (cas des applications SPMD), les mêmes instructions sont souvent exécutées avec des entrées différentes. Les architectures SMT traditionnelles exploitent le parallélisme entre threads, ainsi que du parallélisme de données explicite au travers d'unités d'exécution SIMD. L'exécution SIMD est efficace en énergie car le nombre total d'instructions nécessaire pour exécuter un programme est significativement réduit. Cette réduction du nombre d'instructions est fonction de la largeur des unités SIMD et de l'efficacité de la vectorisation. L'efficacité de la vectorisation est cependant souvent limitée en pratique. Dans cette thèse, nous proposons l'architecture de vectorisation dynamique inter-thread (DITVA) pour tirer parti du parallélisme de données implicite des applications SPMD en assemblant dynamiquement des instructions vectorielles à l'exécution. DITVA augmente un processeur à exécution dans l'ordre doté d'unités SIMD en lui ajoutant un mode d'exécution vectorisant entre threads. Lorsque les threads exécutent les mêmes instructions simultanément, DITVA vectorise dynamiquement ces instructions pour assembler des instructions SIMD entre threads. Les threads synchronisés sur le même chemin d'exécution partagent le même flot d'instructions. Pour conserver du parallélisme de threads, DITVA groupe de manière statique les threads en warps ordonnancés indépendamment. DITVA tire parti des unités SIMD existantes et maintient la compatibilité binaire avec les architectures CPU existantes.

Many modern microprocessors implement Simultaneous Multi-Threading (SMT) to improve the overall efficiency of superscalar CPU. SMT hides long latency operations by executing instructions from multiple threads simultaneously. SMT may execute threads of different processes, threads of the same processes or any combination of them. When the threads are from the same process, they often execute the same instructions with different data most of the time, especially in the case of Single-Program Multiple Data (SPMD) applications.Traditional SMT architecture exploit thread-level parallelism and with the use of SIMD execution units, they also support explicit data-level parallelism. SIMD execution is power efficient as the total number of instructions required to execute a complete program is significantly reduced. This instruction reduction is a factor of the width of SIMD execution units and the vectorization efficiency. Static vectorization efficiency depends on the programmer skill and the compiler. Often, the programs are not optimized for vectorization and hence it results in inefficient static vectorization by the compiler.In this thesis, we propose the Dynamic Inter-Thread vectorization Architecture (DITVA) to leverage the implicit…

Advisors/Committee Members: Seznec, André (thesis director), Collange, Sylvain (thesis director).

Subjects/Keywords: Multi-Threading simultané; SPMD; SIMD; Vectorisation dynamique; Architectures des microprocesseurs; Simultaneous Multi-Threading; SPMD; SIMD; Dynamic inter-Thread vectorization; Microprocessor architectures

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kalathingal, S. (2016). Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread. (Doctoral Dissertation). Rennes 1. Retrieved from http://www.theses.fr/2016REN1S133

Chicago Manual of Style (16^th Edition):

Kalathingal, Sajith. “Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread.” 2016. Doctoral Dissertation, Rennes 1. Accessed July 23, 2019. http://www.theses.fr/2016REN1S133.

MLA Handbook (7^th Edition):

Kalathingal, Sajith. “Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread.” 2016. Web. 23 Jul 2019.

Vancouver:

Kalathingal S. Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread. [Internet] [Doctoral dissertation]. Rennes 1; 2016. [cited 2019 Jul 23]. Available from: http://www.theses.fr/2016REN1S133.

Council of Science Editors:

Kalathingal S. Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread. [Doctoral Dissertation]. Rennes 1; 2016. Available from: http://www.theses.fr/2016REN1S133

Delft University of Technology

21. Shahbahrami, A. Avoiding conversion and rearrangement overhead in SIMD architecures.

Degree: 2008, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5

► In this dissertation, a novel SIMD extension called Modified MMX (MMMX) for multimedia computing is presented. Specifically, the MMX architecture is enhanced with the extended… (more)

▼ In this dissertation, a novel SIMD extension called Modified MMX (MMMX) for multimedia computing is presented. Specifically, the MMX architecture is enhanced with the extended subwords and the matrix register file techniques. The extended subwords technique uses SIMD registers that are wider than the packed format used to store the data. The extended subwords technique avoids data type conversion overhead and increases parallelism in SIMD architectures. This is because promoting the subwords of the source SIMD registers to larger subwords before they can be processed and demoting the results again before they can be written back to memory incurs conversion overhead. The matrix register file technique allows to load data that is stored consecutively in memory into a column of the register file, where a column corresponds to the corresponding subwords of different registers. In other words, this technique provides both row-wise as well as column-wise accesses to the media register file. It is a useful approach for matrix operations that are common in multimedia processing. In addition, in this work, new and general SIMD instructions addressing the multimedia application domain are investigated. It does not consider an ISA that is application specific. For example, special-purpose instructions are synthesized using a few general-purpose SIMD instructions. The performance of the MMMX architecture is compared to the performance of the MMX/SSE architecture for different multimedia applications and kernels using the sim-outorder simulator of the SimpleScalar toolset. Additionally, three issues related to the efficient implementation of the 2D Discrete Wavelet Transform (DWT)on general-purpose processors, in particular the Pentium 4, are discussed. These are 64K aliasing, cache conflict misses, and SIMD vectorization. 64K aliasing is a phenomenon that happens on the Pentium 4, which can degrade performance by an order of magnitude. It occurs if two or more data items whose addresses differ by a multiple of 64K need to be cached simultaneously. There are also many cache conflict misses in the implementation of vertical filtering of the DWT, if the filter length exceeds the number of cache ways. In this dissertation, techniques are proposed to avoid 64K aliasing and to mitigate cache conflict misses. Furthermore, the performance of the 2D DWT is improved by exploiting the data-level parallelism using the SIMD instructions supported by most general-purpose processors. Advisors/Committee Members: Goossens, K.G.W..

Subjects/Keywords: SIMD architectures; vectorization; SIMD programming; multimedia application; cache optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Shahbahrami, A. (2008). Avoiding conversion and rearrangement overhead in SIMD architecures. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5

Chicago Manual of Style (16^th Edition):

Shahbahrami, A. “Avoiding conversion and rearrangement overhead in SIMD architecures.” 2008. Doctoral Dissertation, Delft University of Technology. Accessed July 23, 2019. http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5.

MLA Handbook (7^th Edition):

Shahbahrami, A. “Avoiding conversion and rearrangement overhead in SIMD architecures.” 2008. Web. 23 Jul 2019.

Vancouver:

Shahbahrami A. Avoiding conversion and rearrangement overhead in SIMD architecures. [Internet] [Doctoral dissertation]. Delft University of Technology; 2008. [cited 2019 Jul 23]. Available from: http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5.

Council of Science Editors:

Shahbahrami A. Avoiding conversion and rearrangement overhead in SIMD architecures. [Doctoral Dissertation]. Delft University of Technology; 2008. Available from: http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5

KTH

22. Guo, Jiabing. Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor.

Degree: Radio Systems Laboratory (RS Lab), 2015, KTH

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474

►

With the wide spread of wireless technology, the time for 4G has arrived, and 5G will appear not so far in the future. However,… (more)

▼

With the wide spread of wireless technology, the time for 4G has arrived, and 5G will appear not so far in the future. However, no matter whether it is 4G or 5G, low latency is a mandatory requirement for baseband processing at base stations for modern cellular standards. In particular, in a future 5G wireless system, with massive MIMO and ultra-dense cells, the demand for low round trip latency between the mobile device and the base station requires a baseband processing delay of 1 ms. This is 10 percentage of today’s LTE-A round trip latency, while at the same time massive MIMO requires large-scale matrix computations. This is especially true for channel estimation and MIMO detection at the base station. Therefore, it is essential to ensure low latency for the user data traffic. In this master’s thesis, LTE/LTE-A uplink physical layer processing is examined, especially the process of channel estimation and MIMO detection. In order to analyze this processing we compare two conventional algorithms’ performance and complexity for channel estimation and MIMO detection. The key aspect which affects the algorithms’ speed is identified as the need for “massive complex matrix inversion”. A parallel coding scheme is proposed to implement a matrix inversion kernel algorithm on a single instruction multiple data stream (SIMD) vector processor. The major contribution of this thesis is implementation and evaluation of a parallel massive complex matrix inversion algorithm. Two aspects have been addressed: the selection of the algorithm to perform this matrix computation and the implementation of a highly parallel version of this algorithm.

Med den breda spridningen av trådlös teknik, har tiden för 4G kommit, och 5G kommer inom en överskådlig framtid. Men oavsett om det gäller 4G eller 5G, låg latens är ett obligatoriskt krav för basbandsbehandling vid basstationer för moderna mobila standarder. I synnerhet i ett framtida trådlöst 5G-system, med massiva MIMO och ultratäta celler, behövs en basbandsbehandling fördröjning på 1 ms för att klara efterfrågan på en låg rundresa latens mellan den mobila enheten och basstationen. Detta är 10 procent av dagens LTE-E rundresa latens, medan massiva MIMO samtidigt kräver storskaliga matrisberäkningar. Detta är särskilt viktigt för kanaluppskattning och MIMO-detektion vid basstationen. Därför är det viktigt att se till att det är låg latens för användardatatrafik. I detta examensarbete, skall LTE/LTE-A upplänk fysiska lagret bearbetning undersökas, och då särskilt processen för kanaluppskattning och MIMO-detektion. För att analysera denna processing jämför vi två konventionella algoritmers prestationer och komplexitet för kanaluppskattning och MIMO-detektion. Den viktigaste aspekten som påverkar algoritmernas hastighet identifieras som behovet av "massiva komplex matrisinversion". Ett parallellt kodningsschema föreslås för att implementera en "matrisinversion kernel-algoritmen" på singelinstruktion multidataström (SIMD) vektorprocessor. Det största…

Subjects/Keywords: channel estimation; MIMO detection; massive complex matrix inversion; SIMD; kanaluppskattning; MIMO-detektion; massiva komplex matrisinversion; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Guo, J. (2015). Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Guo, Jiabing. “Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor.” 2015. Thesis, KTH. Accessed July 23, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Guo, Jiabing. “Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor.” 2015. Web. 23 Jul 2019.

Vancouver:

Guo J. Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor. [Internet] [Thesis]. KTH; 2015. [cited 2019 Jul 23]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guo J. Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor. [Thesis]. KTH; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

23. Tomec, Martin. Optimalizace rozpoznávání řeči pro mobilní zařízení .

Degree: 2010, Brno University of Technology

URL: http://hdl.handle.net/11012/54275

► Práce se zabývá optimalizací algoritmů pro detekci klíčových slov na procesorové architektuře ARM Cortex-A8. Nejprve je popsána tato architektura a zejména její jednotka NEON pro… (more)

Subjects/Keywords: optimalizace; ARM; NEON; SIMD; detekce klíčových slov; rozpoznávání řeči; neuronová síť; optimization; ARM; NEON; SIMD; keyword spotting; speech recognition; neural net

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tomec, M. (2010). Optimalizace rozpoznávání řeči pro mobilní zařízení . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54275

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tomec, Martin. “Optimalizace rozpoznávání řeči pro mobilní zařízení .” 2010. Thesis, Brno University of Technology. Accessed July 23, 2019. http://hdl.handle.net/11012/54275.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tomec, Martin. “Optimalizace rozpoznávání řeči pro mobilní zařízení .” 2010. Web. 23 Jul 2019.

Vancouver:

Tomec M. Optimalizace rozpoznávání řeči pro mobilní zařízení . [Internet] [Thesis]. Brno University of Technology; 2010. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/11012/54275.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tomec M. Optimalizace rozpoznávání řeči pro mobilní zařízení . [Thesis]. Brno University of Technology; 2010. Available from: http://hdl.handle.net/11012/54275

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

24. Fuksa, Tomáš. Paralelizace výpočtů pro zpracování obrazu .

Degree: 2011, Brno University of Technology

URL: http://hdl.handle.net/11012/8264

► Tato práce se zabývá problematikou paralelních výpočtů na moderních procesorech, ať už se jedná o vícejádrová CPU nebo grafické karty. Cílem práce je seznámit se… (more)

Subjects/Keywords: Grafický procesor; GPGPU; Nvidia; CUDA; Paralelismus; OpenCL; Intel IPP; SIMD; Graphic processor; GPGPU; Nvidia; CUDA; Paralelism; OpenCL; Intel IPP; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Fuksa, T. (2011). Paralelizace výpočtů pro zpracování obrazu . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/8264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Fuksa, Tomáš. “Paralelizace výpočtů pro zpracování obrazu .” 2011. Thesis, Brno University of Technology. Accessed July 23, 2019. http://hdl.handle.net/11012/8264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Fuksa, Tomáš. “Paralelizace výpočtů pro zpracování obrazu .” 2011. Web. 23 Jul 2019.

Vancouver:

Fuksa T. Paralelizace výpočtů pro zpracování obrazu . [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/11012/8264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fuksa T. Paralelizace výpočtů pro zpracování obrazu . [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/8264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

25. Šlenker, Samuel. Výpočetní jednotky procesorů poslední generace a jejich využití .

Degree: 2015, Brno University of Technology

URL: http://hdl.handle.net/11012/41353

► Cieľom tejto práce bolo naštudovať a následne spracovať rozdiely medzi staršími inštrukčnými sadami a novšími inštrukčnými sadami, uviesť prínosy jednotlivých rozšírení, porovnať spôsoby výpočtov jednotlivých… (more)

Subjects/Keywords: SIMD; SSE; AVX; FMA; vektorové spracovanie dát; Intel; AMD; SIMD; SSE; AVX; FMA; vector data processing; Intel; AMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Šlenker, S. (2015). Výpočetní jednotky procesorů poslední generace a jejich využití . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/41353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Šlenker, Samuel. “Výpočetní jednotky procesorů poslední generace a jejich využití .” 2015. Thesis, Brno University of Technology. Accessed July 23, 2019. http://hdl.handle.net/11012/41353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Šlenker, Samuel. “Výpočetní jednotky procesorů poslední generace a jejich využití .” 2015. Web. 23 Jul 2019.

Vancouver:

Šlenker S. Výpočetní jednotky procesorů poslední generace a jejich využití . [Internet] [Thesis]. Brno University of Technology; 2015. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/11012/41353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šlenker S. Výpočetní jednotky procesorů poslední generace a jejich využití . [Thesis]. Brno University of Technology; 2015. Available from: http://hdl.handle.net/11012/41353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

26. Beneš, Vojtěch. Generování kódu optimalizovaných matematických operací .

Degree: 2010, Brno University of Technology

URL: http://hdl.handle.net/11012/55969

► Bakalářská práce se zabývá vytvořením jednoduchého programovacího jazyka pro práci s matematickými operacemi. Hlavním cílem práce je vytvořit kompilátor tohoto jazyka, který pro generování instrukcí cílového… (more)

Subjects/Keywords: Generování kódu; překladač; optimalizace; algoritmus kontextového generování; MMX; SSE; SIMD; Code generation; compiler; optimization; algorithm of context generation; MMX; SSE; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Beneš, V. (2010). Generování kódu optimalizovaných matematických operací . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Beneš, Vojtěch. “Generování kódu optimalizovaných matematických operací .” 2010. Thesis, Brno University of Technology. Accessed July 23, 2019. http://hdl.handle.net/11012/55969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Beneš, Vojtěch. “Generování kódu optimalizovaných matematických operací .” 2010. Web. 23 Jul 2019.

Vancouver:

Beneš V. Generování kódu optimalizovaných matematických operací . [Internet] [Thesis]. Brno University of Technology; 2010. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/11012/55969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Beneš V. Generování kódu optimalizovaných matematických operací . [Thesis]. Brno University of Technology; 2010. Available from: http://hdl.handle.net/11012/55969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

27. Tomečko, Lukáš. Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech .

Degree: 2016, Brno University of Technology

URL: http://hdl.handle.net/11012/62068

► Cieľom tejto práce je paralelizovať a vektorizovať simuláciu toku kvapalín. Dosiahne sa to pomocou knižnice OpenMP a prekladaču od Intelu. Implementované boli rôzne prístupy k… (more)

Subjects/Keywords: paralelizácia; vektorizácia; OpenMP; simd; Intel; SPH; simulácia; násobenie matíc; parallelization; vectorization; OpenMP; simd; Intel; SPH; simulation; matmul

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tomečko, L. (2016). Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/62068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tomečko, Lukáš. “Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech .” 2016. Thesis, Brno University of Technology. Accessed July 23, 2019. http://hdl.handle.net/11012/62068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tomečko, Lukáš. “Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech .” 2016. Web. 23 Jul 2019.

Vancouver:

Tomečko L. Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech . [Internet] [Thesis]. Brno University of Technology; 2016. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/11012/62068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tomečko L. Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech . [Thesis]. Brno University of Technology; 2016. Available from: http://hdl.handle.net/11012/62068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

28. Juránek, Roman. Akcelerace detekce objektů pomocí klasifikátorů .

Degree: 2012, Brno University of Technology

URL: http://hdl.handle.net/11012/63272

► Detekce objektů v počítačovém vidění je složítá úloha. Velmi populární a rozšířená metoda pro detekci je využití statistických klasifikátorů a skenovacích oken. Pro učení kalsifikátorů… (more)

▼ Detekce objektů v počítačovém vidění je složítá úloha. Velmi populární a rozšířená metoda pro detekci je využití statistických klasifikátorů a skenovacích oken. Pro učení kalsifikátorů se často používá algoritmus AdaBoost (nebo jeho modifikace), protože dosahuje vysoké úspěšnosti detekce, nízkého počtu chybných detekcí a je vhodný pro detekci v reálném čase. Implementaci detekce objektů je možné provést různými způsoby a lze využít vlastnosti konkrétní architektury, pro urychlení detekce. Pro akceleraci je možné využít grafické procesory, vícejádrové architektury, SIMD instrukce, nebo programovatelný hardware. Tato práce představuje metodu optimalizace, která vylepšuje výkon detekce objektů s ohledem na cenovou funkci zadanou uživatelem. Metoda rozděluje předem natrénovaný klasifikátor do několika různých implementací, tak aby celková cena klasifikace byla minimalizována. Metoda je verifikována na základním experimentu, kdy je klasifikátor rozdělen do předzpracovací jednotku v FPGA a do jednotky ve standardním PC.; Detection of objects in computer vision is a complex task. One of most popular and well explored approaches is the use of statistical classifiers and scanning windows. In this approach, classifiers learned by AdaBoost algorithm (or some modification) are often used as they achieve low error rates, high detection rates and they are suitable for detection in real-time applications. Object detection run-time which uses such classifiers can be implemented by various methods and properties of underlying architecture can be used for speed-up of the detection. For the purpose of acceleration, graphics hardware, multi-core architectures, SIMD or other means can be used. The detection is often implemented on programmable hardware. The contribution of this thesis is to introduce an optimization technique which enhances object detection performance with respect to an user defined cost function. The optimization balances computations of previously learned classifiers between two or more run-time implementations in order to minimize the cost function. The optimization method is verified on a basic example – division of a classifier to a pre-processing unit implemented in FPGA, and a post-processing unit in standard PC. Advisors/Committee Members: Zemčík, Pavel (advisor).

Subjects/Keywords: Detekce objektů; AdaBoost; WaldBoost; Akcelerace; SIMD; Minimalizace ceny; Object Detection; AdaBoost; WaldBoost; Acceleration; SIMD; Cost Minimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Juránek, R. (2012). Akcelerace detekce objektů pomocí klasifikátorů . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/63272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Juránek, Roman. “Akcelerace detekce objektů pomocí klasifikátorů .” 2012. Thesis, Brno University of Technology. Accessed July 23, 2019. http://hdl.handle.net/11012/63272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Juránek, Roman. “Akcelerace detekce objektů pomocí klasifikátorů .” 2012. Web. 23 Jul 2019.

Vancouver:

Juránek R. Akcelerace detekce objektů pomocí klasifikátorů . [Internet] [Thesis]. Brno University of Technology; 2012. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/11012/63272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Juránek R. Akcelerace detekce objektů pomocí klasifikátorů . [Thesis]. Brno University of Technology; 2012. Available from: http://hdl.handle.net/11012/63272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Westermann, Peter. Exploration of the scalability of SIMD processing for software defined radio.

Degree: 2011, Technische Universität Dortmund

URL: http://hdl.handle.net/2003/27666

► The idea of software defined radio (SDR) describes a signal processing system for wireless communications that allows performing major parts of the physical layer processing… (more)

▼ The idea of software defined radio (SDR) describes a signal processing system for wireless communications that allows performing major parts of the physical layer processing in software. SDR systems are more flexible and have lower development costs than traditional systems based on application-specific integrated circuits (ASICs). Yet, SDR requires programmable processor architectures that can meet the throughput and energy efficiency requirements of current third generation (3G) and future fourth generation (4G) wireless standards for mobile devices. Single instruction, multiple data (SIMD) processors operate on long data vectors in parallel data lanes and can achieve a good ratio of computing power to energy consumption. Hence, SIMD processors could be the basis of future SDR systems. Yet, SIMD processors only achieve a high efficiency if all parallel data lanes can be utilized. This thesis investigates the scalability of SIMD processing for algorithms required in 4G wireless systems; i. e. the scaling of performance and energy consumption with increasing SIMD vector lengths is explored. The basis of the exploration is a scalable SIMD processor architecture, which also supports long instruction word (LIW) execution and can be configured with four different permutation networks for vector element permutations. Radix-2 and mixed-radix fast Fourier transform (FFT) algorithms, sphere decoding for multiple input, multiple output (MIMO) systems, and the decoding of quasi-cyclic lowdensity parity check (LDPC) codes have been examined, as these are key algorithms for 4G wireless systems. The results show that the performance of all algorithms scales with the SIMD vector length, yet there are different constraints on the ratios between algorithm and architecture parameters. The radix-2 FFT algorithm allows close to linear speedups if the FFT size is at least twice the SIMD vector length, the mixed-radix FFT algorithm requires the FFT size to be a multiple of the squared SIMD width. The performance of the implemented sphere decoding algorithm scales linearly with the SIMD vector length. The scalability of LDPC decoding is determined by the expansion factor of the quasicyclic code. Wider SIMD processors offer better performance and also require less energy than processors with a shorter vector length for all considered algorithms. The results for different permutations networks show that a simple permutation network is sufficient for most applications. Advisors/Committee Members: Schröder, Hartmut.

Subjects/Keywords: FFT; LDPC; MIMO; SIMD; Software defined radio (SDR); Sphere decoding; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Westermann, P. (2011). Exploration of the scalability of SIMD processing for software defined radio. (Thesis). Technische Universität Dortmund. Retrieved from http://hdl.handle.net/2003/27666

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Westermann, Peter. “Exploration of the scalability of SIMD processing for software defined radio.” 2011. Thesis, Technische Universität Dortmund. Accessed July 23, 2019. http://hdl.handle.net/2003/27666.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Westermann, Peter. “Exploration of the scalability of SIMD processing for software defined radio.” 2011. Web. 23 Jul 2019.

Vancouver:

Westermann P. Exploration of the scalability of SIMD processing for software defined radio. [Internet] [Thesis]. Technische Universität Dortmund; 2011. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/2003/27666.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Westermann P. Exploration of the scalability of SIMD processing for software defined radio. [Thesis]. Technische Universität Dortmund; 2011. Available from: http://hdl.handle.net/2003/27666

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Linköping University

30. Hussain, Sajid. Verification and FPGA implementation of a floating point SIMD processor for MIMO processing.

Degree: Computer Engineering, 2010, Linköping University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-64077

►

The rapidly increasing capabilities of digital electronics have increased the demand of Software Defined Radio (SDR), which were not possible in the special purpose… (more)

▼

The rapidly increasing capabilities of digital electronics have increased the demand of Software Defined Radio (SDR), which were not possible in the special purpose hardware. These enhanced capabilities come at the cost of time due to complex operations involved in multi-antenna wireless communications, one of those operations is complex matrix inversion. This thesis presents the verification and FPGA implementation of a SIMD processor, which was developed at Computer Engineering division of Linköping university, Sweden. This SIMD processor was designed specifically for performing complex matrix inversion in an efficient way, but it can also be reused for other operations. The processor is fully verified using all the possible combinations of instructions. An optimized firmware for this processor is implemented for efficiently inverting 4×4 matrices. Due to large number of subtractions involved in direct analytical approach, it losses stability for 4×4 matrices. Instead of this, a blockwise subdivision is used, in which 4×4 matrix is subdivided into four 2×2 matrices. Based on these 2×2 matrices, the inverse of 4×4 matrix is computed using the direct analytical approach and some other computations. Finally, the SIMD processor is integrated with Senior processor (a controlprocessor) and synthesized on Xilinx, Virtex-4 FPGA. After this, the performance of the proposed architecture is evaluated. A firmware is implemented for the Senior which uploads and downloads data/program into the SIMD unit using both I/O and DMA.

Den snabbt ökande prestandan hos digital elektronik har ökat behovet av Software Defined Radio (SDR), vilket inte var möjligt med tidigare hårdvara. Denna ökade förmåga kommer till priset av tidsåtgång, till följd av komplexa procedureri samband med trådlös kommunikation med flera antenner, en av dessa procedurer är komplex matrisinvertering. Denna avhandling presenterar verifiering och FPGA implementering hos en SIMD processor, vilken har blivit utvecklad vid institutionen för datorteknik, Linköpings universitet, Sverige. Denna SIMD processor blev specifikt designad för att genomföra komplex matrisinvertering på ett effektivt sätt, men kan också användas för andra tillämpningar. Processorn har testats och verifierats för alla möjliga kombinationer av instruktioner. En optimerad firmware för denna processor är implementerad för att effektivt invertera 4×4 matriser. På grund av att ett stort antal subtraktioner är inblandade i ett direkt analytiskt angreppssätt, så förlorar den stabilitet för 4×4 matriser. Istället används en stegvis indelning i underavdelningar, där 4×4 matrisen delasin i fyra 2×2 matriser. Baserat på dessa 2×2 matriser beräknas inversen av 4×4 matrisen med hjälp av ett direkt analytiskt angreppssätt samt andra beräkningar. Slutligen, SIMD processorn är integrerad i en huvudprocessor och körs påXilinx, Virtex-4 FPGA. Efter detta utvärderas prestandan hos den föreslagna arkitekturen. Firmware implementeras hos huvudprocessorn som laddar…

Subjects/Keywords: SDR; SIMD; Xilinx; FPGA; DMA; Computer Engineering; Datorteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hussain, S. (2010). Verification and FPGA implementation of a floating point SIMD processor for MIMO processing. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-64077

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hussain, Sajid. “Verification and FPGA implementation of a floating point SIMD processor for MIMO processing.” 2010. Thesis, Linköping University. Accessed July 23, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-64077.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hussain, Sajid. “Verification and FPGA implementation of a floating point SIMD processor for MIMO processing.” 2010. Web. 23 Jul 2019.

Vancouver:

Hussain S. Verification and FPGA implementation of a floating point SIMD processor for MIMO processing. [Internet] [Thesis]. Linköping University; 2010. [cited 2019 Jul 23]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-64077.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hussain S. Verification and FPGA implementation of a floating point SIMD processor for MIMO processing. [Thesis]. Linköping University; 2010. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-64077

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations