subject:(SIMD)

Rochester Institute of Technology

1. Mazza, James P. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.

Degree: MS, Electrical Engineering, 2014, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/8604

► Data parallel image processing algorithms have numerous uses in many real time applications. Depending on the complexity of the computations involved, these algorithms may… (more)

Subjects/Keywords: FPGA; Hardward; SIMD

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APA (6^th Edition):

Mazza, J. P. (2014). Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8604

Chicago Manual of Style (16^th Edition):

Mazza, James P. “Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.” 2014. Masters Thesis, Rochester Institute of Technology. Accessed March 04, 2021. https://scholarworks.rit.edu/theses/8604.

MLA Handbook (7^th Edition):

Mazza, James P. “Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.” 2014. Web. 04 Mar 2021.

Vancouver:

Mazza JP. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. [Internet] [Masters thesis]. Rochester Institute of Technology; 2014. [cited 2021 Mar 04]. Available from: https://scholarworks.rit.edu/theses/8604.

Council of Science Editors:

Mazza JP. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. [Masters Thesis]. Rochester Institute of Technology; 2014. Available from: https://scholarworks.rit.edu/theses/8604

NSYSU

2. Huang, Kuan-min. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

► 3D graphics pipeline can be divided into two subsystems: geometry subsystem and rendering subsystem. Hardware implementation of the transformation and lighting in the geometric subsystem… (more)

Subjects/Keywords: Vertex Shader; SIMD; Programmable

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APA (6^th Edition):

Huang, K. (2009). Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Web. 04 Mar 2021.

Vancouver:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

3. Pan, Po-Hsun. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.

Degree: Master, Electrical Engineering, 2011, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

► In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. To identify human behavior which achieve… (more)

▼ In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. To identify human behavior which achieve the surveillance has great help by video automation in aspect of home caring, personal property and homeland security. To achieve action recognition, there are many factors to be considered, primarily the accuracy and real-time. If we can parallelize the action recognition algorithm, it will be a greatly improvement to the real-time processing capability of the algorithm. To achieve real-time demand, we study how to implement action recognition algorithm parallelization in the CELL B.E. platform. The action recognition algorithm with our design is faster than the original algorithm; it has 231 times speed up. We found that in the action recognition algorithm, there are many repeated operation between blocks, it can be parallelize by using single-instruction multiple-data architecture. In the action recognition algorithms, there are four major algorithms, DMASKS, HMHHb, MGD, SVM. The SIMD instructions in CELL B.E. platform can compute 128 bits data at once. While doing DMASKS, SIMD parallelism can reach 16 times, HMHHb parallelism up to 128 times, MGD parallelism up to 8 times, and SVM can reach 4 times. Based on CELL B.E. acceleration mechanism, we achieve high-performance computing models with multi-threading and multiple streaming. Our study showed that the action recognition algorithm is very suitable for multi-core system with parallel processing SIMD architecture. The parallelization for action recognition algorithm will have more immediate response in identifying human action. With the advantages of real-time, it can be expected to include more complex algorithms for the accuracy of algorithm in the future, to achieve both immediacy and accuracy. Advisors/Committee Members: Wann-Yun Shieh (chair), Chung-Ping Chung (chair), Jih-Ching Chiu (committee member), Chia-Hung Yeh (chair).

Subjects/Keywords: action recognition; SIMD; CELL; parallelize

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APA (6^th Edition):

Pan, P. (2011). The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pan, Po-Hsun. “The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.” 2011. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pan, Po-Hsun. “The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.” 2011. Web. 04 Mar 2021.

Vancouver:

Pan P. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pan P. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. 松本, 剛英. 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

URL: http://hdl.handle.net/10061/1770

Subjects/Keywords: プロセッサ; SIMD

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APA (6^th Edition):

松本, �. (n.d.). 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1770

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

松本, 剛英. “組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed March 04, 2021. http://hdl.handle.net/10061/1770.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

松本, 剛英. “組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ.” Web. 04 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

松本 �. 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10061/1770.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

松本 �. 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケマルチスレッドプロセッサノセッケイトヒョウカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1770

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

NSYSU

5. Chang, Hsin-Tzu. Study on LTE MIMO System in SIMD Architecture.

Degree: Master, Communications Engineering, 2018, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738

► In order to increase the spectral efficiency under limited bandwidth, the main technology Long Term Evolution (LTE) of the Fourth Generation of Mobile Phone Mobile… (more)

Subjects/Keywords: MKL; MIMO; SIMD; OFDM; LTE

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APA (6^th Edition):

Chang, H. (2018). Study on LTE MIMO System in SIMD Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chang, Hsin-Tzu. “Study on LTE MIMO System in SIMD Architecture.” 2018. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chang, Hsin-Tzu. “Study on LTE MIMO System in SIMD Architecture.” 2018. Web. 04 Mar 2021.

Vancouver:

Chang H. Study on LTE MIMO System in SIMD Architecture. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang H. Study on LTE MIMO System in SIMD Architecture. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Linköping University

6. Chan, Chun-Jung. Investigation of NoGap : SIMD Datapath Implementation.

Degree: Electrical Engineering, 2011, Linköping University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131

► Nowadays, many ASIP systems with high computational capabilities are designed in order to fulfill the increasing demands of technical applications. However, the design of… (more)

Subjects/Keywords: ASIP; NoGap; ePUMA; Sleipnir; SIMD

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APA (6^th Edition):

Chan, C. (2011). Investigation of NoGap : SIMD Datapath Implementation. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chan, Chun-Jung. “Investigation of NoGap : SIMD Datapath Implementation.” 2011. Thesis, Linköping University. Accessed March 04, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chan, Chun-Jung. “Investigation of NoGap : SIMD Datapath Implementation.” 2011. Web. 04 Mar 2021.

Vancouver:

Chan C. Investigation of NoGap : SIMD Datapath Implementation. [Internet] [Thesis]. Linköping University; 2011. [cited 2021 Mar 04]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chan C. Investigation of NoGap : SIMD Datapath Implementation. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

7. Benna, Filip. Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library.

Degree: 2018, Brno University of Technology

URL: http://hdl.handle.net/11012/52377

► This bachelor's thesis deals with compilation of OpenCV library with Codix RISC processor core as the target machine and following optimization of chosen applications based… (more)

Subjects/Keywords: OpenCV; Codix RISC; SIMD; optimalizace; OpenCV; Codix RISC; SIMD; optimization

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APA (6^th Edition):

Benna, F. (2018). Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/52377

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Benna, Filip. “Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library.” 2018. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/52377.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Benna, Filip. “Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library.” 2018. Web. 04 Mar 2021.

Vancouver:

Benna F. Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/52377.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Benna F. Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/52377

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

8. Šnobl, Pavel. Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/61853

► This master's thesis deals with the support for compilation and execution of programs written using OpenCL framework on embedded systems. OpenCL is a system for… (more)

Subjects/Keywords: OpenCL; LLVM; Codasip; SIMD; VLIW; OpenCL; LLVM; Codasip; SIMD; VLIW

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APA (6^th Edition):

Šnobl, P. (2019). Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/61853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems.” 2019. Web. 04 Mar 2021.

Vancouver:

Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/61853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/61853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

9. Šnobl, Pavel. Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/56572

► This bachelor thesis deals with support of automatic vectorization of code in the LLVM compilation framework and with extension of Codix processor model of SIMD… (more)

Subjects/Keywords: SIMD; LLVM; Codix; CodAL; autovektorizace; SIMD; LLVM; Codix; CodAL; Auto-Vectorization

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APA (6^th Edition):

Šnobl, P. (2019). Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/56572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Šnobl, Pavel. “Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/56572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Šnobl, Pavel. “Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler.” 2019. Web. 04 Mar 2021.

Vancouver:

Šnobl P. Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/56572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šnobl P. Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/56572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

10. Chen, Li-Yao. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

► OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations… (more)

Subjects/Keywords: Integration; SOC; Programmable; SIMD; Vertex Shader

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APA (6^th Edition):

Chen, L. (2010). Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Web. 04 Mar 2021.

Vancouver:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

11. Li, Shang-Yu. Design and Implementation of a Vision Processor Based on the OpenVX Specification.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

► Embedded computer vision applications emphasizes fast and real-time processing speed with low power consumption. To face these challenge, we need more suitable hardware accelerator for… (more)

Subjects/Keywords: Computer vision applications; OpenVX; SIMD; Vision Processor

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APA (6^th Edition):

Li, S. (2016). Design and Implementation of a Vision Processor Based on the OpenVX Specification. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Web. 04 Mar 2021.

Vancouver:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

12. Hsieh, Cheng-han. Study on Real-Time Software Architecture for LTE MIMO System.

Degree: Master, Communications Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659

► Long-term-evolution (LTE) and LTE-Advance are undoubtedly the most successful mobile broadband technologies in the fourth generation (4G) wireless system. LTE employs orthogonal frequency division multiplexing… (more)

Subjects/Keywords: MKL; parallel processing; MIMO; OFDM; LTE; SIMD

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APA (6^th Edition):

Hsieh, C. (2017). Study on Real-Time Software Architecture for LTE MIMO System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hsieh, Cheng-han. “Study on Real-Time Software Architecture for LTE MIMO System.” 2017. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hsieh, Cheng-han. “Study on Real-Time Software Architecture for LTE MIMO System.” 2017. Web. 04 Mar 2021.

Vancouver:

Hsieh C. Study on Real-Time Software Architecture for LTE MIMO System. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh C. Study on Real-Time Software Architecture for LTE MIMO System. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Manchester

13. Garcia Ordaz, Jose Raul. Dynamic CPU ISA Customizations through FPGA Interlays.

Degree: 2018, University of Manchester

URL: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:316951

► General purpose processors (GPPs) are designed to provide a substantial level of performance for a wide range of applications. However, GPPs, in particular those aimed… (more)

▼ General purpose processors (GPPs) are designed to provide a substantial level of performance for a wide range of applications. However, GPPs, in particular those aimed to power mobile systems, face a design dilemma in which, on the one hand, they are required to deliver high performance for some applications and, on the other hand, they are required to operate very efficiently to keep energy consumption at a minimum because they are often bounded by strict energy budgets. A common approach to provide GPPs with enhanced performance is to integrate hardened instruction set extensions (ISE) as they provide application domain-specific functionality to accelerate, for example, media applications. While the hardened ISE approach can boost CPU performance, it also introduces an overhead in terms of area (and consequently, in terms of associated energy consumption). In consequence, adding more and more hardened ISEs is not well suited for battery-operated processors. Therefore, alternative approaches to tackle the previously described design dilemma for GPPs are required. To address that design dilemma, this thesis proposes embedding a small mixed-grained (FPGA) reconfigurable fabric into an otherwise hardened CPU in order to allow for a dynamic customization of a CPU ISA. In this thesis, the term â€œInterlayâ€ is used to refer to this reconfigurable fabric as it logically sits between the software layer and the physical substrate of a CPU. This thesis demonstrates that an Interlay can make it possible to customize the ISA of a CPU at run-time by integrating application-specific instructions. To evaluate the feasibility of this approach, this thesis presents a case study that demonstrates that the Interlay approach is realistic and that it can provide hardened CPUs with a level of flexibility and efficiency that is not found in conventional processors. Moreover, this thesis discusses architectural and management details for the Interlay. This includes a study of the Interlay in the context of multi-processor systems. Furthermore, this thesis demonstrates different paths to generate custom instructions targeting the Interlay and presents encouraging results that show the potential performance boosts that this approach can deliver. Ultimately, with the methods, techniques, and results presented, this thesis aims to stimulate research that eventually fully exploits the potential behind the herein proposed Interlay approach. Advisors/Committee Members: GARSIDE, JAMES J, Koch, Dirk, Garside, James.

Subjects/Keywords: FPGA; Partial Reconfigution; SIMD; Soft-processor

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APA (6^th Edition):

Garcia Ordaz, J. R. (2018). Dynamic CPU ISA Customizations through FPGA Interlays. (Doctoral Dissertation). University of Manchester. Retrieved from http://www.manchester.ac.uk/escholar/uk-ac-man-scw:316951

Chicago Manual of Style (16^th Edition):

Garcia Ordaz, Jose Raul. “Dynamic CPU ISA Customizations through FPGA Interlays.” 2018. Doctoral Dissertation, University of Manchester. Accessed March 04, 2021. http://www.manchester.ac.uk/escholar/uk-ac-man-scw:316951.

MLA Handbook (7^th Edition):

Garcia Ordaz, Jose Raul. “Dynamic CPU ISA Customizations through FPGA Interlays.” 2018. Web. 04 Mar 2021.

Vancouver:

Garcia Ordaz JR. Dynamic CPU ISA Customizations through FPGA Interlays. [Internet] [Doctoral dissertation]. University of Manchester; 2018. [cited 2021 Mar 04]. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:316951.

Council of Science Editors:

Garcia Ordaz JR. Dynamic CPU ISA Customizations through FPGA Interlays. [Doctoral Dissertation]. University of Manchester; 2018. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:316951

Northeastern University

14. Yilmazer, Ayse. Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS.

Degree: PhD, Department of Electrical and Computer Engineering, 2013, Northeastern University

URL: http://hdl.handle.net/2047/d20004880

► GPUs dedicate a majority of their transistor budgets to compute units rather than control logic. As a result, they can achieve excellent data-parallel power/performance. Given… (more)

▼ GPUs dedicate a majority of their transistor budgets to compute units rather than control logic. As a result, they can achieve excellent data-parallel power/performance. Given the continual demands for performance and power eefficiency, GPUs have become today's compute accelerators for many application domains.; The general purpose community has been focusing on developing strategies to move a broader class of applications to these powerful devices. The underlying GPU architecture has been adapted to run a limited class of general purpose computations present across a range of applications. Many applications have already been ported to GPU platforms to take advantage of the potential data-parallel performance that GPUs afford. But there still remain barriers to migrating a broader class of applications onto GPUs.; Being originally designed to run 3-D graphics, GPUs are highly optimized for graphics workloads. Graphics workloads possess a high degree of uniformity in their execution. Therefore, GPU architectures are optimized for efficient uniform execution. GPUs achieve high performance with data-parallel applications possessing regular control flow (i.e., predictable loops) and data access patterns that can effectively exploit high o-chip memory bandwidth. However, many general-purpose real world applications differ from graphics workloads-they come with large input sets exhibiting irregular access and synchronization patterns, and they possess varying computational granularity and irregular control flow. The current requirements for uniformity and predictability present barriers to moving a broader range of applications to GPUs. We believe if GPUs are going to become a mainstream computing device that it is necessary to relax some of these constraints. Only then can a wider variety of applications exploit the computational power of GPUs.; One critical barrier present in non-uniform data-parallel applications is the need to synchronize between threads. Fine-grained synchronization is needed to support shared data access, especially when faced with irregular access and communication patterns. This dissertation presents a new approach to enhance the efficiency and scalability of GPU synchronization. The proposed scheme can enable applications that work on shared data to effectively communicate at finer levels of granularity.; To achieve this ambitious goal, we propose a new synchronization approach called Hierarchical Queuing Locks (HQL). HQL is a novel hardware-based synchronization mechanism which provides efficient use of resources through execution blocking and hierarchical queuing. To provide a queue-based locking mechanism, HQL extends current GPU L1 and L2 cache management protocols by adding a synchronization protocol. Integration of HQL's synchronization protocol simplies the synchronization, but adds a level of complexity to the cache management protocol. Given this added complexity to the cache management scheme, as part of this dissertation we provide a formal verication of the proposed HQL synchronization…

Subjects/Keywords: GPU; SIMD Execution; Synchronization; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yilmazer, A. (2013). Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20004880

Chicago Manual of Style (16^th Edition):

Yilmazer, Ayse. “Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS.” 2013. Doctoral Dissertation, Northeastern University. Accessed March 04, 2021. http://hdl.handle.net/2047/d20004880.

MLA Handbook (7^th Edition):

Yilmazer, Ayse. “Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS.” 2013. Web. 04 Mar 2021.

Vancouver:

Yilmazer A. Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS. [Internet] [Doctoral dissertation]. Northeastern University; 2013. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2047/d20004880.

Council of Science Editors:

Yilmazer A. Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS. [Doctoral Dissertation]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20004880

15. Pang, Yihan. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.

Degree: MS, Computer Engineering, 2019, Virginia Tech

URL: http://hdl.handle.net/10919/95299

► The author of this thesis has a family full of non-engineers. To persuade family members that the work of this thesis is meaningful, aka the… (more)

▼ The author of this thesis has a family full of non-engineers. To persuade family members that the work of this thesis is meaningful, aka the author is not procrastinating in school, the author decided to draw an analogy between processors and cars. Suppose in an alternative universe, cars (systems) can be powered by engines (processors) that uses two different fuel-sources (ISAs): gasoline or electric (single-ISA) processors but not both (heterogeneous-ISA). Car manufacturers (chip designers) can build engines with different design choices (processors with varying design options): engines combined with turbochargers for gasoline-powered cars, high-performance batteries combined with energy-efficient batteries for electric-powered cars (added extended instruction sets, CPU designs that target vastly different use cases, etc.). However, each design choice is limited to improving performance for a specific type of fuel-source based engine. For example, having battery alternatives has no performance impact on gasoline-powered engines. As time passes by, car manufacturers have exhausted options to make a drastic improvement to their existing engine designs (limited performance gains in recent chips). To tackle this problem, in this thesis, the author first examined the usage of cars: driving on the road (running applications). The author's study found that no single engine is suitable for all routes (no single processor is good for all workloads), and cars powered by different fuel-source based engines showed a significant diversity in performance (application performance varies drastically between systems with processors built on different ISAs). Gasoline-powered cars perform well on high-speed roads, whereas electric-powered cars perform well on low-speed roads. Unfortunately, in real life, a person's commute (a workload of applications) consists of a mixture of high-speed roads and low-speed roads, and one cannot know the exact percentage of each kind of path they travel (exact application composition in a workload) beforehand. Therefore it is challenging for a person to make the correct car selection for the incoming commute (choose the right system for a workload). This thesis tries to solve this commuting problem by building a car that has multiple engines fitted to suit different road needs (systems with processors that have vastly different use cases). This thesis looks at a particular dimension of combining various fuel-powered engines in the same car (a system with heterogeneous-ISA processors). The author believes that adding diversity in fuel-powered engine selections provide an exciting dimension in car design choices (adding ISA-heterogeneity in processors provide a unique dimension in system design). Thus, this thesis focuses on estimating a theoretical multi fuel-powered car's performance by combining two different fuel-powered cars into a single mega-car using some framework (Popcorn Linux). This framework allows this mega-car to be driven by a combined fuel source with fuel intake freely transfer… Advisors/Committee Members: Ravindran, Binoy (committeechair), Min, Chang Woo (committee member), Patterson, Cameron D. (committee member).

Subjects/Keywords: System Software; Heterogeneous Architectures; SIMD; Scheduling; ISA

10 more images…

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Pang, Y. (2019). Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/95299

Chicago Manual of Style (16^th Edition):

Pang, Yihan. “Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.” 2019. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/95299.

MLA Handbook (7^th Edition):

Pang, Yihan. “Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.” 2019. Web. 04 Mar 2021.

Vancouver:

Pang Y. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/95299.

Council of Science Editors:

Pang Y. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/95299

University of Manchester

16. Garcia Ordaz, Jose. Dynamic CPU ISA customizations through FPGA interlays.

Degree: PhD, 2018, University of Manchester

URL: https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa-customizations-through-fpga-interlays(fb111711-1be8-4b04-8b46-aeb5dbd520c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799290

► General purpose processors (GPPs) are designed to provide a substantial level of performance for a wide range of applications. However, GPPs, in particular those aimed… (more)

▼ General purpose processors (GPPs) are designed to provide a substantial level of performance for a wide range of applications. However, GPPs, in particular those aimed to power mobile systems, face a design dilemma in which, on the one hand, they are required to deliver high performance for some applications and, on the other hand, they are required to operate very efficiently to keep energy consumption at a minimum because they are often bounded by strict energy budgets. A common approach to provide GPPs with enhanced performance is to integrate hardened instruction set extensions (ISE) as they provide application domain-specific functionality to accelerate, for example, media applications. While the hardened ISE approach can boost CPU performance, it also introduces an overhead in terms of area (and consequently, in terms of associated energy consumption). In consequence, adding more and more hardened ISEs is not well suited for battery-operated processors. Therefore, alternative approaches to tackle the previously described design dilemma for GPPs are required. To address that design dilemma, this thesis proposes embedding a small mixed-grained (FPGA) reconfigurable fabric into an otherwise hardened CPU in order to allow for a dynamic customization of a CPU ISA. In this thesis, the term âInterlayâ is used to refer to this reconfigurable fabric as it logically sits between the software layer and the physical substrate of a CPU. This thesis demonstrates that an Interlay can make it possible to customize the ISA of a CPU at run-time by integrating application-specific instructions. To evaluate the feasibility of this approach, this thesis presents a case study that demonstrates that the Interlay approach is realistic and that it can provide hardened CPUs with a level of flexibility and efficiency that is not found in conventional processors. Moreover, this thesis discusses architectural and management details for the Interlay. This includes a study of the Interlay in the context of multi-processor systems. Furthermore, this thesis demonstrates different paths to generate custom instructions targeting the Interlay and presents encouraging results that show the potential performance boosts that this approach can deliver. Ultimately, with the methods, techniques, and results presented, this thesis aims to stimulate research that eventually fully exploits the potential behind the herein proposed Interlay approach.

Subjects/Keywords: FPGA; Partial Reconfigution; SIMD; Soft-processor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Garcia Ordaz, J. (2018). Dynamic CPU ISA customizations through FPGA interlays. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa-customizations-through-fpga-interlays(fb111711-1be8-4b04-8b46-aeb5dbd520c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799290

Chicago Manual of Style (16^th Edition):

Garcia Ordaz, Jose. “Dynamic CPU ISA customizations through FPGA interlays.” 2018. Doctoral Dissertation, University of Manchester. Accessed March 04, 2021. https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa-customizations-through-fpga-interlays(fb111711-1be8-4b04-8b46-aeb5dbd520c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799290.

MLA Handbook (7^th Edition):

Garcia Ordaz, Jose. “Dynamic CPU ISA customizations through FPGA interlays.” 2018. Web. 04 Mar 2021.

Vancouver:

Garcia Ordaz J. Dynamic CPU ISA customizations through FPGA interlays. [Internet] [Doctoral dissertation]. University of Manchester; 2018. [cited 2021 Mar 04]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa-customizations-through-fpga-interlays(fb111711-1be8-4b04-8b46-aeb5dbd520c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799290.

Council of Science Editors:

Garcia Ordaz J. Dynamic CPU ISA customizations through FPGA interlays. [Doctoral Dissertation]. University of Manchester; 2018. Available from: https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa-customizations-through-fpga-interlays(fb111711-1be8-4b04-8b46-aeb5dbd520c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799290

University of New South Wales

17. Zhou, Hao. Compiler techniques for improving SIMD parallelism.

Degree: Computer Science & Engineering, 2016, University of New South Wales

URL: http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true

► Modern CPUs are equipped with Single Instruction Multiple Data (SIMD) engines operating on short vectors, in order to meet the growing demands of accelerating multimedia… (more)

▼ Modern CPUs are equipped with Single Instruction Multiple Data (SIMD) engines operating on short vectors, in order to meet the growing demands of accelerating multimedia and scientific applications. Automatic simdization performed by the compiler, as a convenient way of utilizing the SIMD ISA extensions, however, faces challenges of translating SIMD resource into actual performance. Despite the fact that discovering SIMD parallelism is sometimes difficult due to the imprecise dependence analysis, for some SIMD parallelism that can be identified, current vectorization techniques are ineffective. In this thesis, we examine mixed SIMD parallelism and partial SIMD parallelism, which are both poorly exploited by the existing approaches. Two new vectorization techniques, i.e., Loop-Mix and Paver, are proposed, to tackle themrespectively. Existing loop vectorization techniques exploit either intra- or inter-iteration SIMD parallelism alone in a code region, if one part of the region vectorized for one type of parallelism has data dependences (called mixed-parallelism-inhibitingdependences) on the other part of the region vectorized for the other type of parallelism. We consider a class of loops that exhibit both types of parallelism in its code regions that contain mixed-parallelism-inhibiting data dependences (i.e.,mixed SIMD parallelism). We present a new compiler approach Loop-Mix for exploiting such mixed SIMD parallelism effectively by reducing the data reorganization overhead incurred when one type of parallelism is switched to the other. Additionally, existing loop vectorization techniques are ineffective for loops that exhibit little loop-level parallelism but some limited superword-level parallelism (SLP), where the SIMD parallelism is insufficient to fulfil the SIMD datapath (i.e., partial SIMD parallelism). We show that effectively vectorizing such loops requires partial vector operations to be executed correctly and efficiently. We present a simple yet effective SLP compiler technique, called Paver (PArtial VEctorizeR), formulated as a generalization of the traditional SLP algorithm, to optimize such partially vectorizable loops. The key idea is to maximize SIMD utilization by widening vector instructions used while minimizing the overheads caused by memory access, packing/unpacking, and/or masking operations, without introducing new memory errors or new numeric exceptions. Both Loop-Mix and Paver are simple and have been implemented in LLVM. We evaluate them with several real-world programs containing mixed or partial SIMD parallelism and demonstrate their performance advantages over the state-of-the-art. Advisors/Committee Members: Xue, Jingling, Computer Science & Engineering, Faculty of Engineering, UNSW.

Subjects/Keywords: Compiler; Vectorization; SIMD; Loop Vectorizer; SLP; Simdization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhou, H. (2016). Compiler techniques for improving SIMD parallelism. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true

Chicago Manual of Style (16^th Edition):

Zhou, Hao. “Compiler techniques for improving SIMD parallelism.” 2016. Doctoral Dissertation, University of New South Wales. Accessed March 04, 2021. http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true.

MLA Handbook (7^th Edition):

Zhou, Hao. “Compiler techniques for improving SIMD parallelism.” 2016. Web. 04 Mar 2021.

Vancouver:

Zhou H. Compiler techniques for improving SIMD parallelism. [Internet] [Doctoral dissertation]. University of New South Wales; 2016. [cited 2021 Mar 04]. Available from: http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true.

Council of Science Editors:

Zhou H. Compiler techniques for improving SIMD parallelism. [Doctoral Dissertation]. University of New South Wales; 2016. Available from: http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true

University of Texas – Austin

18. Krimer, Evgeni. Improving energy efficiency of reliable massively-parallel architectures.

Degree: PhD, Electrical and Computer Engineering, 2012, University of Texas – Austin

URL: http://hdl.handle.net/2152/ETD-UT-2012-05-5473

► While transistor size continues to shrink every technology generation increasing the amount of transistors on a die, the reduction in energy consumption is less significant.… (more)

▼ While transistor size continues to shrink every technology generation increasing the amount of transistors on a die, the reduction in energy consumption is less significant. Furthermore, newer technologies induce fabrication challenges resulting in uncertainties in transistor and wire properties. Therefore to ensure correctness, design margins are introduced resulting in significantly sub-optimal energy efficiency. While increasing parallelism and the use of gating methods contribute to energy consumption reduction, ultimately, more radical changes to the architecture and better integration of architectural and circuit techniques will be necessary. This dissertation explores one such approach, combining a highly-efficient massively-parallel processor architecture with a design methodology that reduces energy by trimming design margins. Using a massively-parallel GPU-like (graphics processing unit) base- line architecture, we discuss the different components of process variation and design microarchitectural approaches supporting efficient margins reduction. We evaluate our design using a cycle-based GPU simulator, describe the conditions where efficiency improvements can be obtained, and explore the benefits of decoupling across a wide range of parameters. We architect a test-chip that was fabricated and show these mechanisms to work. We also discuss why previously developed related approaches fall short when process variation is very large, such as in low-voltage operation or as expected for future VLSI technology. We therefore develop and evaluate a new approach specifically for high-variation scenarios. To summarize, in this work, we address the emerging challenges of modern massively parallel architectures including energy efficient, reliable operation and high process variation. We believe that the results of this work are essential for breaking through the energy wall, continuing to improve the efficiency of future generations of the massively parallel architectures. Advisors/Committee Members: Erez, Mattan (advisor), John, Lizy K. (committee member), Orshansky, Michael (committee member), Gerstlauer, Andreas (committee member), Sentis, Luis (committee member).

Subjects/Keywords: SIMD; Energy-efficiency; Process variation; GPU; GPGPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Krimer, E. (2012). Improving energy efficiency of reliable massively-parallel architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2012-05-5473

Chicago Manual of Style (16^th Edition):

Krimer, Evgeni. “Improving energy efficiency of reliable massively-parallel architectures.” 2012. Doctoral Dissertation, University of Texas – Austin. Accessed March 04, 2021. http://hdl.handle.net/2152/ETD-UT-2012-05-5473.

MLA Handbook (7^th Edition):

Krimer, Evgeni. “Improving energy efficiency of reliable massively-parallel architectures.” 2012. Web. 04 Mar 2021.

Vancouver:

Krimer E. Improving energy efficiency of reliable massively-parallel architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5473.

Council of Science Editors:

Krimer E. Improving energy efficiency of reliable massively-parallel architectures. [Doctoral Dissertation]. University of Texas – Austin; 2012. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5473

Colorado State University

19. Thivagara Sarma, Janarthanan. Pruning and acceleration of deep neural networks.

Degree: MS(M.S.), Electrical and Computer Engineering, 2020, Colorado State University

URL: http://hdl.handle.net/10217/208485

► Deep neural networks are computational and memory intensive applications. Many network pruning and compression solutions has been introduced to deploy inference of large trained models… (more)

Subjects/Keywords: compression; pruning; acceleration; SIMD; deep neural networks

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APA (6^th Edition):

Thivagara Sarma, J. (2020). Pruning and acceleration of deep neural networks. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/208485

Chicago Manual of Style (16^th Edition):

Thivagara Sarma, Janarthanan. “Pruning and acceleration of deep neural networks.” 2020. Masters Thesis, Colorado State University. Accessed March 04, 2021. http://hdl.handle.net/10217/208485.

MLA Handbook (7^th Edition):

Thivagara Sarma, Janarthanan. “Pruning and acceleration of deep neural networks.” 2020. Web. 04 Mar 2021.

Vancouver:

Thivagara Sarma J. Pruning and acceleration of deep neural networks. [Internet] [Masters thesis]. Colorado State University; 2020. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10217/208485.

Council of Science Editors:

Thivagara Sarma J. Pruning and acceleration of deep neural networks. [Masters Thesis]. Colorado State University; 2020. Available from: http://hdl.handle.net/10217/208485

20. Bergach, Mohamed Amine. Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture.

Degree: Docteur es, Informatique, 2015, Nice

URL: http://www.theses.fr/2015NICE4060

►

Les architectures multi-cœurs Intel Core (IvyBridge, Haswell,...) contiennent à la fois des cœurs CPU généralistes (4), mais aussi des cœurs dédiés GPU embarqués sur cette… (more)

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Les architectures multi-cœurs Intel Core (IvyBridge, Haswell,...) contiennent à la fois des cœurs CPU généralistes (4), mais aussi des cœurs dédiés GPU embarqués sur cette même puce (16 et 40 respectivement). Dans le cadre de l'activité de la société Kontron (qui participe à ce financement de nature CIFRE) un objectif important est de calculer efficacement sur cette architecture des tableaux et séquences de transformées de Fourier rapides (FFT), comme par exemple on en trouve dans des applications radar. Alors que des bibliothèques natives (mais propriétaires) existent chez Intel pour les CPU, rien de tel n'est actuellement disponible pour la partie GPU. L'objectif de la thèse était donc de définir le placement efficace de modules FFT, en étudiant au niveau théorique la forme optimale permettant de regrouper des étages de calcul d'une telle FFT en fonction de la localité des données sur un cœur de calcul unique. Ce choix a priori permet d'espérer une efficacité des traitements, en ajustant la taille de la mémoire disponible à celles des données nécessaires. Ensuite la multiplicité des cœurs reste exploitable pour disposer plusieurs FFT calculées en parallèle, sans interférence (sauf contention du bus entre CPU et GPU). Nous avons obtenu des résultats significatifs, tant au niveau de l'implantation d'une FFT (1024 points) sur un cœur CPU SIMD, exprimée en langage C, que pour l'implantation d'une FFT de même taille sur un cœur GPU SIMT, exprimée alors en OpenCL. De plus nos résultats permettent de définir des règles pour synthétiser automatiquement de telles solutions, en fonction uniquement de la taille de la FFT son nombre d'étages plus précisément), et de la taille de la mémoire locale pour un coeur de calcul donné. Les performances obtenues sont supérieures à celles de la bibliothèque native Intel pour CPU), et démontrent un gain important de consommation sur GPU. Tous ces points sont détaillés dans le document de thèse. Ces résultats devraient donner lieu à exploitation au sein de la société Kontron.

Multicore architectures Intel Core (IvyBridge, Haswell…) contain both general purpose CPU cores (4) and dedicated GPU cores embedded on the same chip (16 and 40 respectively). As part of the activity of Kontron (the company partially funding this CIFRE scholarship), an important objective is to efficiently compute arrays and sequences of fast Fourier transforms (FFT) such as one finds in radar applications, on this architecture. While native (but proprietary) libraries exist for Intel CPU, nothing is currently available for the GPU part.The aim of the thesis was to define the efficient placement of FFT modules, and to study theoretically the optimal form for grouping computing stages of such FFT according to data locality on a single computing core. This choice should allow processing efficiency, by adjusting the memory size available to the required application data size. Then the multiplicity of cores is exploitable to compute several FFT in parallel, without interference (except for possible bus contention…

Advisors/Committee Members: Simone, Robert de (thesis director).

Subjects/Keywords: FFT; OpenCL; GPGPU; CPU; SIMD; SIMT; AAA; FFT; OpenCL; GPGPU; CPU; SIMD; SIMT; AAA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bergach, M. A. (2015). Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture. (Doctoral Dissertation). Nice. Retrieved from http://www.theses.fr/2015NICE4060

Chicago Manual of Style (16^th Edition):

Bergach, Mohamed Amine. “Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture.” 2015. Doctoral Dissertation, Nice. Accessed March 04, 2021. http://www.theses.fr/2015NICE4060.

MLA Handbook (7^th Edition):

Bergach, Mohamed Amine. “Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture.” 2015. Web. 04 Mar 2021.

Vancouver:

Bergach MA. Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture. [Internet] [Doctoral dissertation]. Nice; 2015. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2015NICE4060.

Council of Science Editors:

Bergach MA. Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture. [Doctoral Dissertation]. Nice; 2015. Available from: http://www.theses.fr/2015NICE4060

21. Kalathingal, Sajith. Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread.

Degree: Docteur es, Informatique, 2016, Rennes 1

URL: http://www.theses.fr/2016REN1S133

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De nombreux microprocesseurs modernes mettent en œuvre le multi-threading simultané (SMT) pour améliorer l'efficacité globale des processeurs superscalaires. SMT masque les opérations à longue latence… (more)

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De nombreux microprocesseurs modernes mettent en œuvre le multi-threading simultané (SMT) pour améliorer l'efficacité globale des processeurs superscalaires. SMT masque les opérations à longue latence en exécutant les instructions de plusieurs threads simultanément. Lorsque les threads exécutent le même programme (cas des applications SPMD), les mêmes instructions sont souvent exécutées avec des entrées différentes. Les architectures SMT traditionnelles exploitent le parallélisme entre threads, ainsi que du parallélisme de données explicite au travers d'unités d'exécution SIMD. L'exécution SIMD est efficace en énergie car le nombre total d'instructions nécessaire pour exécuter un programme est significativement réduit. Cette réduction du nombre d'instructions est fonction de la largeur des unités SIMD et de l'efficacité de la vectorisation. L'efficacité de la vectorisation est cependant souvent limitée en pratique. Dans cette thèse, nous proposons l'architecture de vectorisation dynamique inter-thread (DITVA) pour tirer parti du parallélisme de données implicite des applications SPMD en assemblant dynamiquement des instructions vectorielles à l'exécution. DITVA augmente un processeur à exécution dans l'ordre doté d'unités SIMD en lui ajoutant un mode d'exécution vectorisant entre threads. Lorsque les threads exécutent les mêmes instructions simultanément, DITVA vectorise dynamiquement ces instructions pour assembler des instructions SIMD entre threads. Les threads synchronisés sur le même chemin d'exécution partagent le même flot d'instructions. Pour conserver du parallélisme de threads, DITVA groupe de manière statique les threads en warps ordonnancés indépendamment. DITVA tire parti des unités SIMD existantes et maintient la compatibilité binaire avec les architectures CPU existantes.

Many modern microprocessors implement Simultaneous Multi-Threading (SMT) to improve the overall efficiency of superscalar CPU. SMT hides long latency operations by executing instructions from multiple threads simultaneously. SMT may execute threads of different processes, threads of the same processes or any combination of them. When the threads are from the same process, they often execute the same instructions with different data most of the time, especially in the case of Single-Program Multiple Data (SPMD) applications.Traditional SMT architecture exploit thread-level parallelism and with the use of SIMD execution units, they also support explicit data-level parallelism. SIMD execution is power efficient as the total number of instructions required to execute a complete program is significantly reduced. This instruction reduction is a factor of the width of SIMD execution units and the vectorization efficiency. Static vectorization efficiency depends on the programmer skill and the compiler. Often, the programs are not optimized for vectorization and hence it results in inefficient static vectorization by the compiler.In this thesis, we propose the Dynamic Inter-Thread vectorization Architecture (DITVA) to leverage the implicit…

Advisors/Committee Members: Seznec, André (thesis director), Collange, Sylvain (thesis director).

Subjects/Keywords: Multi-Threading simultané; SPMD; SIMD; Vectorisation dynamique; Architectures des microprocesseurs; Simultaneous Multi-Threading; SPMD; SIMD; Dynamic inter-Thread vectorization; Microprocessor architectures

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kalathingal, S. (2016). Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread. (Doctoral Dissertation). Rennes 1. Retrieved from http://www.theses.fr/2016REN1S133

Chicago Manual of Style (16^th Edition):

Kalathingal, Sajith. “Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread.” 2016. Doctoral Dissertation, Rennes 1. Accessed March 04, 2021. http://www.theses.fr/2016REN1S133.

MLA Handbook (7^th Edition):

Kalathingal, Sajith. “Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread.” 2016. Web. 04 Mar 2021.

Vancouver:

Kalathingal S. Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread. [Internet] [Doctoral dissertation]. Rennes 1; 2016. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2016REN1S133.

Council of Science Editors:

Kalathingal S. Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread. [Doctoral Dissertation]. Rennes 1; 2016. Available from: http://www.theses.fr/2016REN1S133

Brno University of Technology

22. Tomec, Martin. Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/54275

► This work deals with optimization of keyword spotting algorithms on processor architecture ARM Cortex-A8. At first it describes this architecture and especially the NEON unit… (more)

Subjects/Keywords: optimalizace; ARM; NEON; SIMD; detekce klíčových slov; rozpoznávání řeči; neuronová síť; optimization; ARM; NEON; SIMD; keyword spotting; speech recognition; neural net

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tomec, M. (2019). Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54275

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tomec, Martin. “Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/54275.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tomec, Martin. “Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices.” 2019. Web. 04 Mar 2021.

Vancouver:

Tomec M. Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/54275.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tomec M. Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/54275

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

23. Beneš, Vojtěch. Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/55969

► Bachelor's thesis deals with creating a simple programming language for working with mathematical operations. Main point of the thesis is to create a compiler of… (more)

Subjects/Keywords: Generování kódu; překladač; optimalizace; algoritmus kontextového generování; MMX; SSE; SIMD; Code generation; compiler; optimization; algorithm of context generation; MMX; SSE; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Beneš, V. (2019). Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Beneš, Vojtěch. “Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/55969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Beneš, Vojtěch. “Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations.” 2019. Web. 04 Mar 2021.

Vancouver:

Beneš V. Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/55969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Beneš V. Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/55969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

24. Tomečko, Lukáš. Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/62068

► This thesis describes the process of parallelization and vectorization of fluid simulation using OpenMP library and Intel compiler. Various approaches were tried e.g. cache blocking,… (more)

Subjects/Keywords: paralelizácia; vektorizácia; OpenMP; simd; Intel; SPH; simulácia; násobenie matíc; parallelization; vectorization; OpenMP; simd; Intel; SPH; simulation; matmul

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tomečko, L. (2019). Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/62068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tomečko, Lukáš. “Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/62068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tomečko, Lukáš. “Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors.” 2019. Web. 04 Mar 2021.

Vancouver:

Tomečko L. Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/62068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tomečko L. Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/62068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

KTH

25. Guo, Jiabing. Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor.

Degree: Radio Systems Laboratory (RS Lab), 2015, KTH

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474

►

With the wide spread of wireless technology, the time for 4G has arrived, and 5G will appear not so far in the future. However,… (more)

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With the wide spread of wireless technology, the time for 4G has arrived, and 5G will appear not so far in the future. However, no matter whether it is 4G or 5G, low latency is a mandatory requirement for baseband processing at base stations for modern cellular standards. In particular, in a future 5G wireless system, with massive MIMO and ultra-dense cells, the demand for low round trip latency between the mobile device and the base station requires a baseband processing delay of 1 ms. This is 10 percentage of today’s LTE-A round trip latency, while at the same time massive MIMO requires large-scale matrix computations. This is especially true for channel estimation and MIMO detection at the base station. Therefore, it is essential to ensure low latency for the user data traffic. In this master’s thesis, LTE/LTE-A uplink physical layer processing is examined, especially the process of channel estimation and MIMO detection. In order to analyze this processing we compare two conventional algorithms’ performance and complexity for channel estimation and MIMO detection. The key aspect which affects the algorithms’ speed is identified as the need for “massive complex matrix inversion”. A parallel coding scheme is proposed to implement a matrix inversion kernel algorithm on a single instruction multiple data stream (SIMD) vector processor. The major contribution of this thesis is implementation and evaluation of a parallel massive complex matrix inversion algorithm. Two aspects have been addressed: the selection of the algorithm to perform this matrix computation and the implementation of a highly parallel version of this algorithm.

Med den breda spridningen av trådlös teknik, har tiden för 4G kommit, och 5G kommer inom en överskådlig framtid. Men oavsett om det gäller 4G eller 5G, låg latens är ett obligatoriskt krav för basbandsbehandling vid basstationer för moderna mobila standarder. I synnerhet i ett framtida trådlöst 5G-system, med massiva MIMO och ultratäta celler, behövs en basbandsbehandling fördröjning på 1 ms för att klara efterfrågan på en låg rundresa latens mellan den mobila enheten och basstationen. Detta är 10 procent av dagens LTE-E rundresa latens, medan massiva MIMO samtidigt kräver storskaliga matrisberäkningar. Detta är särskilt viktigt för kanaluppskattning och MIMO-detektion vid basstationen. Därför är det viktigt att se till att det är låg latens för användardatatrafik. I detta examensarbete, skall LTE/LTE-A upplänk fysiska lagret bearbetning undersökas, och då särskilt processen för kanaluppskattning och MIMO-detektion. För att analysera denna processing jämför vi två konventionella algoritmers prestationer och komplexitet för kanaluppskattning och MIMO-detektion. Den viktigaste aspekten som påverkar algoritmernas hastighet identifieras som behovet av "massiva komplex matrisinversion". Ett parallellt kodningsschema föreslås för att implementera en "matrisinversion kernel-algoritmen" på singelinstruktion multidataström (SIMD) vektorprocessor. Det största…

Subjects/Keywords: channel estimation; MIMO detection; massive complex matrix inversion; SIMD; kanaluppskattning; MIMO-detektion; massiva komplex matrisinversion; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Guo, J. (2015). Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Guo, Jiabing. “Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor.” 2015. Thesis, KTH. Accessed March 04, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Guo, Jiabing. “Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor.” 2015. Web. 04 Mar 2021.

Vancouver:

Guo J. Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor. [Internet] [Thesis]. KTH; 2015. [cited 2021 Mar 04]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guo J. Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor. [Thesis]. KTH; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

26. Juránek, Roman. Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers.

Degree: 2018, Brno University of Technology

URL: http://hdl.handle.net/11012/63272

► Detection of objects in computer vision is a complex task. One of most popular and well explored approaches is the use of statistical classifiers and… (more)

Subjects/Keywords: Detekce objektů; AdaBoost; WaldBoost; Akcelerace; SIMD; Minimalizace ceny; Object Detection; AdaBoost; WaldBoost; Acceleration; SIMD; Cost Minimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Juránek, R. (2018). Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/63272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Juránek, Roman. “Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers.” 2018. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/63272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Juránek, Roman. “Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers.” 2018. Web. 04 Mar 2021.

Vancouver:

Juránek R. Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/63272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Juránek R. Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/63272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Delft University of Technology

27. Shahbahrami, A. Avoiding conversion and rearrangement overhead in SIMD architecures.

Degree: 2008, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5

► In this dissertation, a novel SIMD extension called Modified MMX (MMMX) for multimedia computing is presented. Specifically, the MMX architecture is enhanced with the extended… (more)

▼ In this dissertation, a novel SIMD extension called Modified MMX (MMMX) for multimedia computing is presented. Specifically, the MMX architecture is enhanced with the extended subwords and the matrix register file techniques. The extended subwords technique uses SIMD registers that are wider than the packed format used to store the data. The extended subwords technique avoids data type conversion overhead and increases parallelism in SIMD architectures. This is because promoting the subwords of the source SIMD registers to larger subwords before they can be processed and demoting the results again before they can be written back to memory incurs conversion overhead. The matrix register file technique allows to load data that is stored consecutively in memory into a column of the register file, where a column corresponds to the corresponding subwords of different registers. In other words, this technique provides both row-wise as well as column-wise accesses to the media register file. It is a useful approach for matrix operations that are common in multimedia processing. In addition, in this work, new and general SIMD instructions addressing the multimedia application domain are investigated. It does not consider an ISA that is application specific. For example, special-purpose instructions are synthesized using a few general-purpose SIMD instructions. The performance of the MMMX architecture is compared to the performance of the MMX/SSE architecture for different multimedia applications and kernels using the sim-outorder simulator of the SimpleScalar toolset. Additionally, three issues related to the efficient implementation of the 2D Discrete Wavelet Transform (DWT)on general-purpose processors, in particular the Pentium 4, are discussed. These are 64K aliasing, cache conflict misses, and SIMD vectorization. 64K aliasing is a phenomenon that happens on the Pentium 4, which can degrade performance by an order of magnitude. It occurs if two or more data items whose addresses differ by a multiple of 64K need to be cached simultaneously. There are also many cache conflict misses in the implementation of vertical filtering of the DWT, if the filter length exceeds the number of cache ways. In this dissertation, techniques are proposed to avoid 64K aliasing and to mitigate cache conflict misses. Furthermore, the performance of the 2D DWT is improved by exploiting the data-level parallelism using the SIMD instructions supported by most general-purpose processors. Advisors/Committee Members: Goossens, K.G.W..

Subjects/Keywords: SIMD architectures; vectorization; SIMD programming; multimedia application; cache optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Shahbahrami, A. (2008). Avoiding conversion and rearrangement overhead in SIMD architecures. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5

Chicago Manual of Style (16^th Edition):

Shahbahrami, A. “Avoiding conversion and rearrangement overhead in SIMD architecures.” 2008. Doctoral Dissertation, Delft University of Technology. Accessed March 04, 2021. http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5.

MLA Handbook (7^th Edition):

Shahbahrami, A. “Avoiding conversion and rearrangement overhead in SIMD architecures.” 2008. Web. 04 Mar 2021.

Vancouver:

Shahbahrami A. Avoiding conversion and rearrangement overhead in SIMD architecures. [Internet] [Doctoral dissertation]. Delft University of Technology; 2008. [cited 2021 Mar 04]. Available from: http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5.

Council of Science Editors:

Shahbahrami A. Avoiding conversion and rearrangement overhead in SIMD architecures. [Doctoral Dissertation]. Delft University of Technology; 2008. Available from: http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5

28. Lemaitre, Florian. Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction.

Degree: Docteur es, Informatique, télécommunications et électronique, 2019, Sorbonne université

URL: http://www.theses.fr/2019SORUS221

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Tout au long de cette thèse, nous avons étudié des problèmes d'algèbre linéaire de petite dimension (typiquement de 2x2 à 5x5) utilisés au sein de… (more)

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Tout au long de cette thèse, nous avons étudié des problèmes d'algèbre linéaire de petite dimension (typiquement de 2x2 à 5x5) utilisés au sein de l'expérience LHCb (mais aussi dans d'autres domaines tels que la vision par ordinateur). Les bibliothèques d’algèbre linéaire telles que Eigen, Magma ou la MKL ne sont pas optimisées pour de petites matrices. Nous avons utilisé et combiné plusieurs transformations connues facilitant le SIMD ainsi que des transformations moins usuelles comme la racine carré inverse rapide. Pour faciliter l’écriture de ces transformations, mais également dans le but d’avoir un code portable, nous avons écrit un générateur de code. Nous avons testé ces transformations et analysé leur impact sur la vitesse de traitement d’algorithmes simples. Le traitement par lot (batch) en SoA est crucial pour maximiser la vitesse de traitements de ces problèmes à faible dimension. Une analyse de la précision des résultats en fonction de la précision de calcul a également été faite sur ces exemples. Nous avons alors implémenté ces transformations dans le but d’accélérer la factorisation de Cholesky de petites matrices (jusqu'à 12x12). La vitesse de traitement plafonne sans l’utilisation du calcul rapide de la racine carrée inverse. Nous avons obtenu une accélération entre x10 et x33 en F32. Notre code est ainsi de x3 à x10 plus rapide que la MKL. Enfin, nous avons étudié et accéléré le filtre de Kalman généraliste. Nous avons ainsi obtenu une accélération de x90 sur l'implémentation 4x4 F32. Le filtre de Kalman utilisé au sein de LHCb a été accéléré d'un facteur x2,2 par rapport à la version actuelle SIMD et supérieur à x2,3 par rapport aux filtres d'autres expériences de physique des particules.

During this thesis, we studied linear algebra systems with small matrices (typically from 2x2 to 5x5) used within the LHCb experiment (and also in other domains like computer vision). Linear algebra libraries like Eigen, Magma or the MKL are not optimized for such small matrices. We used and combined many well-known transforms helping SIMD and some unusual transforms like the fast reciprocal square root computation. We wrote a code generator in order to simplify the use of such transforms and to have a portable code. We tested these optimizations and analyzed their impact on the speed of simple algorithm. Batch processing in SoA is crucial to process fast these small matrices. We also analyzed how the accuracy of the results depends on the precision of the data. We implemented these transforms in order to speed-up the Cholesky factorization of small matrices (up to 12x12). The processing speed is capped if the fast reciprocal square root computation is not used. We got a speed up between x10 and x33 using F32. Our version is then from x3 to x10 faster than MKL. Finally, we studied and sped up the Kalman filter in its general form. Our 4x4 F32 implementation is x90 faster. The Kalman filter used within LHCb has been sped up by x2.2 compared to the current SIMD version and by at least x2.3 compared to filters used…

Advisors/Committee Members: Lacassagne, Lionel (thesis director).

Subjects/Keywords: SIMD; Petites matrices; Kalman; Cholesky; Génération de code; Multithread; SIMD; Small matrices; Kalman; Cholesky; Code generation; Multithread; 512.5; 003.75

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lemaitre, F. (2019). Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction. (Doctoral Dissertation). Sorbonne université. Retrieved from http://www.theses.fr/2019SORUS221

Chicago Manual of Style (16^th Edition):

Lemaitre, Florian. “Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction.” 2019. Doctoral Dissertation, Sorbonne université. Accessed March 04, 2021. http://www.theses.fr/2019SORUS221.

MLA Handbook (7^th Edition):

Lemaitre, Florian. “Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction.” 2019. Web. 04 Mar 2021.

Vancouver:

Lemaitre F. Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction. [Internet] [Doctoral dissertation]. Sorbonne université; 2019. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2019SORUS221.

Council of Science Editors:

Lemaitre F. Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction. [Doctoral Dissertation]. Sorbonne université; 2019. Available from: http://www.theses.fr/2019SORUS221

Brno University of Technology

29. Fuksa, Tomáš. Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library.

Degree: 2018, Brno University of Technology

URL: http://hdl.handle.net/11012/8264

► This work deals with parallel computing on modern processors - multi-core CPU and GPU. The goal is to learn about computing on this devices suitable… (more)

Subjects/Keywords: Grafický procesor; GPGPU; Nvidia; CUDA; Paralelismus; OpenCL; Intel IPP; SIMD; Graphic processor; GPGPU; Nvidia; CUDA; Paralelism; OpenCL; Intel IPP; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Fuksa, T. (2018). Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/8264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Fuksa, Tomáš. “Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library.” 2018. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/8264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Fuksa, Tomáš. “Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library.” 2018. Web. 04 Mar 2021.

Vancouver:

Fuksa T. Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/8264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fuksa T. Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/8264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

30. Šlenker, Samuel. Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/41353

► The aim of this thesis was to study and subsequently process the differences between the older instruction sets and newer instruction sets, to specify the… (more)

Subjects/Keywords: SIMD; SSE; AVX; FMA; vektorové spracovanie dát; Intel; AMD; SIMD; SSE; AVX; FMA; vector data processing; Intel; AMD

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Šlenker, S. (2019). Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/41353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Šlenker, Samuel. “Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/41353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Šlenker, Samuel. “Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization.” 2019. Web. 04 Mar 2021.

Vancouver:

Šlenker S. Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/41353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šlenker S. Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/41353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations