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You searched for subject:(SIMD). Showing records 1 – 30 of 175 total matches.

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Rochester Institute of Technology

1. Mazza, James P. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.

Degree: MS, Electrical Engineering, 2014, Rochester Institute of Technology

  Data parallel image processing algorithms have numerous uses in many real time applications. Depending on the complexity of the computations involved, these algorithms may… (more)

Subjects/Keywords: FPGA; Hardward; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mazza, J. P. (2014). Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8604

Chicago Manual of Style (16th Edition):

Mazza, James P. “Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.” 2014. Masters Thesis, Rochester Institute of Technology. Accessed March 04, 2021. https://scholarworks.rit.edu/theses/8604.

MLA Handbook (7th Edition):

Mazza, James P. “Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.” 2014. Web. 04 Mar 2021.

Vancouver:

Mazza JP. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. [Internet] [Masters thesis]. Rochester Institute of Technology; 2014. [cited 2021 Mar 04]. Available from: https://scholarworks.rit.edu/theses/8604.

Council of Science Editors:

Mazza JP. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. [Masters Thesis]. Rochester Institute of Technology; 2014. Available from: https://scholarworks.rit.edu/theses/8604


NSYSU

2. Huang, Kuan-min. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 3D graphics pipeline can be divided into two subsystems: geometry subsystem and rendering subsystem. Hardware implementation of the transformation and lighting in the geometric subsystem… (more)

Subjects/Keywords: Vertex Shader; SIMD; Programmable

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, K. (2009). Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Web. 04 Mar 2021.

Vancouver:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Pan, Po-Hsun. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.

Degree: Master, Electrical Engineering, 2011, NSYSU

 In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. To identify human behavior which achieve… (more)

Subjects/Keywords: action recognition; SIMD; CELL; parallelize

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pan, P. (2011). The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pan, Po-Hsun. “The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.” 2011. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pan, Po-Hsun. “The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.” 2011. Web. 04 Mar 2021.

Vancouver:

Pan P. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pan P. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. 松本, 剛英. 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケ マルチスレッド プロセッサ ノ セッケイ ト ヒョウカ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: プロセッサ; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

松本, . (n.d.). 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケ マルチスレッド プロセッサ ノ セッケイ ト ヒョウカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1770

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

松本, 剛英. “組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケ マルチスレッド プロセッサ ノ セッケイ ト ヒョウカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed March 04, 2021. http://hdl.handle.net/10061/1770.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

松本, 剛英. “組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケ マルチスレッド プロセッサ ノ セッケイ ト ヒョウカ.” Web. 04 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

松本 . 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケ マルチスレッド プロセッサ ノ セッケイ ト ヒョウカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10061/1770.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

松本 . 組み込み向けマルチスレッドプロセッサの設計と評価 : Design and evaluation of multithread processor for embedded system; クミコミムケ マルチスレッド プロセッサ ノ セッケイ ト ヒョウカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1770

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


NSYSU

5. Chang, Hsin-Tzu. Study on LTE MIMO System in SIMD Architecture.

Degree: Master, Communications Engineering, 2018, NSYSU

 In order to increase the spectral efficiency under limited bandwidth, the main technology Long Term Evolution (LTE) of the Fourth Generation of Mobile Phone Mobile… (more)

Subjects/Keywords: MKL; MIMO; SIMD; OFDM; LTE

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, H. (2018). Study on LTE MIMO System in SIMD Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Hsin-Tzu. “Study on LTE MIMO System in SIMD Architecture.” 2018. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Hsin-Tzu. “Study on LTE MIMO System in SIMD Architecture.” 2018. Web. 04 Mar 2021.

Vancouver:

Chang H. Study on LTE MIMO System in SIMD Architecture. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang H. Study on LTE MIMO System in SIMD Architecture. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-175738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

6. Chan, Chun-Jung. Investigation of NoGap : SIMD Datapath Implementation.

Degree: Electrical Engineering, 2011, Linköping University

  Nowadays, many ASIP systems with high computational capabilities are designed in order to fulfill the increasing demands of technical applications. However, the design of… (more)

Subjects/Keywords: ASIP; NoGap; ePUMA; Sleipnir; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chan, C. (2011). Investigation of NoGap : SIMD Datapath Implementation. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chan, Chun-Jung. “Investigation of NoGap : SIMD Datapath Implementation.” 2011. Thesis, Linköping University. Accessed March 04, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chan, Chun-Jung. “Investigation of NoGap : SIMD Datapath Implementation.” 2011. Web. 04 Mar 2021.

Vancouver:

Chan C. Investigation of NoGap : SIMD Datapath Implementation. [Internet] [Thesis]. Linköping University; 2011. [cited 2021 Mar 04]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chan C. Investigation of NoGap : SIMD Datapath Implementation. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

7. Benna, Filip. Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library.

Degree: 2018, Brno University of Technology

 This bachelor's thesis deals with compilation of OpenCV library with Codix RISC processor core as the target machine and following optimization of chosen applications based… (more)

Subjects/Keywords: OpenCV; Codix RISC; SIMD; optimalizace; OpenCV; Codix RISC; SIMD; optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Benna, F. (2018). Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/52377

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Benna, Filip. “Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library.” 2018. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/52377.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Benna, Filip. “Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library.” 2018. Web. 04 Mar 2021.

Vancouver:

Benna F. Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/52377.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Benna F. Optimalizace procesorového jádra pro knihovnu OpenCV: Optimization of a Processor Core for the OpenCV Library. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/52377

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

8. Šnobl, Pavel. Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems.

Degree: 2019, Brno University of Technology

 This master's thesis deals with the support for compilation and execution of programs written using OpenCL framework on embedded systems. OpenCL is a system for… (more)

Subjects/Keywords: OpenCL; LLVM; Codasip; SIMD; VLIW; OpenCL; LLVM; Codasip; SIMD; VLIW

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Šnobl, P. (2019). Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/61853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems.” 2019. Web. 04 Mar 2021.

Vancouver:

Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/61853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/61853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

9. Šnobl, Pavel. Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler.

Degree: 2019, Brno University of Technology

 This bachelor thesis deals with support of automatic vectorization of code in the LLVM compilation framework and with extension of Codix processor model of SIMD(more)

Subjects/Keywords: SIMD; LLVM; Codix; CodAL; autovektorizace; SIMD; LLVM; Codix; CodAL; Auto-Vectorization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Šnobl, P. (2019). Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/56572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Šnobl, Pavel. “Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/56572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Šnobl, Pavel. “Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler.” 2019. Web. 04 Mar 2021.

Vancouver:

Šnobl P. Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/56572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šnobl P. Podpora SIMD instrukcí v překladači LLVM: SIMD Instructions Support in LLVM Compiler. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/56572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Chen, Li-Yao. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations… (more)

Subjects/Keywords: Integration; SOC; Programmable; SIMD; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, L. (2010). Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Web. 04 Mar 2021.

Vancouver:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Li, Shang-Yu. Design and Implementation of a Vision Processor Based on the OpenVX Specification.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Embedded computer vision applications emphasizes fast and real-time processing speed with low power consumption. To face these challenge, we need more suitable hardware accelerator for… (more)

Subjects/Keywords: Computer vision applications; OpenVX; SIMD; Vision Processor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, S. (2016). Design and Implementation of a Vision Processor Based on the OpenVX Specification. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Web. 04 Mar 2021.

Vancouver:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Hsieh, Cheng-han. Study on Real-Time Software Architecture for LTE MIMO System.

Degree: Master, Communications Engineering, 2017, NSYSU

 Long-term-evolution (LTE) and LTE-Advance are undoubtedly the most successful mobile broadband technologies in the fourth generation (4G) wireless system. LTE employs orthogonal frequency division multiplexing… (more)

Subjects/Keywords: MKL; parallel processing; MIMO; OFDM; LTE; SIMD

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APA (6th Edition):

Hsieh, C. (2017). Study on Real-Time Software Architecture for LTE MIMO System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsieh, Cheng-han. “Study on Real-Time Software Architecture for LTE MIMO System.” 2017. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsieh, Cheng-han. “Study on Real-Time Software Architecture for LTE MIMO System.” 2017. Web. 04 Mar 2021.

Vancouver:

Hsieh C. Study on Real-Time Software Architecture for LTE MIMO System. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh C. Study on Real-Time Software Architecture for LTE MIMO System. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618117-094659

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Manchester

13. Garcia Ordaz, Jose Raul. Dynamic CPU ISA Customizations through FPGA Interlays.

Degree: 2018, University of Manchester

 General purpose processors (GPPs) are designed to provide a substantial level of performance for a wide range of applications. However, GPPs, in particular those aimed… (more)

Subjects/Keywords: FPGA; Partial Reconfigution; SIMD; Soft-processor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Garcia Ordaz, J. R. (2018). Dynamic CPU ISA Customizations through FPGA Interlays. (Doctoral Dissertation). University of Manchester. Retrieved from http://www.manchester.ac.uk/escholar/uk-ac-man-scw:316951

Chicago Manual of Style (16th Edition):

Garcia Ordaz, Jose Raul. “Dynamic CPU ISA Customizations through FPGA Interlays.” 2018. Doctoral Dissertation, University of Manchester. Accessed March 04, 2021. http://www.manchester.ac.uk/escholar/uk-ac-man-scw:316951.

MLA Handbook (7th Edition):

Garcia Ordaz, Jose Raul. “Dynamic CPU ISA Customizations through FPGA Interlays.” 2018. Web. 04 Mar 2021.

Vancouver:

Garcia Ordaz JR. Dynamic CPU ISA Customizations through FPGA Interlays. [Internet] [Doctoral dissertation]. University of Manchester; 2018. [cited 2021 Mar 04]. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:316951.

Council of Science Editors:

Garcia Ordaz JR. Dynamic CPU ISA Customizations through FPGA Interlays. [Doctoral Dissertation]. University of Manchester; 2018. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:316951


Northeastern University

14. Yilmazer, Ayse. Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS.

Degree: PhD, Department of Electrical and Computer Engineering, 2013, Northeastern University

 GPUs dedicate a majority of their transistor budgets to compute units rather than control logic. As a result, they can achieve excellent data-parallel power/performance. Given… (more)

Subjects/Keywords: GPU; SIMD Execution; Synchronization; Computer Engineering

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APA (6th Edition):

Yilmazer, A. (2013). Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20004880

Chicago Manual of Style (16th Edition):

Yilmazer, Ayse. “Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS.” 2013. Doctoral Dissertation, Northeastern University. Accessed March 04, 2021. http://hdl.handle.net/2047/d20004880.

MLA Handbook (7th Edition):

Yilmazer, Ayse. “Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS.” 2013. Web. 04 Mar 2021.

Vancouver:

Yilmazer A. Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS. [Internet] [Doctoral dissertation]. Northeastern University; 2013. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2047/d20004880.

Council of Science Editors:

Yilmazer A. Micro-architectural support for improving synchronization and efficiency of SIMD execution on GPUS. [Doctoral Dissertation]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20004880

15. Pang, Yihan. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 The author of this thesis has a family full of non-engineers. To persuade family members that the work of this thesis is meaningful, aka the… (more)

Subjects/Keywords: System Software; Heterogeneous Architectures; SIMD; Scheduling; ISA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pang, Y. (2019). Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/95299

Chicago Manual of Style (16th Edition):

Pang, Yihan. “Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.” 2019. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/95299.

MLA Handbook (7th Edition):

Pang, Yihan. “Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.” 2019. Web. 04 Mar 2021.

Vancouver:

Pang Y. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/95299.

Council of Science Editors:

Pang Y. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/95299


University of Manchester

16. Garcia Ordaz, Jose. Dynamic CPU ISA customizations through FPGA interlays.

Degree: PhD, 2018, University of Manchester

 General purpose processors (GPPs) are designed to provide a substantial level of performance for a wide range of applications. However, GPPs, in particular those aimed… (more)

Subjects/Keywords: FPGA; Partial Reconfigution; SIMD; Soft-processor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Garcia Ordaz, J. (2018). Dynamic CPU ISA customizations through FPGA interlays. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa-customizations-through-fpga-interlays(fb111711-1be8-4b04-8b46-aeb5dbd520c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799290

Chicago Manual of Style (16th Edition):

Garcia Ordaz, Jose. “Dynamic CPU ISA customizations through FPGA interlays.” 2018. Doctoral Dissertation, University of Manchester. Accessed March 04, 2021. https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa-customizations-through-fpga-interlays(fb111711-1be8-4b04-8b46-aeb5dbd520c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799290.

MLA Handbook (7th Edition):

Garcia Ordaz, Jose. “Dynamic CPU ISA customizations through FPGA interlays.” 2018. Web. 04 Mar 2021.

Vancouver:

Garcia Ordaz J. Dynamic CPU ISA customizations through FPGA interlays. [Internet] [Doctoral dissertation]. University of Manchester; 2018. [cited 2021 Mar 04]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa-customizations-through-fpga-interlays(fb111711-1be8-4b04-8b46-aeb5dbd520c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799290.

Council of Science Editors:

Garcia Ordaz J. Dynamic CPU ISA customizations through FPGA interlays. [Doctoral Dissertation]. University of Manchester; 2018. Available from: https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa-customizations-through-fpga-interlays(fb111711-1be8-4b04-8b46-aeb5dbd520c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799290


University of New South Wales

17. Zhou, Hao. Compiler techniques for improving SIMD parallelism.

Degree: Computer Science & Engineering, 2016, University of New South Wales

 Modern CPUs are equipped with Single Instruction Multiple Data (SIMD) engines operating on short vectors, in order to meet the growing demands of accelerating multimedia… (more)

Subjects/Keywords: Compiler; Vectorization; SIMD; Loop Vectorizer; SLP; Simdization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, H. (2016). Compiler techniques for improving SIMD parallelism. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Zhou, Hao. “Compiler techniques for improving SIMD parallelism.” 2016. Doctoral Dissertation, University of New South Wales. Accessed March 04, 2021. http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true.

MLA Handbook (7th Edition):

Zhou, Hao. “Compiler techniques for improving SIMD parallelism.” 2016. Web. 04 Mar 2021.

Vancouver:

Zhou H. Compiler techniques for improving SIMD parallelism. [Internet] [Doctoral dissertation]. University of New South Wales; 2016. [cited 2021 Mar 04]. Available from: http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true.

Council of Science Editors:

Zhou H. Compiler techniques for improving SIMD parallelism. [Doctoral Dissertation]. University of New South Wales; 2016. Available from: http://handle.unsw.edu.au/1959.4/56842 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41633/SOURCE02?view=true


University of Texas – Austin

18. Krimer, Evgeni. Improving energy efficiency of reliable massively-parallel architectures.

Degree: PhD, Electrical and Computer Engineering, 2012, University of Texas – Austin

 While transistor size continues to shrink every technology generation increasing the amount of transistors on a die, the reduction in energy consumption is less significant.… (more)

Subjects/Keywords: SIMD; Energy-efficiency; Process variation; GPU; GPGPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Krimer, E. (2012). Improving energy efficiency of reliable massively-parallel architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2012-05-5473

Chicago Manual of Style (16th Edition):

Krimer, Evgeni. “Improving energy efficiency of reliable massively-parallel architectures.” 2012. Doctoral Dissertation, University of Texas – Austin. Accessed March 04, 2021. http://hdl.handle.net/2152/ETD-UT-2012-05-5473.

MLA Handbook (7th Edition):

Krimer, Evgeni. “Improving energy efficiency of reliable massively-parallel architectures.” 2012. Web. 04 Mar 2021.

Vancouver:

Krimer E. Improving energy efficiency of reliable massively-parallel architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5473.

Council of Science Editors:

Krimer E. Improving energy efficiency of reliable massively-parallel architectures. [Doctoral Dissertation]. University of Texas – Austin; 2012. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5473


Colorado State University

19. Thivagara Sarma, Janarthanan. Pruning and acceleration of deep neural networks.

Degree: MS(M.S.), Electrical and Computer Engineering, 2020, Colorado State University

 Deep neural networks are computational and memory intensive applications. Many network pruning and compression solutions has been introduced to deploy inference of large trained models… (more)

Subjects/Keywords: compression; pruning; acceleration; SIMD; deep neural networks

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Thivagara Sarma, J. (2020). Pruning and acceleration of deep neural networks. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/208485

Chicago Manual of Style (16th Edition):

Thivagara Sarma, Janarthanan. “Pruning and acceleration of deep neural networks.” 2020. Masters Thesis, Colorado State University. Accessed March 04, 2021. http://hdl.handle.net/10217/208485.

MLA Handbook (7th Edition):

Thivagara Sarma, Janarthanan. “Pruning and acceleration of deep neural networks.” 2020. Web. 04 Mar 2021.

Vancouver:

Thivagara Sarma J. Pruning and acceleration of deep neural networks. [Internet] [Masters thesis]. Colorado State University; 2020. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10217/208485.

Council of Science Editors:

Thivagara Sarma J. Pruning and acceleration of deep neural networks. [Masters Thesis]. Colorado State University; 2020. Available from: http://hdl.handle.net/10217/208485

20. Bergach, Mohamed Amine. Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture.

Degree: Docteur es, Informatique, 2015, Nice

Les architectures multi-cœurs Intel Core (IvyBridge, Haswell,...) contiennent à la fois des cœurs CPU généralistes (4), mais aussi des cœurs dédiés GPU embarqués sur cette… (more)

Subjects/Keywords: FFT; OpenCL; GPGPU; CPU; SIMD; SIMT; AAA; FFT; OpenCL; GPGPU; CPU; SIMD; SIMT; AAA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bergach, M. A. (2015). Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture. (Doctoral Dissertation). Nice. Retrieved from http://www.theses.fr/2015NICE4060

Chicago Manual of Style (16th Edition):

Bergach, Mohamed Amine. “Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture.” 2015. Doctoral Dissertation, Nice. Accessed March 04, 2021. http://www.theses.fr/2015NICE4060.

MLA Handbook (7th Edition):

Bergach, Mohamed Amine. “Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture.” 2015. Web. 04 Mar 2021.

Vancouver:

Bergach MA. Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture. [Internet] [Doctoral dissertation]. Nice; 2015. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2015NICE4060.

Council of Science Editors:

Bergach MA. Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée : Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture. [Doctoral Dissertation]. Nice; 2015. Available from: http://www.theses.fr/2015NICE4060

21. Kalathingal, Sajith. Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread.

Degree: Docteur es, Informatique, 2016, Rennes 1

De nombreux microprocesseurs modernes mettent en œuvre le multi-threading simultané (SMT) pour améliorer l'efficacité globale des processeurs superscalaires. SMT masque les opérations à longue latence… (more)

Subjects/Keywords: Multi-Threading simultané; SPMD; SIMD; Vectorisation dynamique; Architectures des microprocesseurs; Simultaneous Multi-Threading; SPMD; SIMD; Dynamic inter-Thread vectorization; Microprocessor architectures

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kalathingal, S. (2016). Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread. (Doctoral Dissertation). Rennes 1. Retrieved from http://www.theses.fr/2016REN1S133

Chicago Manual of Style (16th Edition):

Kalathingal, Sajith. “Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread.” 2016. Doctoral Dissertation, Rennes 1. Accessed March 04, 2021. http://www.theses.fr/2016REN1S133.

MLA Handbook (7th Edition):

Kalathingal, Sajith. “Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread.” 2016. Web. 04 Mar 2021.

Vancouver:

Kalathingal S. Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread. [Internet] [Doctoral dissertation]. Rennes 1; 2016. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2016REN1S133.

Council of Science Editors:

Kalathingal S. Transforming TLP into DLP with the dynamic inter-thread vectorization architecture : Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread. [Doctoral Dissertation]. Rennes 1; 2016. Available from: http://www.theses.fr/2016REN1S133


Brno University of Technology

22. Tomec, Martin. Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices.

Degree: 2019, Brno University of Technology

 This work deals with optimization of keyword spotting algorithms   on processor architecture ARM Cortex-A8. At first it describes this    architecture and especially the NEON unit… (more)

Subjects/Keywords: optimalizace; ARM; NEON; SIMD; detekce klíčových slov; rozpoznávání řeči; neuronová síť; optimization; ARM; NEON; SIMD; keyword spotting; speech recognition; neural net

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APA (6th Edition):

Tomec, M. (2019). Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54275

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tomec, Martin. “Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/54275.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tomec, Martin. “Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices.” 2019. Web. 04 Mar 2021.

Vancouver:

Tomec M. Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/54275.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tomec M. Optimalizace rozpoznávání řeči pro mobilní zařízení: Optimization of Voice Recognition for Mobile Devices. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/54275

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

23. Beneš, Vojtěch. Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations.

Degree: 2019, Brno University of Technology

 Bachelor's thesis deals with creating a simple programming language for working with mathematical operations. Main point of the thesis is to create a compiler of… (more)

Subjects/Keywords: Generování kódu; překladač; optimalizace; algoritmus kontextového generování; MMX; SSE; SIMD; Code generation; compiler; optimization; algorithm of context generation; MMX; SSE; SIMD

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APA (6th Edition):

Beneš, V. (2019). Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Beneš, Vojtěch. “Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/55969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Beneš, Vojtěch. “Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations.” 2019. Web. 04 Mar 2021.

Vancouver:

Beneš V. Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/55969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Beneš V. Generování kódu optimalizovaných matematických operací: Generating Code of Optimised Mathematical Operations. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/55969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

24. Tomečko, Lukáš. Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors.

Degree: 2019, Brno University of Technology

 This thesis describes the process of parallelization and vectorization of fluid simulation using OpenMP library and Intel compiler. Various approaches were tried e.g. cache blocking,… (more)

Subjects/Keywords: paralelizácia; vektorizácia; OpenMP; simd; Intel; SPH; simulácia; násobenie matíc; parallelization; vectorization; OpenMP; simd; Intel; SPH; simulation; matmul

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APA (6th Edition):

Tomečko, L. (2019). Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/62068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tomečko, Lukáš. “Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/62068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tomečko, Lukáš. “Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors.” 2019. Web. 04 Mar 2021.

Vancouver:

Tomečko L. Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/62068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tomečko L. Efektivní implementace vysoce náročných algoritmů na vícejádrových procesorech: Efficient Implementation of High Performance Algorithms on Multi-Core Processors. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/62068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

25. Guo, Jiabing. Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor.

Degree: Radio Systems Laboratory (RS Lab), 2015, KTH

With the wide spread of wireless technology, the time for 4G has arrived, and 5G will appear not so far in the future. However,… (more)

Subjects/Keywords: channel estimation; MIMO detection; massive complex matrix inversion; SIMD; kanaluppskattning; MIMO-detektion; massiva komplex matrisinversion; SIMD

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APA (6th Edition):

Guo, J. (2015). Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guo, Jiabing. “Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor.” 2015. Thesis, KTH. Accessed March 04, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guo, Jiabing. “Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor.” 2015. Web. 04 Mar 2021.

Vancouver:

Guo J. Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor. [Internet] [Thesis]. KTH; 2015. [cited 2021 Mar 04]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guo J. Design and implementation of LTE-A and 5G kernel algorithms on SIMD vector processor. [Thesis]. KTH; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-159474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

26. Juránek, Roman. Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers.

Degree: 2018, Brno University of Technology

 Detection of objects in computer vision is a complex task. One of most popular and well explored  approaches is the use of statistical classifiers and… (more)

Subjects/Keywords: Detekce objektů; AdaBoost; WaldBoost; Akcelerace; SIMD; Minimalizace ceny; Object Detection; AdaBoost; WaldBoost; Acceleration; SIMD; Cost Minimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Juránek, R. (2018). Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/63272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Juránek, Roman. “Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers.” 2018. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/63272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Juránek, Roman. “Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers.” 2018. Web. 04 Mar 2021.

Vancouver:

Juránek R. Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/63272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Juránek R. Akcelerace detekce objektů pomocí klasifikátorů: Acceleration of Object Detection Using Classifiers. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/63272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

27. Shahbahrami, A. Avoiding conversion and rearrangement overhead in SIMD architecures.

Degree: 2008, Delft University of Technology

 In this dissertation, a novel SIMD extension called Modified MMX (MMMX) for multimedia computing is presented. Specifically, the MMX architecture is enhanced with the extended… (more)

Subjects/Keywords: SIMD architectures; vectorization; SIMD programming; multimedia application; cache optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shahbahrami, A. (2008). Avoiding conversion and rearrangement overhead in SIMD architecures. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5

Chicago Manual of Style (16th Edition):

Shahbahrami, A. “Avoiding conversion and rearrangement overhead in SIMD architecures.” 2008. Doctoral Dissertation, Delft University of Technology. Accessed March 04, 2021. http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5.

MLA Handbook (7th Edition):

Shahbahrami, A. “Avoiding conversion and rearrangement overhead in SIMD architecures.” 2008. Web. 04 Mar 2021.

Vancouver:

Shahbahrami A. Avoiding conversion and rearrangement overhead in SIMD architecures. [Internet] [Doctoral dissertation]. Delft University of Technology; 2008. [cited 2021 Mar 04]. Available from: http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5.

Council of Science Editors:

Shahbahrami A. Avoiding conversion and rearrangement overhead in SIMD architecures. [Doctoral Dissertation]. Delft University of Technology; 2008. Available from: http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; urn:NBN:nl:ui:24-uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5 ; http://resolver.tudelft.nl/uuid:4fd01d95-6bf6-4864-8662-f7adf837e2f5

28. Lemaitre, Florian. Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction.

Degree: Docteur es, Informatique, télécommunications et électronique, 2019, Sorbonne université

Tout au long de cette thèse, nous avons étudié des problèmes d'algèbre linéaire de petite dimension (typiquement de 2x2 à 5x5) utilisés au sein de… (more)

Subjects/Keywords: SIMD; Petites matrices; Kalman; Cholesky; Génération de code; Multithread; SIMD; Small matrices; Kalman; Cholesky; Code generation; Multithread; 512.5; 003.75

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lemaitre, F. (2019). Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction. (Doctoral Dissertation). Sorbonne université. Retrieved from http://www.theses.fr/2019SORUS221

Chicago Manual of Style (16th Edition):

Lemaitre, Florian. “Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction.” 2019. Doctoral Dissertation, Sorbonne université. Accessed March 04, 2021. http://www.theses.fr/2019SORUS221.

MLA Handbook (7th Edition):

Lemaitre, Florian. “Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction.” 2019. Web. 04 Mar 2021.

Vancouver:

Lemaitre F. Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction. [Internet] [Doctoral dissertation]. Sorbonne université; 2019. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2019SORUS221.

Council of Science Editors:

Lemaitre F. Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb : High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction. [Doctoral Dissertation]. Sorbonne université; 2019. Available from: http://www.theses.fr/2019SORUS221


Brno University of Technology

29. Fuksa, Tomáš. Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library.

Degree: 2018, Brno University of Technology

 This work deals with parallel computing on modern processors - multi-core CPU and GPU. The goal is to learn about computing on this devices suitable… (more)

Subjects/Keywords: Grafický procesor; GPGPU; Nvidia; CUDA; Paralelismus; OpenCL; Intel IPP; SIMD; Graphic processor; GPGPU; Nvidia; CUDA; Paralelism; OpenCL; Intel IPP; SIMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fuksa, T. (2018). Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/8264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fuksa, Tomáš. “Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library.” 2018. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/8264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fuksa, Tomáš. “Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library.” 2018. Web. 04 Mar 2021.

Vancouver:

Fuksa T. Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/8264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fuksa T. Paralelizace výpočtů pro zpracování obrazu: Paralelized image processing library. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/8264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

30. Šlenker, Samuel. Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization.

Degree: 2019, Brno University of Technology

 The aim of this thesis was to study and subsequently process the differences between the older instruction sets and newer instruction sets, to specify the… (more)

Subjects/Keywords: SIMD; SSE; AVX; FMA; vektorové spracovanie dát; Intel; AMD; SIMD; SSE; AVX; FMA; vector data processing; Intel; AMD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Šlenker, S. (2019). Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/41353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Šlenker, Samuel. “Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/41353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Šlenker, Samuel. “Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization.” 2019. Web. 04 Mar 2021.

Vancouver:

Šlenker S. Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/41353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šlenker S. Výpočetní jednotky procesorů poslední generace a jejich využití: Processing units of last generation processors and their utilization. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/41353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] [6]

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