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You searched for subject:(SAR ADC). Showing records 1 – 30 of 57 total matches.

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University of Texas – Austin

1. Gulati, Paridhi. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.

Degree: MSin Engineering, Electrical and Computer Engineering, 2016, University of Texas – Austin

 A pipelined ADC is generally used for high speeds and high resolutions in applications where latency is not a major concern. This project involves the… (more)

Subjects/Keywords: Pipelined ADC; SAR ADC

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APA (6th Edition):

Gulati, P. (2016). A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65964

Chicago Manual of Style (16th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Masters Thesis, University of Texas – Austin. Accessed September 15, 2019. http://hdl.handle.net/2152/65964.

MLA Handbook (7th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Web. 15 Sep 2019.

Vancouver:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Internet] [Masters thesis]. University of Texas – Austin; 2016. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2152/65964.

Council of Science Editors:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Masters Thesis]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/65964

2. Hallström, Claes. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  In this master’s thesis a model of a digitally compensated N-bit C-xC sar adc was developed.The architecture uses charge redistribution in a C-xC capacitor… (more)

Subjects/Keywords: adc; sar; digital calibration

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APA (6th Edition):

Hallström, C. (2013). Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hallström, Claes. “Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC.” 2013. Thesis, Linköping UniversityLinköping University. Accessed September 15, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hallström, Claes. “Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC.” 2013. Web. 15 Sep 2019.

Vancouver:

Hallström C. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2019 Sep 15]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hallström C. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

3. Hu, W. A 9-bit 33MHz Hybrid SAR Single-slope ADC :.

Degree: 2015, Delft University of Technology

 In this work a 9-bit, 33MHz hybrid SAR single-slope ADC for element-level digitization in 2D ultrasound transducer arrays is presented. This hybrid architecture consists of… (more)

Subjects/Keywords: ADC; Hybrid SAR single-slope

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APA (6th Edition):

Hu, W. (2015). A 9-bit 33MHz Hybrid SAR Single-slope ADC :. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842

Chicago Manual of Style (16th Edition):

Hu, W. “A 9-bit 33MHz Hybrid SAR Single-slope ADC :.” 2015. Masters Thesis, Delft University of Technology. Accessed September 15, 2019. http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842.

MLA Handbook (7th Edition):

Hu, W. “A 9-bit 33MHz Hybrid SAR Single-slope ADC :.” 2015. Web. 15 Sep 2019.

Vancouver:

Hu W. A 9-bit 33MHz Hybrid SAR Single-slope ADC :. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2019 Sep 15]. Available from: http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842.

Council of Science Editors:

Hu W. A 9-bit 33MHz Hybrid SAR Single-slope ADC :. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842


University of Texas – Austin

4. Varier, Vivek. Built-in-self-test and foreground calibration of SAR ADCs.

Degree: MSin Engineering, Electrical and Computer Engineering, 2018, University of Texas – Austin

 This thesis explores the scope of ‘Built-in-Self-Test’(BIST) schemes to reduce the time cost complexity associated with the production tests for static linearity errors in Successive… (more)

Subjects/Keywords: SAR ADC; Calibration; BIST; SEIR

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APA (6th Edition):

Varier, V. (2018). Built-in-self-test and foreground calibration of SAR ADCs. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/64115

Chicago Manual of Style (16th Edition):

Varier, Vivek. “Built-in-self-test and foreground calibration of SAR ADCs.” 2018. Masters Thesis, University of Texas – Austin. Accessed September 15, 2019. http://hdl.handle.net/2152/64115.

MLA Handbook (7th Edition):

Varier, Vivek. “Built-in-self-test and foreground calibration of SAR ADCs.” 2018. Web. 15 Sep 2019.

Vancouver:

Varier V. Built-in-self-test and foreground calibration of SAR ADCs. [Internet] [Masters thesis]. University of Texas – Austin; 2018. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2152/64115.

Council of Science Editors:

Varier V. Built-in-self-test and foreground calibration of SAR ADCs. [Masters Thesis]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/64115


Oregon State University

5. Guerber, Jon. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and… (more)

Subjects/Keywords: SAR ADC; Analog-to-digital converters

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APA (6th Edition):

Guerber, J. (2012). Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/36019

Chicago Manual of Style (16th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed September 15, 2019. http://hdl.handle.net/1957/36019.

MLA Handbook (7th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Web. 15 Sep 2019.

Vancouver:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/1957/36019.

Council of Science Editors:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/36019


University of Minnesota

6. Palani, Rakesh Kumar. Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages.

Degree: PhD, Electrical Engineering, 2015, University of Minnesota

 Rapid advances in the field of integrated circuit design has been advantageous from the point of view of cost and miniaturization. Although technology scaling is… (more)

Subjects/Keywords: Amplifiers; Biasing; filters; Inverters; PVT; SAR ADC

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APA (6th Edition):

Palani, R. K. (2015). Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/190512

Chicago Manual of Style (16th Edition):

Palani, Rakesh Kumar. “Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages.” 2015. Doctoral Dissertation, University of Minnesota. Accessed September 15, 2019. http://hdl.handle.net/11299/190512.

MLA Handbook (7th Edition):

Palani, Rakesh Kumar. “Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages.” 2015. Web. 15 Sep 2019.

Vancouver:

Palani RK. Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages. [Internet] [Doctoral dissertation]. University of Minnesota; 2015. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/11299/190512.

Council of Science Editors:

Palani RK. Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages. [Doctoral Dissertation]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/190512


University of Texas – Austin

7. -3568-5180. Direct sampling receivers for broadband communications.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 Today everything tends to be connected in the Internet of Things (IoT) universe, where a broad variety of communication standards and technologies are used for… (more)

Subjects/Keywords: RFPGA; RF front end; ADC; SAR

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APA (6th Edition):

-3568-5180. (2019). Direct sampling receivers for broadband communications. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2178

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-3568-5180. “Direct sampling receivers for broadband communications.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed September 15, 2019. http://dx.doi.org/10.26153/tsw/2178.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-3568-5180. “Direct sampling receivers for broadband communications.” 2019. Web. 15 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-3568-5180. Direct sampling receivers for broadband communications. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2019 Sep 15]. Available from: http://dx.doi.org/10.26153/tsw/2178.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-3568-5180. Direct sampling receivers for broadband communications. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/2178

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


NSYSU

8. Chen, Bang-Cyuan. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 A high speed and low power Pipelined-SAR ADC is proposed in this thesis. The Flash ADC which is often found in traditional Pipelined ADC is… (more)

Subjects/Keywords: SAR; ADC; Low Power; Pipelined-SAR ADC; Pipelined; Analog-to-Digital Converter

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APA (6th Edition):

Chen, B. (2013). A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Bang-Cyuan. “A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.” 2013. Thesis, NSYSU. Accessed September 15, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Bang-Cyuan. “A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.” 2013. Web. 15 Sep 2019.

Vancouver:

Chen B. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Sep 15]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen B. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

9. Hedayati, Raheleh. A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology.

Degree: Electronic Devices, 2011, Linköping University

  In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand… (more)

Subjects/Keywords: SAR ADC; SAR Logic; Dynamic Comparator; Low Power

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APA (6th Edition):

Hedayati, R. (2011). A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hedayati, Raheleh. “A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology.” 2011. Thesis, Linköping University. Accessed September 15, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hedayati, Raheleh. “A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology.” 2011. Web. 15 Sep 2019.

Vancouver:

Hedayati R. A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology. [Internet] [Thesis]. Linköping University; 2011. [cited 2019 Sep 15]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hedayati R. A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

10. -4604-3482. Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 This thesis focuses on low power and high speed design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale CMOS technologies. SAR ADCs’… (more)

Subjects/Keywords: SAR ADC; DAC; Radix-3 SAR; Radix-2 SAR; Figure of Merit (FOM)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

-4604-3482. (2018). Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63366

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-4604-3482. “Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed September 15, 2019. http://hdl.handle.net/2152/63366.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-4604-3482. “Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies.” 2018. Web. 15 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-4604-3482. Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2152/63366.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-4604-3482. Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/63366

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Georgia Tech

11. Tirunelveli Kanthi, Saravanan. Analysis and; design of successive approximation ADC and 3.5 GHz RF transmitter in 90nm CMOS.

Degree: MS, Electrical and Computer Engineering, 2010, Georgia Tech

 In this work, a 3.5 GHz RF Transmitter and Successive Approximation ADC design has been presented. The transmitter serves as an intermediate block which translates… (more)

Subjects/Keywords: 90nm; Mixer; ADC; SAR ADC; Metal oxide semiconductors, Complementary; Microelectronics packaging; Feedback control systems

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APA (6th Edition):

Tirunelveli Kanthi, S. (2010). Analysis and; design of successive approximation ADC and 3.5 GHz RF transmitter in 90nm CMOS. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/33884

Chicago Manual of Style (16th Edition):

Tirunelveli Kanthi, Saravanan. “Analysis and; design of successive approximation ADC and 3.5 GHz RF transmitter in 90nm CMOS.” 2010. Masters Thesis, Georgia Tech. Accessed September 15, 2019. http://hdl.handle.net/1853/33884.

MLA Handbook (7th Edition):

Tirunelveli Kanthi, Saravanan. “Analysis and; design of successive approximation ADC and 3.5 GHz RF transmitter in 90nm CMOS.” 2010. Web. 15 Sep 2019.

Vancouver:

Tirunelveli Kanthi S. Analysis and; design of successive approximation ADC and 3.5 GHz RF transmitter in 90nm CMOS. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/1853/33884.

Council of Science Editors:

Tirunelveli Kanthi S. Analysis and; design of successive approximation ADC and 3.5 GHz RF transmitter in 90nm CMOS. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/33884


University of Texas – Austin

12. Chen, Long. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.

Degree: PhD, Electrical and Computer engineering, 2016, University of Texas – Austin

 This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two… (more)

Subjects/Keywords: Analog-to-digital converter; SAR ADC; ADC; Low power; Comparator; High speed

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APA (6th Edition):

Chen, L. (2016). Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/40286

Chicago Manual of Style (16th Edition):

Chen, Long. “Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.” 2016. Doctoral Dissertation, University of Texas – Austin. Accessed September 15, 2019. http://hdl.handle.net/2152/40286.

MLA Handbook (7th Edition):

Chen, Long. “Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.” 2016. Web. 15 Sep 2019.

Vancouver:

Chen L. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2016. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2152/40286.

Council of Science Editors:

Chen L. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. [Doctoral Dissertation]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/40286


NSYSU

13. Chung, Meng-hsun. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt… (more)

Subjects/Keywords: Analog-to-Digital Converter; ADC; Binary-Search ADC; Successive Approximation; SAR ADC; Time-Interleaved; Non-overlapping circuit

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APA (6th Edition):

Chung, M. (2015). A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed September 15, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 15 Sep 2019.

Vancouver:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Sep 15]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Hsieh, Yi-Jie. A Process and Temperature Compensation Oscillator and A Successive-Approximation Register Analog to Digital Converter for Biomedical Systems.

Degree: Master, Electrical Engineering, 2013, NSYSU

 This thesis consists of two topics, i.e., a process and temperature compensation oscillator and a successive-approximation register analog to digital converter, which are mainly designed… (more)

Subjects/Keywords: temperature compensation; oscillator; charge sharing architecture; SAR ADC

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APA (6th Edition):

Hsieh, Y. (2013). A Process and Temperature Compensation Oscillator and A Successive-Approximation Register Analog to Digital Converter for Biomedical Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0131113-134235

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsieh, Yi-Jie. “A Process and Temperature Compensation Oscillator and A Successive-Approximation Register Analog to Digital Converter for Biomedical Systems.” 2013. Thesis, NSYSU. Accessed September 15, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0131113-134235.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsieh, Yi-Jie. “A Process and Temperature Compensation Oscillator and A Successive-Approximation Register Analog to Digital Converter for Biomedical Systems.” 2013. Web. 15 Sep 2019.

Vancouver:

Hsieh Y. A Process and Temperature Compensation Oscillator and A Successive-Approximation Register Analog to Digital Converter for Biomedical Systems. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Sep 15]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0131113-134235.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh Y. A Process and Temperature Compensation Oscillator and A Successive-Approximation Register Analog to Digital Converter for Biomedical Systems. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0131113-134235

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Akron

15. ZHANG, GUANGLEI, ZHANG. SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC.

Degree: MSin Engineering, Electrical Engineering, 2018, University of Akron

 This work presents a successive-approximation-register (SAR) analog-to-digital converter (ADC) using a single-capacitor-pulse-width-to-analog converter-based digital-to-analog (DAC). In the proposed SAR ADC, the single-capacitor DAC is realized… (more)

Subjects/Keywords: Electrical Engineering; SAR ADC, Low power, small area

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APA (6th Edition):

ZHANG, GUANGLEI, Z. (2018). SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1516622725471522

Chicago Manual of Style (16th Edition):

ZHANG, GUANGLEI, ZHANG. “SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC.” 2018. Masters Thesis, University of Akron. Accessed September 15, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=akron1516622725471522.

MLA Handbook (7th Edition):

ZHANG, GUANGLEI, ZHANG. “SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC.” 2018. Web. 15 Sep 2019.

Vancouver:

ZHANG, GUANGLEI Z. SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC. [Internet] [Masters thesis]. University of Akron; 2018. [cited 2019 Sep 15]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1516622725471522.

Council of Science Editors:

ZHANG, GUANGLEI Z. SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC. [Masters Thesis]. University of Akron; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1516622725471522


UCLA

16. Mathew, Joseph Palackal. SAR ADC architecture using time domain processing.

Degree: Electrical Engineering, 2012, UCLA

 Successive approximation (SAR) type Analog to Digital Conveter (ADC) is a Nyquist Rate ADC which has acquired tremendous pupularity recently due to its digital nature… (more)

Subjects/Keywords: Electrical engineering; ADC; Calibration; SAR; Self Healing; TDC

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APA (6th Edition):

Mathew, J. P. (2012). SAR ADC architecture using time domain processing. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/0hp7g77c

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mathew, Joseph Palackal. “SAR ADC architecture using time domain processing.” 2012. Thesis, UCLA. Accessed September 15, 2019. http://www.escholarship.org/uc/item/0hp7g77c.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mathew, Joseph Palackal. “SAR ADC architecture using time domain processing.” 2012. Web. 15 Sep 2019.

Vancouver:

Mathew JP. SAR ADC architecture using time domain processing. [Internet] [Thesis]. UCLA; 2012. [cited 2019 Sep 15]. Available from: http://www.escholarship.org/uc/item/0hp7g77c.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mathew JP. SAR ADC architecture using time domain processing. [Thesis]. UCLA; 2012. Available from: http://www.escholarship.org/uc/item/0hp7g77c

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

17. Mirhaj, Seyed Arash. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.

Degree: Electrical Engineering, 2014, UCLA

 In recent years, Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) has received significant attention due to its well-known energy and hardware efficiency, which also benefits even… (more)

Subjects/Keywords: Electrical engineering; Analog to Digital Converter; Calibration; Piecewise Linear; SAR-ADC

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APA (6th Edition):

Mirhaj, S. A. (2014). Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9jx6c9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mirhaj, Seyed Arash. “Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.” 2014. Thesis, UCLA. Accessed September 15, 2019. http://www.escholarship.org/uc/item/9jx6c9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mirhaj, Seyed Arash. “Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.” 2014. Web. 15 Sep 2019.

Vancouver:

Mirhaj SA. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. [Internet] [Thesis]. UCLA; 2014. [cited 2019 Sep 15]. Available from: http://www.escholarship.org/uc/item/9jx6c9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mirhaj SA. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/9jx6c9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

18. Yang, Jing. Time Domain Interference Cancellation for Cognitive Radios and Future Wireless Systems.

Degree: Electrical Engineering & Computer Sciences, 2010, University of California – Berkeley

 The discrepancy between perceived spectrum shortage and the actual availability by measurements motivates the use of cognitive radio concepts. In this approach the radio locates… (more)

Subjects/Keywords: Electrical engineering; Interference cancellation; metastability; SAR ADC; time domain; wideband

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APA (6th Edition):

Yang, J. (2010). Time Domain Interference Cancellation for Cognitive Radios and Future Wireless Systems. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/9w35b0j1

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Jing. “Time Domain Interference Cancellation for Cognitive Radios and Future Wireless Systems.” 2010. Thesis, University of California – Berkeley. Accessed September 15, 2019. http://www.escholarship.org/uc/item/9w35b0j1.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Jing. “Time Domain Interference Cancellation for Cognitive Radios and Future Wireless Systems.” 2010. Web. 15 Sep 2019.

Vancouver:

Yang J. Time Domain Interference Cancellation for Cognitive Radios and Future Wireless Systems. [Internet] [Thesis]. University of California – Berkeley; 2010. [cited 2019 Sep 15]. Available from: http://www.escholarship.org/uc/item/9w35b0j1.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang J. Time Domain Interference Cancellation for Cognitive Radios and Future Wireless Systems. [Thesis]. University of California – Berkeley; 2010. Available from: http://www.escholarship.org/uc/item/9w35b0j1

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

19. Elumalai, I. A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC:.

Degree: 2013, Delft University of Technology

 Voltage reference buffers have always been the most power-hungry blocks in switched-capacitor SAR ADCs. High frequency dynamic loading of the buffer by the capacitive DAC… (more)

Subjects/Keywords: ADC; SAR; charge redistribution; reference buffer; high speed; low power

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APA (6th Edition):

Elumalai, I. (2013). A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:8b94e22b-cd51-407c-af86-9c2389f20e4c

Chicago Manual of Style (16th Edition):

Elumalai, I. “A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC:.” 2013. Masters Thesis, Delft University of Technology. Accessed September 15, 2019. http://resolver.tudelft.nl/uuid:8b94e22b-cd51-407c-af86-9c2389f20e4c.

MLA Handbook (7th Edition):

Elumalai, I. “A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC:.” 2013. Web. 15 Sep 2019.

Vancouver:

Elumalai I. A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC:. [Internet] [Masters thesis]. Delft University of Technology; 2013. [cited 2019 Sep 15]. Available from: http://resolver.tudelft.nl/uuid:8b94e22b-cd51-407c-af86-9c2389f20e4c.

Council of Science Editors:

Elumalai I. A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC:. [Masters Thesis]. Delft University of Technology; 2013. Available from: http://resolver.tudelft.nl/uuid:8b94e22b-cd51-407c-af86-9c2389f20e4c

20. Zhang, R. A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC:.

Degree: 2015, Delft University of Technology

 This thesis presents a 1-Mega pixels high-dynamic range and UV sensitive image sensor in 0.18 µm technology with 14-bit interleaved 64Ms/s SAR ADC. It can… (more)

Subjects/Keywords: UV sensitive; interleaved SAR ADC; comparator; offset calibration; high dynamic range

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APA (6th Edition):

Zhang, R. (2015). A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846

Chicago Manual of Style (16th Edition):

Zhang, R. “A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC:.” 2015. Masters Thesis, Delft University of Technology. Accessed September 15, 2019. http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846.

MLA Handbook (7th Edition):

Zhang, R. “A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC:.” 2015. Web. 15 Sep 2019.

Vancouver:

Zhang R. A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC:. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2019 Sep 15]. Available from: http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846.

Council of Science Editors:

Zhang R. A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC:. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846


University of Toronto

21. Wang, Luke. Timing Skew Calibration for Time Interleaved Analog to Digital Converters.

Degree: 2014, University of Toronto

This thesis presents a novel background timing skew calibration method used to improve the dynamic performance of time-interleaved analog-to-digital converters. A prototype 10GS/s 8bit 80-way… (more)

Subjects/Keywords: ADC; Calibration; SAR; Time-Interleaved; Timing Skew; 0544

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APA (6th Edition):

Wang, L. (2014). Timing Skew Calibration for Time Interleaved Analog to Digital Converters. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/67846

Chicago Manual of Style (16th Edition):

Wang, Luke. “Timing Skew Calibration for Time Interleaved Analog to Digital Converters.” 2014. Masters Thesis, University of Toronto. Accessed September 15, 2019. http://hdl.handle.net/1807/67846.

MLA Handbook (7th Edition):

Wang, Luke. “Timing Skew Calibration for Time Interleaved Analog to Digital Converters.” 2014. Web. 15 Sep 2019.

Vancouver:

Wang L. Timing Skew Calibration for Time Interleaved Analog to Digital Converters. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/1807/67846.

Council of Science Editors:

Wang L. Timing Skew Calibration for Time Interleaved Analog to Digital Converters. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/67846


University of Minnesota

22. Hu, Chia-Lin. A low power biosensor for medical applications.

Degree: PhD, Electrical Engineering, 2014, University of Minnesota

 This research presents on a CMOS sensor, which includes a chopper stabilized front-end amplifier with DC suppressed feedback and a 12-bit successive approximation register (SAR)… (more)

Subjects/Keywords: Chopper stabilization; Flicker noise; SAR ADC; Electrical engineering

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APA (6th Edition):

Hu, C. (2014). A low power biosensor for medical applications. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/171174

Chicago Manual of Style (16th Edition):

Hu, Chia-Lin. “A low power biosensor for medical applications.” 2014. Doctoral Dissertation, University of Minnesota. Accessed September 15, 2019. http://hdl.handle.net/11299/171174.

MLA Handbook (7th Edition):

Hu, Chia-Lin. “A low power biosensor for medical applications.” 2014. Web. 15 Sep 2019.

Vancouver:

Hu C. A low power biosensor for medical applications. [Internet] [Doctoral dissertation]. University of Minnesota; 2014. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/11299/171174.

Council of Science Editors:

Hu C. A low power biosensor for medical applications. [Doctoral Dissertation]. University of Minnesota; 2014. Available from: http://hdl.handle.net/11299/171174


San Jose State University

23. Mazidi, Ehsan. Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices.

Degree: MS, Electrical Engineering, 2016, San Jose State University

  This thesis project involves the design and analysis of an 8-bit Successive Approximation Register (SAR) Analog to Digital Convertor (ADC), designed for low- power… (more)

Subjects/Keywords: ADC; bio-implant; bio-medical; low-power; SAR

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APA (6th Edition):

Mazidi, E. (2016). Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices. (Masters Thesis). San Jose State University. Retrieved from https://doi.org/10.31979/etd.tq8n-42kd ; https://scholarworks.sjsu.edu/etd_theses/4767

Chicago Manual of Style (16th Edition):

Mazidi, Ehsan. “Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices.” 2016. Masters Thesis, San Jose State University. Accessed September 15, 2019. https://doi.org/10.31979/etd.tq8n-42kd ; https://scholarworks.sjsu.edu/etd_theses/4767.

MLA Handbook (7th Edition):

Mazidi, Ehsan. “Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices.” 2016. Web. 15 Sep 2019.

Vancouver:

Mazidi E. Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices. [Internet] [Masters thesis]. San Jose State University; 2016. [cited 2019 Sep 15]. Available from: https://doi.org/10.31979/etd.tq8n-42kd ; https://scholarworks.sjsu.edu/etd_theses/4767.

Council of Science Editors:

Mazidi E. Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices. [Masters Thesis]. San Jose State University; 2016. Available from: https://doi.org/10.31979/etd.tq8n-42kd ; https://scholarworks.sjsu.edu/etd_theses/4767


Wright State University

24. Kommareddy, Jeevani. 10-bit C2C DAC Design in 65nm CMOS Technology.

Degree: MSEE, Electrical Engineering, 2019, Wright State University

 Many wired and wireless communication systems require high-speed and high-performance data converters. These data converters act as bridge between digital signal processing blocks and power… (more)

Subjects/Keywords: Electrical Engineering; 65nmCMOS; C2C DAC; SAR ADC logic

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APA (6th Edition):

Kommareddy, J. (2019). 10-bit C2C DAC Design in 65nm CMOS Technology. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1565538915029852

Chicago Manual of Style (16th Edition):

Kommareddy, Jeevani. “10-bit C2C DAC Design in 65nm CMOS Technology.” 2019. Masters Thesis, Wright State University. Accessed September 15, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1565538915029852.

MLA Handbook (7th Edition):

Kommareddy, Jeevani. “10-bit C2C DAC Design in 65nm CMOS Technology.” 2019. Web. 15 Sep 2019.

Vancouver:

Kommareddy J. 10-bit C2C DAC Design in 65nm CMOS Technology. [Internet] [Masters thesis]. Wright State University; 2019. [cited 2019 Sep 15]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1565538915029852.

Council of Science Editors:

Kommareddy J. 10-bit C2C DAC Design in 65nm CMOS Technology. [Masters Thesis]. Wright State University; 2019. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1565538915029852


University of Texas – Austin

25. Fontaine, Robert Alexander. Investigation of 10-bit SAR ADC using flip-flip bypass circuit.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by… (more)

Subjects/Keywords: SAR; Successive Approximation Register; ADC; Flip-flop bypass

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APA (6th Edition):

Fontaine, R. A. (2013). Investigation of 10-bit SAR ADC using flip-flip bypass circuit. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/24011

Chicago Manual of Style (16th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Masters Thesis, University of Texas – Austin. Accessed September 15, 2019. http://hdl.handle.net/2152/24011.

MLA Handbook (7th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Web. 15 Sep 2019.

Vancouver:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2152/24011.

Council of Science Editors:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/24011

26. Kardonik, Olga. A study of SAR ADC and implementation of 10-bit asynchronous design.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not… (more)

Subjects/Keywords: SAR ADC; Asynchronous

…60 ix List of Figures Figure 1.1: SAR ADC architecture… …2 Figure 1.2: 4-bit SAR ADC operation… …4 Figure 1.4: Single-ended capacitive DAC of 3-bit SAR ADC, Vcm = 0. .............5 Figure… …1.5: Differential capacitive DAC of 3-bit SAR ADC, sampling phase. ....8 Figure 1.6: Bit3… …34 Figure 5.2: Bottom plate switch network for asynchronous SAR ADC. ............35 Figure… 

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APA (6th Edition):

Kardonik, O. (2013). A study of SAR ADC and implementation of 10-bit asynchronous design. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/22693

Chicago Manual of Style (16th Edition):

Kardonik, Olga. “A study of SAR ADC and implementation of 10-bit asynchronous design.” 2013. Masters Thesis, University of Texas – Austin. Accessed September 15, 2019. http://hdl.handle.net/2152/22693.

MLA Handbook (7th Edition):

Kardonik, Olga. “A study of SAR ADC and implementation of 10-bit asynchronous design.” 2013. Web. 15 Sep 2019.

Vancouver:

Kardonik O. A study of SAR ADC and implementation of 10-bit asynchronous design. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2152/22693.

Council of Science Editors:

Kardonik O. A study of SAR ADC and implementation of 10-bit asynchronous design. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/22693

27. Ma, Ji, active 2013. A study of capacitor array calibration for a successive approximation analog-to-digital converter.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 Analog-to-digital converters (ADCs) are driven by rapid development of mobile communication systems to have higher speed, higher resolution and lower power consumption. Among multiple ADC(more)

Subjects/Keywords: SAR ADC; Calibration; Capacitors

…monotonic switching in a SAR ADC to gain one extra bit, and switches a dummy capacitor between the… …12 Figure 3.1 Binary searching path for a single-ended SAR ADC [4]… …18 Figure 3.5 Binary searching path for a fully differential SAR ADC… …in a binary search manner, the core analog blocks in a SAR ADC are a comparator and a… …normal operation of a SAR ADC, the missing codes widths are extracted by detecting metastable… 

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APA (6th Edition):

Ma, Ji, a. 2. (2013). A study of capacitor array calibration for a successive approximation analog-to-digital converter. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/26338

Chicago Manual of Style (16th Edition):

Ma, Ji, active 2013. “A study of capacitor array calibration for a successive approximation analog-to-digital converter.” 2013. Masters Thesis, University of Texas – Austin. Accessed September 15, 2019. http://hdl.handle.net/2152/26338.

MLA Handbook (7th Edition):

Ma, Ji, active 2013. “A study of capacitor array calibration for a successive approximation analog-to-digital converter.” 2013. Web. 15 Sep 2019.

Vancouver:

Ma, Ji a2. A study of capacitor array calibration for a successive approximation analog-to-digital converter. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2152/26338.

Council of Science Editors:

Ma, Ji a2. A study of capacitor array calibration for a successive approximation analog-to-digital converter. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/26338


University of Texas – Austin

28. Rajendran, Kaarthik. Application specific DAC and ADC for a bio-impedance measurement circuit.

Degree: MSin Engineering, Electrical and Computer Engineering, 2017, University of Texas – Austin

 A transistor level implementation of a 3 bit digital harmonic canceling (DHC) digital to analog converter (DAC), and a 10 bit successive approximation register (SAR)… (more)

Subjects/Keywords: ADC; DAC; Bio-impedance; Comparator; Switch; Harmonic cancellation; Digital; SAR

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APA (6th Edition):

Rajendran, K. (2017). Application specific DAC and ADC for a bio-impedance measurement circuit. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/61590

Chicago Manual of Style (16th Edition):

Rajendran, Kaarthik. “Application specific DAC and ADC for a bio-impedance measurement circuit.” 2017. Masters Thesis, University of Texas – Austin. Accessed September 15, 2019. http://hdl.handle.net/2152/61590.

MLA Handbook (7th Edition):

Rajendran, Kaarthik. “Application specific DAC and ADC for a bio-impedance measurement circuit.” 2017. Web. 15 Sep 2019.

Vancouver:

Rajendran K. Application specific DAC and ADC for a bio-impedance measurement circuit. [Internet] [Masters thesis]. University of Texas – Austin; 2017. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2152/61590.

Council of Science Editors:

Rajendran K. Application specific DAC and ADC for a bio-impedance measurement circuit. [Masters Thesis]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/61590


Université de Grenoble

29. Regis, Guillaume. Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning.

Degree: Docteur es, Physique Expérimentale et Instrumentation, 2011, Université de Grenoble

Le domaine de l'instrumentation des capteurs est en constante évolution. Ce travail propose la conception des éléments clefs qui constituent les chaines d'instrumentations de capteurs… (more)

Subjects/Keywords: Convertisseur Analogique/Numérique; CAN SAR; CAN Sigma Delta; Chaine d’amplification analogique; Analog-to-Digital Converter; ADC SAR; ADC Sigma Delta; Analog amplifier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Regis, G. (2011). Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2011GRENA001

Chicago Manual of Style (16th Edition):

Regis, Guillaume. “Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning.” 2011. Doctoral Dissertation, Université de Grenoble. Accessed September 15, 2019. http://www.theses.fr/2011GRENA001.

MLA Handbook (7th Edition):

Regis, Guillaume. “Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning.” 2011. Web. 15 Sep 2019.

Vancouver:

Regis G. Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning. [Internet] [Doctoral dissertation]. Université de Grenoble; 2011. [cited 2019 Sep 15]. Available from: http://www.theses.fr/2011GRENA001.

Council of Science Editors:

Regis G. Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning. [Doctoral Dissertation]. Université de Grenoble; 2011. Available from: http://www.theses.fr/2011GRENA001


NSYSU

30. Chen, Hung-Yen. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 In this thesis, a 10-bit binary search assisted two channel SAR ADC with a two bit per conversion and error tolerance ability operating in 250Ms/s… (more)

Subjects/Keywords: Two bits per conversion; Non-binary; Time-interleaved; Binary search; SAR ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, H. (2017). A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Hung-Yen. “A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.” 2017. Thesis, NSYSU. Accessed September 15, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Hung-Yen. “A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.” 2017. Web. 15 Sep 2019.

Vancouver:

Chen H. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Sep 15]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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