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You searched for subject:(Resource contraints). Showing records 1 – 3 of 3 total matches.

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University of Texas – Austin

1. -4065-8654. Resource-constrained, scalable learning.

Degree: Electrical and Computer Engineering, 2015, University of Texas – Austin

Our unprecedented capacity for data generation and acquisition often reaches the limits of our data storage capabilities. Situations when data are generated faster or at a greater volume than can be stored demand a streaming approach. Memory is an even more valuable resource. Algorithms that use more memory than necessary can pose bottlenecks when processing high-dimensional data and the need for memory-efficient algorithms is especially stressed in the streaming setting. Finally, network along with storage, emerge as the critical bottlenecks in the context of distributed computation. These computational constraints spell out a demand for efficient tools that guarantee a solution in the face of limited resources, even when the data is very noisy or highly incomplete. For the first part of this dissertation, we present our work on streaming, memory-limited Principal Component Analysis (PCA). Therein, we give the first convergence guarantees for an algorithm that solves PCA in the single-pass streaming setting. Then, we discuss the distinct challenges that arise when the received samples are overwhelmingly incomplete and present an algorithm and analysis that deals with this issue. Finally, we give a set of extensive experiment results that showcase the practical merits of our algorithm over the state of the art. The need for heavy network communication arises as the bottleneck when dealing with cluster computation. In that paradigm, a set of worker nodes are connected over the network to produce a cluster with improved computational and storage capacities. This comes with an increased need for communication across the network. In the last part of this work, we consider the problem of PageRank on graph engines. Therein, we make changes to GraphLab, a state-of-the-art platform for distributed graph computation, in a way that leads to a 7x-10x speedup for certain PageRank approximation tasks. Accompanying analysis supports the behaviour we see in our experiments. Advisors/Committee Members: Vishwanath, Sriram (advisor), Caramanis, Constantine (advisor), Dimakis, Alex (committee member), Sanghavi, Sujay (committee member), Ravikumar, Pradeep (committee member).

Subjects/Keywords: Resource contraints; Limited memory; Storage; Network; Principle component analysis; PageRank; Graph engines

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

-4065-8654. (2015). Resource-constrained, scalable learning. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32226

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

-4065-8654. “Resource-constrained, scalable learning.” 2015. Thesis, University of Texas – Austin. Accessed May 22, 2019. http://hdl.handle.net/2152/32226.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

-4065-8654. “Resource-constrained, scalable learning.” 2015. Web. 22 May 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-4065-8654. Resource-constrained, scalable learning. [Internet] [Thesis]. University of Texas – Austin; 2015. [cited 2019 May 22]. Available from: http://hdl.handle.net/2152/32226.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

-4065-8654. Resource-constrained, scalable learning. [Thesis]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32226

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de Catalunya

2. Sánchez Carracedo, Fermín. Loop pipelining with resource and timing constraints.

Degree: Departament d'Arquitectura de Computadors, 1996, Universitat Politècnica de Catalunya

Developing efficient programs for many of the current parallel computers is not easy due to the architectural complexity of those machines. The wide variety of machine organizations often makes it more difficult to port an existing program than to reprogram it completely. Therefore, powerful translators are necessary to generate effective code and free the programmer from concerns about the specific characteristics of the target machine. This work focuses on techniques to be used by an important class of translators, whose objective is to transform sequential programs into equivalent more parallel programs. The transformations are performed at instruction level in order to exploit low level parallelism and increase memory locality. Most of the current applications are programmed in languages which do not allow us to express parallelism between high-level sentences (as Pascal, C or Fortran). Furthermore, a lot of applications written ten or more years ago are still used today, and it is not feasible to rewrite such applications for many reasons (not only technical reasons, but also economic ones). Translators enable programmers to write the application in a familiar sequential programming language, without concerning their selves with the architecture of the target machine. Current compilers for parallel architectures not only translate a program written on a high-level language to the appropriate machine language, but also perform some transformations in the final code in order to execute the program in a more parallel way. The transformations improve the performance in the execution of the program by making use of the knowledge that the compiler has about the machine architecture. The semantics of the program remain intact after any transformation. Experiments show that limiting parallelization to basic blocks not included in loops limits maximum speedup. This is because loops often comprise a large portion of the parallelism available to be exploited in a program. For this reason, a lot of effort has been devoted in the recent years to parallelize loop execution. Several parallel computer architectures and compilation techniques have been proposed to exploit such a parallelism at different granularities. Multiprocessors exploit coarse grained parallelism by distributing entire loop iterations to different processors. Systems oriented to the high-level synthesis (HLS) of VLSI circuits, superscalar processors and very long instruction word (VLIW) processors exploit fine-grained parallelism at instruction level. This work addresses fine-grained parallelization of loops addressed to the HLS of VLSI circuits. Two algorithms are proposed for resource constraints and for timing constraints. An algorithm to reduce the number of registers required to execute a loop in a given architecture is also proposed. Advisors/Committee Members: [email protected] (authoremail), false (authoremailshow), Cortadella, Jordi (Cortadella Fortuny) (director).

Subjects/Keywords: timing contraints; resource constraints; software pipeling; loop pipelining; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sánchez Carracedo, F. (1996). Loop pipelining with resource and timing constraints. (Thesis). Universitat Politècnica de Catalunya. Retrieved from http://hdl.handle.net/10803/5998

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sánchez Carracedo, Fermín. “Loop pipelining with resource and timing constraints.” 1996. Thesis, Universitat Politècnica de Catalunya. Accessed May 22, 2019. http://hdl.handle.net/10803/5998.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sánchez Carracedo, Fermín. “Loop pipelining with resource and timing constraints.” 1996. Web. 22 May 2019.

Vancouver:

Sánchez Carracedo F. Loop pipelining with resource and timing constraints. [Internet] [Thesis]. Universitat Politècnica de Catalunya; 1996. [cited 2019 May 22]. Available from: http://hdl.handle.net/10803/5998.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sánchez Carracedo F. Loop pipelining with resource and timing constraints. [Thesis]. Universitat Politècnica de Catalunya; 1996. Available from: http://hdl.handle.net/10803/5998

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Toulouse II – Le Mirail

3. Ziani, Adel. Modeling of Secure Dependable (S&D) applications based on patterns for Resource-Constrained Embedded Systems (RCES) : Modélisation des applications "sécurisées et sûres" (S&D) à base de patrons pour des systèmes embarqués contraints en ressources (RCES).

Degree: Docteur es, Informatique, 2013, Université Toulouse II – Le Mirail

La complexité croissante du matériel et du logiciel dans le développement des applications pour les systèmes embarqués induit de nouveaux besoins et de nouvelles contraintes en termes de fonctionnalités, de capacité de stockage, de calcul et de consommation d'énergie. Cela entraîne des difficultés accrues pour les concepteurs alors que les contraintes commerciales liées aux développement et à la production de ces systèmes demeurent impondérables. Un autre défi qui s'ajoute à cette complexité est le développement des applications avec de fortes exigences de sécurité et de fiabilité (S&D) pour des systèmes embarqués contraints en ressources (RCES). De ce fait, nous recommandons d'aborder cette complexité via la réutilisation d'un ensemble d'artefacts de modélisation dédiés. Le "patron" constitue l'artefact de base pour représenter des solutions S&D, à spécifier par les experts de ces aspects et à réutiliser par les ingénieurs pour résoudre les problèmes de l'ingénierie système/logicielle du domaine confrontée à ces aspects. Dans le cadre de cette thèse, nous proposons une approche d'ingénierie à base de modèles pour la spécification, le packaging et la réutilisation de ces artefacts pour modéliser et analyser ces systèmes. Le fondement de notre approche est un ensemble de langages de modélisation et des règles de transformation couplés à un référentiel orienté modèles et de moteurs de recherche et d'instantiation. Ces langages de modélisation permettent de spécifier les patrons, les systèmes de patrons et un ensemble de modèles de propriétés et de ressources. Ces modèles permettent de gouverner l'utilisation des patrons, leur organisation et leur analyse pour d'éventuel réutilisation. Pour les transformations, nous avons conçu un ensemble de règles pour l'analyse de la satisfiabilité des architectures logicielles à base de patrons S&D pour des plateformes matérielles à base de modèles de ressources. Pour le développement du référentiel, nous proposons un processus de spécification et de génération basé sur les langages de modélisation décrits au préalable. Les moteurs permettent de retrouver pour ensuite instantier ces artefacts vers des environnements de développement spécifiques.Dans le cadre de l'assistance pour le développement des applications S&D pour les RCES, nous avons implémenté une suite d'outils, basés sur Eclipse EMF/QVTO, pour supporter la spécification de ces artefacts et l'analyse des applications S&D autour d'un référentiel. Afin de faciliter l'utilisation de l'approche proposée, nous préconisons un ensemble de méthodes pour favoriser l'utilisation de cette suite d'outils tout au long du processus de développement. En outre, nous avons abordé la construction par génération automatique de référentiels orientés modèles, basée sur Eclipse EMF/QVTO et la plateforme Eclispe CDO, accompagné d'un ensemble d'outils pour le peuplement, l'accès et la gestion de ce référentiel. Les problèmes étudiés dans ce travail ont été identifiés dans le contexte du projet européen FP7 TERESA. Les solutions proposées ont… Advisors/Committee Members: Bruel, Jean-Michel (thesis director), Hamid, Brahim (thesis director).

Subjects/Keywords: Systèmes embarqués contraints en ressource; Ingénierie dirigée par les modèles; Référentiel à base de modèles; Patrons de fiabilité et sécurité; Suite d'outils IDM; Resource constrained embedded systems; Model driven engineering; Model based repository; Security and dependability patterns; MDE tool-chain

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ziani, A. (2013). Modeling of Secure Dependable (S&D) applications based on patterns for Resource-Constrained Embedded Systems (RCES) : Modélisation des applications "sécurisées et sûres" (S&D) à base de patrons pour des systèmes embarqués contraints en ressources (RCES). (Doctoral Dissertation). Université Toulouse II – Le Mirail. Retrieved from http://www.theses.fr/2013TOU20074

Chicago Manual of Style (16th Edition):

Ziani, Adel. “Modeling of Secure Dependable (S&D) applications based on patterns for Resource-Constrained Embedded Systems (RCES) : Modélisation des applications "sécurisées et sûres" (S&D) à base de patrons pour des systèmes embarqués contraints en ressources (RCES).” 2013. Doctoral Dissertation, Université Toulouse II – Le Mirail. Accessed May 22, 2019. http://www.theses.fr/2013TOU20074.

MLA Handbook (7th Edition):

Ziani, Adel. “Modeling of Secure Dependable (S&D) applications based on patterns for Resource-Constrained Embedded Systems (RCES) : Modélisation des applications "sécurisées et sûres" (S&D) à base de patrons pour des systèmes embarqués contraints en ressources (RCES).” 2013. Web. 22 May 2019.

Vancouver:

Ziani A. Modeling of Secure Dependable (S&D) applications based on patterns for Resource-Constrained Embedded Systems (RCES) : Modélisation des applications "sécurisées et sûres" (S&D) à base de patrons pour des systèmes embarqués contraints en ressources (RCES). [Internet] [Doctoral dissertation]. Université Toulouse II – Le Mirail; 2013. [cited 2019 May 22]. Available from: http://www.theses.fr/2013TOU20074.

Council of Science Editors:

Ziani A. Modeling of Secure Dependable (S&D) applications based on patterns for Resource-Constrained Embedded Systems (RCES) : Modélisation des applications "sécurisées et sûres" (S&D) à base de patrons pour des systèmes embarqués contraints en ressources (RCES). [Doctoral Dissertation]. Université Toulouse II – Le Mirail; 2013. Available from: http://www.theses.fr/2013TOU20074

.