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You searched for subject:(Reconfigurable Computing). Showing records 1 – 30 of 183 total matches.

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NSYSU

1. Yeh, Ta-li. Design of the Software/Hardware Codesign Platform-IRES.

Degree: Master, Electrical Engineering, 2008, NSYSU

 High-performance reconfigurable computing has demonstrated its potential to accelerate demanding computational applications. Thus, the current trend is towards combining the microprocessor with the power of… (more)

Subjects/Keywords: reconfigurable computing; embedded system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yeh, T. (2008). Design of the Software/Hardware Codesign Platform-IRES. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820108-032534

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeh, Ta-li. “Design of the Software/Hardware Codesign Platform-IRES.” 2008. Thesis, NSYSU. Accessed February 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820108-032534.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeh, Ta-li. “Design of the Software/Hardware Codesign Platform-IRES.” 2008. Web. 25 Feb 2020.

Vancouver:

Yeh T. Design of the Software/Hardware Codesign Platform-IRES. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Feb 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820108-032534.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh T. Design of the Software/Hardware Codesign Platform-IRES. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820108-032534

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Nakai, Nobuo. Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Reconfigurable Computing

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APA (6th Edition):

Nakai, N. (n.d.). Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1730

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nakai, Nobuo. “Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed February 25, 2020. http://hdl.handle.net/10061/1730.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nakai, Nobuo. “Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ.” Web. 25 Feb 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Nakai N. Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10061/1730.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Nakai N. Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1730

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Virginia Tech

3. Chandrasekharan, Athira. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or… (more)

Subjects/Keywords: Reconfigurable Computing; Incremental Floorplanning; FPGAs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chandrasekharan, A. (2010). Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34499

Chicago Manual of Style (16th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Masters Thesis, Virginia Tech. Accessed February 25, 2020. http://hdl.handle.net/10919/34499.

MLA Handbook (7th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Web. 25 Feb 2020.

Vancouver:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10919/34499.

Council of Science Editors:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34499


Virginia Tech

4. Raja Gopalan, Sureshwar. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without… (more)

Subjects/Keywords: FPGAs; Reconfigurable Computing; Automatic Floorplanning

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Raja Gopalan, S. (2010). Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34993

Chicago Manual of Style (16th Edition):

Raja Gopalan, Sureshwar. “Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.” 2010. Masters Thesis, Virginia Tech. Accessed February 25, 2020. http://hdl.handle.net/10919/34993.

MLA Handbook (7th Edition):

Raja Gopalan, Sureshwar. “Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.” 2010. Web. 25 Feb 2020.

Vancouver:

Raja Gopalan S. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10919/34993.

Council of Science Editors:

Raja Gopalan S. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34993


University of Toronto

5. Ahmed, Taneem. OpenCL Framework for a CPU, GPU, and FPGA Platform.

Degree: 2011, University of Toronto

With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any… (more)

Subjects/Keywords: FPGA; Heterogeneous Computing; OpenCL; Reconfigurable Computing; 0544

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ahmed, T. (2011). OpenCL Framework for a CPU, GPU, and FPGA Platform. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/30149

Chicago Manual of Style (16th Edition):

Ahmed, Taneem. “OpenCL Framework for a CPU, GPU, and FPGA Platform.” 2011. Masters Thesis, University of Toronto. Accessed February 25, 2020. http://hdl.handle.net/1807/30149.

MLA Handbook (7th Edition):

Ahmed, Taneem. “OpenCL Framework for a CPU, GPU, and FPGA Platform.” 2011. Web. 25 Feb 2020.

Vancouver:

Ahmed T. OpenCL Framework for a CPU, GPU, and FPGA Platform. [Internet] [Masters thesis]. University of Toronto; 2011. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1807/30149.

Council of Science Editors:

Ahmed T. OpenCL Framework for a CPU, GPU, and FPGA Platform. [Masters Thesis]. University of Toronto; 2011. Available from: http://hdl.handle.net/1807/30149


Virginia Tech

6. Rutishauser, David. Implementing Scientific Simulation Codes Tailored for Vector Architectures Using Custom Configurable Computing Machines.

Degree: PhD, Electrical and Computer Engineering, 2010, Virginia Tech

 Prior to the availability of massively parallel supercomputers, the implementation of choice for scientific computing problems such as large numerical physical simulations was typically a… (more)

Subjects/Keywords: Scientific Computing; Vector Computing; Reconfigurable Computing; Field-Programmable Gate Arrays

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rutishauser, D. (2010). Implementing Scientific Simulation Codes Tailored for Vector Architectures Using Custom Configurable Computing Machines. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/26838

Chicago Manual of Style (16th Edition):

Rutishauser, David. “Implementing Scientific Simulation Codes Tailored for Vector Architectures Using Custom Configurable Computing Machines.” 2010. Doctoral Dissertation, Virginia Tech. Accessed February 25, 2020. http://hdl.handle.net/10919/26838.

MLA Handbook (7th Edition):

Rutishauser, David. “Implementing Scientific Simulation Codes Tailored for Vector Architectures Using Custom Configurable Computing Machines.” 2010. Web. 25 Feb 2020.

Vancouver:

Rutishauser D. Implementing Scientific Simulation Codes Tailored for Vector Architectures Using Custom Configurable Computing Machines. [Internet] [Doctoral dissertation]. Virginia Tech; 2010. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10919/26838.

Council of Science Editors:

Rutishauser D. Implementing Scientific Simulation Codes Tailored for Vector Architectures Using Custom Configurable Computing Machines. [Doctoral Dissertation]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/26838


Brunel University

7. Afandi, Ahmad. Efficient reconfigurable architectures for 3D medical image compression.

Degree: PhD, 2010, Brunel University

 Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound… (more)

Subjects/Keywords: 621.39; Field programmable gate array; Reconfigurable computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Afandi, A. (2010). Efficient reconfigurable architectures for 3D medical image compression. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880

Chicago Manual of Style (16th Edition):

Afandi, Ahmad. “Efficient reconfigurable architectures for 3D medical image compression.” 2010. Doctoral Dissertation, Brunel University. Accessed February 25, 2020. http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880.

MLA Handbook (7th Edition):

Afandi, Ahmad. “Efficient reconfigurable architectures for 3D medical image compression.” 2010. Web. 25 Feb 2020.

Vancouver:

Afandi A. Efficient reconfigurable architectures for 3D medical image compression. [Internet] [Doctoral dissertation]. Brunel University; 2010. [cited 2020 Feb 25]. Available from: http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880.

Council of Science Editors:

Afandi A. Efficient reconfigurable architectures for 3D medical image compression. [Doctoral Dissertation]. Brunel University; 2010. Available from: http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880


Rochester Institute of Technology

8. Webster, David. Versatile FPGA architecture for skein hashing algorithm.

Degree: Computer Engineering, 2011, Rochester Institute of Technology

 Digital communications and data storage are expanding at fast rates, increasing the need for advanced cryptographic standards to validate and provide privacy for that data.… (more)

Subjects/Keywords: FPGA; Hashing; Reconfigurable computing; Skein; Xilinx

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APA (6th Edition):

Webster, D. (2011). Versatile FPGA architecture for skein hashing algorithm. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/497

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Webster, David. “Versatile FPGA architecture for skein hashing algorithm.” 2011. Thesis, Rochester Institute of Technology. Accessed February 25, 2020. https://scholarworks.rit.edu/theses/497.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Webster, David. “Versatile FPGA architecture for skein hashing algorithm.” 2011. Web. 25 Feb 2020.

Vancouver:

Webster D. Versatile FPGA architecture for skein hashing algorithm. [Internet] [Thesis]. Rochester Institute of Technology; 2011. [cited 2020 Feb 25]. Available from: https://scholarworks.rit.edu/theses/497.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Webster D. Versatile FPGA architecture for skein hashing algorithm. [Thesis]. Rochester Institute of Technology; 2011. Available from: https://scholarworks.rit.edu/theses/497

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Louisiana State University

9. Kongari, Raghavendra. Cost and performance modeling of the MU-Decoder.

Degree: MSEE, Electrical and Computer Engineering, 2011, Louisiana State University

 In this thesis we study the implementation details of the MU-Decoders, a recently proposed hardware module that has been theoretically shown to be superior to… (more)

Subjects/Keywords: fpga; subset generation; reconfigurable computing; configurable decoder

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kongari, R. (2011). Cost and performance modeling of the MU-Decoder. (Masters Thesis). Louisiana State University. Retrieved from etd-04282011-065004 ; https://digitalcommons.lsu.edu/gradschool_theses/795

Chicago Manual of Style (16th Edition):

Kongari, Raghavendra. “Cost and performance modeling of the MU-Decoder.” 2011. Masters Thesis, Louisiana State University. Accessed February 25, 2020. etd-04282011-065004 ; https://digitalcommons.lsu.edu/gradschool_theses/795.

MLA Handbook (7th Edition):

Kongari, Raghavendra. “Cost and performance modeling of the MU-Decoder.” 2011. Web. 25 Feb 2020.

Vancouver:

Kongari R. Cost and performance modeling of the MU-Decoder. [Internet] [Masters thesis]. Louisiana State University; 2011. [cited 2020 Feb 25]. Available from: etd-04282011-065004 ; https://digitalcommons.lsu.edu/gradschool_theses/795.

Council of Science Editors:

Kongari R. Cost and performance modeling of the MU-Decoder. [Masters Thesis]. Louisiana State University; 2011. Available from: etd-04282011-065004 ; https://digitalcommons.lsu.edu/gradschool_theses/795


Virginia Tech

10. Bhardwaj, Prabhaav. Framework for Hardware Agility on FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated… (more)

Subjects/Keywords: Virtex 5; Dynamic Routing; FPGA; Reconfigurable Computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bhardwaj, P. (2010). Framework for Hardware Agility on FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36347

Chicago Manual of Style (16th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed February 25, 2020. http://hdl.handle.net/10919/36347.

MLA Handbook (7th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Web. 25 Feb 2020.

Vancouver:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10919/36347.

Council of Science Editors:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36347


University of Illinois – Chicago

11. Banerjee, Soumya. Cookie-Cutter: Achieving Defect/Fault Tolerance For Large-Scale Systems with Highly Unreliable Components.

Degree: 2017, University of Illinois – Chicago

 The work proposes generalized “cookie-cutter” defect and fault tolerance approaches for nano-scale systems. The systems under considerations include Parallel Prefix Adders (PPA’s) and Large-scale Many-processor… (more)

Subjects/Keywords: Defect tolerance; Fault tolerance; Reliability; Reconfigurable Computing

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APA (6th Edition):

Banerjee, S. (2017). Cookie-Cutter: Achieving Defect/Fault Tolerance For Large-Scale Systems with Highly Unreliable Components. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/22138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Banerjee, Soumya. “Cookie-Cutter: Achieving Defect/Fault Tolerance For Large-Scale Systems with Highly Unreliable Components.” 2017. Thesis, University of Illinois – Chicago. Accessed February 25, 2020. http://hdl.handle.net/10027/22138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Banerjee, Soumya. “Cookie-Cutter: Achieving Defect/Fault Tolerance For Large-Scale Systems with Highly Unreliable Components.” 2017. Web. 25 Feb 2020.

Vancouver:

Banerjee S. Cookie-Cutter: Achieving Defect/Fault Tolerance For Large-Scale Systems with Highly Unreliable Components. [Internet] [Thesis]. University of Illinois – Chicago; 2017. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10027/22138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Banerjee S. Cookie-Cutter: Achieving Defect/Fault Tolerance For Large-Scale Systems with Highly Unreliable Components. [Thesis]. University of Illinois – Chicago; 2017. Available from: http://hdl.handle.net/10027/22138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Clemson University

12. Nallamuthu, Ananth. Acceleration of Biomolecular Simulations using FPGA-based Reconfigurable Computing.

Degree: MS, Computer Engineering, 2010, Clemson University

  A paradigm shift is occurring in the way compute-intensive scientific applications are developed. Thanks to advancements in commercially viable hybrid architectures for High-Performance Computing(more)

Subjects/Keywords: Biomolecular simulations; FPGA; Hybrid Computing; Molecular Dynamics; Reconfigurable Computing; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nallamuthu, A. (2010). Acceleration of Biomolecular Simulations using FPGA-based Reconfigurable Computing. (Masters Thesis). Clemson University. Retrieved from https://tigerprints.clemson.edu/all_theses/855

Chicago Manual of Style (16th Edition):

Nallamuthu, Ananth. “Acceleration of Biomolecular Simulations using FPGA-based Reconfigurable Computing.” 2010. Masters Thesis, Clemson University. Accessed February 25, 2020. https://tigerprints.clemson.edu/all_theses/855.

MLA Handbook (7th Edition):

Nallamuthu, Ananth. “Acceleration of Biomolecular Simulations using FPGA-based Reconfigurable Computing.” 2010. Web. 25 Feb 2020.

Vancouver:

Nallamuthu A. Acceleration of Biomolecular Simulations using FPGA-based Reconfigurable Computing. [Internet] [Masters thesis]. Clemson University; 2010. [cited 2020 Feb 25]. Available from: https://tigerprints.clemson.edu/all_theses/855.

Council of Science Editors:

Nallamuthu A. Acceleration of Biomolecular Simulations using FPGA-based Reconfigurable Computing. [Masters Thesis]. Clemson University; 2010. Available from: https://tigerprints.clemson.edu/all_theses/855


Bucknell University

13. Su, Juliana. Design and Development of an FPGA-based Distributed Computing Processing Platform.

Degree: 2011, Bucknell University

 This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using… (more)

Subjects/Keywords: field-programmable gate array; FPGA; distributed computing; reconfigurable computing; processing platform

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APA (6th Edition):

Su, J. (2011). Design and Development of an FPGA-based Distributed Computing Processing Platform. (Thesis). Bucknell University. Retrieved from https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Thesis, Bucknell University. Accessed February 25, 2020. https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Web. 25 Feb 2020.

Vancouver:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Internet] [Thesis]. Bucknell University; 2011. [cited 2020 Feb 25]. Available from: https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Thesis]. Bucknell University; 2011. Available from: https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Northeastern University

14. Drozdenko, Benjamin. Enabling protocol coexistence: hardware-software codesign of wireless transceivers on heterogeneous computing architectures.

Degree: PhD, Department of Electrical and Computer Engineering, 2017, Northeastern University

 In an increasingly interconnected world, there has been an explosion in the number of wireless devices in the Internet of Things. This recent increase in… (more)

Subjects/Keywords: hardware-software codesign; heterogeneous computing; reconfigurable computing; wireless communications; wireless networking

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APA (6th Edition):

Drozdenko, B. (2017). Enabling protocol coexistence: hardware-software codesign of wireless transceivers on heterogeneous computing architectures. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20249265

Chicago Manual of Style (16th Edition):

Drozdenko, Benjamin. “Enabling protocol coexistence: hardware-software codesign of wireless transceivers on heterogeneous computing architectures.” 2017. Doctoral Dissertation, Northeastern University. Accessed February 25, 2020. http://hdl.handle.net/2047/D20249265.

MLA Handbook (7th Edition):

Drozdenko, Benjamin. “Enabling protocol coexistence: hardware-software codesign of wireless transceivers on heterogeneous computing architectures.” 2017. Web. 25 Feb 2020.

Vancouver:

Drozdenko B. Enabling protocol coexistence: hardware-software codesign of wireless transceivers on heterogeneous computing architectures. [Internet] [Doctoral dissertation]. Northeastern University; 2017. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/2047/D20249265.

Council of Science Editors:

Drozdenko B. Enabling protocol coexistence: hardware-software codesign of wireless transceivers on heterogeneous computing architectures. [Doctoral Dissertation]. Northeastern University; 2017. Available from: http://hdl.handle.net/2047/D20249265


University of Toronto

15. Eskandari, Nariman. A Modular Heterogeneous Communication Layer for a Cluster of FPGAs and CPUs.

Degree: 2018, University of Toronto

A key infrastructure required to make heterogeneous clusters easier to use is a standard communication mechanism between computing nodes. Without this infrastructure, application developers of… (more)

Subjects/Keywords: Communication Layer; Data Centers; FPGAs; Heterogeneous Computing; High-Performance Computing; Reconfigurable Computing; 0464

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Eskandari, N. (2018). A Modular Heterogeneous Communication Layer for a Cluster of FPGAs and CPUs. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/91684

Chicago Manual of Style (16th Edition):

Eskandari, Nariman. “A Modular Heterogeneous Communication Layer for a Cluster of FPGAs and CPUs.” 2018. Masters Thesis, University of Toronto. Accessed February 25, 2020. http://hdl.handle.net/1807/91684.

MLA Handbook (7th Edition):

Eskandari, Nariman. “A Modular Heterogeneous Communication Layer for a Cluster of FPGAs and CPUs.” 2018. Web. 25 Feb 2020.

Vancouver:

Eskandari N. A Modular Heterogeneous Communication Layer for a Cluster of FPGAs and CPUs. [Internet] [Masters thesis]. University of Toronto; 2018. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1807/91684.

Council of Science Editors:

Eskandari N. A Modular Heterogeneous Communication Layer for a Cluster of FPGAs and CPUs. [Masters Thesis]. University of Toronto; 2018. Available from: http://hdl.handle.net/1807/91684


University of Western Australia

16. George, David Frederick James. Reconfigurable cellular automata computing for complex systems on the SPACE machine.

Degree: MS, 2005, University of Western Australia

Many complex natural and man made systems are inherently concurrent in nature, consisting of many autonomous parts that interact with each other. Cellular automata allow… (more)

Subjects/Keywords: Adaptive computing systems; Reconfigurable computing; FPGHAs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

George, D. F. J. (2005). Reconfigurable cellular automata computing for complex systems on the SPACE machine. (Masters Thesis). University of Western Australia. Retrieved from http://repository.uwa.edu.au:80/R/?func=dbin-jump-full&object_id=6881&local_base=GEN01-INS01

Chicago Manual of Style (16th Edition):

George, David Frederick James. “Reconfigurable cellular automata computing for complex systems on the SPACE machine.” 2005. Masters Thesis, University of Western Australia. Accessed February 25, 2020. http://repository.uwa.edu.au:80/R/?func=dbin-jump-full&object_id=6881&local_base=GEN01-INS01.

MLA Handbook (7th Edition):

George, David Frederick James. “Reconfigurable cellular automata computing for complex systems on the SPACE machine.” 2005. Web. 25 Feb 2020.

Vancouver:

George DFJ. Reconfigurable cellular automata computing for complex systems on the SPACE machine. [Internet] [Masters thesis]. University of Western Australia; 2005. [cited 2020 Feb 25]. Available from: http://repository.uwa.edu.au:80/R/?func=dbin-jump-full&object_id=6881&local_base=GEN01-INS01.

Council of Science Editors:

George DFJ. Reconfigurable cellular automata computing for complex systems on the SPACE machine. [Masters Thesis]. University of Western Australia; 2005. Available from: http://repository.uwa.edu.au:80/R/?func=dbin-jump-full&object_id=6881&local_base=GEN01-INS01


Penn State University

17. Al Maashri, Ahmed. Accelerating Design and Implementation of Embedded Vision Systems.

Degree: PhD, Computer Science and Engineering, 2012, Penn State University

 In today’s world, embedded systems have become a necessity in our daily lives. Ranging from digital watches to factory controllers, these systems are dedicated to… (more)

Subjects/Keywords: Embedded Vision Systems; Domain-Specific Computing; Reconfigurable Computing; Power Efficiency; Neuromophic Accelerators

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Al Maashri, A. (2012). Accelerating Design and Implementation of Embedded Vision Systems. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/16137

Chicago Manual of Style (16th Edition):

Al Maashri, Ahmed. “Accelerating Design and Implementation of Embedded Vision Systems.” 2012. Doctoral Dissertation, Penn State University. Accessed February 25, 2020. https://etda.libraries.psu.edu/catalog/16137.

MLA Handbook (7th Edition):

Al Maashri, Ahmed. “Accelerating Design and Implementation of Embedded Vision Systems.” 2012. Web. 25 Feb 2020.

Vancouver:

Al Maashri A. Accelerating Design and Implementation of Embedded Vision Systems. [Internet] [Doctoral dissertation]. Penn State University; 2012. [cited 2020 Feb 25]. Available from: https://etda.libraries.psu.edu/catalog/16137.

Council of Science Editors:

Al Maashri A. Accelerating Design and Implementation of Embedded Vision Systems. [Doctoral Dissertation]. Penn State University; 2012. Available from: https://etda.libraries.psu.edu/catalog/16137


University of Southern California

18. Wang, Qingbo. Multi-softcore architectures and algorithms for a class of sparse computations.

Degree: PhD, Electrical Engineering, 2011, University of Southern California

 Field-programmable gate array (FPGA) is a representative reconfigurable computing platform. It has been used in many applications to execute computationally intensive workloads. In this work,… (more)

Subjects/Keywords: reconfigurable computing; multi-core architecture; field-programmable gate array; algorithm; sparse computation; computing system

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APA (6th Edition):

Wang, Q. (2011). Multi-softcore architectures and algorithms for a class of sparse computations. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/387367/rec/4254

Chicago Manual of Style (16th Edition):

Wang, Qingbo. “Multi-softcore architectures and algorithms for a class of sparse computations.” 2011. Doctoral Dissertation, University of Southern California. Accessed February 25, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/387367/rec/4254.

MLA Handbook (7th Edition):

Wang, Qingbo. “Multi-softcore architectures and algorithms for a class of sparse computations.” 2011. Web. 25 Feb 2020.

Vancouver:

Wang Q. Multi-softcore architectures and algorithms for a class of sparse computations. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2020 Feb 25]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/387367/rec/4254.

Council of Science Editors:

Wang Q. Multi-softcore architectures and algorithms for a class of sparse computations. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/387367/rec/4254


Virginia Tech

19. Kim, Song Hun. Distributed Reconfigurable Simulation for Communication Systems.

Degree: PhD, Electrical and Computer Engineering, 2002, Virginia Tech

 The simulation of physical-layer communication systems often requires long execution times. This is due to the nature of the Monte Carlo simulation. To obtain a… (more)

Subjects/Keywords: middleware; distributed computing; reconfigurable computing; simulation

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APA (6th Edition):

Kim, S. H. (2002). Distributed Reconfigurable Simulation for Communication Systems. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29700

Chicago Manual of Style (16th Edition):

Kim, Song Hun. “Distributed Reconfigurable Simulation for Communication Systems.” 2002. Doctoral Dissertation, Virginia Tech. Accessed February 25, 2020. http://hdl.handle.net/10919/29700.

MLA Handbook (7th Edition):

Kim, Song Hun. “Distributed Reconfigurable Simulation for Communication Systems.” 2002. Web. 25 Feb 2020.

Vancouver:

Kim SH. Distributed Reconfigurable Simulation for Communication Systems. [Internet] [Doctoral dissertation]. Virginia Tech; 2002. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10919/29700.

Council of Science Editors:

Kim SH. Distributed Reconfigurable Simulation for Communication Systems. [Doctoral Dissertation]. Virginia Tech; 2002. Available from: http://hdl.handle.net/10919/29700


University of Arkansas

20. Cartwright, Eugene. Enabling Runtime Profiling to Hide and Exploit Heterogeneity within Chip Heterogeneous Multiprocessor Systems (CHMPS).

Degree: PhD, 2016, University of Arkansas

  The heterogeneity of multiprocessor systems on chip (MPSoC) has presented unique opportunities for furthering today’s diverse application needs. FPGA-based MPSoCs have the potential of… (more)

Subjects/Keywords: Applied sciences; Adaptive computing; FPGA; MPSoCs; Partial reconfiguration; Reconfigurable computing; Software Engineering; Systems Architecture

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APA (6th Edition):

Cartwright, E. (2016). Enabling Runtime Profiling to Hide and Exploit Heterogeneity within Chip Heterogeneous Multiprocessor Systems (CHMPS). (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1571

Chicago Manual of Style (16th Edition):

Cartwright, Eugene. “Enabling Runtime Profiling to Hide and Exploit Heterogeneity within Chip Heterogeneous Multiprocessor Systems (CHMPS).” 2016. Doctoral Dissertation, University of Arkansas. Accessed February 25, 2020. https://scholarworks.uark.edu/etd/1571.

MLA Handbook (7th Edition):

Cartwright, Eugene. “Enabling Runtime Profiling to Hide and Exploit Heterogeneity within Chip Heterogeneous Multiprocessor Systems (CHMPS).” 2016. Web. 25 Feb 2020.

Vancouver:

Cartwright E. Enabling Runtime Profiling to Hide and Exploit Heterogeneity within Chip Heterogeneous Multiprocessor Systems (CHMPS). [Internet] [Doctoral dissertation]. University of Arkansas; 2016. [cited 2020 Feb 25]. Available from: https://scholarworks.uark.edu/etd/1571.

Council of Science Editors:

Cartwright E. Enabling Runtime Profiling to Hide and Exploit Heterogeneity within Chip Heterogeneous Multiprocessor Systems (CHMPS). [Doctoral Dissertation]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1571


Boston University

21. Yang, Chen. High-performance communication infrastructure design on FPGA-centric clusters.

Degree: PhD, Electrical & Computer Engineering, 2019, Boston University

 FPGA-Centric Clusters (FCCs) with the FPGAs directly linked through their Multi-Gigabit Transceivers (MGTs) have a proven advantage over other commodity architectures for communication bound applications.… (more)

Subjects/Keywords: Computer engineering; Communication; Dark matter detection; FPGA-cluster; High-performance computing; Molecular dynamics; Reconfigurable computing

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APA (6th Edition):

Yang, C. (2019). High-performance communication infrastructure design on FPGA-centric clusters. (Doctoral Dissertation). Boston University. Retrieved from http://hdl.handle.net/2144/38207

Chicago Manual of Style (16th Edition):

Yang, Chen. “High-performance communication infrastructure design on FPGA-centric clusters.” 2019. Doctoral Dissertation, Boston University. Accessed February 25, 2020. http://hdl.handle.net/2144/38207.

MLA Handbook (7th Edition):

Yang, Chen. “High-performance communication infrastructure design on FPGA-centric clusters.” 2019. Web. 25 Feb 2020.

Vancouver:

Yang C. High-performance communication infrastructure design on FPGA-centric clusters. [Internet] [Doctoral dissertation]. Boston University; 2019. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/2144/38207.

Council of Science Editors:

Yang C. High-performance communication infrastructure design on FPGA-centric clusters. [Doctoral Dissertation]. Boston University; 2019. Available from: http://hdl.handle.net/2144/38207

22. Pelegrini, Eder José. Códigos adaptativos e linguagem para programação adaptativa: conceitos e tecnologia.

Degree: Mestrado, Sistemas Digitais, 2009, University of São Paulo

Esse trabalho relata o estudo sobre a aplicação da tecnologia adaptativa na área de linguagens de programação e códigos, tendo como objetivo a proposição de… (more)

Subjects/Keywords: Computação reconfigurável; Linguagem de programação; Programming language; Reconfigurable computing

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APA (6th Edition):

Pelegrini, E. J. (2009). Códigos adaptativos e linguagem para programação adaptativa: conceitos e tecnologia. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3141/tde-13072009-160204/ ;

Chicago Manual of Style (16th Edition):

Pelegrini, Eder José. “Códigos adaptativos e linguagem para programação adaptativa: conceitos e tecnologia.” 2009. Masters Thesis, University of São Paulo. Accessed February 25, 2020. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-13072009-160204/ ;.

MLA Handbook (7th Edition):

Pelegrini, Eder José. “Códigos adaptativos e linguagem para programação adaptativa: conceitos e tecnologia.” 2009. Web. 25 Feb 2020.

Vancouver:

Pelegrini EJ. Códigos adaptativos e linguagem para programação adaptativa: conceitos e tecnologia. [Internet] [Masters thesis]. University of São Paulo; 2009. [cited 2020 Feb 25]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3141/tde-13072009-160204/ ;.

Council of Science Editors:

Pelegrini EJ. Códigos adaptativos e linguagem para programação adaptativa: conceitos e tecnologia. [Masters Thesis]. University of São Paulo; 2009. Available from: http://www.teses.usp.br/teses/disponiveis/3/3141/tde-13072009-160204/ ;

23. Menotti, Ricardo. LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável.

Degree: PhD, Ciências de Computação e Matemática Computacional, 2010, University of São Paulo

A computação reconfigurável tem se tornado cada vez mais importante em sistemas computacionais embarcados e de alto desempenho. Ela permite níveis de desempenho próximos aos… (more)

Subjects/Keywords: Compiladores; Compilers; Computação reconfigurável; FPGA; FPGA; Reconfigurable computing

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APA (6th Edition):

Menotti, R. (2010). LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-17082010-151100/ ;

Chicago Manual of Style (16th Edition):

Menotti, Ricardo. “LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável.” 2010. Doctoral Dissertation, University of São Paulo. Accessed February 25, 2020. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-17082010-151100/ ;.

MLA Handbook (7th Edition):

Menotti, Ricardo. “LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável.” 2010. Web. 25 Feb 2020.

Vancouver:

Menotti R. LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável. [Internet] [Doctoral dissertation]. University of São Paulo; 2010. [cited 2020 Feb 25]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-17082010-151100/ ;.

Council of Science Editors:

Menotti R. LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável. [Doctoral Dissertation]. University of São Paulo; 2010. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-17082010-151100/ ;

24. Kiehn, Luiz Henrique. Técnicas de profiling para o co-projeto de hardware e software baseado em computação reconfigurável aplicadas ao processador softcore Nios II da Altera.

Degree: Mestrado, Ciências de Computação e Matemática Computacional, 2012, University of São Paulo

Como avanço dos paradigmas de desenvolvimento de sistemas eletrônicos, novos conceitos, modelos e técnicas resultaram dessa evolução, gerando ferramentas mais eficientes e objetivas. Entre estas,… (more)

Subjects/Keywords: Codesign; Computação reconfigurável; Coprojeto; FPGA; FPGA; Profiling; Profiling; Reconfigurable computing

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APA (6th Edition):

Kiehn, L. H. (2012). Técnicas de profiling para o co-projeto de hardware e software baseado em computação reconfigurável aplicadas ao processador softcore Nios II da Altera. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-24012013-104256/ ;

Chicago Manual of Style (16th Edition):

Kiehn, Luiz Henrique. “Técnicas de profiling para o co-projeto de hardware e software baseado em computação reconfigurável aplicadas ao processador softcore Nios II da Altera.” 2012. Masters Thesis, University of São Paulo. Accessed February 25, 2020. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-24012013-104256/ ;.

MLA Handbook (7th Edition):

Kiehn, Luiz Henrique. “Técnicas de profiling para o co-projeto de hardware e software baseado em computação reconfigurável aplicadas ao processador softcore Nios II da Altera.” 2012. Web. 25 Feb 2020.

Vancouver:

Kiehn LH. Técnicas de profiling para o co-projeto de hardware e software baseado em computação reconfigurável aplicadas ao processador softcore Nios II da Altera. [Internet] [Masters thesis]. University of São Paulo; 2012. [cited 2020 Feb 25]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-24012013-104256/ ;.

Council of Science Editors:

Kiehn LH. Técnicas de profiling para o co-projeto de hardware e software baseado em computação reconfigurável aplicadas ao processador softcore Nios II da Altera. [Masters Thesis]. University of São Paulo; 2012. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-24012013-104256/ ;


NSYSU

25. Chen, Juei-Tsung. Design and Implement the Memory Unit with Reconfigurable Computing Unit.

Degree: Master, Electrical Engineering, 2011, NSYSU

 It has been confirmed that reconfigurable computing system has potential to accelerate in large amounts of data computing. However, current trend is towards combining a… (more)

Subjects/Keywords: Software-hardware co-work; Hardware Management Unit; Reconfigurable computing system

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APA (6th Edition):

Chen, J. (2011). Design and Implement the Memory Unit with Reconfigurable Computing Unit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172812

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Juei-Tsung. “Design and Implement the Memory Unit with Reconfigurable Computing Unit.” 2011. Thesis, NSYSU. Accessed February 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172812.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Juei-Tsung. “Design and Implement the Memory Unit with Reconfigurable Computing Unit.” 2011. Web. 25 Feb 2020.

Vancouver:

Chen J. Design and Implement the Memory Unit with Reconfigurable Computing Unit. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Feb 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172812.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen J. Design and Implement the Memory Unit with Reconfigurable Computing Unit. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172812

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Case Western Reserve University

26. Qian, Wenchao. Energy-efficientSpatio-temporalComputing Framework.

Degree: PhD, EECS - Computer Engineering, 2016, Case Western Reserve University

 Digital system design incorporates components ranging from general purpose processors (GPPs) to application specific integrated circuits (ASICs). GPPs provide flexible implementation of diverse applications at… (more)

Subjects/Keywords: Computer Engineering; Reconfigurable Computing; FPGA; Computer Architecture; Computer Hardware; Computer Software

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APA (6th Edition):

Qian, W. (2016). Energy-efficientSpatio-temporalComputing Framework. (Doctoral Dissertation). Case Western Reserve University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1459257723

Chicago Manual of Style (16th Edition):

Qian, Wenchao. “Energy-efficientSpatio-temporalComputing Framework.” 2016. Doctoral Dissertation, Case Western Reserve University. Accessed February 25, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1459257723.

MLA Handbook (7th Edition):

Qian, Wenchao. “Energy-efficientSpatio-temporalComputing Framework.” 2016. Web. 25 Feb 2020.

Vancouver:

Qian W. Energy-efficientSpatio-temporalComputing Framework. [Internet] [Doctoral dissertation]. Case Western Reserve University; 2016. [cited 2020 Feb 25]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1459257723.

Council of Science Editors:

Qian W. Energy-efficientSpatio-temporalComputing Framework. [Doctoral Dissertation]. Case Western Reserve University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1459257723


Virginia Tech

27. Iskander, Yousef Shafik. Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug.

Degree: PhD, Electrical and Computer Engineering, 2012, Virginia Tech

 Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different… (more)

Subjects/Keywords: partial reconfiguration; reconfigurable computing; FPGA; development; debug; design validation

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APA (6th Edition):

Iskander, Y. S. (2012). Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/28716

Chicago Manual of Style (16th Edition):

Iskander, Yousef Shafik. “Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug.” 2012. Doctoral Dissertation, Virginia Tech. Accessed February 25, 2020. http://hdl.handle.net/10919/28716.

MLA Handbook (7th Edition):

Iskander, Yousef Shafik. “Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug.” 2012. Web. 25 Feb 2020.

Vancouver:

Iskander YS. Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug. [Internet] [Doctoral dissertation]. Virginia Tech; 2012. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10919/28716.

Council of Science Editors:

Iskander YS. Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug. [Doctoral Dissertation]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/28716


University of California – Riverside

28. Budhkar, Prerna. Accelerating Irregular Applications Using Latency Masking Multithreaded Techniques.

Degree: Computer Science, 2018, University of California – Riverside

 The last two decade has witnessed two opposing hardware trends where the DRAM capacity and the access bandwidth has rapidly increased by 128x and 20x… (more)

Subjects/Keywords: Computer science; Irregular Applications; Latency Masking; Reconfigurable Computing

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APA (6th Edition):

Budhkar, P. (2018). Accelerating Irregular Applications Using Latency Masking Multithreaded Techniques. (Thesis). University of California – Riverside. Retrieved from http://www.escholarship.org/uc/item/62428630

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Budhkar, Prerna. “Accelerating Irregular Applications Using Latency Masking Multithreaded Techniques.” 2018. Thesis, University of California – Riverside. Accessed February 25, 2020. http://www.escholarship.org/uc/item/62428630.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Budhkar, Prerna. “Accelerating Irregular Applications Using Latency Masking Multithreaded Techniques.” 2018. Web. 25 Feb 2020.

Vancouver:

Budhkar P. Accelerating Irregular Applications Using Latency Masking Multithreaded Techniques. [Internet] [Thesis]. University of California – Riverside; 2018. [cited 2020 Feb 25]. Available from: http://www.escholarship.org/uc/item/62428630.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Budhkar P. Accelerating Irregular Applications Using Latency Masking Multithreaded Techniques. [Thesis]. University of California – Riverside; 2018. Available from: http://www.escholarship.org/uc/item/62428630

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

29. Kachris, C. Reconfigurable network processing platforms.

Degree: 2007, Delft University of Technology

 This dissertation presents our investigation on how to efficiently exploit reconfigurable hardware to design flexible, high performance, and power efficient network devices capable to adapt… (more)

Subjects/Keywords: reconfigurable computing; network processing; fpgas

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APA (6th Edition):

Kachris, C. (2007). Reconfigurable network processing platforms. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:a5157424-63cf-4770-9e07-20c35971a84c ; urn:NBN:nl:ui:24-uuid:a5157424-63cf-4770-9e07-20c35971a84c ; urn:NBN:nl:ui:24-uuid:a5157424-63cf-4770-9e07-20c35971a84c ; http://resolver.tudelft.nl/uuid:a5157424-63cf-4770-9e07-20c35971a84c

Chicago Manual of Style (16th Edition):

Kachris, C. “Reconfigurable network processing platforms.” 2007. Doctoral Dissertation, Delft University of Technology. Accessed February 25, 2020. http://resolver.tudelft.nl/uuid:a5157424-63cf-4770-9e07-20c35971a84c ; urn:NBN:nl:ui:24-uuid:a5157424-63cf-4770-9e07-20c35971a84c ; urn:NBN:nl:ui:24-uuid:a5157424-63cf-4770-9e07-20c35971a84c ; http://resolver.tudelft.nl/uuid:a5157424-63cf-4770-9e07-20c35971a84c.

MLA Handbook (7th Edition):

Kachris, C. “Reconfigurable network processing platforms.” 2007. Web. 25 Feb 2020.

Vancouver:

Kachris C. Reconfigurable network processing platforms. [Internet] [Doctoral dissertation]. Delft University of Technology; 2007. [cited 2020 Feb 25]. Available from: http://resolver.tudelft.nl/uuid:a5157424-63cf-4770-9e07-20c35971a84c ; urn:NBN:nl:ui:24-uuid:a5157424-63cf-4770-9e07-20c35971a84c ; urn:NBN:nl:ui:24-uuid:a5157424-63cf-4770-9e07-20c35971a84c ; http://resolver.tudelft.nl/uuid:a5157424-63cf-4770-9e07-20c35971a84c.

Council of Science Editors:

Kachris C. Reconfigurable network processing platforms. [Doctoral Dissertation]. Delft University of Technology; 2007. Available from: http://resolver.tudelft.nl/uuid:a5157424-63cf-4770-9e07-20c35971a84c ; urn:NBN:nl:ui:24-uuid:a5157424-63cf-4770-9e07-20c35971a84c ; urn:NBN:nl:ui:24-uuid:a5157424-63cf-4770-9e07-20c35971a84c ; http://resolver.tudelft.nl/uuid:a5157424-63cf-4770-9e07-20c35971a84c


Drexel University

30. Sworo, George Dimanson. Pattern Diversity Characterization of Reconfigurable Antenna Arrays for Next Generation Wireless Systems.

Degree: 2015, Drexel University

The use of multi-antenna technology in wireless radio communications has attracted tremendous attention due to its potential to increase data rates without requiring additional bandwidth… (more)

Subjects/Keywords: Electrical engineering; Adaptive computing systems; MIMO systems; Reconfigurable antenna

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sworo, G. D. (2015). Pattern Diversity Characterization of Reconfigurable Antenna Arrays for Next Generation Wireless Systems. (Thesis). Drexel University. Retrieved from http://hdl.handle.net/1860/idea:7059

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sworo, George Dimanson. “Pattern Diversity Characterization of Reconfigurable Antenna Arrays for Next Generation Wireless Systems.” 2015. Thesis, Drexel University. Accessed February 25, 2020. http://hdl.handle.net/1860/idea:7059.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sworo, George Dimanson. “Pattern Diversity Characterization of Reconfigurable Antenna Arrays for Next Generation Wireless Systems.” 2015. Web. 25 Feb 2020.

Vancouver:

Sworo GD. Pattern Diversity Characterization of Reconfigurable Antenna Arrays for Next Generation Wireless Systems. [Internet] [Thesis]. Drexel University; 2015. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1860/idea:7059.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sworo GD. Pattern Diversity Characterization of Reconfigurable Antenna Arrays for Next Generation Wireless Systems. [Thesis]. Drexel University; 2015. Available from: http://hdl.handle.net/1860/idea:7059

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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