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You searched for subject:(RTOS performance). Showing records 1 – 2 of 2 total matches.

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Boise State University

1. Gauba, Deepak Kumar. Hardware Implementation of Real-Time Operating System’s Thread Context Switch.

Degree: 2010, Boise State University

Increasingly, embedded real-time applications use multi-threading. The benefits of multi-threading include greater throughput, improved responsiveness, and ease of development and maintenance. However, there are costs and pitfalls associated with multi-threading. In some of hard real-time applications, with very precise timing requirements, multi-threading itself becomes an overhead cost mainly due to scheduling and contextswitching components of the real-time operating system (RTOS). Different scheduling algorithms have been suggested to improve the overall system performance. However, context-switching still consumes much of the processor’s time and becomes a major overhead cost especially for hard real-time embedded systems. A typical RTOS context switch consumes 50 to 80 processor clock cycles (depending on processor architecture and context size) to store and restore the thread context. If a real-time application needs to respond to an event repeatedly less than this time, then the overall system performance may not be acceptable. The suggested approach in this thesis improves the context-switching time drastically. This technique has been implemented in hardware, as part of the processor state along with new central processing unit (CPU) instructions to take care of the context-switching process without interacting with external memory. With the suggested approach, the thread contextswitch can be achieved in 4 CPU clock cycles independent of context size. This is a significant improvement to thread context switching.

Subjects/Keywords: Context-Switch; Context-switching time; Hardware context-switching; RTOS performance; Computer and Systems Architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gauba, D. K. (2010). Hardware Implementation of Real-Time Operating System’s Thread Context Switch. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/141

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gauba, Deepak Kumar. “Hardware Implementation of Real-Time Operating System’s Thread Context Switch.” 2010. Thesis, Boise State University. Accessed November 30, 2020. https://scholarworks.boisestate.edu/td/141.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gauba, Deepak Kumar. “Hardware Implementation of Real-Time Operating System’s Thread Context Switch.” 2010. Web. 30 Nov 2020.

Vancouver:

Gauba DK. Hardware Implementation of Real-Time Operating System’s Thread Context Switch. [Internet] [Thesis]. Boise State University; 2010. [cited 2020 Nov 30]. Available from: https://scholarworks.boisestate.edu/td/141.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gauba DK. Hardware Implementation of Real-Time Operating System’s Thread Context Switch. [Thesis]. Boise State University; 2010. Available from: https://scholarworks.boisestate.edu/td/141

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Mancuso, Renato. Next-generation safety-critical systems on multi-core platforms.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. In fact, multi-core platforms can deliver large computational power together with minimum costs, compact size, weight and power usage. Multi-core architectures however are shaking the very foundation of modern real-time computing theory, i.e. the assumption that worst case execution time (WCET) can be calculated on individual tasks to compute the schedulability of the complete system when tasks are running together. This fundamental assumption has been broadly accepted by classic scheduling theory for the past three decades; unfortunately, it is not even true in an approximate sense in a modern multi-core chip, and this leads to a lack of composability. Shared hardware resources like caches, main memory, and I/O buses are all sources of unpredictable timing behavior and temporal dependencies among real-time tasks running in parallel. As a result, certifying systems deployed using multi-core platforms is significantly more challenging compared to single-core implementations. In this work, we tackle the challenge of restoring the constant WCET assumption for real-time tasks deployed on multi-core systems. While predictability and performance determinism are of paramount importance in safety-critical applications, cost containment and time-to-market are dominant factors for the large-scale adoption of novel technologies. Hence, our work proposes solutions that can be adopted with commercially available components, also known as commercial-off-the-shelf (COTS) components. In order to achieve deterministic performance on COTS multi-core platforms, we propose software-level techniques to enforce usage control over shared hardware resources. We also demonstrate that when proper enforcement is performed, real-time analysis can be carried out efficiently. We focus our attention on two main multi-core architectural paradigms: cache-based and scratchpad-based platforms. On multi-core cache-based architectures, we design, implement and analyse a set of OS-level techniques that enforce hardware resource partitioning. In this context, we set two main goals. Our first objective is to achieve strong inter-core performance isolation in spite of inherent hardware resource sharing. On the other hand, our techniques are designed to remain transparent from an application perspective. This requirement allows for minimum re-engineering being required to port legacy single-core systems on multi-core platforms partitioned with the proposed techniques. On scratchpad-based platforms, we follow a different approach. In fact, we propose a redesign of the OS-level scheduling strategies. The goal is to include scratchpad space scheduling, as well as shared memory bus access, together with traditional processor time scheduling. The resulting resource co-scheduling strategy introduces a set of new challenges compared to processor-only scheduling. Nonetheless, it allows to significantly mitigate the problem of inter-core performance… Advisors/Committee Members: Caccamo, Marco (advisor), Caccamo, Marco (Committee Chair), Sha, Lui (committee member), Abdelzaher, Tarek F. (committee member), Brandenburg, Björn (committee member).

Subjects/Keywords: Real-time systems; Multi-core systems; Commercial-off-the-shelf (COTS); Single-core equivalence; Single-core equivalent; Hardware resource management; Operating system (OS); Real-time operating system (RTOS); Worst case execution time (WCET); Scheduling; Schedulability analysis; Multi-core real-time operating system (RTOS); Profiling; Avionics; Safety-critical; Cyber-physical systems (CPS); Memguard; Colored lockdown; Palloc; Kernel verification; Scratchpad-centric operating system (OS); Scratchpad memories operating system (SPM-OS); Scratchpad scheduling; Direct memory access (DMA) scheduling; Flow-shop task; Flow-shop scheduling; Hardware scheduler; Field-programmable gate array (FPGA) scheduler; Real-time Linux; Automotive; Smart manufacturing; Real-time networking; Embedded systems; Multi-core avionics; Multi-core automotive; Self-driving cars; Multi-core safety-critical; Many-core; Reconfigurable computing; Internet of things; Real-time cloud computing; Provably safe cyber-physical systems (CPS); Multi-core scheduling; Performance isolation; Real-time resource management; Real-time cache; Real-time dynamic random access memory (DRAM); P4080; MPC5777M; Inter-core interference; Interference channels; CAST32; CAST32A; Federal Aviation Administration (FAA); Minimal multicore avionics certification guidance; Multi-core automotive open system architecture (AUTOSAR); DO-178C; DO-178B; Resource partitioning; Multi-core resource partitioning; Predictable execution model (PREM); Multi-core predictable execution model (PREM)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mancuso, R. (2017). Next-generation safety-critical systems on multi-core platforms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97399

Chicago Manual of Style (16th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed November 30, 2020. http://hdl.handle.net/2142/97399.

MLA Handbook (7th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Web. 30 Nov 2020.

Vancouver:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Nov 30]. Available from: http://hdl.handle.net/2142/97399.

Council of Science Editors:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97399

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