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You searched for subject:(Pt ALD). Showing records 1 – 3 of 3 total matches.

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North Carolina State University

1. Du, Yan. Study of Si1-xGex Junction Formation for SOI Based CMOS Technology.

Degree: PhD, Electrical Engineering, 2009, North Carolina State University

SiGe source/drain technology has been sucessfully applied to bulk metal oxide semiconductor field effect transistors (MOSFETs). Both channel mobility and source/drain contact resistivity are substantially improved with this technology. In this dissertation, SiGe junction formation for silicon on insulator (SOI) based CMOS technology was investigated. Strain in epitaxially grown films on SOI films and silicon nanowires is studied using Raman spectroscopy and transmission electron microscope (TEM). For epitaxially grown SiGe film on SOI, there is lower degree of strain development in the SOI layer due to the rigid interface between the SOI and the burried oxide as compared to bulk. However, for silicon nanowires on oxide, the situation is different since nanowires serve as compliant substrates. Part of the strain energy is transferred to silicon nanowires. The consistency between synthesized Raman peak shifts and the experimental measurements verified the strain sharing between the epitaxially grown SiGe films and the silicon nanowires. Splittings of high order Laue zone line (HOLZ) from a convergent beam electron diffraction (CBED) pattern was quantified to study the strain distribution in epitaxial SiGe films grown on silicon nanowires. It was found out in this study that elastic deformation of epitaxial SiGe at free surfaces leads to strain relaxation at these surfaces. This phenomenon is detrimental to strain engineering in a nanowire MOSFET and provides new challenges to develop smart designs for constraining strain in the nano-structures. Moreover, atomic layer deposition (ALD) Platinum is proposed for metal deposition on 3D epitaxial SiGe source/drain. The uniform deposition around 3D SiGe films effectively increases the contact surface area which is highly desired in the FinFET application. Advisors/Committee Members: Dr. Mehmet C Ozturk, Committee Co-Chair (advisor), Dr. Veena Misra, Committee Chair (advisor), Dr. Carlton Osburn, Committee Member (advisor), Dr. Gerd Duscher, Committee Member (advisor).

Subjects/Keywords: nanowire; SiGe; Pt ALD; strain; CBED

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APA (6th Edition):

Du, Y. (2009). Study of Si1-xGex Junction Formation for SOI Based CMOS Technology. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3433

Chicago Manual of Style (16th Edition):

Du, Yan. “Study of Si1-xGex Junction Formation for SOI Based CMOS Technology.” 2009. Doctoral Dissertation, North Carolina State University. Accessed January 22, 2020. http://www.lib.ncsu.edu/resolver/1840.16/3433.

MLA Handbook (7th Edition):

Du, Yan. “Study of Si1-xGex Junction Formation for SOI Based CMOS Technology.” 2009. Web. 22 Jan 2020.

Vancouver:

Du Y. Study of Si1-xGex Junction Formation for SOI Based CMOS Technology. [Internet] [Doctoral dissertation]. North Carolina State University; 2009. [cited 2020 Jan 22]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3433.

Council of Science Editors:

Du Y. Study of Si1-xGex Junction Formation for SOI Based CMOS Technology. [Doctoral Dissertation]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3433

2. Thomas, Daniel. Réalisation de transistors à un électron par encapsulation d’îlots nanométriques de platine dans une matrice diélectrique en utilisant un procédé ALD : Building single electron transistors from platinum nano-island matrices produced via atomic layer deposition.

Degree: Docteur es, Électronique, micro et nano-électronique, optique et laser, 2017, Lyon

L'introduction du transistor à un électron (SET) a secoué l'industrie des semi-conducteurs, avec des promesses d'efficacité inégalée. Cependant, le coût et la complexité associés à la réalisation d'un fonctionnement stable ont fortement entravé leur adoption. Après être tombé en dehors des grâces de l'industrie, la recherche universitaire a continué à pousser, démontrant des techniques novatrices pour la création de SET. Au cœur de ce problème de stabilité, il y a le besoin de construire de manière contrôlable des nanoislands de moins de 10 nm. Parmi les méthodes disponibles pour cette formation nanoisland, le dépôt de couche atomique (ALD) se distingue comme un processus hautement contrôlable industriellement. La deuxième barrière à l'entrée est la création d'électrodes nanogap, utilisées pour injecter du courant à travers ces nanoislands, pour lesquelles les chercheurs se sont largement appuyés sur des techniques de fabrication non évolutives comme la lithographie par faisceau d'électrons et le faisceau ionique focalisé. La technique d'évaporation de bord d'ombre surmonte les problèmes de complexité et d'échelle de la fabrication de nanogap, ouvrant de nouvelles possibilités. Dans ce travail, ALD sera démontré comme une superbe technique pour la culture de vastes réseaux 3D de nanoparticules de platine sous 2nm encapsulées dans Al2O3. ALD a fourni un moyen de faire croître ces matrices de nanoparticules en un seul processus, sous vide et à basse température. Grâce à l'évaporation du bord d'ombre, la lithographie UV a ensuite été utilisée pour former des électrodes nanogap avec des largeurs latérales élevées (100μm), avec des écarts démontrés au-dessous de 7 nm. La combinaison de ces techniques aboutit à un procédé de fabrication à haut rendement et à faible besoin pour la construction de SET complets. A partir des transistors résultants, de fines lamelles ont été préparées à l'aide de FIB et des modèles 3D ont été reconstruits par tomographie TEM pour analyse. La caractérisation électrique a été effectuée jusqu'à 77K, avec une modélisation révélant le transport de Poole-Frenkel en parallèle à un éventuel cotunneling. Des blocus de Coulomb stables, la signature des SET, ont été observés avec une périodicité régulière et étaient identifiables jusqu'à 170K. L'optimisation de ce processus pourrait produire des SETs de surface élevée capables de fonctionner de manière stable à température ambiante.

The introduction of the single electron transistor (SET) shook the semiconductor industry, with promises of unrivaled efficiency. However, the cost and complexity associated with achieving stable operation have heavily hindered their adoption. Having fallen out of the graces of industry, academic research has continued to push, demonstrating novel techniques for SET creation. At the core of this stability issue is a need to controllably build nanoislands smaller than 10nm. Among the methods available for this nanoisland formation, atomic layer deposition (ALD) sets itself apart as an industrially scalable, highly…

Advisors/Committee Members: Le Berre, Martine (thesis director).

Subjects/Keywords: Nanotechnologie; Nanoélectronique; Transistor à électron unique; Nanoparticules de Pt; ALD - Atomic layer deposition; Evaporation du bord d'ombre; Nanogap; Nanotechnology; Nanoélectronique; Single electron transistor; Pt nanoparticles; ALD - Atomic layer deposition; Shadow edge evaporation; Nanogap; 621.381 520 72

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Thomas, D. (2017). Réalisation de transistors à un électron par encapsulation d’îlots nanométriques de platine dans une matrice diélectrique en utilisant un procédé ALD : Building single electron transistors from platinum nano-island matrices produced via atomic layer deposition. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2017LYSEI131

Chicago Manual of Style (16th Edition):

Thomas, Daniel. “Réalisation de transistors à un électron par encapsulation d’îlots nanométriques de platine dans une matrice diélectrique en utilisant un procédé ALD : Building single electron transistors from platinum nano-island matrices produced via atomic layer deposition.” 2017. Doctoral Dissertation, Lyon. Accessed January 22, 2020. http://www.theses.fr/2017LYSEI131.

MLA Handbook (7th Edition):

Thomas, Daniel. “Réalisation de transistors à un électron par encapsulation d’îlots nanométriques de platine dans une matrice diélectrique en utilisant un procédé ALD : Building single electron transistors from platinum nano-island matrices produced via atomic layer deposition.” 2017. Web. 22 Jan 2020.

Vancouver:

Thomas D. Réalisation de transistors à un électron par encapsulation d’îlots nanométriques de platine dans une matrice diélectrique en utilisant un procédé ALD : Building single electron transistors from platinum nano-island matrices produced via atomic layer deposition. [Internet] [Doctoral dissertation]. Lyon; 2017. [cited 2020 Jan 22]. Available from: http://www.theses.fr/2017LYSEI131.

Council of Science Editors:

Thomas D. Réalisation de transistors à un électron par encapsulation d’îlots nanométriques de platine dans une matrice diélectrique en utilisant un procédé ALD : Building single electron transistors from platinum nano-island matrices produced via atomic layer deposition. [Doctoral Dissertation]. Lyon; 2017. Available from: http://www.theses.fr/2017LYSEI131

3. Hoover, Robert R., Jr. New Method for Coating Nickel with Ultrathin Platinum Films.

Degree: MS, College of Arts and Sciences / Department of Chemistry, 2010, Kent State University

An atomic layer deposition (ALD) technique for applying very thin platinum coatings onto nickel substrates is presented. In this research, a removable nickel rotating disk electrode was used as the substrate for a process involving MeCpPtMe3 and H2, both of which were in the gas phase when exposed to the substrate. The substrate was exposed to the two aforementioned compounds sequentially. Ultra pure N2 was used to remove each component before introducing the next one into the chamber. This process of alternately exposing the nickel disk to MeCpPtMe3 and H2 (with N2 in between) was repeated for specified numbers of times in order to produce films of various thicknesses. Electrochemical properties of the coatings were tested using rotating disk electrode geometry. On several occasions, the total amount of Pt applied was determined in order to assess the economic feasibility of potential scale up. Advisors/Committee Members: Tolmachev, Yuriy (Advisor).

Subjects/Keywords: Analytical Chemistry; Automotive Materials; Chemical Engineering; Chemistry; Energy; Environmental Engineering; Materials Science; Molecules; ALD; Pt; oxygen reduction

…of Pt ALD [9], [12], but all the ones previously reported are quite… …however, does not necessarily mean that Pt ALD using (methylcyclopentadienyl)… …uniform <5nm thick films of Pt onto a Ni surface. Chapter IV Development of Reductive ALD… …11, which shows two samples prepared using 30 cycles of ALD (a bulk Pt disk is also… …3 oxygen reducing size, which further increases the Pt requirement by necessitating… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hoover, Robert R., J. (2010). New Method for Coating Nickel with Ultrathin Platinum Films. (Masters Thesis). Kent State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=kent1274984392

Chicago Manual of Style (16th Edition):

Hoover, Robert R., Jr. “New Method for Coating Nickel with Ultrathin Platinum Films.” 2010. Masters Thesis, Kent State University. Accessed January 22, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=kent1274984392.

MLA Handbook (7th Edition):

Hoover, Robert R., Jr. “New Method for Coating Nickel with Ultrathin Platinum Films.” 2010. Web. 22 Jan 2020.

Vancouver:

Hoover, Robert R. J. New Method for Coating Nickel with Ultrathin Platinum Films. [Internet] [Masters thesis]. Kent State University; 2010. [cited 2020 Jan 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=kent1274984392.

Council of Science Editors:

Hoover, Robert R. J. New Method for Coating Nickel with Ultrathin Platinum Films. [Masters Thesis]. Kent State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=kent1274984392

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