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You searched for subject:(Programmable). Showing records 1 – 30 of 921 total matches.

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Texas A&M University

1. Islas Ohlmaier, Abraham. Design of programmable, low power, low dropout voltage regulators for portable applications.

Degree: MS, Electrical Engineering, 2007, Texas A&M University

 As portable electronics constantly find their way into the hands of eager consumers, the demands placed on these products and their circuits are ever increasing.… (more)

Subjects/Keywords: Programmable LDO

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APA (6th Edition):

Islas Ohlmaier, A. (2007). Design of programmable, low power, low dropout voltage regulators for portable applications. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/4689

Chicago Manual of Style (16th Edition):

Islas Ohlmaier, Abraham. “Design of programmable, low power, low dropout voltage regulators for portable applications.” 2007. Masters Thesis, Texas A&M University. Accessed September 23, 2020. http://hdl.handle.net/1969.1/4689.

MLA Handbook (7th Edition):

Islas Ohlmaier, Abraham. “Design of programmable, low power, low dropout voltage regulators for portable applications.” 2007. Web. 23 Sep 2020.

Vancouver:

Islas Ohlmaier A. Design of programmable, low power, low dropout voltage regulators for portable applications. [Internet] [Masters thesis]. Texas A&M University; 2007. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/1969.1/4689.

Council of Science Editors:

Islas Ohlmaier A. Design of programmable, low power, low dropout voltage regulators for portable applications. [Masters Thesis]. Texas A&M University; 2007. Available from: http://hdl.handle.net/1969.1/4689


Nelson Mandela Metropolitan University

2. Potgieter, Juan-Pierre. Single event upset testing of flash based field programmable gate arrays.

Degree: Faculty of Engineering, the Built Environment and Information Technology, 2015, Nelson Mandela Metropolitan University

 In the last 50 years microelectronics have advanced at an exponential rate, causing microelectronic devices to shrink, have very low operating voltages and increased complexities;… (more)

Subjects/Keywords: Field programmable gate arrays

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APA (6th Edition):

Potgieter, J. (2015). Single event upset testing of flash based field programmable gate arrays. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/12520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Potgieter, Juan-Pierre. “Single event upset testing of flash based field programmable gate arrays.” 2015. Thesis, Nelson Mandela Metropolitan University. Accessed September 23, 2020. http://hdl.handle.net/10948/12520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Potgieter, Juan-Pierre. “Single event upset testing of flash based field programmable gate arrays.” 2015. Web. 23 Sep 2020.

Vancouver:

Potgieter J. Single event upset testing of flash based field programmable gate arrays. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2015. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/10948/12520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Potgieter J. Single event upset testing of flash based field programmable gate arrays. [Thesis]. Nelson Mandela Metropolitan University; 2015. Available from: http://hdl.handle.net/10948/12520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Huang, Kuan-min. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 3D graphics pipeline can be divided into two subsystems: geometry subsystem and rendering subsystem. Hardware implementation of the transformation and lighting in the geometric subsystem… (more)

Subjects/Keywords: Vertex Shader; SIMD; Programmable

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APA (6th Edition):

Huang, K. (2009). Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Thesis, NSYSU. Accessed September 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Web. 23 Sep 2020.

Vancouver:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

4. Zhao, Yichen. Design and FPGA implementation of digital transmission over severe ISI channels.

Degree: MS, Electrical and Computer Engineering, 2013, Oregon State University

 Inter-symbol interference is one of the major factors that make the realization of high-data-rate digital communications system complex. Current designs face two main challenges: how… (more)

Subjects/Keywords: ISI; Field programmable gate arrays

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APA (6th Edition):

Zhao, Y. (2013). Design and FPGA implementation of digital transmission over severe ISI channels. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39400

Chicago Manual of Style (16th Edition):

Zhao, Yichen. “Design and FPGA implementation of digital transmission over severe ISI channels.” 2013. Masters Thesis, Oregon State University. Accessed September 23, 2020. http://hdl.handle.net/1957/39400.

MLA Handbook (7th Edition):

Zhao, Yichen. “Design and FPGA implementation of digital transmission over severe ISI channels.” 2013. Web. 23 Sep 2020.

Vancouver:

Zhao Y. Design and FPGA implementation of digital transmission over severe ISI channels. [Internet] [Masters thesis]. Oregon State University; 2013. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/1957/39400.

Council of Science Editors:

Zhao Y. Design and FPGA implementation of digital transmission over severe ISI channels. [Masters Thesis]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39400


University of North Texas

5. Gautam, Mahesh. Exploring Memristor Based Analog Design in Simscape.

Degree: 2013, University of North Texas

 With conventional CMOS technologies approaching their scaling limits, researchers are actively investigating alternative technologies for ever increasing computing and mobile demand. A number of different… (more)

Subjects/Keywords: Memristor; Simscape; programmable; oscillator; Wien

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APA (6th Edition):

Gautam, M. (2013). Exploring Memristor Based Analog Design in Simscape. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc271817/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gautam, Mahesh. “Exploring Memristor Based Analog Design in Simscape.” 2013. Thesis, University of North Texas. Accessed September 23, 2020. https://digital.library.unt.edu/ark:/67531/metadc271817/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gautam, Mahesh. “Exploring Memristor Based Analog Design in Simscape.” 2013. Web. 23 Sep 2020.

Vancouver:

Gautam M. Exploring Memristor Based Analog Design in Simscape. [Internet] [Thesis]. University of North Texas; 2013. [cited 2020 Sep 23]. Available from: https://digital.library.unt.edu/ark:/67531/metadc271817/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gautam M. Exploring Memristor Based Analog Design in Simscape. [Thesis]. University of North Texas; 2013. Available from: https://digital.library.unt.edu/ark:/67531/metadc271817/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Alberta

6. Fraga, Werner Eusebio. Memory-segmented programmable sequential controllers.

Degree: MS, Department of Electrical Engineering, 1987, University of Alberta

Subjects/Keywords: Sequence controllers, Programmable.; Programmable controllers.

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APA (6th Edition):

Fraga, W. E. (1987). Memory-segmented programmable sequential controllers. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/4t64gq206

Chicago Manual of Style (16th Edition):

Fraga, Werner Eusebio. “Memory-segmented programmable sequential controllers.” 1987. Masters Thesis, University of Alberta. Accessed September 23, 2020. https://era.library.ualberta.ca/files/4t64gq206.

MLA Handbook (7th Edition):

Fraga, Werner Eusebio. “Memory-segmented programmable sequential controllers.” 1987. Web. 23 Sep 2020.

Vancouver:

Fraga WE. Memory-segmented programmable sequential controllers. [Internet] [Masters thesis]. University of Alberta; 1987. [cited 2020 Sep 23]. Available from: https://era.library.ualberta.ca/files/4t64gq206.

Council of Science Editors:

Fraga WE. Memory-segmented programmable sequential controllers. [Masters Thesis]. University of Alberta; 1987. Available from: https://era.library.ualberta.ca/files/4t64gq206

7. Ben Dhia, Arwa. Durcissement de circuits logiques reconfigurables : Hardening basic blocks in a mesh of clusters FPGA.

Degree: Docteur es, Electronique et communications, 2014, Paris, ENST

 Avec les réductions d'échelle, les circuits électroniques deviennent de plus en plus petits, plus performants, consommant moins de puissance, mais aussi moins fiables. En effet,… (more)

Subjects/Keywords: Circuit logique programmable; FPGA; Programmable logic device; FPGA

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APA (6th Edition):

Ben Dhia, A. (2014). Durcissement de circuits logiques reconfigurables : Hardening basic blocks in a mesh of clusters FPGA. (Doctoral Dissertation). Paris, ENST. Retrieved from http://www.theses.fr/2014ENST0068

Chicago Manual of Style (16th Edition):

Ben Dhia, Arwa. “Durcissement de circuits logiques reconfigurables : Hardening basic blocks in a mesh of clusters FPGA.” 2014. Doctoral Dissertation, Paris, ENST. Accessed September 23, 2020. http://www.theses.fr/2014ENST0068.

MLA Handbook (7th Edition):

Ben Dhia, Arwa. “Durcissement de circuits logiques reconfigurables : Hardening basic blocks in a mesh of clusters FPGA.” 2014. Web. 23 Sep 2020.

Vancouver:

Ben Dhia A. Durcissement de circuits logiques reconfigurables : Hardening basic blocks in a mesh of clusters FPGA. [Internet] [Doctoral dissertation]. Paris, ENST; 2014. [cited 2020 Sep 23]. Available from: http://www.theses.fr/2014ENST0068.

Council of Science Editors:

Ben Dhia A. Durcissement de circuits logiques reconfigurables : Hardening basic blocks in a mesh of clusters FPGA. [Doctoral Dissertation]. Paris, ENST; 2014. Available from: http://www.theses.fr/2014ENST0068


Ryerson University

8. Mutukuda, Omesh. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.

Degree: 2010, Ryerson University

 Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented application that are designed to process multiple-bit wide data. Studies have shown… (more)

Subjects/Keywords: Field programmable gate arrays; Integrated circuits

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APA (6th Edition):

Mutukuda, O. (2010). Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mutukuda, Omesh. “Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.” 2010. Thesis, Ryerson University. Accessed September 23, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A1868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mutukuda, Omesh. “Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.” 2010. Web. 23 Sep 2020.

Vancouver:

Mutukuda O. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. [Internet] [Thesis]. Ryerson University; 2010. [cited 2020 Sep 23]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mutukuda O. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

9. Casebeer, Christopher Ness. A system to eavesdrop on marmosets.

Degree: College of Engineering, 2015, Montana State University

 This masters thesis describes developing a custom digital recording system to record the vocalizations and behavior of marmosets, which are small primates native to the… (more)

Subjects/Keywords: Field programmable gate arrays.; Animal behavior.; Monkeys.

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APA (6th Edition):

Casebeer, C. N. (2015). A system to eavesdrop on marmosets. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/12731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Casebeer, Christopher Ness. “A system to eavesdrop on marmosets.” 2015. Thesis, Montana State University. Accessed September 23, 2020. https://scholarworks.montana.edu/xmlui/handle/1/12731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Casebeer, Christopher Ness. “A system to eavesdrop on marmosets.” 2015. Web. 23 Sep 2020.

Vancouver:

Casebeer CN. A system to eavesdrop on marmosets. [Internet] [Thesis]. Montana State University; 2015. [cited 2020 Sep 23]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Casebeer CN. A system to eavesdrop on marmosets. [Thesis]. Montana State University; 2015. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

10. Gilbert, John D. Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification.

Degree: MS, Electrical and Computer Engineering, 1988, Oregon State University

 Minimizing the number of product terms in a PLA implementation is a large step towards saving area on a VLSI chip using PLA logic. Due… (more)

Subjects/Keywords: Programmable array logic

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APA (6th Edition):

Gilbert, J. D. (1988). Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/40437

Chicago Manual of Style (16th Edition):

Gilbert, John D. “Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification.” 1988. Masters Thesis, Oregon State University. Accessed September 23, 2020. http://hdl.handle.net/1957/40437.

MLA Handbook (7th Edition):

Gilbert, John D. “Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification.” 1988. Web. 23 Sep 2020.

Vancouver:

Gilbert JD. Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification. [Internet] [Masters thesis]. Oregon State University; 1988. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/1957/40437.

Council of Science Editors:

Gilbert JD. Acceleration of a heuristic PLA product term reduction program through complementation of the PLA specification. [Masters Thesis]. Oregon State University; 1988. Available from: http://hdl.handle.net/1957/40437


Cornell University

11. Kalontarov, Michael. 3D Assembly For Programmable Matter And Hollow Fiber Membrane Gas Exchange In Planar Photobioreactors.

Degree: PhD, Mechanical Engineering, 2014, Cornell University

 In my Ph.D. research I have applied mechanical engineering knowledge and approaches to develop technologies for two topics: programmable matter and green energy through biofuels.… (more)

Subjects/Keywords: Photobioreactors; Hollow Fiber Membranes; Programmable Matter

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APA (6th Edition):

Kalontarov, M. (2014). 3D Assembly For Programmable Matter And Hollow Fiber Membrane Gas Exchange In Planar Photobioreactors. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/36130

Chicago Manual of Style (16th Edition):

Kalontarov, Michael. “3D Assembly For Programmable Matter And Hollow Fiber Membrane Gas Exchange In Planar Photobioreactors.” 2014. Doctoral Dissertation, Cornell University. Accessed September 23, 2020. http://hdl.handle.net/1813/36130.

MLA Handbook (7th Edition):

Kalontarov, Michael. “3D Assembly For Programmable Matter And Hollow Fiber Membrane Gas Exchange In Planar Photobioreactors.” 2014. Web. 23 Sep 2020.

Vancouver:

Kalontarov M. 3D Assembly For Programmable Matter And Hollow Fiber Membrane Gas Exchange In Planar Photobioreactors. [Internet] [Doctoral dissertation]. Cornell University; 2014. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/1813/36130.

Council of Science Editors:

Kalontarov M. 3D Assembly For Programmable Matter And Hollow Fiber Membrane Gas Exchange In Planar Photobioreactors. [Doctoral Dissertation]. Cornell University; 2014. Available from: http://hdl.handle.net/1813/36130


Cornell University

12. Krishnan, Mekala. Active Fluid Mechanics For Programmable Matter.

Degree: PhD, Mechanical Engineering, 2011, Cornell University

 In this research I have explored the use of fluid mechanics to create programmable matter. Programmable, reconfigurable systems are those whose properties can be reconfigured… (more)

Subjects/Keywords: Microfluidics; Optofluidics; Programmable Matter; Assembly; Reconfigurable Microfluidics

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APA (6th Edition):

Krishnan, M. (2011). Active Fluid Mechanics For Programmable Matter. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/30692

Chicago Manual of Style (16th Edition):

Krishnan, Mekala. “Active Fluid Mechanics For Programmable Matter.” 2011. Doctoral Dissertation, Cornell University. Accessed September 23, 2020. http://hdl.handle.net/1813/30692.

MLA Handbook (7th Edition):

Krishnan, Mekala. “Active Fluid Mechanics For Programmable Matter.” 2011. Web. 23 Sep 2020.

Vancouver:

Krishnan M. Active Fluid Mechanics For Programmable Matter. [Internet] [Doctoral dissertation]. Cornell University; 2011. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/1813/30692.

Council of Science Editors:

Krishnan M. Active Fluid Mechanics For Programmable Matter. [Doctoral Dissertation]. Cornell University; 2011. Available from: http://hdl.handle.net/1813/30692


Drexel University

13. Petrovich, Mark Jr. Virtual Cultural Heritage: Virtual Reality Navigation of Cultural Heritage Environments.

Degree: 2015, Drexel University

With the plethora of digital devices that can provide information about almost anything anywhere the Virtual Cultural Heritage project implements a prototype for the integration… (more)

Subjects/Keywords: Digital media; Virtual reality; Kinect (Programmable controller)

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APA (6th Edition):

Petrovich, M. J. (2015). Virtual Cultural Heritage: Virtual Reality Navigation of Cultural Heritage Environments. (Thesis). Drexel University. Retrieved from http://hdl.handle.net/1860/idea:6517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Petrovich, Mark Jr. “Virtual Cultural Heritage: Virtual Reality Navigation of Cultural Heritage Environments.” 2015. Thesis, Drexel University. Accessed September 23, 2020. http://hdl.handle.net/1860/idea:6517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Petrovich, Mark Jr. “Virtual Cultural Heritage: Virtual Reality Navigation of Cultural Heritage Environments.” 2015. Web. 23 Sep 2020.

Vancouver:

Petrovich MJ. Virtual Cultural Heritage: Virtual Reality Navigation of Cultural Heritage Environments. [Internet] [Thesis]. Drexel University; 2015. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/1860/idea:6517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Petrovich MJ. Virtual Cultural Heritage: Virtual Reality Navigation of Cultural Heritage Environments. [Thesis]. Drexel University; 2015. Available from: http://hdl.handle.net/1860/idea:6517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

14. Turner, David Lee Douglas. Implementation of a radiation-tolerant computer based on a LEON3 architecture.

Degree: College of Engineering, 2015, Montana State University

 It is desired to create an inexpensive, open-source, radiation-tolerant computer for space applications using commercial, off-the-shelf parts and a proven space-grade processor. Building upon previous… (more)

Subjects/Keywords: Field programmable gate arrays.; Radiation.; Computer software.

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APA (6th Edition):

Turner, D. L. D. (2015). Implementation of a radiation-tolerant computer based on a LEON3 architecture. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/10163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Turner, David Lee Douglas. “Implementation of a radiation-tolerant computer based on a LEON3 architecture.” 2015. Thesis, Montana State University. Accessed September 23, 2020. https://scholarworks.montana.edu/xmlui/handle/1/10163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Turner, David Lee Douglas. “Implementation of a radiation-tolerant computer based on a LEON3 architecture.” 2015. Web. 23 Sep 2020.

Vancouver:

Turner DLD. Implementation of a radiation-tolerant computer based on a LEON3 architecture. [Internet] [Thesis]. Montana State University; 2015. [cited 2020 Sep 23]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/10163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Turner DLD. Implementation of a radiation-tolerant computer based on a LEON3 architecture. [Thesis]. Montana State University; 2015. Available from: https://scholarworks.montana.edu/xmlui/handle/1/10163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Koudri, Ali. Processus de conception conjointe logiciel matériel dirigés par les modèles : Co-design process software-hardware model driven.

Degree: Docteur es, Informatique, 2010, Université Lille I – Sciences et Technologies

L'ingénierie des modèles (IDM) a depuis très largement démontré sa pertinence dans les développements logiciels; restait alors à démontrer son applicabilité dans le développement de… (more)

Subjects/Keywords: Système sur puce programmable; Langage SPEM; 004.21

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APA (6th Edition):

Koudri, A. (2010). Processus de conception conjointe logiciel matériel dirigés par les modèles : Co-design process software-hardware model driven. (Doctoral Dissertation). Université Lille I – Sciences et Technologies. Retrieved from http://www.theses.fr/2010LIL10181

Chicago Manual of Style (16th Edition):

Koudri, Ali. “Processus de conception conjointe logiciel matériel dirigés par les modèles : Co-design process software-hardware model driven.” 2010. Doctoral Dissertation, Université Lille I – Sciences et Technologies. Accessed September 23, 2020. http://www.theses.fr/2010LIL10181.

MLA Handbook (7th Edition):

Koudri, Ali. “Processus de conception conjointe logiciel matériel dirigés par les modèles : Co-design process software-hardware model driven.” 2010. Web. 23 Sep 2020.

Vancouver:

Koudri A. Processus de conception conjointe logiciel matériel dirigés par les modèles : Co-design process software-hardware model driven. [Internet] [Doctoral dissertation]. Université Lille I – Sciences et Technologies; 2010. [cited 2020 Sep 23]. Available from: http://www.theses.fr/2010LIL10181.

Council of Science Editors:

Koudri A. Processus de conception conjointe logiciel matériel dirigés par les modèles : Co-design process software-hardware model driven. [Doctoral Dissertation]. Université Lille I – Sciences et Technologies; 2010. Available from: http://www.theses.fr/2010LIL10181


University of Toronto

16. Fard, Miad. An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters.

Degree: 2016, University of Toronto

In this thesis, two Phase-Locked-Loop (PLL) based synchronization schemes are introduced and applied to a bi-directional Dual-Active-Bridge (DAB) dc-dc converter with an input voltage up… (more)

Subjects/Keywords: DAB; Isolated; Photovoltaics; PLL; Programmable; Synchronization; 0544

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fard, M. (2016). An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/72693

Chicago Manual of Style (16th Edition):

Fard, Miad. “An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters.” 2016. Masters Thesis, University of Toronto. Accessed September 23, 2020. http://hdl.handle.net/1807/72693.

MLA Handbook (7th Edition):

Fard, Miad. “An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters.” 2016. Web. 23 Sep 2020.

Vancouver:

Fard M. An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters. [Internet] [Masters thesis]. University of Toronto; 2016. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/1807/72693.

Council of Science Editors:

Fard M. An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters. [Masters Thesis]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/72693


NSYSU

17. Chen, Li-Yao. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations… (more)

Subjects/Keywords: Integration; SOC; Programmable; SIMD; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, L. (2010). Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Thesis, NSYSU. Accessed September 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Web. 23 Sep 2020.

Vancouver:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. 早苗, 駿一. PPCに基づく歩留まり改善に向けた論理最適化 : Logic Optimizations for Yield Improvement based on PPCs; PPC ニ モトズク ブドマリ カイゼン ニ ムケタ ロンリ サイテキカ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Partially-Programmable Circuit

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APA (6th Edition):

早苗, . (n.d.). PPCに基づく歩留まり改善に向けた論理最適化 : Logic Optimizations for Yield Improvement based on PPCs; PPC ニ モトズク ブドマリ カイゼン ニ ムケタ ロンリ サイテキカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/9398

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

早苗, 駿一. “PPCに基づく歩留まり改善に向けた論理最適化 : Logic Optimizations for Yield Improvement based on PPCs; PPC ニ モトズク ブドマリ カイゼン ニ ムケタ ロンリ サイテキカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed September 23, 2020. http://hdl.handle.net/10061/9398.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

早苗, 駿一. “PPCに基づく歩留まり改善に向けた論理最適化 : Logic Optimizations for Yield Improvement based on PPCs; PPC ニ モトズク ブドマリ カイゼン ニ ムケタ ロンリ サイテキカ.” Web. 23 Sep 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

早苗 . PPCに基づく歩留まり改善に向けた論理最適化 : Logic Optimizations for Yield Improvement based on PPCs; PPC ニ モトズク ブドマリ カイゼン ニ ムケタ ロンリ サイテキカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2020 Sep 23]. Available from: http://hdl.handle.net/10061/9398.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

早苗 . PPCに基づく歩留まり改善に向けた論理最適化 : Logic Optimizations for Yield Improvement based on PPCs; PPC ニ モトズク ブドマリ カイゼン ニ ムケタ ロンリ サイテキカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/9398

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


UCLA

19. Mohamed, Mohamed Ismail Ali. MIMO Accelerator: Programmable MIMO Decoder Chip and Design Environment.

Degree: Electrical Engineering, 2012, UCLA

 With wireless communications becoming an essential part of human life, wireless technology advances to meet the increasing demands. New standards are introduced every couple of… (more)

Subjects/Keywords: Electrical engineering; Decoder; Equalization; MIMO; OFDM; Programmable

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mohamed, M. I. A. (2012). MIMO Accelerator: Programmable MIMO Decoder Chip and Design Environment. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/0x34m19n

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mohamed, Mohamed Ismail Ali. “MIMO Accelerator: Programmable MIMO Decoder Chip and Design Environment.” 2012. Thesis, UCLA. Accessed September 23, 2020. http://www.escholarship.org/uc/item/0x34m19n.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mohamed, Mohamed Ismail Ali. “MIMO Accelerator: Programmable MIMO Decoder Chip and Design Environment.” 2012. Web. 23 Sep 2020.

Vancouver:

Mohamed MIA. MIMO Accelerator: Programmable MIMO Decoder Chip and Design Environment. [Internet] [Thesis]. UCLA; 2012. [cited 2020 Sep 23]. Available from: http://www.escholarship.org/uc/item/0x34m19n.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mohamed MIA. MIMO Accelerator: Programmable MIMO Decoder Chip and Design Environment. [Thesis]. UCLA; 2012. Available from: http://www.escholarship.org/uc/item/0x34m19n

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

20. Moorman, Anna Julia. Alternate Fault testing on a Bus on a Dynamic Position Vessel.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Direct fault testing onboard Dynamic Position Vessels is a requirement to maintain the ships classification and ensure redundancy of the power system onboard to maintain… (more)

Subjects/Keywords: Dynamic Position; Fault testing; Programmable Logic Controller

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moorman, A. J. (2015). Alternate Fault testing on a Bus on a Dynamic Position Vessel. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/56568

Chicago Manual of Style (16th Edition):

Moorman, Anna Julia. “Alternate Fault testing on a Bus on a Dynamic Position Vessel.” 2015. Masters Thesis, Virginia Tech. Accessed September 23, 2020. http://hdl.handle.net/10919/56568.

MLA Handbook (7th Edition):

Moorman, Anna Julia. “Alternate Fault testing on a Bus on a Dynamic Position Vessel.” 2015. Web. 23 Sep 2020.

Vancouver:

Moorman AJ. Alternate Fault testing on a Bus on a Dynamic Position Vessel. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/10919/56568.

Council of Science Editors:

Moorman AJ. Alternate Fault testing on a Bus on a Dynamic Position Vessel. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/56568


Virginia Tech

21. Rice, Maryjoe Kathryn. Programmable Microparticle Scaffolds for Enhanced Diagnostic Devices.

Degree: MS, Mechanical Engineering, 2017, Virginia Tech

 Microrobotics is an emerging discipline with the potential to radically affect fields ranging from medicine to environmental stewardship. Already, there have been remarkable breakthroughs; small… (more)

Subjects/Keywords: Synthetic biology; cell-free systems; programmable microparticles

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APA (6th Edition):

Rice, M. K. (2017). Programmable Microparticle Scaffolds for Enhanced Diagnostic Devices. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78267

Chicago Manual of Style (16th Edition):

Rice, Maryjoe Kathryn. “Programmable Microparticle Scaffolds for Enhanced Diagnostic Devices.” 2017. Masters Thesis, Virginia Tech. Accessed September 23, 2020. http://hdl.handle.net/10919/78267.

MLA Handbook (7th Edition):

Rice, Maryjoe Kathryn. “Programmable Microparticle Scaffolds for Enhanced Diagnostic Devices.” 2017. Web. 23 Sep 2020.

Vancouver:

Rice MK. Programmable Microparticle Scaffolds for Enhanced Diagnostic Devices. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/10919/78267.

Council of Science Editors:

Rice MK. Programmable Microparticle Scaffolds for Enhanced Diagnostic Devices. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78267

22. Tahmasbi Arashloo, Mina. Stateful Programming of High-Speed Network Hardware .

Degree: PhD, 2019, Princeton University

 Modern networks need to operate at speeds as high as 100Gbps while running sophisticated algorithms and protocols to provide strict performance, security and reliability guarantees.… (more)

Subjects/Keywords: Computer Networks; Network Hardware; Programmable Networks

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tahmasbi Arashloo, M. (2019). Stateful Programming of High-Speed Network Hardware . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01fq977x65s

Chicago Manual of Style (16th Edition):

Tahmasbi Arashloo, Mina. “Stateful Programming of High-Speed Network Hardware .” 2019. Doctoral Dissertation, Princeton University. Accessed September 23, 2020. http://arks.princeton.edu/ark:/88435/dsp01fq977x65s.

MLA Handbook (7th Edition):

Tahmasbi Arashloo, Mina. “Stateful Programming of High-Speed Network Hardware .” 2019. Web. 23 Sep 2020.

Vancouver:

Tahmasbi Arashloo M. Stateful Programming of High-Speed Network Hardware . [Internet] [Doctoral dissertation]. Princeton University; 2019. [cited 2020 Sep 23]. Available from: http://arks.princeton.edu/ark:/88435/dsp01fq977x65s.

Council of Science Editors:

Tahmasbi Arashloo M. Stateful Programming of High-Speed Network Hardware . [Doctoral Dissertation]. Princeton University; 2019. Available from: http://arks.princeton.edu/ark:/88435/dsp01fq977x65s


Rutgers University

23. Mahmood, Bashar Abdulaziz. Lower body gait analysis through real time gait parameter measurements using KINECT.

Degree: MS, Electrical and Computer Engineering, 2015, Rutgers University

 Gait analysis is one of the important areas of research, with applications including diagnosis, monitoring, and rehabilitation. Current gait analysis systems, such as those used… (more)

Subjects/Keywords: Gait in humans; Kinect (Programmable controller); Ankle

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mahmood, B. A. (2015). Lower body gait analysis through real time gait parameter measurements using KINECT. (Masters Thesis). Rutgers University. Retrieved from https://rucore.libraries.rutgers.edu/rutgers-lib/46391/

Chicago Manual of Style (16th Edition):

Mahmood, Bashar Abdulaziz. “Lower body gait analysis through real time gait parameter measurements using KINECT.” 2015. Masters Thesis, Rutgers University. Accessed September 23, 2020. https://rucore.libraries.rutgers.edu/rutgers-lib/46391/.

MLA Handbook (7th Edition):

Mahmood, Bashar Abdulaziz. “Lower body gait analysis through real time gait parameter measurements using KINECT.” 2015. Web. 23 Sep 2020.

Vancouver:

Mahmood BA. Lower body gait analysis through real time gait parameter measurements using KINECT. [Internet] [Masters thesis]. Rutgers University; 2015. [cited 2020 Sep 23]. Available from: https://rucore.libraries.rutgers.edu/rutgers-lib/46391/.

Council of Science Editors:

Mahmood BA. Lower body gait analysis through real time gait parameter measurements using KINECT. [Masters Thesis]. Rutgers University; 2015. Available from: https://rucore.libraries.rutgers.edu/rutgers-lib/46391/


Michigan State University

24. Chang, Tsin-Yuan. Design of fault-tolerant programmable logic arrays for yield enhancement.

Degree: PhD, Department of Electrical Engineering, 1989, Michigan State University

Subjects/Keywords: Programmable array logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, T. (1989). Design of fault-tolerant programmable logic arrays for yield enhancement. (Doctoral Dissertation). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:25463

Chicago Manual of Style (16th Edition):

Chang, Tsin-Yuan. “Design of fault-tolerant programmable logic arrays for yield enhancement.” 1989. Doctoral Dissertation, Michigan State University. Accessed September 23, 2020. http://etd.lib.msu.edu/islandora/object/etd:25463.

MLA Handbook (7th Edition):

Chang, Tsin-Yuan. “Design of fault-tolerant programmable logic arrays for yield enhancement.” 1989. Web. 23 Sep 2020.

Vancouver:

Chang T. Design of fault-tolerant programmable logic arrays for yield enhancement. [Internet] [Doctoral dissertation]. Michigan State University; 1989. [cited 2020 Sep 23]. Available from: http://etd.lib.msu.edu/islandora/object/etd:25463.

Council of Science Editors:

Chang T. Design of fault-tolerant programmable logic arrays for yield enhancement. [Doctoral Dissertation]. Michigan State University; 1989. Available from: http://etd.lib.msu.edu/islandora/object/etd:25463


Michigan State University

25. Chang, Tsin-Yuan. The design of testable programmable logic arrays.

Degree: MS, Department of Electric Engineering and Systems Science, 1987, Michigan State University

Subjects/Keywords: Programmable array logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, T. (1987). The design of testable programmable logic arrays. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:46649

Chicago Manual of Style (16th Edition):

Chang, Tsin-Yuan. “The design of testable programmable logic arrays.” 1987. Masters Thesis, Michigan State University. Accessed September 23, 2020. http://etd.lib.msu.edu/islandora/object/etd:46649.

MLA Handbook (7th Edition):

Chang, Tsin-Yuan. “The design of testable programmable logic arrays.” 1987. Web. 23 Sep 2020.

Vancouver:

Chang T. The design of testable programmable logic arrays. [Internet] [Masters thesis]. Michigan State University; 1987. [cited 2020 Sep 23]. Available from: http://etd.lib.msu.edu/islandora/object/etd:46649.

Council of Science Editors:

Chang T. The design of testable programmable logic arrays. [Masters Thesis]. Michigan State University; 1987. Available from: http://etd.lib.msu.edu/islandora/object/etd:46649


Delft University of Technology

26. Rautmare, Shardul (author). A Programmable Temperature Switch.

Degree: 2019, Delft University of Technology

Temperature threshold sensors facilitate temperature protection in microprocessors by indicating when the processor gets overheated or too cold. This thesis presents a BJT based temperature… (more)

Subjects/Keywords: BJT; Temperature Switch; Trimming; Programmable; offset

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rautmare, S. (. (2019). A Programmable Temperature Switch. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6d2746d7-7ba0-4274-a79e-deb6dd72cd3f

Chicago Manual of Style (16th Edition):

Rautmare, Shardul (author). “A Programmable Temperature Switch.” 2019. Masters Thesis, Delft University of Technology. Accessed September 23, 2020. http://resolver.tudelft.nl/uuid:6d2746d7-7ba0-4274-a79e-deb6dd72cd3f.

MLA Handbook (7th Edition):

Rautmare, Shardul (author). “A Programmable Temperature Switch.” 2019. Web. 23 Sep 2020.

Vancouver:

Rautmare S(. A Programmable Temperature Switch. [Internet] [Masters thesis]. Delft University of Technology; 2019. [cited 2020 Sep 23]. Available from: http://resolver.tudelft.nl/uuid:6d2746d7-7ba0-4274-a79e-deb6dd72cd3f.

Council of Science Editors:

Rautmare S(. A Programmable Temperature Switch. [Masters Thesis]. Delft University of Technology; 2019. Available from: http://resolver.tudelft.nl/uuid:6d2746d7-7ba0-4274-a79e-deb6dd72cd3f


Texas Tech University

27. Kannappan, Karthikeyan. Partition-based algorithms for PLA folding.

Degree: Computer Science, 1989, Texas Tech University

Subjects/Keywords: Programmable array logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kannappan, K. (1989). Partition-based algorithms for PLA folding. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/16433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kannappan, Karthikeyan. “Partition-based algorithms for PLA folding.” 1989. Thesis, Texas Tech University. Accessed September 23, 2020. http://hdl.handle.net/2346/16433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kannappan, Karthikeyan. “Partition-based algorithms for PLA folding.” 1989. Web. 23 Sep 2020.

Vancouver:

Kannappan K. Partition-based algorithms for PLA folding. [Internet] [Thesis]. Texas Tech University; 1989. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/2346/16433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kannappan K. Partition-based algorithms for PLA folding. [Thesis]. Texas Tech University; 1989. Available from: http://hdl.handle.net/2346/16433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

28. Slováček, František. Realizace programovatelného posuvu mikroskopu v ose z: Realisation of USB microscope programmable movement in axis z.

Degree: 2019, Brno University of Technology

 This bachalor thesis discuss about realization of USB microscope programmable movement in axis Z. The first chapter desribes solder joint and its quality requirements and… (more)

Subjects/Keywords: Mikroskop; posuv; programovatelný; Microscope; movement; programmable

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APA (6th Edition):

Slováček, F. (2019). Realizace programovatelného posuvu mikroskopu v ose z: Realisation of USB microscope programmable movement in axis z. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/12120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Slováček, František. “Realizace programovatelného posuvu mikroskopu v ose z: Realisation of USB microscope programmable movement in axis z.” 2019. Thesis, Brno University of Technology. Accessed September 23, 2020. http://hdl.handle.net/11012/12120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Slováček, František. “Realizace programovatelného posuvu mikroskopu v ose z: Realisation of USB microscope programmable movement in axis z.” 2019. Web. 23 Sep 2020.

Vancouver:

Slováček F. Realizace programovatelného posuvu mikroskopu v ose z: Realisation of USB microscope programmable movement in axis z. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/11012/12120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Slováček F. Realizace programovatelného posuvu mikroskopu v ose z: Realisation of USB microscope programmable movement in axis z. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/12120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Chico

29. Powers, David J. Effects of Parallelization on Genetic Algorithms in Programmable Logic: Implementing a Solution to the Traveling Salesman Problem .

Degree: 2012, California State University – Chico

 EFFECTS OF PARALLELIZATION ON GENETIC ALGORITHMS IN PROGRAMMABLE LOGIC: IMPLEMENTING A SOLUTION TO THE TRAVELING SALESMAN PROBLEM by David J. Powers Master of Science in… (more)

Subjects/Keywords: Genetic Algorithems; Programmable Logic; Traveling Salesman Problem

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APA (6th Edition):

Powers, D. J. (2012). Effects of Parallelization on Genetic Algorithms in Programmable Logic: Implementing a Solution to the Traveling Salesman Problem . (Thesis). California State University – Chico. Retrieved from http://hdl.handle.net/10211.4/397

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Powers, David J. “Effects of Parallelization on Genetic Algorithms in Programmable Logic: Implementing a Solution to the Traveling Salesman Problem .” 2012. Thesis, California State University – Chico. Accessed September 23, 2020. http://hdl.handle.net/10211.4/397.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Powers, David J. “Effects of Parallelization on Genetic Algorithms in Programmable Logic: Implementing a Solution to the Traveling Salesman Problem .” 2012. Web. 23 Sep 2020.

Vancouver:

Powers DJ. Effects of Parallelization on Genetic Algorithms in Programmable Logic: Implementing a Solution to the Traveling Salesman Problem . [Internet] [Thesis]. California State University – Chico; 2012. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/10211.4/397.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Powers DJ. Effects of Parallelization on Genetic Algorithms in Programmable Logic: Implementing a Solution to the Traveling Salesman Problem . [Thesis]. California State University – Chico; 2012. Available from: http://hdl.handle.net/10211.4/397

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of British Columbia

30. Quinton, Bradley. A reconfigurable post-silicon debug infrastructure for systems-on-chip .

Degree: 2008, University of British Columbia

 As the level of integrated circuit (IC) complexity continues to increase, the post-silicon validation stage is becoming a large component of the overall development cost.… (more)

Subjects/Keywords: Debug; Programmable logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Quinton, B. (2008). A reconfigurable post-silicon debug infrastructure for systems-on-chip . (Thesis). University of British Columbia. Retrieved from http://hdl.handle.net/2429/2686

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Quinton, Bradley. “A reconfigurable post-silicon debug infrastructure for systems-on-chip .” 2008. Thesis, University of British Columbia. Accessed September 23, 2020. http://hdl.handle.net/2429/2686.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Quinton, Bradley. “A reconfigurable post-silicon debug infrastructure for systems-on-chip .” 2008. Web. 23 Sep 2020.

Vancouver:

Quinton B. A reconfigurable post-silicon debug infrastructure for systems-on-chip . [Internet] [Thesis]. University of British Columbia; 2008. [cited 2020 Sep 23]. Available from: http://hdl.handle.net/2429/2686.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Quinton B. A reconfigurable post-silicon debug infrastructure for systems-on-chip . [Thesis]. University of British Columbia; 2008. Available from: http://hdl.handle.net/2429/2686

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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