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You searched for subject:(Processors). Showing records 1 – 30 of 408 total matches.

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University of Edinburgh

1. Jones, Timothy M. Compiler-directed energy savings in superscalar processors.

Degree: 2006, University of Edinburgh

 Superscalar processors contain large, complex structures to hold data and instructions as they wait to be executed. However, many of these structures consume large amounts… (more)

Subjects/Keywords: 004; Superscalar processors; complex processors

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APA (6th Edition):

Jones, T. M. (2006). Compiler-directed energy savings in superscalar processors. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/864

Chicago Manual of Style (16th Edition):

Jones, Timothy M. “Compiler-directed energy savings in superscalar processors.” 2006. Doctoral Dissertation, University of Edinburgh. Accessed January 29, 2020. http://hdl.handle.net/1842/864.

MLA Handbook (7th Edition):

Jones, Timothy M. “Compiler-directed energy savings in superscalar processors.” 2006. Web. 29 Jan 2020.

Vancouver:

Jones TM. Compiler-directed energy savings in superscalar processors. [Internet] [Doctoral dissertation]. University of Edinburgh; 2006. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1842/864.

Council of Science Editors:

Jones TM. Compiler-directed energy savings in superscalar processors. [Doctoral Dissertation]. University of Edinburgh; 2006. Available from: http://hdl.handle.net/1842/864


Rochester Institute of Technology

2. Nichols, Stephen. Design and synthesis of a high-performance, hyper-programmable DSP on an FPGA.

Degree: Computer Engineering, 2011, Rochester Institute of Technology

 In the field of high performance digital signal processing, DSPs and FPGAs provide the most flexibility. Due to the extensive customization available on FPGAs, DSP… (more)

Subjects/Keywords: Digital signal processors

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APA (6th Edition):

Nichols, S. (2011). Design and synthesis of a high-performance, hyper-programmable DSP on an FPGA. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3179

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nichols, Stephen. “Design and synthesis of a high-performance, hyper-programmable DSP on an FPGA.” 2011. Thesis, Rochester Institute of Technology. Accessed January 29, 2020. https://scholarworks.rit.edu/theses/3179.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nichols, Stephen. “Design and synthesis of a high-performance, hyper-programmable DSP on an FPGA.” 2011. Web. 29 Jan 2020.

Vancouver:

Nichols S. Design and synthesis of a high-performance, hyper-programmable DSP on an FPGA. [Internet] [Thesis]. Rochester Institute of Technology; 2011. [cited 2020 Jan 29]. Available from: https://scholarworks.rit.edu/theses/3179.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nichols S. Design and synthesis of a high-performance, hyper-programmable DSP on an FPGA. [Thesis]. Rochester Institute of Technology; 2011. Available from: https://scholarworks.rit.edu/theses/3179

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

3. Khogali, Rashid. Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors.

Degree: 2013, Ryerson University

 We synthesize online scheduling algorithms to optimally assign a set of arriving heterogeneous tasks to heterogeneous speed-scalable processors under the single threaded computing architecture. By… (more)

Subjects/Keywords: High performance processors

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APA (6th Edition):

Khogali, R. (2013). Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A2919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khogali, Rashid. “Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors.” 2013. Thesis, Ryerson University. Accessed January 29, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A2919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khogali, Rashid. “Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors.” 2013. Web. 29 Jan 2020.

Vancouver:

Khogali R. Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors. [Internet] [Thesis]. Ryerson University; 2013. [cited 2020 Jan 29]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A2919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khogali R. Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors. [Thesis]. Ryerson University; 2013. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A2919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

4. Durgam, Jaisimha K. Dynamically configurable systolic arrays.

Degree: MS, Electrical and Computer Engineering, 1988, Oregon State University

 Digital signal and image processing and other real time applications involve simple but large amounts of computations. These problems have an enormous amount of inherent… (more)

Subjects/Keywords: Array processors

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APA (6th Edition):

Durgam, J. K. (1988). Dynamically configurable systolic arrays. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39843

Chicago Manual of Style (16th Edition):

Durgam, Jaisimha K. “Dynamically configurable systolic arrays.” 1988. Masters Thesis, Oregon State University. Accessed January 29, 2020. http://hdl.handle.net/1957/39843.

MLA Handbook (7th Edition):

Durgam, Jaisimha K. “Dynamically configurable systolic arrays.” 1988. Web. 29 Jan 2020.

Vancouver:

Durgam JK. Dynamically configurable systolic arrays. [Internet] [Masters thesis]. Oregon State University; 1988. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1957/39843.

Council of Science Editors:

Durgam JK. Dynamically configurable systolic arrays. [Masters Thesis]. Oregon State University; 1988. Available from: http://hdl.handle.net/1957/39843


Oregon State University

5. Zier, David A. The dynamic speculation and performance prediction of parallel loops.

Degree: PhD, Electrical and Computer Engineering, 2009, Oregon State University

 General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained… (more)

Subjects/Keywords: Computer Architecture; Simultaneous multithreading processors

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APA (6th Edition):

Zier, D. A. (2009). The dynamic speculation and performance prediction of parallel loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/11579

Chicago Manual of Style (16th Edition):

Zier, David A. “The dynamic speculation and performance prediction of parallel loops.” 2009. Doctoral Dissertation, Oregon State University. Accessed January 29, 2020. http://hdl.handle.net/1957/11579.

MLA Handbook (7th Edition):

Zier, David A. “The dynamic speculation and performance prediction of parallel loops.” 2009. Web. 29 Jan 2020.

Vancouver:

Zier DA. The dynamic speculation and performance prediction of parallel loops. [Internet] [Doctoral dissertation]. Oregon State University; 2009. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1957/11579.

Council of Science Editors:

Zier DA. The dynamic speculation and performance prediction of parallel loops. [Doctoral Dissertation]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/11579

6. Ausavarungnirun, Rachata. Techniques for Shared Resource Management in Systems with Throughput Processors.

Degree: 2017, Carnegie Mellon University

 The continued growth of the computational capability of throughput processors has made throughput processors the platform of choice for a wide variety of high performance… (more)

Subjects/Keywords: GPU; Resource Management; Throughput Processors

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APA (6th Edition):

Ausavarungnirun, R. (2017). Techniques for Shared Resource Management in Systems with Throughput Processors. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ausavarungnirun, Rachata. “Techniques for Shared Resource Management in Systems with Throughput Processors.” 2017. Thesis, Carnegie Mellon University. Accessed January 29, 2020. http://repository.cmu.edu/dissertations/905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ausavarungnirun, Rachata. “Techniques for Shared Resource Management in Systems with Throughput Processors.” 2017. Web. 29 Jan 2020.

Vancouver:

Ausavarungnirun R. Techniques for Shared Resource Management in Systems with Throughput Processors. [Internet] [Thesis]. Carnegie Mellon University; 2017. [cited 2020 Jan 29]. Available from: http://repository.cmu.edu/dissertations/905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ausavarungnirun R. Techniques for Shared Resource Management in Systems with Throughput Processors. [Thesis]. Carnegie Mellon University; 2017. Available from: http://repository.cmu.edu/dissertations/905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

7. Li, Aihua. Synthesis of multi-rate arrays from directional uniform recurrence equations.

Degree: MS, Electrical and Computer Engineering, 1990, Oregon State University

 Advances in VLSI array processing have led to many new parallel structures for real-time Digital Signal Processing (DSP) applications. Among all the architectures, systolic arrays… (more)

Subjects/Keywords: Array processors

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APA (6th Edition):

Li, A. (1990). Synthesis of multi-rate arrays from directional uniform recurrence equations. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39873

Chicago Manual of Style (16th Edition):

Li, Aihua. “Synthesis of multi-rate arrays from directional uniform recurrence equations.” 1990. Masters Thesis, Oregon State University. Accessed January 29, 2020. http://hdl.handle.net/1957/39873.

MLA Handbook (7th Edition):

Li, Aihua. “Synthesis of multi-rate arrays from directional uniform recurrence equations.” 1990. Web. 29 Jan 2020.

Vancouver:

Li A. Synthesis of multi-rate arrays from directional uniform recurrence equations. [Internet] [Masters thesis]. Oregon State University; 1990. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1957/39873.

Council of Science Editors:

Li A. Synthesis of multi-rate arrays from directional uniform recurrence equations. [Masters Thesis]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/39873


Kansas State University

8. Schmidt, David A., 1953 May 10-. Design and implementation of a general purpose macroprocessor for software conversion.

Degree: 1977, Kansas State University

Subjects/Keywords: Macro processors

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APA (6th Edition):

Schmidt, David A., 1. M. 1. (1977). Design and implementation of a general purpose macroprocessor for software conversion. (Thesis). Kansas State University. Retrieved from http://hdl.handle.net/2097/9047

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Schmidt, David A., 1953 May 10-. “Design and implementation of a general purpose macroprocessor for software conversion.” 1977. Thesis, Kansas State University. Accessed January 29, 2020. http://hdl.handle.net/2097/9047.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Schmidt, David A., 1953 May 10-. “Design and implementation of a general purpose macroprocessor for software conversion.” 1977. Web. 29 Jan 2020.

Vancouver:

Schmidt, David A. 1M1. Design and implementation of a general purpose macroprocessor for software conversion. [Internet] [Thesis]. Kansas State University; 1977. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2097/9047.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Schmidt, David A. 1M1. Design and implementation of a general purpose macroprocessor for software conversion. [Thesis]. Kansas State University; 1977. Available from: http://hdl.handle.net/2097/9047

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

9. Chandramohan, Kiran. Mapping parallelism to heterogeneous processors.

Degree: PhD, 2016, University of Edinburgh

 Most embedded devices are based on heterogeneous Multiprocessor System on Chips (MPSoCs). These contain a variety of processors like CPUs, micro-controllers, DSPs, GPUs and specialised… (more)

Subjects/Keywords: 004; heterogeneous processors; compiler

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APA (6th Edition):

Chandramohan, K. (2016). Mapping parallelism to heterogeneous processors. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/22028

Chicago Manual of Style (16th Edition):

Chandramohan, Kiran. “Mapping parallelism to heterogeneous processors.” 2016. Doctoral Dissertation, University of Edinburgh. Accessed January 29, 2020. http://hdl.handle.net/1842/22028.

MLA Handbook (7th Edition):

Chandramohan, Kiran. “Mapping parallelism to heterogeneous processors.” 2016. Web. 29 Jan 2020.

Vancouver:

Chandramohan K. Mapping parallelism to heterogeneous processors. [Internet] [Doctoral dissertation]. University of Edinburgh; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1842/22028.

Council of Science Editors:

Chandramohan K. Mapping parallelism to heterogeneous processors. [Doctoral Dissertation]. University of Edinburgh; 2016. Available from: http://hdl.handle.net/1842/22028


Nelson Mandela Metropolitan University

10. [No author]. Scoping of a commercial micro reformer for the production of hydrogen.

Degree: Faculty of Science, 2016, Nelson Mandela Metropolitan University

 Hydrogen has gained interest as fuel recently as the harmful effects of fossil fuels on the environment can no longer be ignored. Hydrogen, which produces… (more)

Subjects/Keywords: Hydrogen as fuel; Fuel processors

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APA (6th Edition):

author], [. (2016). Scoping of a commercial micro reformer for the production of hydrogen. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/8175

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “Scoping of a commercial micro reformer for the production of hydrogen.” 2016. Thesis, Nelson Mandela Metropolitan University. Accessed January 29, 2020. http://hdl.handle.net/10948/8175.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “Scoping of a commercial micro reformer for the production of hydrogen.” 2016. Web. 29 Jan 2020.

Vancouver:

author] [. Scoping of a commercial micro reformer for the production of hydrogen. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10948/8175.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Scoping of a commercial micro reformer for the production of hydrogen. [Thesis]. Nelson Mandela Metropolitan University; 2016. Available from: http://hdl.handle.net/10948/8175

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Li, Dong, active 21st century. Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors.

Degree: PhD, Computer Science, 2014, University of Texas – Austin

 Throughput processors such as GPUs continue to provide higher peak arithmetic capability. Designing a high throughput memory system to keep the computational units busy is… (more)

Subjects/Keywords: Throughput processors; GPU; Architecture

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APA (6th Edition):

Li, Dong, a. 2. c. (2014). Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/25098

Chicago Manual of Style (16th Edition):

Li, Dong, active 21st century. “Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed January 29, 2020. http://hdl.handle.net/2152/25098.

MLA Handbook (7th Edition):

Li, Dong, active 21st century. “Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors.” 2014. Web. 29 Jan 2020.

Vancouver:

Li, Dong a2c. Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2152/25098.

Council of Science Editors:

Li, Dong a2c. Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/25098


Uppsala University

12. Karlsson, Johan. Efficient use of Multi-core Technology in Interactive Desktop Applications.

Degree: Information Technology, 2015, Uppsala University

  The emergence of multi-core processors has successfully ended the era where applications could enjoy free and regular performance improvements without source code modifications. This… (more)

Subjects/Keywords: Multi-core processors; parallelism

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APA (6th Edition):

Karlsson, J. (2015). Efficient use of Multi-core Technology in Interactive Desktop Applications. (Thesis). Uppsala University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-246120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Karlsson, Johan. “Efficient use of Multi-core Technology in Interactive Desktop Applications.” 2015. Thesis, Uppsala University. Accessed January 29, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-246120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Karlsson, Johan. “Efficient use of Multi-core Technology in Interactive Desktop Applications.” 2015. Web. 29 Jan 2020.

Vancouver:

Karlsson J. Efficient use of Multi-core Technology in Interactive Desktop Applications. [Internet] [Thesis]. Uppsala University; 2015. [cited 2020 Jan 29]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-246120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Karlsson J. Efficient use of Multi-core Technology in Interactive Desktop Applications. [Thesis]. Uppsala University; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-246120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Hogg, R. S. A comparative study of synchronous and self-timed systolic array architectures.

Degree: PhD, 1997, Sheffield Hallam University

 This thesis examines systolic array architectures and their methods of control and communication synchronisation. Systolic array processors suffer from synchronisation problems associated with the clocking… (more)

Subjects/Keywords: 005; Processors; Synchronisation

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APA (6th Edition):

Hogg, R. S. (1997). A comparative study of synchronous and self-timed systolic array architectures. (Doctoral Dissertation). Sheffield Hallam University. Retrieved from http://shura.shu.ac.uk/19807/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.363522

Chicago Manual of Style (16th Edition):

Hogg, R S. “A comparative study of synchronous and self-timed systolic array architectures.” 1997. Doctoral Dissertation, Sheffield Hallam University. Accessed January 29, 2020. http://shura.shu.ac.uk/19807/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.363522.

MLA Handbook (7th Edition):

Hogg, R S. “A comparative study of synchronous and self-timed systolic array architectures.” 1997. Web. 29 Jan 2020.

Vancouver:

Hogg RS. A comparative study of synchronous and self-timed systolic array architectures. [Internet] [Doctoral dissertation]. Sheffield Hallam University; 1997. [cited 2020 Jan 29]. Available from: http://shura.shu.ac.uk/19807/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.363522.

Council of Science Editors:

Hogg RS. A comparative study of synchronous and self-timed systolic array architectures. [Doctoral Dissertation]. Sheffield Hallam University; 1997. Available from: http://shura.shu.ac.uk/19807/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.363522


University of Minnesota

14. Kolpe, Tejaswini. Power management in multicore processors through clustered DVFS.

Degree: MS, Electrical Engineering, 2010, University of Minnesota

University of Minnesota M.S. thesis. July 2010. Major: Electrical Engineering. Advisor: Sachin Suresh Sapatnekar. 1 computer file (PDF); viii, 57 pages. Ill. (some col.)

The… (more)

Subjects/Keywords: Cores; Processors; Clusters; Parallelism; Electrical Engineering

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APA (6th Edition):

Kolpe, T. (2010). Power management in multicore processors through clustered DVFS. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/93628

Chicago Manual of Style (16th Edition):

Kolpe, Tejaswini. “Power management in multicore processors through clustered DVFS.” 2010. Masters Thesis, University of Minnesota. Accessed January 29, 2020. http://purl.umn.edu/93628.

MLA Handbook (7th Edition):

Kolpe, Tejaswini. “Power management in multicore processors through clustered DVFS.” 2010. Web. 29 Jan 2020.

Vancouver:

Kolpe T. Power management in multicore processors through clustered DVFS. [Internet] [Masters thesis]. University of Minnesota; 2010. [cited 2020 Jan 29]. Available from: http://purl.umn.edu/93628.

Council of Science Editors:

Kolpe T. Power management in multicore processors through clustered DVFS. [Masters Thesis]. University of Minnesota; 2010. Available from: http://purl.umn.edu/93628

15. Magni, Alberto. Analysis and parameter prediction of compiler transformation for graphics processors.

Degree: PhD, 2016, University of Edinburgh

 In the last decade graphics processors (GPUs) have been extensively used to solve computationally intensive problems. A variety of GPU architectures by different hardware manufacturers… (more)

Subjects/Keywords: 006.6; compliers; graphics processors; performance optimization

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APA (6th Edition):

Magni, A. (2016). Analysis and parameter prediction of compiler transformation for graphics processors. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/15831

Chicago Manual of Style (16th Edition):

Magni, Alberto. “Analysis and parameter prediction of compiler transformation for graphics processors.” 2016. Doctoral Dissertation, University of Edinburgh. Accessed January 29, 2020. http://hdl.handle.net/1842/15831.

MLA Handbook (7th Edition):

Magni, Alberto. “Analysis and parameter prediction of compiler transformation for graphics processors.” 2016. Web. 29 Jan 2020.

Vancouver:

Magni A. Analysis and parameter prediction of compiler transformation for graphics processors. [Internet] [Doctoral dissertation]. University of Edinburgh; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1842/15831.

Council of Science Editors:

Magni A. Analysis and parameter prediction of compiler transformation for graphics processors. [Doctoral Dissertation]. University of Edinburgh; 2016. Available from: http://hdl.handle.net/1842/15831


Oregon State University

16. Pattery, Vinu J. Analysis of the effectiveness of multithreading for interrupts on communication processors.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

 High bandwidth of networks demands high performance communication processors that integrate application processing, network processing, and system support functions into a single, low cost System-On-Chip… (more)

Subjects/Keywords: Simultaneous multithreading processors

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APA (6th Edition):

Pattery, V. J. (2003). Analysis of the effectiveness of multithreading for interrupts on communication processors. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/30122

Chicago Manual of Style (16th Edition):

Pattery, Vinu J. “Analysis of the effectiveness of multithreading for interrupts on communication processors.” 2003. Masters Thesis, Oregon State University. Accessed January 29, 2020. http://hdl.handle.net/1957/30122.

MLA Handbook (7th Edition):

Pattery, Vinu J. “Analysis of the effectiveness of multithreading for interrupts on communication processors.” 2003. Web. 29 Jan 2020.

Vancouver:

Pattery VJ. Analysis of the effectiveness of multithreading for interrupts on communication processors. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1957/30122.

Council of Science Editors:

Pattery VJ. Analysis of the effectiveness of multithreading for interrupts on communication processors. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/30122


University of Missouri – Columbia

17. Vicente, Luis M., 1964-. Adaptive array signal processing using the concentric ring array and the spherical array.

Degree: 2009, University of Missouri – Columbia

 This thesis introduces new methods for partial adaptive beamforming using concentric ring and spherical arrays for acoustic signals on a partially known interference environment. We… (more)

Subjects/Keywords: Beamforming; Adaptive signal processing; Array processors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vicente, Luis M., 1. (2009). Adaptive array signal processing using the concentric ring array and the spherical array. (Thesis). University of Missouri – Columbia. Retrieved from http://hdl.handle.net/10355/9568

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vicente, Luis M., 1964-. “Adaptive array signal processing using the concentric ring array and the spherical array.” 2009. Thesis, University of Missouri – Columbia. Accessed January 29, 2020. http://hdl.handle.net/10355/9568.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vicente, Luis M., 1964-. “Adaptive array signal processing using the concentric ring array and the spherical array.” 2009. Web. 29 Jan 2020.

Vancouver:

Vicente, Luis M. 1. Adaptive array signal processing using the concentric ring array and the spherical array. [Internet] [Thesis]. University of Missouri – Columbia; 2009. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10355/9568.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vicente, Luis M. 1. Adaptive array signal processing using the concentric ring array and the spherical array. [Thesis]. University of Missouri – Columbia; 2009. Available from: http://hdl.handle.net/10355/9568

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

18. Kolpe, Tejaswini. Power management in multicore processors through clustered DVFS.

Degree: MS, Electrical Engineering, 2010, University of Minnesota

 The need for high speed processors in recent years has increased the need to exploit more parallelism than instruction level parallelism (ILP) and thread level… (more)

Subjects/Keywords: Cores; Processors; Clusters; Parallelism; Electrical Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kolpe, T. (2010). Power management in multicore processors through clustered DVFS. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/93628

Chicago Manual of Style (16th Edition):

Kolpe, Tejaswini. “Power management in multicore processors through clustered DVFS.” 2010. Masters Thesis, University of Minnesota. Accessed January 29, 2020. http://purl.umn.edu/93628.

MLA Handbook (7th Edition):

Kolpe, Tejaswini. “Power management in multicore processors through clustered DVFS.” 2010. Web. 29 Jan 2020.

Vancouver:

Kolpe T. Power management in multicore processors through clustered DVFS. [Internet] [Masters thesis]. University of Minnesota; 2010. [cited 2020 Jan 29]. Available from: http://purl.umn.edu/93628.

Council of Science Editors:

Kolpe T. Power management in multicore processors through clustered DVFS. [Masters Thesis]. University of Minnesota; 2010. Available from: http://purl.umn.edu/93628


University of Illinois – Urbana-Champaign

19. Crago, Neal. Efficient memory-level parallelism extraction with decoupled strands.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

 We present Outrider, an architecture for throughput-oriented processors that exploits intra-thread memory-level parallelism (MLP) to improve performance efficiency on highly threaded workloads. Outrider enables a… (more)

Subjects/Keywords: Memory Latency Tolerance; Accelerators; Processors; Decoupled

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APA (6th Edition):

Crago, N. (2011). Efficient memory-level parallelism extraction with decoupled strands. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24372

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Crago, Neal. “Efficient memory-level parallelism extraction with decoupled strands.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed January 29, 2020. http://hdl.handle.net/2142/24372.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Crago, Neal. “Efficient memory-level parallelism extraction with decoupled strands.” 2011. Web. 29 Jan 2020.

Vancouver:

Crago N. Efficient memory-level parallelism extraction with decoupled strands. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2142/24372.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Crago N. Efficient memory-level parallelism extraction with decoupled strands. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24372

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Duquesne University

20. Glenn, Amos. The Relationships of Word Processing in Academic Work and Student Achievement Scores on the National Assessment of Educational Progress.

Degree: PhD, Instructional Technology (EdDIT), 2015, Duquesne University

 This study is a secondary analysis of the 2011 NAEP writing test investigating the relationships between word processing in academic work and achievement test scores.… (more)

Subjects/Keywords: computers; editing; NAEP; revision; word processors; writing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Glenn, A. (2015). The Relationships of Word Processing in Academic Work and Student Achievement Scores on the National Assessment of Educational Progress. (Doctoral Dissertation). Duquesne University. Retrieved from https://dsc.duq.edu/etd/584

Chicago Manual of Style (16th Edition):

Glenn, Amos. “The Relationships of Word Processing in Academic Work and Student Achievement Scores on the National Assessment of Educational Progress.” 2015. Doctoral Dissertation, Duquesne University. Accessed January 29, 2020. https://dsc.duq.edu/etd/584.

MLA Handbook (7th Edition):

Glenn, Amos. “The Relationships of Word Processing in Academic Work and Student Achievement Scores on the National Assessment of Educational Progress.” 2015. Web. 29 Jan 2020.

Vancouver:

Glenn A. The Relationships of Word Processing in Academic Work and Student Achievement Scores on the National Assessment of Educational Progress. [Internet] [Doctoral dissertation]. Duquesne University; 2015. [cited 2020 Jan 29]. Available from: https://dsc.duq.edu/etd/584.

Council of Science Editors:

Glenn A. The Relationships of Word Processing in Academic Work and Student Achievement Scores on the National Assessment of Educational Progress. [Doctoral Dissertation]. Duquesne University; 2015. Available from: https://dsc.duq.edu/etd/584


North Carolina State University

21. Iyer, Balaji Viswanathan. Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems.

Degree: PhD, Computer Engineering, 2009, North Carolina State University

 Embedded-handheld devices are the predominant computing platform today. These devices are required to perform complex tasks yet run on batteries. Some architects use ASIC to… (more)

Subjects/Keywords: Energy Reduction Low-Power Embedded Processors Len

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Iyer, B. V. (2009). Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/4680

Chicago Manual of Style (16th Edition):

Iyer, Balaji Viswanathan. “Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems.” 2009. Doctoral Dissertation, North Carolina State University. Accessed January 29, 2020. http://www.lib.ncsu.edu/resolver/1840.16/4680.

MLA Handbook (7th Edition):

Iyer, Balaji Viswanathan. “Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems.” 2009. Web. 29 Jan 2020.

Vancouver:

Iyer BV. Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems. [Internet] [Doctoral dissertation]. North Carolina State University; 2009. [cited 2020 Jan 29]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4680.

Council of Science Editors:

Iyer BV. Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems. [Doctoral Dissertation]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4680


Ryerson University

22. Dennis, Christopher. Error locating: degree constraints.

Degree: 2016, Ryerson University

 Error graphs are a useful mathematical tool for representing failing interactions in a system. This representation is used as the basis for constructing an error… (more)

Subjects/Keywords: Array processors.; Graph theory.; Combinatorial analysis.

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APA (6th Edition):

Dennis, C. (2016). Error locating: degree constraints. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5690

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dennis, Christopher. “Error locating: degree constraints.” 2016. Thesis, Ryerson University. Accessed January 29, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A5690.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dennis, Christopher. “Error locating: degree constraints.” 2016. Web. 29 Jan 2020.

Vancouver:

Dennis C. Error locating: degree constraints. [Internet] [Thesis]. Ryerson University; 2016. [cited 2020 Jan 29]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5690.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dennis C. Error locating: degree constraints. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5690

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Queens University

23. Ma, Nicholas. Modeling and evaluation of multi-core multithreading processor architectures in SystemC .

Degree: Electrical and Computer Engineering, 2007, Queens University

 Processor design has evolved over the years to take advantage of new technology and innovative concepts in order to improve performance. Diminishing returns for improvements… (more)

Subjects/Keywords: SystemC; CMT; Processors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ma, N. (2007). Modeling and evaluation of multi-core multithreading processor architectures in SystemC . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ma, Nicholas. “Modeling and evaluation of multi-core multithreading processor architectures in SystemC .” 2007. Thesis, Queens University. Accessed January 29, 2020. http://hdl.handle.net/1974/510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ma, Nicholas. “Modeling and evaluation of multi-core multithreading processor architectures in SystemC .” 2007. Web. 29 Jan 2020.

Vancouver:

Ma N. Modeling and evaluation of multi-core multithreading processor architectures in SystemC . [Internet] [Thesis]. Queens University; 2007. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1974/510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ma N. Modeling and evaluation of multi-core multithreading processor architectures in SystemC . [Thesis]. Queens University; 2007. Available from: http://hdl.handle.net/1974/510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

24. Gajaria, Dhruv Mayur. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .

Degree: 2019, University of Arizona

 Spin-transfer torque RAMs (STT-RAMs) have been studied as a promising alternative to SRAMs in emerging caches and main memories due to their low leakage power… (more)

Subjects/Keywords: Caches; DVFS; Multi-Core Processors; STT-RAM

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APA (6th Edition):

Gajaria, D. M. (2019). DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/633246

Chicago Manual of Style (16th Edition):

Gajaria, Dhruv Mayur. “DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .” 2019. Masters Thesis, University of Arizona. Accessed January 29, 2020. http://hdl.handle.net/10150/633246.

MLA Handbook (7th Edition):

Gajaria, Dhruv Mayur. “DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .” 2019. Web. 29 Jan 2020.

Vancouver:

Gajaria DM. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . [Internet] [Masters thesis]. University of Arizona; 2019. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10150/633246.

Council of Science Editors:

Gajaria DM. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . [Masters Thesis]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/633246


UCLA

25. Moazeni, Maryam. Parallel Algorithms for Medical Informatics on Data-Parallel Many-Core Processors.

Degree: Computer Science, 2013, UCLA

 The extensive use of medical monitoring devices has resulted in the generation of tremendous amounts of data. Storage, retrieval, and analysis of such data require… (more)

Subjects/Keywords: Computer science; Computer engineering; GPGPU; Graphics Processors; Many-Core Processors; Medical Informatics; Parallel Algorithms

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moazeni, M. (2013). Parallel Algorithms for Medical Informatics on Data-Parallel Many-Core Processors. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/4pf726r4

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Moazeni, Maryam. “Parallel Algorithms for Medical Informatics on Data-Parallel Many-Core Processors.” 2013. Thesis, UCLA. Accessed January 29, 2020. http://www.escholarship.org/uc/item/4pf726r4.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Moazeni, Maryam. “Parallel Algorithms for Medical Informatics on Data-Parallel Many-Core Processors.” 2013. Web. 29 Jan 2020.

Vancouver:

Moazeni M. Parallel Algorithms for Medical Informatics on Data-Parallel Many-Core Processors. [Internet] [Thesis]. UCLA; 2013. [cited 2020 Jan 29]. Available from: http://www.escholarship.org/uc/item/4pf726r4.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Moazeni M. Parallel Algorithms for Medical Informatics on Data-Parallel Many-Core Processors. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/4pf726r4

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

26. Govind, S. Performance Modeling And Evaluation Of Network Processors.

Degree: 2006, Indian Institute of Science

 In recent years there has been an exponential growth in Internet traffic resulting in increased network bandwidth requirements which, in turn, has led to stringent… (more)

Subjects/Keywords: Network Processors; Computer Networks; Petri Nets; Petri Net Model; Network Processors - Packet Reordering; Network Processors - Perormance Analysis; Internet Traffic - Network Processor Performance; Bursty Traffic; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Govind, S. (2006). Performance Modeling And Evaluation Of Network Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/388

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Govind, S. “Performance Modeling And Evaluation Of Network Processors.” 2006. Thesis, Indian Institute of Science. Accessed January 29, 2020. http://hdl.handle.net/2005/388.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Govind, S. “Performance Modeling And Evaluation Of Network Processors.” 2006. Web. 29 Jan 2020.

Vancouver:

Govind S. Performance Modeling And Evaluation Of Network Processors. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2005/388.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Govind S. Performance Modeling And Evaluation Of Network Processors. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/388

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Δακουρού, Στεφανία. Optimized SIMD architecture exploration and implementation for ultra-low energy processors.

Degree: 2011, University of Patras

 On-line monitoring is an important challenge in future biotechnology applications, for instance in the domain of precision livestock farming where a strong need is present… (more)

Subjects/Keywords: SIMD; Ultra-low energy processors; ASIP; Instruction set processors; 621.395; Επεξεργαστές χαμηλής κατανάλωσης; Επαναπρογραμματιζόμενοι επεξεργαστές; Σετ εντολών επεξεργαστή

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APA (6th Edition):

Δακουρού, . (2011). Optimized SIMD architecture exploration and implementation for ultra-low energy processors. (Masters Thesis). University of Patras. Retrieved from http://hdl.handle.net/10889/5372

Chicago Manual of Style (16th Edition):

Δακουρού, Στεφανία. “Optimized SIMD architecture exploration and implementation for ultra-low energy processors.” 2011. Masters Thesis, University of Patras. Accessed January 29, 2020. http://hdl.handle.net/10889/5372.

MLA Handbook (7th Edition):

Δακουρού, Στεφανία. “Optimized SIMD architecture exploration and implementation for ultra-low energy processors.” 2011. Web. 29 Jan 2020.

Vancouver:

Δακουρού . Optimized SIMD architecture exploration and implementation for ultra-low energy processors. [Internet] [Masters thesis]. University of Patras; 2011. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10889/5372.

Council of Science Editors:

Δακουρού . Optimized SIMD architecture exploration and implementation for ultra-low energy processors. [Masters Thesis]. University of Patras; 2011. Available from: http://hdl.handle.net/10889/5372


Indian Institute of Science

28. Prasad, Ashwin. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.

Degree: 2012, Indian Institute of Science

 MATLAB is an array language, initially popular for rapid prototyping, but is now being in-creasingly used to develop production code for numerical and scientific applications.… (more)

Subjects/Keywords: Compilers (Computer Programs); MATLAB (Computer Program); MEGHA (Compiler); Parallel Processors; Heterogeneous Processors; MATLAB Programs - Compilation; MATLAB Program; Computer Science

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APA (6th Edition):

Prasad, A. (2012). Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prasad, Ashwin. “Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.” 2012. Thesis, Indian Institute of Science. Accessed January 29, 2020. http://hdl.handle.net/2005/2312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prasad, Ashwin. “Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.” 2012. Web. 29 Jan 2020.

Vancouver:

Prasad A. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2005/2312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prasad A. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

29. Prasad, Ashwin. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.

Degree: 2012, Indian Institute of Science

 MATLAB is an array language, initially popular for rapid prototyping, but is now being in-creasingly used to develop production code for numerical and scientific applications.… (more)

Subjects/Keywords: Compilers (Computer Programs); MATLAB (Computer Program); MEGHA (Compiler); Parallel Processors; Heterogeneous Processors; MATLAB Programs - Compilation; MATLAB Program; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prasad, A. (2012). Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2312 ; http://etd.ncsi.iisc.ernet.in/abstracts/2974/G25101-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prasad, Ashwin. “Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.” 2012. Thesis, Indian Institute of Science. Accessed January 29, 2020. http://etd.iisc.ernet.in/handle/2005/2312 ; http://etd.ncsi.iisc.ernet.in/abstracts/2974/G25101-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prasad, Ashwin. “Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.” 2012. Web. 29 Jan 2020.

Vancouver:

Prasad A. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2020 Jan 29]. Available from: http://etd.iisc.ernet.in/handle/2005/2312 ; http://etd.ncsi.iisc.ernet.in/abstracts/2974/G25101-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prasad A. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2312 ; http://etd.ncsi.iisc.ernet.in/abstracts/2974/G25101-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

30. Santhosh P. Shape based techniques for effective Content based image retrieval;.

Degree: Shape based techniques for effective Content based image retrieval, 2015, Anna University

Shape is one of the most important visual features that characterizes an newlineobject and enable human beings to recognize it In Content based image newlineretrieval,… (more)

Subjects/Keywords: Content based image; Contour based Region; High speed processors

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APA (6th Edition):

P, S. (2015). Shape based techniques for effective Content based image retrieval;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40771

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

P, Santhosh. “Shape based techniques for effective Content based image retrieval;.” 2015. Thesis, Anna University. Accessed January 29, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/40771.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

P, Santhosh. “Shape based techniques for effective Content based image retrieval;.” 2015. Web. 29 Jan 2020.

Vancouver:

P S. Shape based techniques for effective Content based image retrieval;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Jan 29]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40771.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P S. Shape based techniques for effective Content based image retrieval;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40771

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [14]

.