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You searched for subject:(Processor). Showing records 1 – 30 of 753 total matches.

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University of Pretoria

1. Broich, René. A Soft-core processor architecture optimised for radar signal processing applications.

Degree: Electrical, Electronic and Computer Engineering, 2014, University of Pretoria

 Current radar signal processor architectures lack either performance or flexibility in terms of ease of modification and large design time overheads. Combinations of processors and… (more)

Subjects/Keywords: Radar signal processor; Soft-core processor; FPGA architecture; Signal lflow characteristics; Streaming processor; Pipelined processor; Soft-core DSP; Processor design; DSP architecture; Transport-based processor; UCTD

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APA (6th Edition):

Broich, R. (2014). A Soft-core processor architecture optimised for radar signal processing applications. (Masters Thesis). University of Pretoria. Retrieved from http://hdl.handle.net/2263/40821

Chicago Manual of Style (16th Edition):

Broich, René. “A Soft-core processor architecture optimised for radar signal processing applications.” 2014. Masters Thesis, University of Pretoria. Accessed April 09, 2020. http://hdl.handle.net/2263/40821.

MLA Handbook (7th Edition):

Broich, René. “A Soft-core processor architecture optimised for radar signal processing applications.” 2014. Web. 09 Apr 2020.

Vancouver:

Broich R. A Soft-core processor architecture optimised for radar signal processing applications. [Internet] [Masters thesis]. University of Pretoria; 2014. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/2263/40821.

Council of Science Editors:

Broich R. A Soft-core processor architecture optimised for radar signal processing applications. [Masters Thesis]. University of Pretoria; 2014. Available from: http://hdl.handle.net/2263/40821


Rochester Institute of Technology

2. Johnstone, Benjamin C. Bandwidth Requirements of GPU Architectures.

Degree: MS, Computer Engineering, 2014, Rochester Institute of Technology

  A new trend in chip multiprocessor (CMP) design is to incorporate graphics processing unit (GPU) cores, making them heterogeneous. GPU cores have a higher… (more)

Subjects/Keywords: Bandwidth; GPU; Graphics processor; Photonic

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APA (6th Edition):

Johnstone, B. C. (2014). Bandwidth Requirements of GPU Architectures. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8296

Chicago Manual of Style (16th Edition):

Johnstone, Benjamin C. “Bandwidth Requirements of GPU Architectures.” 2014. Masters Thesis, Rochester Institute of Technology. Accessed April 09, 2020. https://scholarworks.rit.edu/theses/8296.

MLA Handbook (7th Edition):

Johnstone, Benjamin C. “Bandwidth Requirements of GPU Architectures.” 2014. Web. 09 Apr 2020.

Vancouver:

Johnstone BC. Bandwidth Requirements of GPU Architectures. [Internet] [Masters thesis]. Rochester Institute of Technology; 2014. [cited 2020 Apr 09]. Available from: https://scholarworks.rit.edu/theses/8296.

Council of Science Editors:

Johnstone BC. Bandwidth Requirements of GPU Architectures. [Masters Thesis]. Rochester Institute of Technology; 2014. Available from: https://scholarworks.rit.edu/theses/8296


Addis Ababa University

3. Kassaye, Tafesse. HIGH THROUGHPUT AES CRYPTO CO-PROCESSOR .

Degree: 2013, Addis Ababa University

 In 2001, National Institute of Standards and Technology (NIST) approved Rijndael as Advanced Encryption Standard(AES).Since its approval, AES is being used widely in different security… (more)

Subjects/Keywords: AES; CRYPTO CO-PROCESSOR

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APA (6th Edition):

Kassaye, T. (2013). HIGH THROUGHPUT AES CRYPTO CO-PROCESSOR . (Thesis). Addis Ababa University. Retrieved from http://etd.aau.edu.et/dspace/handle/123456789/4502

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kassaye, Tafesse. “HIGH THROUGHPUT AES CRYPTO CO-PROCESSOR .” 2013. Thesis, Addis Ababa University. Accessed April 09, 2020. http://etd.aau.edu.et/dspace/handle/123456789/4502.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kassaye, Tafesse. “HIGH THROUGHPUT AES CRYPTO CO-PROCESSOR .” 2013. Web. 09 Apr 2020.

Vancouver:

Kassaye T. HIGH THROUGHPUT AES CRYPTO CO-PROCESSOR . [Internet] [Thesis]. Addis Ababa University; 2013. [cited 2020 Apr 09]. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4502.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kassaye T. HIGH THROUGHPUT AES CRYPTO CO-PROCESSOR . [Thesis]. Addis Ababa University; 2013. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4502

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

4. Trienekens, R. Porting the GCC Compiler to a VLIW Vector Processor:.

Degree: 2009, Delft University of Technology

 Applications run on embedded DSPs become increasingly complex, while the demands on speed and power continue to grow. One method of meeting these demands is… (more)

Subjects/Keywords: GCC; VLIW; Vector Processor

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APA (6th Edition):

Trienekens, R. (2009). Porting the GCC Compiler to a VLIW Vector Processor:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6d74b3b5-cb4e-462c-be1d-91af20a8e057

Chicago Manual of Style (16th Edition):

Trienekens, R. “Porting the GCC Compiler to a VLIW Vector Processor:.” 2009. Masters Thesis, Delft University of Technology. Accessed April 09, 2020. http://resolver.tudelft.nl/uuid:6d74b3b5-cb4e-462c-be1d-91af20a8e057.

MLA Handbook (7th Edition):

Trienekens, R. “Porting the GCC Compiler to a VLIW Vector Processor:.” 2009. Web. 09 Apr 2020.

Vancouver:

Trienekens R. Porting the GCC Compiler to a VLIW Vector Processor:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2020 Apr 09]. Available from: http://resolver.tudelft.nl/uuid:6d74b3b5-cb4e-462c-be1d-91af20a8e057.

Council of Science Editors:

Trienekens R. Porting the GCC Compiler to a VLIW Vector Processor:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:6d74b3b5-cb4e-462c-be1d-91af20a8e057


Delft University of Technology

5. Van As, T. ρ-VEX: A reconfigurable and extensible VLIW processor:.

Degree: Electrical Engineering, Mathematics and Computer Science, Computer Engineering, 2008, Delft University of Technology

 Increasingly more computing power is being demanded in the domain of multimedia applications. Computer architectures based on reconfigurable hardware are becoming more popular now that… (more)

Subjects/Keywords: vliw; vex; processor; fpga; molen

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APA (6th Edition):

Van As, T. (2008). ρ-VEX: A reconfigurable and extensible VLIW processor:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:280fe4d8-d1de-4a46-ad99-be8129d85dab

Chicago Manual of Style (16th Edition):

Van As, T. “ρ-VEX: A reconfigurable and extensible VLIW processor:.” 2008. Masters Thesis, Delft University of Technology. Accessed April 09, 2020. http://resolver.tudelft.nl/uuid:280fe4d8-d1de-4a46-ad99-be8129d85dab.

MLA Handbook (7th Edition):

Van As, T. “ρ-VEX: A reconfigurable and extensible VLIW processor:.” 2008. Web. 09 Apr 2020.

Vancouver:

Van As T. ρ-VEX: A reconfigurable and extensible VLIW processor:. [Internet] [Masters thesis]. Delft University of Technology; 2008. [cited 2020 Apr 09]. Available from: http://resolver.tudelft.nl/uuid:280fe4d8-d1de-4a46-ad99-be8129d85dab.

Council of Science Editors:

Van As T. ρ-VEX: A reconfigurable and extensible VLIW processor:. [Masters Thesis]. Delft University of Technology; 2008. Available from: http://resolver.tudelft.nl/uuid:280fe4d8-d1de-4a46-ad99-be8129d85dab


University of Toronto

6. Sadeghian, Vahid. FormWorks-Plus: Improved Pre-processor for VecTor Analysis Software.

Degree: 2012, University of Toronto

VecTor© is a suite of computer programs developed for nonlinear finite element analysis of reinforced concrete. A graphics-based pre-processor (FormWorks) was developed for 2D concrete… (more)

Subjects/Keywords: FormWorks; VecTor; Pre-processor; 0543

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APA (6th Edition):

Sadeghian, V. (2012). FormWorks-Plus: Improved Pre-processor for VecTor Analysis Software. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/32277

Chicago Manual of Style (16th Edition):

Sadeghian, Vahid. “FormWorks-Plus: Improved Pre-processor for VecTor Analysis Software.” 2012. Masters Thesis, University of Toronto. Accessed April 09, 2020. http://hdl.handle.net/1807/32277.

MLA Handbook (7th Edition):

Sadeghian, Vahid. “FormWorks-Plus: Improved Pre-processor for VecTor Analysis Software.” 2012. Web. 09 Apr 2020.

Vancouver:

Sadeghian V. FormWorks-Plus: Improved Pre-processor for VecTor Analysis Software. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1807/32277.

Council of Science Editors:

Sadeghian V. FormWorks-Plus: Improved Pre-processor for VecTor Analysis Software. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/32277


University of New South Wales

7. Israt, Presila. Broadband Beamforming without Pre-steering Delays by studying PIC Processor.

Degree: Engineering & Information Technology, 2011, University of New South Wales

 Time domain processing of broadband signals requires the use of steering delays. In this work a postbeamformer interference canceler (PIC) processor for processing broadband directional… (more)

Subjects/Keywords: PIC Processor; Broadband; Beamforming

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APA (6th Edition):

Israt, P. (2011). Broadband Beamforming without Pre-steering Delays by studying PIC Processor. (Masters Thesis). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/51419 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10103/SOURCE01?view=true

Chicago Manual of Style (16th Edition):

Israt, Presila. “Broadband Beamforming without Pre-steering Delays by studying PIC Processor.” 2011. Masters Thesis, University of New South Wales. Accessed April 09, 2020. http://handle.unsw.edu.au/1959.4/51419 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10103/SOURCE01?view=true.

MLA Handbook (7th Edition):

Israt, Presila. “Broadband Beamforming without Pre-steering Delays by studying PIC Processor.” 2011. Web. 09 Apr 2020.

Vancouver:

Israt P. Broadband Beamforming without Pre-steering Delays by studying PIC Processor. [Internet] [Masters thesis]. University of New South Wales; 2011. [cited 2020 Apr 09]. Available from: http://handle.unsw.edu.au/1959.4/51419 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10103/SOURCE01?view=true.

Council of Science Editors:

Israt P. Broadband Beamforming without Pre-steering Delays by studying PIC Processor. [Masters Thesis]. University of New South Wales; 2011. Available from: http://handle.unsw.edu.au/1959.4/51419 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10103/SOURCE01?view=true


Cal Poly

8. Furlan, Carmelo C. Analysis of Hardware Sorting Units in Processor Design.

Degree: MS, Electrical Engineering, 2019, Cal Poly

  Sorting is often computationally intensive and can cause the application in which it is used to run slowly. To date, the quickest software sorting… (more)

Subjects/Keywords: Sorting Units; Processor Design

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APA (6th Edition):

Furlan, C. C. (2019). Analysis of Hardware Sorting Units in Processor Design. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/2020 ; 10.15368/theses.2019.32

Chicago Manual of Style (16th Edition):

Furlan, Carmelo C. “Analysis of Hardware Sorting Units in Processor Design.” 2019. Masters Thesis, Cal Poly. Accessed April 09, 2020. https://digitalcommons.calpoly.edu/theses/2020 ; 10.15368/theses.2019.32.

MLA Handbook (7th Edition):

Furlan, Carmelo C. “Analysis of Hardware Sorting Units in Processor Design.” 2019. Web. 09 Apr 2020.

Vancouver:

Furlan CC. Analysis of Hardware Sorting Units in Processor Design. [Internet] [Masters thesis]. Cal Poly; 2019. [cited 2020 Apr 09]. Available from: https://digitalcommons.calpoly.edu/theses/2020 ; 10.15368/theses.2019.32.

Council of Science Editors:

Furlan CC. Analysis of Hardware Sorting Units in Processor Design. [Masters Thesis]. Cal Poly; 2019. Available from: https://digitalcommons.calpoly.edu/theses/2020 ; 10.15368/theses.2019.32


Georgia Tech

9. Kim, Woongrae. Design and test methodologies with statistical analysis for reliable memory and processor implementations.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of the proposed research is to develop comprehensive methodologies, including circuit design, new test methodologies, and statistical failure analysis, to implement reliable microprocessor… (more)

Subjects/Keywords: Reliability; SRAM; DRAM; Processor

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APA (6th Edition):

Kim, W. (2016). Design and test methodologies with statistical analysis for reliable memory and processor implementations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59737

Chicago Manual of Style (16th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 09, 2020. http://hdl.handle.net/1853/59737.

MLA Handbook (7th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Web. 09 Apr 2020.

Vancouver:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1853/59737.

Council of Science Editors:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59737


University College Cork

10. Zeinolabedini, Nasim. Average-case analysis of power consumption in embedded systems.

Degree: 2015, University College Cork

 Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited… (more)

Subjects/Keywords: Embedded systems; Processor power estimation

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APA (6th Edition):

Zeinolabedini, N. (2015). Average-case analysis of power consumption in embedded systems. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/3375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zeinolabedini, Nasim. “Average-case analysis of power consumption in embedded systems.” 2015. Thesis, University College Cork. Accessed April 09, 2020. http://hdl.handle.net/10468/3375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zeinolabedini, Nasim. “Average-case analysis of power consumption in embedded systems.” 2015. Web. 09 Apr 2020.

Vancouver:

Zeinolabedini N. Average-case analysis of power consumption in embedded systems. [Internet] [Thesis]. University College Cork; 2015. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/10468/3375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zeinolabedini N. Average-case analysis of power consumption in embedded systems. [Thesis]. University College Cork; 2015. Available from: http://hdl.handle.net/10468/3375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

11. Xu, Zhentao. Pricing European options using Monte Carlo methods.

Degree: MS, Computer Science, 2015, University of Illinois – Urbana-Champaign

 European-style options are quite popular nowadays. Calculating their theo- retical price is not an easy task because there are many sources of uncertainty. However, we… (more)

Subjects/Keywords: graphics processor unit (GPU); Reduction

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APA (6th Edition):

Xu, Z. (2015). Pricing European options using Monte Carlo methods. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78794

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Zhentao. “Pricing European options using Monte Carlo methods.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 09, 2020. http://hdl.handle.net/2142/78794.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Zhentao. “Pricing European options using Monte Carlo methods.” 2015. Web. 09 Apr 2020.

Vancouver:

Xu Z. Pricing European options using Monte Carlo methods. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/2142/78794.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu Z. Pricing European options using Monte Carlo methods. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78794

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Sacramento

12. Gogikar, Geetha Mallik Raj. ZF microsystem based embedded system application for fingerprint verification.

Degree: MS, Electric and Electronic Engineering, 2011, California State University – Sacramento

 In today???s complex world the need to maintain the security of information or physical property has become more important and difficult task. Developing a trusted… (more)

Subjects/Keywords: Minutiae; Matching; MediaGX processor

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APA (6th Edition):

Gogikar, G. M. R. (2011). ZF microsystem based embedded system application for fingerprint verification. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/891

Chicago Manual of Style (16th Edition):

Gogikar, Geetha Mallik Raj. “ZF microsystem based embedded system application for fingerprint verification.” 2011. Masters Thesis, California State University – Sacramento. Accessed April 09, 2020. http://hdl.handle.net/10211.9/891.

MLA Handbook (7th Edition):

Gogikar, Geetha Mallik Raj. “ZF microsystem based embedded system application for fingerprint verification.” 2011. Web. 09 Apr 2020.

Vancouver:

Gogikar GMR. ZF microsystem based embedded system application for fingerprint verification. [Internet] [Masters thesis]. California State University – Sacramento; 2011. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/10211.9/891.

Council of Science Editors:

Gogikar GMR. ZF microsystem based embedded system application for fingerprint verification. [Masters Thesis]. California State University – Sacramento; 2011. Available from: http://hdl.handle.net/10211.9/891


University of Dayton

13. Zhang, Bin. FPGA Design of a Multicore Neuromorphic Processing System.

Degree: MS(M.S.), Electrical Engineering, 2016, University of Dayton

 Neuromorphic computing architecture has developed rapidly during recent years. Neuronmorphic network processor FPGA implementation is 3x and 127x faster than Intel E8400 processor with edge… (more)

Subjects/Keywords: Electrical Engineering; Neuronmorphic Network; micro-processor; FPGA; ultra-low power processor

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APA (6th Edition):

Zhang, B. (2016). FPGA Design of a Multicore Neuromorphic Processing System. (Masters Thesis). University of Dayton. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=dayton1461694994

Chicago Manual of Style (16th Edition):

Zhang, Bin. “FPGA Design of a Multicore Neuromorphic Processing System.” 2016. Masters Thesis, University of Dayton. Accessed April 09, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1461694994.

MLA Handbook (7th Edition):

Zhang, Bin. “FPGA Design of a Multicore Neuromorphic Processing System.” 2016. Web. 09 Apr 2020.

Vancouver:

Zhang B. FPGA Design of a Multicore Neuromorphic Processing System. [Internet] [Masters thesis]. University of Dayton; 2016. [cited 2020 Apr 09]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1461694994.

Council of Science Editors:

Zhang B. FPGA Design of a Multicore Neuromorphic Processing System. [Masters Thesis]. University of Dayton; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1461694994


Delft University of Technology

14. van de Waerdt, J.W. The TM3270 Media-processor.

Degree: 2006, Delft University of Technology

 I n this thesis, we present the TM3270 VLIW media-processor, the latest of TriMedia processors, and describe the innovations with respect to its prede- cessor:… (more)

Subjects/Keywords: media-processor; processor design

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APA (6th Edition):

van de Waerdt, J. W. (2006). The TM3270 Media-processor. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; urn:NBN:nl:ui:24-uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; urn:NBN:nl:ui:24-uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; http://resolver.tudelft.nl/uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a

Chicago Manual of Style (16th Edition):

van de Waerdt, J W. “The TM3270 Media-processor.” 2006. Doctoral Dissertation, Delft University of Technology. Accessed April 09, 2020. http://resolver.tudelft.nl/uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; urn:NBN:nl:ui:24-uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; urn:NBN:nl:ui:24-uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; http://resolver.tudelft.nl/uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a.

MLA Handbook (7th Edition):

van de Waerdt, J W. “The TM3270 Media-processor.” 2006. Web. 09 Apr 2020.

Vancouver:

van de Waerdt JW. The TM3270 Media-processor. [Internet] [Doctoral dissertation]. Delft University of Technology; 2006. [cited 2020 Apr 09]. Available from: http://resolver.tudelft.nl/uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; urn:NBN:nl:ui:24-uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; urn:NBN:nl:ui:24-uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; http://resolver.tudelft.nl/uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a.

Council of Science Editors:

van de Waerdt JW. The TM3270 Media-processor. [Doctoral Dissertation]. Delft University of Technology; 2006. Available from: http://resolver.tudelft.nl/uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; urn:NBN:nl:ui:24-uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; urn:NBN:nl:ui:24-uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a ; http://resolver.tudelft.nl/uuid:d4655d6f-ba1b-4306-a0f1-1b495189ca9a


Universitat Politècnica de Catalunya

15. Palomar Pérez, Óscar. Reusing cached schedules in an out-of-order processor with in-order issue logic.

Degree: Departament d'Arquitectura de Computadors, 2011, Universitat Politècnica de Catalunya

 Modern processors use out-of-order processing logic to achieve high performance in Instructions Per Cycle (IPC) but this logic has a serious impact on the achievable… (more)

Subjects/Keywords: Issue logic; In-order processor; Out-of-order processor; 004

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APA (6th Edition):

Palomar Pérez, . (2011). Reusing cached schedules in an out-of-order processor with in-order issue logic. (Thesis). Universitat Politècnica de Catalunya. Retrieved from http://hdl.handle.net/10803/80536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Palomar Pérez, Óscar. “Reusing cached schedules in an out-of-order processor with in-order issue logic.” 2011. Thesis, Universitat Politècnica de Catalunya. Accessed April 09, 2020. http://hdl.handle.net/10803/80536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Palomar Pérez, Óscar. “Reusing cached schedules in an out-of-order processor with in-order issue logic.” 2011. Web. 09 Apr 2020.

Vancouver:

Palomar Pérez . Reusing cached schedules in an out-of-order processor with in-order issue logic. [Internet] [Thesis]. Universitat Politècnica de Catalunya; 2011. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/10803/80536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Palomar Pérez . Reusing cached schedules in an out-of-order processor with in-order issue logic. [Thesis]. Universitat Politècnica de Catalunya; 2011. Available from: http://hdl.handle.net/10803/80536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

16. Veerappan J. Performance analysis of optical Signal processing for real time Underwater lidar images;.

Degree: Performance analysis of optical Signal processing for real time Underwater lidar images, 2014, Anna University

newlineThere are several major application areas of underwater Light newlineDetection And Ranging LIDAR in use Due to rapid technological newlineadvancements in signal processing computers and… (more)

Subjects/Keywords: and Hybrid Digital and Optical Signal Processor; Digital Signal Processor; Light Detection And Ranging; Optical Signal Processor; Under Water Lidar Images

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APA (6th Edition):

J, V. (2014). Performance analysis of optical Signal processing for real time Underwater lidar images;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/28430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

J, Veerappan. “Performance analysis of optical Signal processing for real time Underwater lidar images;.” 2014. Thesis, Anna University. Accessed April 09, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/28430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

J, Veerappan. “Performance analysis of optical Signal processing for real time Underwater lidar images;.” 2014. Web. 09 Apr 2020.

Vancouver:

J V. Performance analysis of optical Signal processing for real time Underwater lidar images;. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Apr 09]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/28430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

J V. Performance analysis of optical Signal processing for real time Underwater lidar images;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/28430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

17. Prasantha H S. Digital signal processor implementation Of some novel algorithms for video Processing on mobile devices;.

Degree: Digital signal processor implementation Of some novel algorithms for video Processing on mobile devices, 2014, Anna University

With advancement in technology CISCO S Visual Networking Index VNI newlineforecast report has gained importance due to the fact that 4G services will lead to… (more)

Subjects/Keywords: Digital signal processor; Visual Networking Index

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APA (6th Edition):

S, P. H. (2014). Digital signal processor implementation Of some novel algorithms for video Processing on mobile devices;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/26205

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

S, Prasantha H. “Digital signal processor implementation Of some novel algorithms for video Processing on mobile devices;.” 2014. Thesis, Anna University. Accessed April 09, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/26205.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

S, Prasantha H. “Digital signal processor implementation Of some novel algorithms for video Processing on mobile devices;.” 2014. Web. 09 Apr 2020.

Vancouver:

S PH. Digital signal processor implementation Of some novel algorithms for video Processing on mobile devices;. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Apr 09]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26205.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

S PH. Digital signal processor implementation Of some novel algorithms for video Processing on mobile devices;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26205

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Avudaiammal, R. Network traffic management using embedded network processor for enhancing quality of service of multimedia applications; -.

Degree: Information and Communication Engineering, 2014, Anna University

Internet traffic has increased in recent times due to the explosive newlinegrowth of multimedia applications such as Video on demand Video newlineTelephony Video streaming and… (more)

Subjects/Keywords: Information and communication engineering; Multimedia; Network processor

Page 1

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APA (6th Edition):

Avudaiammal, R. (2014). Network traffic management using embedded network processor for enhancing quality of service of multimedia applications; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/22274

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Avudaiammal, R. “Network traffic management using embedded network processor for enhancing quality of service of multimedia applications; -.” 2014. Thesis, Anna University. Accessed April 09, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/22274.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Avudaiammal, R. “Network traffic management using embedded network processor for enhancing quality of service of multimedia applications; -.” 2014. Web. 09 Apr 2020.

Vancouver:

Avudaiammal R. Network traffic management using embedded network processor for enhancing quality of service of multimedia applications; -. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Apr 09]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/22274.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Avudaiammal R. Network traffic management using embedded network processor for enhancing quality of service of multimedia applications; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/22274

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

19. Streat, Lennard G. A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler.

Degree: MS, Computer Engineering, 2016, Rochester Institute of Technology

  Hierarchical temporal memory (HTM) is a biomimetic machine learning algorithm focused upon modeling the structural and algorithmic properties of the neocortex. It is comprised… (more)

Subjects/Keywords: Flash; Hierarchical; Memory; Processor; Storage; Temporal

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APA (6th Edition):

Streat, L. G. (2016). A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9058

Chicago Manual of Style (16th Edition):

Streat, Lennard G. “A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler.” 2016. Masters Thesis, Rochester Institute of Technology. Accessed April 09, 2020. https://scholarworks.rit.edu/theses/9058.

MLA Handbook (7th Edition):

Streat, Lennard G. “A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler.” 2016. Web. 09 Apr 2020.

Vancouver:

Streat LG. A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler. [Internet] [Masters thesis]. Rochester Institute of Technology; 2016. [cited 2020 Apr 09]. Available from: https://scholarworks.rit.edu/theses/9058.

Council of Science Editors:

Streat LG. A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler. [Masters Thesis]. Rochester Institute of Technology; 2016. Available from: https://scholarworks.rit.edu/theses/9058


Rochester Institute of Technology

20. Rubin, Lawrence H. A Parameterized CMOS standard cell library and a full 8-bit grey scale morphological array processor.

Degree: Computer Engineering, 1991, Rochester Institute of Technology

 The creation of a parameterized, full custom CMOS VLSI design library is discussed. This library consists of a schematic component library that is integrated with… (more)

Subjects/Keywords: Morphological array processor

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APA (6th Edition):

Rubin, L. H. (1991). A Parameterized CMOS standard cell library and a full 8-bit grey scale morphological array processor. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/4607

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rubin, Lawrence H. “A Parameterized CMOS standard cell library and a full 8-bit grey scale morphological array processor.” 1991. Thesis, Rochester Institute of Technology. Accessed April 09, 2020. https://scholarworks.rit.edu/theses/4607.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rubin, Lawrence H. “A Parameterized CMOS standard cell library and a full 8-bit grey scale morphological array processor.” 1991. Web. 09 Apr 2020.

Vancouver:

Rubin LH. A Parameterized CMOS standard cell library and a full 8-bit grey scale morphological array processor. [Internet] [Thesis]. Rochester Institute of Technology; 1991. [cited 2020 Apr 09]. Available from: https://scholarworks.rit.edu/theses/4607.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rubin LH. A Parameterized CMOS standard cell library and a full 8-bit grey scale morphological array processor. [Thesis]. Rochester Institute of Technology; 1991. Available from: https://scholarworks.rit.edu/theses/4607

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

21. Nogaj, Adam. Establishing parameters for problem difficulty in permutation-based genetic algorithms.

Degree: Computer Science (GCCIS), 2011, Rochester Institute of Technology

 This thesis examines the performance of genetic algorithm (GA) crossover techniques within two problems: n-queens with poison (NQWP) and processor scheduling (PS). Each problem was… (more)

Subjects/Keywords: Crossover; Genetic algorithms; N-queens; Processor scheduling

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APA (6th Edition):

Nogaj, A. (2011). Establishing parameters for problem difficulty in permutation-based genetic algorithms. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/252

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nogaj, Adam. “Establishing parameters for problem difficulty in permutation-based genetic algorithms.” 2011. Thesis, Rochester Institute of Technology. Accessed April 09, 2020. https://scholarworks.rit.edu/theses/252.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nogaj, Adam. “Establishing parameters for problem difficulty in permutation-based genetic algorithms.” 2011. Web. 09 Apr 2020.

Vancouver:

Nogaj A. Establishing parameters for problem difficulty in permutation-based genetic algorithms. [Internet] [Thesis]. Rochester Institute of Technology; 2011. [cited 2020 Apr 09]. Available from: https://scholarworks.rit.edu/theses/252.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nogaj A. Establishing parameters for problem difficulty in permutation-based genetic algorithms. [Thesis]. Rochester Institute of Technology; 2011. Available from: https://scholarworks.rit.edu/theses/252

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

22. Konireddygari, Sreekanth. Measuring and Improving TLB Performance for Linux GUI Applications.

Degree: MS, Computer Science, 2009, North Carolina State University

 Modern GUI applications rely on a large number of dynamically linked shared libraries to reduce the applications' memory footprint and to avoid recompilation when newer… (more)

Subjects/Keywords: shared library; gui; performance; TLB; linux; processor

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APA (6th Edition):

Konireddygari, S. (2009). Measuring and Improving TLB Performance for Linux GUI Applications. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/2072

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Konireddygari, Sreekanth. “Measuring and Improving TLB Performance for Linux GUI Applications.” 2009. Thesis, North Carolina State University. Accessed April 09, 2020. http://www.lib.ncsu.edu/resolver/1840.16/2072.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Konireddygari, Sreekanth. “Measuring and Improving TLB Performance for Linux GUI Applications.” 2009. Web. 09 Apr 2020.

Vancouver:

Konireddygari S. Measuring and Improving TLB Performance for Linux GUI Applications. [Internet] [Thesis]. North Carolina State University; 2009. [cited 2020 Apr 09]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/2072.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Konireddygari S. Measuring and Improving TLB Performance for Linux GUI Applications. [Thesis]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/2072

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Notre Dame

23. Daniel Govinda Rinzler. Design and Implementation of an FPGA-Based Image Processor: Exploring a Distributed Data Multi-Core Co-Processor Architecture</h1>.

Degree: MSin Computer Science and Engineering, Computer Science and Engineering, 2009, University of Notre Dame

  This thesis explores using a hybrid processing approach for doing application specific memory intensive processing. The hybrid system uses a general purpose processor (GPP)… (more)

Subjects/Keywords: co-processor; FPGA; image processing; image registration

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APA (6th Edition):

Rinzler, D. G. (2009). Design and Implementation of an FPGA-Based Image Processor: Exploring a Distributed Data Multi-Core Co-Processor Architecture</h1>. (Masters Thesis). University of Notre Dame. Retrieved from https://curate.nd.edu/show/ms35t724t77

Chicago Manual of Style (16th Edition):

Rinzler, Daniel Govinda. “Design and Implementation of an FPGA-Based Image Processor: Exploring a Distributed Data Multi-Core Co-Processor Architecture</h1>.” 2009. Masters Thesis, University of Notre Dame. Accessed April 09, 2020. https://curate.nd.edu/show/ms35t724t77.

MLA Handbook (7th Edition):

Rinzler, Daniel Govinda. “Design and Implementation of an FPGA-Based Image Processor: Exploring a Distributed Data Multi-Core Co-Processor Architecture</h1>.” 2009. Web. 09 Apr 2020.

Vancouver:

Rinzler DG. Design and Implementation of an FPGA-Based Image Processor: Exploring a Distributed Data Multi-Core Co-Processor Architecture</h1>. [Internet] [Masters thesis]. University of Notre Dame; 2009. [cited 2020 Apr 09]. Available from: https://curate.nd.edu/show/ms35t724t77.

Council of Science Editors:

Rinzler DG. Design and Implementation of an FPGA-Based Image Processor: Exploring a Distributed Data Multi-Core Co-Processor Architecture</h1>. [Masters Thesis]. University of Notre Dame; 2009. Available from: https://curate.nd.edu/show/ms35t724t77


University of Notre Dame

24. Sheng Li. An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>.

Degree: PhD, Electrical Engineering, 2010, University of Notre Dame

  Multithreaded and multi/manycore processors have already become an important new research direction. These processors have demonstrated great performance and efficiency advantages. This dissertation presents… (more)

Subjects/Keywords: modeling; power; multicore processor; area; timing

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APA (6th Edition):

Li, S. (2010). An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/show/02870v8510q

Chicago Manual of Style (16th Edition):

Li, Sheng. “An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>.” 2010. Doctoral Dissertation, University of Notre Dame. Accessed April 09, 2020. https://curate.nd.edu/show/02870v8510q.

MLA Handbook (7th Edition):

Li, Sheng. “An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>.” 2010. Web. 09 Apr 2020.

Vancouver:

Li S. An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>. [Internet] [Doctoral dissertation]. University of Notre Dame; 2010. [cited 2020 Apr 09]. Available from: https://curate.nd.edu/show/02870v8510q.

Council of Science Editors:

Li S. An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>. [Doctoral Dissertation]. University of Notre Dame; 2010. Available from: https://curate.nd.edu/show/02870v8510q


NSYSU

25. Li, Shang-Yu. Design and Implementation of a Vision Processor Based on the OpenVX Specification.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Embedded computer vision applications emphasizes fast and real-time processing speed with low power consumption. To face these challenge, we need more suitable hardware accelerator for… (more)

Subjects/Keywords: Computer vision applications; OpenVX; SIMD; Vision Processor

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APA (6th Edition):

Li, S. (2016). Design and Implementation of a Vision Processor Based on the OpenVX Specification. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Thesis, NSYSU. Accessed April 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Web. 09 Apr 2020.

Vancouver:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Apr 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Ku, Chin-Te. Study and Implementation of A Green Energy Power Converter.

Degree: Master, Electrical Engineering, 2013, NSYSU

 Increasing pressure of environmental protection and forthcoming shortage of the conventional energy sources have called for the development of green energy power system. In view… (more)

Subjects/Keywords: Green Energy; Digital Signal Processor; Power Converter

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APA (6th Edition):

Ku, C. (2013). Study and Implementation of A Green Energy Power Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0204113-163046

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ku, Chin-Te. “Study and Implementation of A Green Energy Power Converter.” 2013. Thesis, NSYSU. Accessed April 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0204113-163046.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ku, Chin-Te. “Study and Implementation of A Green Energy Power Converter.” 2013. Web. 09 Apr 2020.

Vancouver:

Ku C. Study and Implementation of A Green Energy Power Converter. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Apr 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0204113-163046.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ku C. Study and Implementation of A Green Energy Power Converter. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0204113-163046

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

27. Chandramoorthy, Nandhini. Design and Exploration of Accelerator-rich Multi-core Systems.

Degree: PhD, Computer Science and Engineering, 2016, Penn State University

 Limited power budgets and the need for high performance computing have led to platform customization with a number of accelerators integrated with many-core CPUs. The… (more)

Subjects/Keywords: heterogeneous architectures; processor modeling; accelerator-rich architectures

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APA (6th Edition):

Chandramoorthy, N. (2016). Design and Exploration of Accelerator-rich Multi-core Systems. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/13547nic5090

Chicago Manual of Style (16th Edition):

Chandramoorthy, Nandhini. “Design and Exploration of Accelerator-rich Multi-core Systems.” 2016. Doctoral Dissertation, Penn State University. Accessed April 09, 2020. https://etda.libraries.psu.edu/catalog/13547nic5090.

MLA Handbook (7th Edition):

Chandramoorthy, Nandhini. “Design and Exploration of Accelerator-rich Multi-core Systems.” 2016. Web. 09 Apr 2020.

Vancouver:

Chandramoorthy N. Design and Exploration of Accelerator-rich Multi-core Systems. [Internet] [Doctoral dissertation]. Penn State University; 2016. [cited 2020 Apr 09]. Available from: https://etda.libraries.psu.edu/catalog/13547nic5090.

Council of Science Editors:

Chandramoorthy N. Design and Exploration of Accelerator-rich Multi-core Systems. [Doctoral Dissertation]. Penn State University; 2016. Available from: https://etda.libraries.psu.edu/catalog/13547nic5090

28. Arunachalam, Venkatesh. Clock Distribution in a 3d Microprocessor.

Degree: MSin Electrical and Computer Engineering (M.S.E.C.E.), Electrical & Computer Engineering, 2009, U of Massachusetts : Masters

 As technology scales, the device delay decreases while the interconnect delay increases. As more devices are being packed into a single chip, the cost of… (more)

Subjects/Keywords: 3D IC's; 3D processor architectures; Clock distribution

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APA (6th Edition):

Arunachalam, V. (2009). Clock Distribution in a 3d Microprocessor. (Masters Thesis). U of Massachusetts : Masters. Retrieved from http://scholarworks.umass.edu/theses/256

Chicago Manual of Style (16th Edition):

Arunachalam, Venkatesh. “Clock Distribution in a 3d Microprocessor.” 2009. Masters Thesis, U of Massachusetts : Masters. Accessed April 09, 2020. http://scholarworks.umass.edu/theses/256.

MLA Handbook (7th Edition):

Arunachalam, Venkatesh. “Clock Distribution in a 3d Microprocessor.” 2009. Web. 09 Apr 2020.

Vancouver:

Arunachalam V. Clock Distribution in a 3d Microprocessor. [Internet] [Masters thesis]. U of Massachusetts : Masters; 2009. [cited 2020 Apr 09]. Available from: http://scholarworks.umass.edu/theses/256.

Council of Science Editors:

Arunachalam V. Clock Distribution in a 3d Microprocessor. [Masters Thesis]. U of Massachusetts : Masters; 2009. Available from: http://scholarworks.umass.edu/theses/256


Delft University of Technology

29. Seedorf, R.A.E. Fingerprint Verification on the VEX Processor:.

Degree: 2010, Delft University of Technology

 The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach… (more)

Subjects/Keywords: VLIW; processor; fingerprint; verification; VEX; toolchain; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Seedorf, R. A. E. (2010). Fingerprint Verification on the VEX Processor:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ab90c888-bbbf-4f67-ba52-b9974b4577eb

Chicago Manual of Style (16th Edition):

Seedorf, R A E. “Fingerprint Verification on the VEX Processor:.” 2010. Masters Thesis, Delft University of Technology. Accessed April 09, 2020. http://resolver.tudelft.nl/uuid:ab90c888-bbbf-4f67-ba52-b9974b4577eb.

MLA Handbook (7th Edition):

Seedorf, R A E. “Fingerprint Verification on the VEX Processor:.” 2010. Web. 09 Apr 2020.

Vancouver:

Seedorf RAE. Fingerprint Verification on the VEX Processor:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 Apr 09]. Available from: http://resolver.tudelft.nl/uuid:ab90c888-bbbf-4f67-ba52-b9974b4577eb.

Council of Science Editors:

Seedorf RAE. Fingerprint Verification on the VEX Processor:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:ab90c888-bbbf-4f67-ba52-b9974b4577eb


Delft University of Technology

30. Leegwater, A.E.C. Scheduling Streaming Applications on a Composable Multi-Processor System:.

Degree: 2010, Delft University of Technology

 For real-time streaming applications such as video decoding, the rate of the application is very important. To fully use the available resources of an multiprocessor… (more)

Subjects/Keywords: composable; scheduling; multi-processor; TDM; CCSP

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Leegwater, A. E. C. (2010). Scheduling Streaming Applications on a Composable Multi-Processor System:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6c779496-a885-48e4-afef-d97704595159

Chicago Manual of Style (16th Edition):

Leegwater, A E C. “Scheduling Streaming Applications on a Composable Multi-Processor System:.” 2010. Masters Thesis, Delft University of Technology. Accessed April 09, 2020. http://resolver.tudelft.nl/uuid:6c779496-a885-48e4-afef-d97704595159.

MLA Handbook (7th Edition):

Leegwater, A E C. “Scheduling Streaming Applications on a Composable Multi-Processor System:.” 2010. Web. 09 Apr 2020.

Vancouver:

Leegwater AEC. Scheduling Streaming Applications on a Composable Multi-Processor System:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 Apr 09]. Available from: http://resolver.tudelft.nl/uuid:6c779496-a885-48e4-afef-d97704595159.

Council of Science Editors:

Leegwater AEC. Scheduling Streaming Applications on a Composable Multi-Processor System:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:6c779496-a885-48e4-afef-d97704595159

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