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You searched for subject:(Process Voltage And Temperature Gate Delay Model). Showing records 1 – 30 of 539993 total matches.

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Indian Institute of Science

1. Das, Bishnu Prasad. Random Local Delay Variability : On-chip Measurement And Modeling.

Degree: 2009, Indian Institute of Science

 This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in… (more)

Subjects/Keywords: Electronic Gates - Design; On-chip Management And Construction; Electronic Gate Delay - Modeling; Random Local Delay Variation; On-chip Gate Delay Measurement; Process Voltage And Temperature Gate Delay Model; Electronic Gate Delay - Measurement; Statistical Static Timing Analysis (SSTA); Gate Delay Variability Measurement; Delay Variability; On-chip Measurement; Gate Delay Models; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, B. P. (2009). Random Local Delay Variability : On-chip Measurement And Modeling. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Thesis, Indian Institute of Science. Accessed April 02, 2020. http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Web. 02 Apr 2020.

Vancouver:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Northeastern University

2. Begur, Soumya Shivakumar. A 45nm CMOS, low jitter, all-digital delayed locked loop with a circuit to dynamically vary phase to achieve fast lock.

Degree: MS, Department of Electrical and Computer Engineering, 2011, Northeastern University

 The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the… (more)

Subjects/Keywords: computer engineering; process; voltage and temperature (PVT); digital delay locked loop (DLL); Computer Engineering

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APA (6th Edition):

Begur, S. S. (2011). A 45nm CMOS, low jitter, all-digital delayed locked loop with a circuit to dynamically vary phase to achieve fast lock. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20002106

Chicago Manual of Style (16th Edition):

Begur, Soumya Shivakumar. “A 45nm CMOS, low jitter, all-digital delayed locked loop with a circuit to dynamically vary phase to achieve fast lock.” 2011. Masters Thesis, Northeastern University. Accessed April 02, 2020. http://hdl.handle.net/2047/d20002106.

MLA Handbook (7th Edition):

Begur, Soumya Shivakumar. “A 45nm CMOS, low jitter, all-digital delayed locked loop with a circuit to dynamically vary phase to achieve fast lock.” 2011. Web. 02 Apr 2020.

Vancouver:

Begur SS. A 45nm CMOS, low jitter, all-digital delayed locked loop with a circuit to dynamically vary phase to achieve fast lock. [Internet] [Masters thesis]. Northeastern University; 2011. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2047/d20002106.

Council of Science Editors:

Begur SS. A 45nm CMOS, low jitter, all-digital delayed locked loop with a circuit to dynamically vary phase to achieve fast lock. [Masters Thesis]. Northeastern University; 2011. Available from: http://hdl.handle.net/2047/d20002106


University of Tennessee – Knoxville

3. McCue, Benjamin Matthew. A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator.

Degree: MS, Electrical Engineering, 2010, University of Tennessee – Knoxville

 Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit… (more)

Subjects/Keywords: voltage regulator; high temperature; high voltage; silicon on insulator; gate driver; LM723; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

McCue, B. M. (2010). A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/646

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

McCue, Benjamin Matthew. “A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator.” 2010. Thesis, University of Tennessee – Knoxville. Accessed April 02, 2020. https://trace.tennessee.edu/utk_gradthes/646.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

McCue, Benjamin Matthew. “A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator.” 2010. Web. 02 Apr 2020.

Vancouver:

McCue BM. A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator. [Internet] [Thesis]. University of Tennessee – Knoxville; 2010. [cited 2020 Apr 02]. Available from: https://trace.tennessee.edu/utk_gradthes/646.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

McCue BM. A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator. [Thesis]. University of Tennessee – Knoxville; 2010. Available from: https://trace.tennessee.edu/utk_gradthes/646

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

4. Gummalla, Samatha. An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design.

Degree: MS, Electrical Engineering, 2011, Arizona State University

Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and… (more)

Subjects/Keywords: Electrical Engineering; Analytical Modeling; Delay Model; Modeling and performance analysis; Threshold voltage variation; Variability

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APA (6th Edition):

Gummalla, S. (2011). An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/9288

Chicago Manual of Style (16th Edition):

Gummalla, Samatha. “An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design.” 2011. Masters Thesis, Arizona State University. Accessed April 02, 2020. http://repository.asu.edu/items/9288.

MLA Handbook (7th Edition):

Gummalla, Samatha. “An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design.” 2011. Web. 02 Apr 2020.

Vancouver:

Gummalla S. An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design. [Internet] [Masters thesis]. Arizona State University; 2011. [cited 2020 Apr 02]. Available from: http://repository.asu.edu/items/9288.

Council of Science Editors:

Gummalla S. An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design. [Masters Thesis]. Arizona State University; 2011. Available from: http://repository.asu.edu/items/9288

5. Venkateshvaran, Deepak. Seebeck coefficient in organic semiconductors.

Degree: PhD, 2014, University of Cambridge

 When a temperature differential is applied across a semiconductor, a thermal voltage develops across it in response. The ratio of this thermal voltage to the… (more)

Subjects/Keywords: 621.3815; Organic Semiconductors; Thermoelectrics; Field Effect Transistor; Energetic Disorder; Vissenberg Matters Model; Microfabricated Temperature Sensors; Seebeck Coefficient; Charge Transport; Entropy; Gate Voltage Modulated Seebeck Coefficient

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APA (6th Edition):

Venkateshvaran, D. (2014). Seebeck coefficient in organic semiconductors. (Doctoral Dissertation). University of Cambridge. Retrieved from https://www.repository.cam.ac.uk/handle/1810/245517 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.607595

Chicago Manual of Style (16th Edition):

Venkateshvaran, Deepak. “Seebeck coefficient in organic semiconductors.” 2014. Doctoral Dissertation, University of Cambridge. Accessed April 02, 2020. https://www.repository.cam.ac.uk/handle/1810/245517 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.607595.

MLA Handbook (7th Edition):

Venkateshvaran, Deepak. “Seebeck coefficient in organic semiconductors.” 2014. Web. 02 Apr 2020.

Vancouver:

Venkateshvaran D. Seebeck coefficient in organic semiconductors. [Internet] [Doctoral dissertation]. University of Cambridge; 2014. [cited 2020 Apr 02]. Available from: https://www.repository.cam.ac.uk/handle/1810/245517 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.607595.

Council of Science Editors:

Venkateshvaran D. Seebeck coefficient in organic semiconductors. [Doctoral Dissertation]. University of Cambridge; 2014. Available from: https://www.repository.cam.ac.uk/handle/1810/245517 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.607595

6. Venkateshvaran, Deepak. Seebeck coefficient in organic semiconductors.

Degree: PhD, 2014, University of Cambridge

 When a temperature differential is applied across a semiconductor, a thermal voltage develops across it in response. The ratio of this thermal voltage to the… (more)

Subjects/Keywords: Organic Semiconductors; Thermoelectrics; Field Effect Transistor; Energetic Disorder; Vissenberg Matters Model; Microfabricated Temperature Sensors; Seebeck Coefficient; Charge Transport; Entropy; Gate Voltage Modulated Seebeck Coefficient

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APA (6th Edition):

Venkateshvaran, D. (2014). Seebeck coefficient in organic semiconductors. (Doctoral Dissertation). University of Cambridge. Retrieved from https://www.repository.cam.ac.uk/handle/1810/245517https://www.repository.cam.ac.uk/bitstream/1810/245517/5/E-thesis%20Venkateshvaran.pdf.txt ; https://www.repository.cam.ac.uk/bitstream/1810/245517/6/E-thesis%20Venkateshvaran.pdf.jpg

Chicago Manual of Style (16th Edition):

Venkateshvaran, Deepak. “Seebeck coefficient in organic semiconductors.” 2014. Doctoral Dissertation, University of Cambridge. Accessed April 02, 2020. https://www.repository.cam.ac.uk/handle/1810/245517https://www.repository.cam.ac.uk/bitstream/1810/245517/5/E-thesis%20Venkateshvaran.pdf.txt ; https://www.repository.cam.ac.uk/bitstream/1810/245517/6/E-thesis%20Venkateshvaran.pdf.jpg.

MLA Handbook (7th Edition):

Venkateshvaran, Deepak. “Seebeck coefficient in organic semiconductors.” 2014. Web. 02 Apr 2020.

Vancouver:

Venkateshvaran D. Seebeck coefficient in organic semiconductors. [Internet] [Doctoral dissertation]. University of Cambridge; 2014. [cited 2020 Apr 02]. Available from: https://www.repository.cam.ac.uk/handle/1810/245517https://www.repository.cam.ac.uk/bitstream/1810/245517/5/E-thesis%20Venkateshvaran.pdf.txt ; https://www.repository.cam.ac.uk/bitstream/1810/245517/6/E-thesis%20Venkateshvaran.pdf.jpg.

Council of Science Editors:

Venkateshvaran D. Seebeck coefficient in organic semiconductors. [Doctoral Dissertation]. University of Cambridge; 2014. Available from: https://www.repository.cam.ac.uk/handle/1810/245517https://www.repository.cam.ac.uk/bitstream/1810/245517/5/E-thesis%20Venkateshvaran.pdf.txt ; https://www.repository.cam.ac.uk/bitstream/1810/245517/6/E-thesis%20Venkateshvaran.pdf.jpg


University of Central Florida

7. Kutty, Karan. Class-e Cascode Power Amplifier Analysis And Design For Long Term Reliability.

Degree: 2010, University of Central Florida

 This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching… (more)

Subjects/Keywords: power amplifier; class-E; cascode; gate oxide; breakdown; oxide breakdown; model; TSMC; voltage stress; zero voltage switching; Electrical and Computer Engineering; Electrical and Electronics; Engineering

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APA (6th Edition):

Kutty, K. (2010). Class-e Cascode Power Amplifier Analysis And Design For Long Term Reliability. (Masters Thesis). University of Central Florida. Retrieved from https://stars.library.ucf.edu/etd/4445

Chicago Manual of Style (16th Edition):

Kutty, Karan. “Class-e Cascode Power Amplifier Analysis And Design For Long Term Reliability.” 2010. Masters Thesis, University of Central Florida. Accessed April 02, 2020. https://stars.library.ucf.edu/etd/4445.

MLA Handbook (7th Edition):

Kutty, Karan. “Class-e Cascode Power Amplifier Analysis And Design For Long Term Reliability.” 2010. Web. 02 Apr 2020.

Vancouver:

Kutty K. Class-e Cascode Power Amplifier Analysis And Design For Long Term Reliability. [Internet] [Masters thesis]. University of Central Florida; 2010. [cited 2020 Apr 02]. Available from: https://stars.library.ucf.edu/etd/4445.

Council of Science Editors:

Kutty K. Class-e Cascode Power Amplifier Analysis And Design For Long Term Reliability. [Masters Thesis]. University of Central Florida; 2010. Available from: https://stars.library.ucf.edu/etd/4445

8. Xie, Jiani. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization.

Degree: PhD, Electrical Engineering and Computer Science, 2014, Syracuse University

  The modeling of an individual gate and the optimization of circuit performance has long been a critical issue in the VLSI industry. In this… (more)

Subjects/Keywords: Circuit optimization; Delay minimization; Discrete gate sizing; Gate and delay model; Power optimization; Engineering

…different gate models. 1.2 Gate Model The way we model the gate and evaluate the delay is of… …its accuracy and simplicity. Since the modified Elmore delay model works for gate sizing… …79 Table 5. 4. Delay Comparison between Modified Elmore Delay Model and Classic Elmore… …circuit delay, layout area or power consumption, etc. Gate sizing is a flexible and powerful… …gate sizing problem for delay 2 minimization. And we may solve the power minimization… 

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APA (6th Edition):

Xie, J. (2014). Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. (Doctoral Dissertation). Syracuse University. Retrieved from https://surface.syr.edu/etd/201

Chicago Manual of Style (16th Edition):

Xie, Jiani. “Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization.” 2014. Doctoral Dissertation, Syracuse University. Accessed April 02, 2020. https://surface.syr.edu/etd/201.

MLA Handbook (7th Edition):

Xie, Jiani. “Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization.” 2014. Web. 02 Apr 2020.

Vancouver:

Xie J. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. [Internet] [Doctoral dissertation]. Syracuse University; 2014. [cited 2020 Apr 02]. Available from: https://surface.syr.edu/etd/201.

Council of Science Editors:

Xie J. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. [Doctoral Dissertation]. Syracuse University; 2014. Available from: https://surface.syr.edu/etd/201


University of Arkansas

9. Lamichhane, Ranjan Raj. A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications.

Degree: MSEE, 2013, University of Arkansas

  The potential of silicon carbide (SiC) for modern power electronics applications is revolutionary because of its superior material properties including substantially better breakdown voltage,… (more)

Subjects/Keywords: Applied sciences; Gate driver; High temperature integrated circuit; High voltage integrated circuit; Integrated circuits integrated circuit; Power electronics; silicon carbide; Electrical and Electronics

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APA (6th Edition):

Lamichhane, R. R. (2013). A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/948

Chicago Manual of Style (16th Edition):

Lamichhane, Ranjan Raj. “A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications.” 2013. Masters Thesis, University of Arkansas. Accessed April 02, 2020. https://scholarworks.uark.edu/etd/948.

MLA Handbook (7th Edition):

Lamichhane, Ranjan Raj. “A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications.” 2013. Web. 02 Apr 2020.

Vancouver:

Lamichhane RR. A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications. [Internet] [Masters thesis]. University of Arkansas; 2013. [cited 2020 Apr 02]. Available from: https://scholarworks.uark.edu/etd/948.

Council of Science Editors:

Lamichhane RR. A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications. [Masters Thesis]. University of Arkansas; 2013. Available from: https://scholarworks.uark.edu/etd/948

10. Rathnala, Prasanthi. Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation.

Degree: PhD, 2017, University of Derby

 Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the… (more)

Subjects/Keywords: 004.67; Differential power analysis; Dynamic voltage and frequency scaling; Internet of things; S-Box; Low power performance improvement; Time-Borrowing; Timing Error; Aggressive Scaling; Process voltage and temperature

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APA (6th Edition):

Rathnala, P. (2017). Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation. (Doctoral Dissertation). University of Derby. Retrieved from http://hdl.handle.net/10545/621716

Chicago Manual of Style (16th Edition):

Rathnala, Prasanthi. “Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation.” 2017. Doctoral Dissertation, University of Derby. Accessed April 02, 2020. http://hdl.handle.net/10545/621716.

MLA Handbook (7th Edition):

Rathnala, Prasanthi. “Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation.” 2017. Web. 02 Apr 2020.

Vancouver:

Rathnala P. Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation. [Internet] [Doctoral dissertation]. University of Derby; 2017. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10545/621716.

Council of Science Editors:

Rathnala P. Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation. [Doctoral Dissertation]. University of Derby; 2017. Available from: http://hdl.handle.net/10545/621716


Universidade do Rio Grande do Sul

11. Posser, Gracieli. Dimensionamento de portas lógicas usando programação geométrica.

Degree: 2011, Universidade do Rio Grande do Sul

Neste trabalho é desenvolvida uma ferramenta de dimensionamento de portas lógicas para circuitos integrados, utilizando técnicas de otimização de problemas baseadas em Programação Geométrica (PG).… (more)

Subjects/Keywords: Gate sizing; Microeletrônica; Physical synthesis; Circuitos integrados; Sintese automatica; Geometric programming; Elmore delay model; Microelectronics

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APA (6th Edition):

Posser, G. (2011). Dimensionamento de portas lógicas usando programação geométrica. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/29571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Posser, Gracieli. “Dimensionamento de portas lógicas usando programação geométrica.” 2011. Thesis, Universidade do Rio Grande do Sul. Accessed April 02, 2020. http://hdl.handle.net/10183/29571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Posser, Gracieli. “Dimensionamento de portas lógicas usando programação geométrica.” 2011. Web. 02 Apr 2020.

Vancouver:

Posser G. Dimensionamento de portas lógicas usando programação geométrica. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2011. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10183/29571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Posser G. Dimensionamento de portas lógicas usando programação geométrica. [Thesis]. Universidade do Rio Grande do Sul; 2011. Available from: http://hdl.handle.net/10183/29571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Irvine

12. Pirbadian, Aras. Analytical State Depended Timing Model for Voltage Scaled Circuits & Low Overhead Delay-Based Physically Unclonable Function.

Degree: Electrical and Computer Engineering, 2016, University of California – Irvine

 With the continued scaling of chip manufacturing technologies, the significance of process variation in performance of the systems is increasing. Specifically, process variation results in… (more)

Subjects/Keywords: Electrical engineering; Analytical Model; Delay Based PUF; Physically Unclonable Function; Timing Model; Voltage Scaled

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APA (6th Edition):

Pirbadian, A. (2016). Analytical State Depended Timing Model for Voltage Scaled Circuits & Low Overhead Delay-Based Physically Unclonable Function. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/5ff3s3qs

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pirbadian, Aras. “Analytical State Depended Timing Model for Voltage Scaled Circuits & Low Overhead Delay-Based Physically Unclonable Function.” 2016. Thesis, University of California – Irvine. Accessed April 02, 2020. http://www.escholarship.org/uc/item/5ff3s3qs.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pirbadian, Aras. “Analytical State Depended Timing Model for Voltage Scaled Circuits & Low Overhead Delay-Based Physically Unclonable Function.” 2016. Web. 02 Apr 2020.

Vancouver:

Pirbadian A. Analytical State Depended Timing Model for Voltage Scaled Circuits & Low Overhead Delay-Based Physically Unclonable Function. [Internet] [Thesis]. University of California – Irvine; 2016. [cited 2020 Apr 02]. Available from: http://www.escholarship.org/uc/item/5ff3s3qs.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pirbadian A. Analytical State Depended Timing Model for Voltage Scaled Circuits & Low Overhead Delay-Based Physically Unclonable Function. [Thesis]. University of California – Irvine; 2016. Available from: http://www.escholarship.org/uc/item/5ff3s3qs

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Dalhousie University

13. Nateghi, Hamidreza. A Self-Healing Technique Using ZTC Biasing for PVT Variations Compensation in 65nm CMOS Technology.

Degree: Master of Applied Science, Department of Electrical & Computer Engineering, 2014, Dalhousie University

 This thesis proposes a digital oriented self-healing technique in 65nm CMOS technology for current sources by biasing the current reference transistor in the vicinity of… (more)

Subjects/Keywords: Process Compensation; Zero Temperature Coefficient; Temperature Compensation; Voltage Compensation; Self-Healing Technique

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APA (6th Edition):

Nateghi, H. (2014). A Self-Healing Technique Using ZTC Biasing for PVT Variations Compensation in 65nm CMOS Technology. (Masters Thesis). Dalhousie University. Retrieved from http://hdl.handle.net/10222/56036

Chicago Manual of Style (16th Edition):

Nateghi, Hamidreza. “A Self-Healing Technique Using ZTC Biasing for PVT Variations Compensation in 65nm CMOS Technology.” 2014. Masters Thesis, Dalhousie University. Accessed April 02, 2020. http://hdl.handle.net/10222/56036.

MLA Handbook (7th Edition):

Nateghi, Hamidreza. “A Self-Healing Technique Using ZTC Biasing for PVT Variations Compensation in 65nm CMOS Technology.” 2014. Web. 02 Apr 2020.

Vancouver:

Nateghi H. A Self-Healing Technique Using ZTC Biasing for PVT Variations Compensation in 65nm CMOS Technology. [Internet] [Masters thesis]. Dalhousie University; 2014. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10222/56036.

Council of Science Editors:

Nateghi H. A Self-Healing Technique Using ZTC Biasing for PVT Variations Compensation in 65nm CMOS Technology. [Masters Thesis]. Dalhousie University; 2014. Available from: http://hdl.handle.net/10222/56036


University of Southern California

14. Das, Prasanjeet. A variation aware resilient framework for post-silicon delay validation of high performance circuits.

Degree: PhD, Electrical Engineering, 2013, University of Southern California

 Despite advances in design and verification, it is becoming increasingly common for high-performance designs to misbehave on silicon. This is due to performance issues, such… (more)

Subjects/Keywords: post-silicon; delay validation; marginality; process variations; delay model; multiple input switching

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APA (6th Edition):

Das, P. (2013). A variation aware resilient framework for post-silicon delay validation of high performance circuits. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/219698/rec/446

Chicago Manual of Style (16th Edition):

Das, Prasanjeet. “A variation aware resilient framework for post-silicon delay validation of high performance circuits.” 2013. Doctoral Dissertation, University of Southern California. Accessed April 02, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/219698/rec/446.

MLA Handbook (7th Edition):

Das, Prasanjeet. “A variation aware resilient framework for post-silicon delay validation of high performance circuits.” 2013. Web. 02 Apr 2020.

Vancouver:

Das P. A variation aware resilient framework for post-silicon delay validation of high performance circuits. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2020 Apr 02]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/219698/rec/446.

Council of Science Editors:

Das P. A variation aware resilient framework for post-silicon delay validation of high performance circuits. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/219698/rec/446


University of Toronto

15. Xie, Shuang. VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors.

Degree: PhD, 2014, University of Toronto

 The power density of microprocessor chips continues to rise due to the growing demand on microprocessor performance and technology scaling. The resulting temperature rise and… (more)

Subjects/Keywords: delay lines; digital temperature sensor; field programmable gate arrays; power management; self-calibration; thermal management; 0544

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APA (6th Edition):

Xie, S. (2014). VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/68366

Chicago Manual of Style (16th Edition):

Xie, Shuang. “VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors.” 2014. Doctoral Dissertation, University of Toronto. Accessed April 02, 2020. http://hdl.handle.net/1807/68366.

MLA Handbook (7th Edition):

Xie, Shuang. “VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors.” 2014. Web. 02 Apr 2020.

Vancouver:

Xie S. VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors. [Internet] [Doctoral dissertation]. University of Toronto; 2014. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/1807/68366.

Council of Science Editors:

Xie S. VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors. [Doctoral Dissertation]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/68366


Louisiana State University

16. Mohammadi Banadaki, Yaser. Physical Modeling of Graphene Nanoribbon Field Effect Transistor Using Non-Equilibrium Green Function Approach for Integrated Circuit Design.

Degree: PhD, Electrical and Computer Engineering, 2016, Louisiana State University

 The driving engine for the exponential growth of digital information processing systems is scaling down the transistor dimensions. For decades, this has enhanced the device… (more)

Subjects/Keywords: NEGF formalism; Tunneling Current Intrinsic Gate-delay Time; Tight-binding Model; Wider Armchair GNR; Subthreshold Swing; Narrow Armchair GNR; DIBL; Cut-off Frequency; Emerging Material and Devices; Moore's Law; Non-equilibrium Green's Function Approach; Position- dependent effective mass model; Effective Mass Model; Power-delay Product; GNRFET; Graphene Nanoribbon Field Effect Transistor; Quantum Transport Model

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APA (6th Edition):

Mohammadi Banadaki, Y. (2016). Physical Modeling of Graphene Nanoribbon Field Effect Transistor Using Non-Equilibrium Green Function Approach for Integrated Circuit Design. (Doctoral Dissertation). Louisiana State University. Retrieved from etd-03292016-151830 ; https://digitalcommons.lsu.edu/gradschool_dissertations/1052

Chicago Manual of Style (16th Edition):

Mohammadi Banadaki, Yaser. “Physical Modeling of Graphene Nanoribbon Field Effect Transistor Using Non-Equilibrium Green Function Approach for Integrated Circuit Design.” 2016. Doctoral Dissertation, Louisiana State University. Accessed April 02, 2020. etd-03292016-151830 ; https://digitalcommons.lsu.edu/gradschool_dissertations/1052.

MLA Handbook (7th Edition):

Mohammadi Banadaki, Yaser. “Physical Modeling of Graphene Nanoribbon Field Effect Transistor Using Non-Equilibrium Green Function Approach for Integrated Circuit Design.” 2016. Web. 02 Apr 2020.

Vancouver:

Mohammadi Banadaki Y. Physical Modeling of Graphene Nanoribbon Field Effect Transistor Using Non-Equilibrium Green Function Approach for Integrated Circuit Design. [Internet] [Doctoral dissertation]. Louisiana State University; 2016. [cited 2020 Apr 02]. Available from: etd-03292016-151830 ; https://digitalcommons.lsu.edu/gradschool_dissertations/1052.

Council of Science Editors:

Mohammadi Banadaki Y. Physical Modeling of Graphene Nanoribbon Field Effect Transistor Using Non-Equilibrium Green Function Approach for Integrated Circuit Design. [Doctoral Dissertation]. Louisiana State University; 2016. Available from: etd-03292016-151830 ; https://digitalcommons.lsu.edu/gradschool_dissertations/1052


Northeastern University

17. Ni, Yuchi. Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation.

Degree: MS, Department of Electrical and Computer Engineering, 2013, Northeastern University

 Low-power oscillators are essential components of battery-powered medical devices for which the battery life must be maximized, such as pacemakers, blood glucose meters and heart… (more)

Subjects/Keywords: CMOS process variations; Low-power analog design; Reference current generation; Reference voltage generation; Relaxation oscillator; Temperature compensation; Electrical and Computer Engineering; Engineering

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APA (6th Edition):

Ni, Y. (2013). Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20004909

Chicago Manual of Style (16th Edition):

Ni, Yuchi. “Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation.” 2013. Masters Thesis, Northeastern University. Accessed April 02, 2020. http://hdl.handle.net/2047/d20004909.

MLA Handbook (7th Edition):

Ni, Yuchi. “Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation.” 2013. Web. 02 Apr 2020.

Vancouver:

Ni Y. Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation. [Internet] [Masters thesis]. Northeastern University; 2013. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2047/d20004909.

Council of Science Editors:

Ni Y. Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation. [Masters Thesis]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20004909


University of South Florida

18. Hanchate, Narender. A game theoretic framework for interconnect optimization in deep submicron and nanometer design.

Degree: 2006, University of South Florida

 The continuous scaling of interconnect wires in deep submicron (DSM)circuits result in increased interconnect delay, power and crosstalk noise. In this dissertation, we address the… (more)

Subjects/Keywords: Game theory; Crosstalk noise; Interconnect delay; Process variations; Delay uncertainty; Transmission line models; Wire sizing; Gate sizing; American Studies; Arts and Humanities

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APA (6th Edition):

Hanchate, N. (2006). A game theoretic framework for interconnect optimization in deep submicron and nanometer design. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/2545

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hanchate, Narender. “A game theoretic framework for interconnect optimization in deep submicron and nanometer design.” 2006. Thesis, University of South Florida. Accessed April 02, 2020. https://scholarcommons.usf.edu/etd/2545.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hanchate, Narender. “A game theoretic framework for interconnect optimization in deep submicron and nanometer design.” 2006. Web. 02 Apr 2020.

Vancouver:

Hanchate N. A game theoretic framework for interconnect optimization in deep submicron and nanometer design. [Internet] [Thesis]. University of South Florida; 2006. [cited 2020 Apr 02]. Available from: https://scholarcommons.usf.edu/etd/2545.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hanchate N. A game theoretic framework for interconnect optimization in deep submicron and nanometer design. [Thesis]. University of South Florida; 2006. Available from: https://scholarcommons.usf.edu/etd/2545

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

19. Su, Chia Hung. A High -Temperature, High-Voltage, Fast Response Time Linear Regulator in 0.8um BCD-on-SOI.

Degree: 2010, University of Tennessee – Knoxville

 The sale of hybrid electric vehicles (HEVs) has increased tenfold from the year 2001 to 2009 [1]. With this the demand for high temperature electronics… (more)

Subjects/Keywords: High-temperature; SOI; CMOS; voltage regulator; high-voltage; fast response; Electrical and Electronics

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APA (6th Edition):

Su, C. H. (2010). A High -Temperature, High-Voltage, Fast Response Time Linear Regulator in 0.8um BCD-on-SOI. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/851

Chicago Manual of Style (16th Edition):

Su, Chia Hung. “A High -Temperature, High-Voltage, Fast Response Time Linear Regulator in 0.8um BCD-on-SOI.” 2010. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed April 02, 2020. https://trace.tennessee.edu/utk_graddiss/851.

MLA Handbook (7th Edition):

Su, Chia Hung. “A High -Temperature, High-Voltage, Fast Response Time Linear Regulator in 0.8um BCD-on-SOI.” 2010. Web. 02 Apr 2020.

Vancouver:

Su CH. A High -Temperature, High-Voltage, Fast Response Time Linear Regulator in 0.8um BCD-on-SOI. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2010. [cited 2020 Apr 02]. Available from: https://trace.tennessee.edu/utk_graddiss/851.

Council of Science Editors:

Su CH. A High -Temperature, High-Voltage, Fast Response Time Linear Regulator in 0.8um BCD-on-SOI. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2010. Available from: https://trace.tennessee.edu/utk_graddiss/851


West Virginia University

20. Tucker, Kody Ray. Low Power Voltage Reference Cells for Sensing Applications.

Degree: MS, Lane Department of Computer Science and Electrical Engineering, 2019, West Virginia University

  Two low-power voltage reference cells for a system on-chip design are presented in this report. Both cells utilize a combination of standard transistors to… (more)

Subjects/Keywords: Analog; Layout; Low Power; Output Voltage; Simulation; Reference Voltage; Temperature Coefficent; Electrical and Electronics

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APA (6th Edition):

Tucker, K. R. (2019). Low Power Voltage Reference Cells for Sensing Applications. (Thesis). West Virginia University. Retrieved from https://researchrepository.wvu.edu/etd/7403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tucker, Kody Ray. “Low Power Voltage Reference Cells for Sensing Applications.” 2019. Thesis, West Virginia University. Accessed April 02, 2020. https://researchrepository.wvu.edu/etd/7403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tucker, Kody Ray. “Low Power Voltage Reference Cells for Sensing Applications.” 2019. Web. 02 Apr 2020.

Vancouver:

Tucker KR. Low Power Voltage Reference Cells for Sensing Applications. [Internet] [Thesis]. West Virginia University; 2019. [cited 2020 Apr 02]. Available from: https://researchrepository.wvu.edu/etd/7403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tucker KR. Low Power Voltage Reference Cells for Sensing Applications. [Thesis]. West Virginia University; 2019. Available from: https://researchrepository.wvu.edu/etd/7403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Northeastern University

21. Lu, Jing. Hybrid DPWM with process and temperature calibration.

Degree: MS, Department of Electrical and Computer Engineering, 2016, Northeastern University

 In this thesis, a 12-bit high resolution, power and area efficiency hybrid DPWM with process and temperature calibration is proposed for DPWM controller IC for… (more)

Subjects/Keywords: buck controller; digital power; hybrid DPWM; process calibration; temperature calibration; Electronic controllers; Design and construction; Digital control systems; Design and construction; Pulse-duration modulation; Pulse modulation (Electronics); DC-to-DC converters; Delay lines; Temperature measuring instruments; Calibration

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APA (6th Edition):

Lu, J. (2016). Hybrid DPWM with process and temperature calibration. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20195190

Chicago Manual of Style (16th Edition):

Lu, Jing. “Hybrid DPWM with process and temperature calibration.” 2016. Masters Thesis, Northeastern University. Accessed April 02, 2020. http://hdl.handle.net/2047/D20195190.

MLA Handbook (7th Edition):

Lu, Jing. “Hybrid DPWM with process and temperature calibration.” 2016. Web. 02 Apr 2020.

Vancouver:

Lu J. Hybrid DPWM with process and temperature calibration. [Internet] [Masters thesis]. Northeastern University; 2016. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2047/D20195190.

Council of Science Editors:

Lu J. Hybrid DPWM with process and temperature calibration. [Masters Thesis]. Northeastern University; 2016. Available from: http://hdl.handle.net/2047/D20195190


University of Tennessee – Knoxville

22. Omoumi, Kevin Christopher. Design of a High-Voltage, Differential Drive Bradbury-Nielsen Gate Amplifier with Ultra-High Slew Rate and Input Isolation.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

 To isolate and study various components of a nuclear reaction, elaborate equipment must be developed to aid in this process. This thesis presents the design… (more)

Subjects/Keywords: High-voltage Amplifier; Input Isolation; Bradbury-Nielsen Gate; Electrical and Electronics; Electronic Devices and Semiconductor Manufacturing; Other Electrical and Computer Engineering

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APA (6th Edition):

Omoumi, K. C. (2011). Design of a High-Voltage, Differential Drive Bradbury-Nielsen Gate Amplifier with Ultra-High Slew Rate and Input Isolation. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/901

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Omoumi, Kevin Christopher. “Design of a High-Voltage, Differential Drive Bradbury-Nielsen Gate Amplifier with Ultra-High Slew Rate and Input Isolation.” 2011. Thesis, University of Tennessee – Knoxville. Accessed April 02, 2020. https://trace.tennessee.edu/utk_gradthes/901.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Omoumi, Kevin Christopher. “Design of a High-Voltage, Differential Drive Bradbury-Nielsen Gate Amplifier with Ultra-High Slew Rate and Input Isolation.” 2011. Web. 02 Apr 2020.

Vancouver:

Omoumi KC. Design of a High-Voltage, Differential Drive Bradbury-Nielsen Gate Amplifier with Ultra-High Slew Rate and Input Isolation. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2020 Apr 02]. Available from: https://trace.tennessee.edu/utk_gradthes/901.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Omoumi KC. Design of a High-Voltage, Differential Drive Bradbury-Nielsen Gate Amplifier with Ultra-High Slew Rate and Input Isolation. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/901

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Lo , Ping-Chi. Development of Temperature Compensation and Calibration Circuits for EGFET-based Ion Sensor.

Degree: Master, Electrical Engineering, 2014, NSYSU

 In the last decade,various structural designs and sensing mechanisms of ion sensors have been widely used in industrial,environmental monitoring and biomedical areas.However,the sensing characteristics of… (more)

Subjects/Keywords: compensation and calibration circuit; temperature effect; micro-electromechanical system; extended-gate field-effect transistor

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APA (6th Edition):

Lo , P. (2014). Development of Temperature Compensation and Calibration Circuits for EGFET-based Ion Sensor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-131520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lo , Ping-Chi. “Development of Temperature Compensation and Calibration Circuits for EGFET-based Ion Sensor.” 2014. Thesis, NSYSU. Accessed April 02, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-131520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lo , Ping-Chi. “Development of Temperature Compensation and Calibration Circuits for EGFET-based Ion Sensor.” 2014. Web. 02 Apr 2020.

Vancouver:

Lo P. Development of Temperature Compensation and Calibration Circuits for EGFET-based Ion Sensor. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Apr 02]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-131520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lo P. Development of Temperature Compensation and Calibration Circuits for EGFET-based Ion Sensor. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-131520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

24. Huque, Mohammad Aminul. A High-Temperature, High-Voltage SOI Gate Driver Integrated Circuit with High Drive Current for Silicon Carbide Power Switches.

Degree: 2010, University of Tennessee – Knoxville

 High-temperature integrated circuit (IC) design is one of the new frontiers in microelectronics that can significantly improve the performance of the electrical systems in extreme… (more)

Subjects/Keywords: high temperature; microelectronics; gate; driver; integrated; circuit; current; power switches; power; Electrical and Computer Engineering

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APA (6th Edition):

Huque, M. A. (2010). A High-Temperature, High-Voltage SOI Gate Driver Integrated Circuit with High Drive Current for Silicon Carbide Power Switches. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/706

Chicago Manual of Style (16th Edition):

Huque, Mohammad Aminul. “A High-Temperature, High-Voltage SOI Gate Driver Integrated Circuit with High Drive Current for Silicon Carbide Power Switches.” 2010. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed April 02, 2020. https://trace.tennessee.edu/utk_graddiss/706.

MLA Handbook (7th Edition):

Huque, Mohammad Aminul. “A High-Temperature, High-Voltage SOI Gate Driver Integrated Circuit with High Drive Current for Silicon Carbide Power Switches.” 2010. Web. 02 Apr 2020.

Vancouver:

Huque MA. A High-Temperature, High-Voltage SOI Gate Driver Integrated Circuit with High Drive Current for Silicon Carbide Power Switches. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2010. [cited 2020 Apr 02]. Available from: https://trace.tennessee.edu/utk_graddiss/706.

Council of Science Editors:

Huque MA. A High-Temperature, High-Voltage SOI Gate Driver Integrated Circuit with High Drive Current for Silicon Carbide Power Switches. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2010. Available from: https://trace.tennessee.edu/utk_graddiss/706

25. Doria, Renan Trevisoli. Operação e modelagem de transistores MOS sem junções.

Degree: PhD, Microeletrônica, 2013, University of São Paulo

Neste trabalho é apresentado um estudo dos transistores MOS sem junções (Junctionless Nanowire Transistors - JNTs), cujo foco é a modelagem de suas características elétricas… (more)

Subjects/Keywords: Extraction method; Junctionless; Junctionless nanowire transistors; Método de extração; Modelagem; Modeling; Múltiplas portas; Multiple-gate; Temperatura; Temperature; Tensão de limiar; Threshold voltage; Transistor MOS sem junções

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APA (6th Edition):

Doria, R. T. (2013). Operação e modelagem de transistores MOS sem junções. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01082013-162413/ ;

Chicago Manual of Style (16th Edition):

Doria, Renan Trevisoli. “Operação e modelagem de transistores MOS sem junções.” 2013. Doctoral Dissertation, University of São Paulo. Accessed April 02, 2020. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01082013-162413/ ;.

MLA Handbook (7th Edition):

Doria, Renan Trevisoli. “Operação e modelagem de transistores MOS sem junções.” 2013. Web. 02 Apr 2020.

Vancouver:

Doria RT. Operação e modelagem de transistores MOS sem junções. [Internet] [Doctoral dissertation]. University of São Paulo; 2013. [cited 2020 Apr 02]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01082013-162413/ ;.

Council of Science Editors:

Doria RT. Operação e modelagem de transistores MOS sem junções. [Doctoral Dissertation]. University of São Paulo; 2013. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01082013-162413/ ;


The Ohio State University

26. Qi, Feng. Peripheral Circuits Study for High Temperature Inverters Using SiC MOSFETs.

Degree: PhD, Electrical and Computer Engineering, 2016, The Ohio State University

 During the last decade, Silicon-Carbide (SiC) power devices have attracted great attention in various industry applications such as hybrid electric vehicles, electric vehicles, and down-hole… (more)

Subjects/Keywords: Electrical Engineering; SiC MOSFET, gate drive circuit, galvanic isolation circuit, desaturation protection, under voltage protection, high temperature, three-phase inverter, commercial off-the-shelf

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APA (6th Edition):

Qi, F. (2016). Peripheral Circuits Study for High Temperature Inverters Using SiC MOSFETs. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1460991531

Chicago Manual of Style (16th Edition):

Qi, Feng. “Peripheral Circuits Study for High Temperature Inverters Using SiC MOSFETs.” 2016. Doctoral Dissertation, The Ohio State University. Accessed April 02, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1460991531.

MLA Handbook (7th Edition):

Qi, Feng. “Peripheral Circuits Study for High Temperature Inverters Using SiC MOSFETs.” 2016. Web. 02 Apr 2020.

Vancouver:

Qi F. Peripheral Circuits Study for High Temperature Inverters Using SiC MOSFETs. [Internet] [Doctoral dissertation]. The Ohio State University; 2016. [cited 2020 Apr 02]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1460991531.

Council of Science Editors:

Qi F. Peripheral Circuits Study for High Temperature Inverters Using SiC MOSFETs. [Doctoral Dissertation]. The Ohio State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1460991531

27. Molin, Quentin. Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits : High Voltage SiC MOSFET Robustness study : Threshold voltage shift and short-circuit behavior.

Degree: Docteur es, Electronique, électrotechnique, automatique, 2018, Lyon

Ce manuscrit est une contribution à l’étude de la fiabilité et de la robustesse des composants MOSFET sur carbure de silicium, matériau semi-conducteur grand gap… (more)

Subjects/Keywords: Electronique de puissance; Interrupteur de puissance; Vieillissement; Fiabilité; High Temperature Gate Bias - HTGB; High Temperature Gate Switching - HTGS; Robustesse; Court-Cicuits; Court-Circuits répétitifs; Dérive; Tension de seuil; Oxyde; Instabilité; Modélisation; Pompage de charge trois terminaux; C-V; Power Electronics; Power switches; MOSFET SiC; Ageing; Reliability; High Temperature Gate Bias - HTGB; High Temperature Gate Switching - HTGS; Short-Circuits; Repetitive short-Circuits; Threshold voltage; Oxide; Instability; Modelization; Protocols; Three terminals charge pumping; C-V; 621.317 072

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APA (6th Edition):

Molin, Q. (2018). Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits : High Voltage SiC MOSFET Robustness study : Threshold voltage shift and short-circuit behavior. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2018LYSEI111

Chicago Manual of Style (16th Edition):

Molin, Quentin. “Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits : High Voltage SiC MOSFET Robustness study : Threshold voltage shift and short-circuit behavior.” 2018. Doctoral Dissertation, Lyon. Accessed April 02, 2020. http://www.theses.fr/2018LYSEI111.

MLA Handbook (7th Edition):

Molin, Quentin. “Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits : High Voltage SiC MOSFET Robustness study : Threshold voltage shift and short-circuit behavior.” 2018. Web. 02 Apr 2020.

Vancouver:

Molin Q. Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits : High Voltage SiC MOSFET Robustness study : Threshold voltage shift and short-circuit behavior. [Internet] [Doctoral dissertation]. Lyon; 2018. [cited 2020 Apr 02]. Available from: http://www.theses.fr/2018LYSEI111.

Council of Science Editors:

Molin Q. Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits : High Voltage SiC MOSFET Robustness study : Threshold voltage shift and short-circuit behavior. [Doctoral Dissertation]. Lyon; 2018. Available from: http://www.theses.fr/2018LYSEI111


University of Pennsylvania

28. King, Chih. The Role of Kv7 in Peripheral Neurons.

Degree: 2012, University of Pennsylvania

 The Kv7 (KCNQ) channel is a family of voltage-gated potassium channels that is considered to be important in the regulation of cellular excitability and axonal… (more)

Subjects/Keywords: Dorsal Root Ganglion; KCNQ; Kv7; Nociception; Sensory Neuron; Voltage-gate Potassium Channels; Biology; Medicine and Health Sciences; Neuroscience and Neurobiology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

King, C. (2012). The Role of Kv7 in Peripheral Neurons. (Thesis). University of Pennsylvania. Retrieved from https://repository.upenn.edu/edissertations/476

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

King, Chih. “The Role of Kv7 in Peripheral Neurons.” 2012. Thesis, University of Pennsylvania. Accessed April 02, 2020. https://repository.upenn.edu/edissertations/476.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

King, Chih. “The Role of Kv7 in Peripheral Neurons.” 2012. Web. 02 Apr 2020.

Vancouver:

King C. The Role of Kv7 in Peripheral Neurons. [Internet] [Thesis]. University of Pennsylvania; 2012. [cited 2020 Apr 02]. Available from: https://repository.upenn.edu/edissertations/476.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

King C. The Role of Kv7 in Peripheral Neurons. [Thesis]. University of Pennsylvania; 2012. Available from: https://repository.upenn.edu/edissertations/476

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Queens University

29. Fu, Jizhen. Topologies and Modelings of Novel Bipolar Gate Driver Techniques for Next-Generation High Frequency Voltage Regulators .

Degree: Electrical and Computer Engineering, 2010, Queens University

 As is predicted by Moore’s law, the transistors in microprocessors increase dramatically. In order to increase the power density of the microprocessors, the switching frequency… (more)

Subjects/Keywords: Voltage Regulators; Bipolar Gate Driver; Current Source Driver; Inductorless Gate Driver

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fu, J. (2010). Topologies and Modelings of Novel Bipolar Gate Driver Techniques for Next-Generation High Frequency Voltage Regulators . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/5950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fu, Jizhen. “Topologies and Modelings of Novel Bipolar Gate Driver Techniques for Next-Generation High Frequency Voltage Regulators .” 2010. Thesis, Queens University. Accessed April 02, 2020. http://hdl.handle.net/1974/5950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fu, Jizhen. “Topologies and Modelings of Novel Bipolar Gate Driver Techniques for Next-Generation High Frequency Voltage Regulators .” 2010. Web. 02 Apr 2020.

Vancouver:

Fu J. Topologies and Modelings of Novel Bipolar Gate Driver Techniques for Next-Generation High Frequency Voltage Regulators . [Internet] [Thesis]. Queens University; 2010. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/1974/5950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fu J. Topologies and Modelings of Novel Bipolar Gate Driver Techniques for Next-Generation High Frequency Voltage Regulators . [Thesis]. Queens University; 2010. Available from: http://hdl.handle.net/1974/5950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Western Ontario

30. Bala Subramanian, Sridhar. State Space Modeling of Smart PV Inverter as STATCOM (PV-STATCOM) for Voltage Control in a Distribution System.

Degree: 2016, University of Western Ontario

 The grid integration of photovoltaic (PV) systems in distribution networks is facing challenges such as transient changes in voltage due to fluctuations in generated real… (more)

Subjects/Keywords: Smart Photovoltaic (PV) Inverter; PV-STATCOM; Voltage Flicker; Low Voltage Ride Through; State Space Model; Voltage Control; Power and Energy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bala Subramanian, S. (2016). State Space Modeling of Smart PV Inverter as STATCOM (PV-STATCOM) for Voltage Control in a Distribution System. (Thesis). University of Western Ontario. Retrieved from https://ir.lib.uwo.ca/etd/3764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bala Subramanian, Sridhar. “State Space Modeling of Smart PV Inverter as STATCOM (PV-STATCOM) for Voltage Control in a Distribution System.” 2016. Thesis, University of Western Ontario. Accessed April 02, 2020. https://ir.lib.uwo.ca/etd/3764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bala Subramanian, Sridhar. “State Space Modeling of Smart PV Inverter as STATCOM (PV-STATCOM) for Voltage Control in a Distribution System.” 2016. Web. 02 Apr 2020.

Vancouver:

Bala Subramanian S. State Space Modeling of Smart PV Inverter as STATCOM (PV-STATCOM) for Voltage Control in a Distribution System. [Internet] [Thesis]. University of Western Ontario; 2016. [cited 2020 Apr 02]. Available from: https://ir.lib.uwo.ca/etd/3764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bala Subramanian S. State Space Modeling of Smart PV Inverter as STATCOM (PV-STATCOM) for Voltage Control in a Distribution System. [Thesis]. University of Western Ontario; 2016. Available from: https://ir.lib.uwo.ca/etd/3764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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