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You searched for subject:(PowerPC). Showing records 1 – 13 of 13 total matches.

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Jönköping University

1. Gustavsson, Henrik. Utvärdering av simulatorer och emulatorer för inbyggda system.

Degree: Computer and Electrical Engineering, 2011, Jönköping University

Uppdragsgivaren Saab Electronic Defence Systems i Jönköping erbjuder ett flertal produkter främst inom avioniksystem. För att kunna utvärdera och kontrollera produktens design i ett… (more)

Subjects/Keywords: simulators; emulators; PowerPC; embedded systems; avionics; simulatorer; emulatorer; PowerPC; inbyggda system; avionik; Computer Systems; Datorsystem

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gustavsson, H. (2011). Utvärdering av simulatorer och emulatorer för inbyggda system. (Thesis). Jönköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-17983

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gustavsson, Henrik. “Utvärdering av simulatorer och emulatorer för inbyggda system.” 2011. Thesis, Jönköping University. Accessed October 21, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-17983.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gustavsson, Henrik. “Utvärdering av simulatorer och emulatorer för inbyggda system.” 2011. Web. 21 Oct 2019.

Vancouver:

Gustavsson H. Utvärdering av simulatorer och emulatorer för inbyggda system. [Internet] [Thesis]. Jönköping University; 2011. [cited 2019 Oct 21]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-17983.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gustavsson H. Utvärdering av simulatorer och emulatorer för inbyggda system. [Thesis]. Jönköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-17983

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

2. Mišák, Ján. Zpětný překlad aplikací pro architekturu PowerPC .

Degree: 2014, Brno University of Technology

 Tato práce se zabývá přidáním podpory pro architekturu PowerPC do přední části zpětného překladače. Nacházejí se v ní základní informace o reverzním inženýrství, jeho využití… (more)

Subjects/Keywords: Reverzní inženýrství; PowerPC; zpětný překlad; dekompilátor; frontend; Lissom; Reverse engineering; PowerPC; decompilation; decompiler; frontend; Lissom

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mišák, J. (2014). Zpětný překlad aplikací pro architekturu PowerPC . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/56564

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mišák, Ján. “Zpětný překlad aplikací pro architekturu PowerPC .” 2014. Thesis, Brno University of Technology. Accessed October 21, 2019. http://hdl.handle.net/11012/56564.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mišák, Ján. “Zpětný překlad aplikací pro architekturu PowerPC .” 2014. Web. 21 Oct 2019.

Vancouver:

Mišák J. Zpětný překlad aplikací pro architekturu PowerPC . [Internet] [Thesis]. Brno University of Technology; 2014. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/11012/56564.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mišák J. Zpětný překlad aplikací pro architekturu PowerPC . [Thesis]. Brno University of Technology; 2014. Available from: http://hdl.handle.net/11012/56564

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

3. Skoglund, Thomas. Prestandajämförelse mellan mjuk och hård FPGA-processorkärna.

Degree: Electrical Engineering, 2008, Linköping University

  Examensarbetsuppgiften har gått ut på att genomföra en prestandajämförelse mellan en hård och en mjuk processorkärna integrerad i en FPGA, i detta fall,… (more)

Subjects/Keywords: Processorkärnor; FPGA; Xilinx; Prestandajämförelse; MicroBlaze; PowerPC; Electrical engineering; Elektroteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Skoglund, T. (2008). Prestandajämförelse mellan mjuk och hård FPGA-processorkärna. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Skoglund, Thomas. “Prestandajämförelse mellan mjuk och hård FPGA-processorkärna.” 2008. Thesis, Linköping University. Accessed October 21, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Skoglund, Thomas. “Prestandajämförelse mellan mjuk och hård FPGA-processorkärna.” 2008. Web. 21 Oct 2019.

Vancouver:

Skoglund T. Prestandajämförelse mellan mjuk och hård FPGA-processorkärna. [Internet] [Thesis]. Linköping University; 2008. [cited 2019 Oct 21]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Skoglund T. Prestandajämförelse mellan mjuk och hård FPGA-processorkärna. [Thesis]. Linköping University; 2008. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

4. Doughty, Philip, Jr. A Generic attack on CubeHash, a SHA-3 candidate.

Degree: Computer Engineering, 2010, Rochester Institute of Technology

 A secure cryptographic hashing function should be resistant to three different scenarios: First, a cryptographic hashing function must be preimage resistant, that is, it should… (more)

Subjects/Keywords: Cryptographic halgorithm; Cryptography; Distributed computing; FPGA; Parallel computing; PowerPC

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APA (6th Edition):

Doughty, Philip, J. (2010). A Generic attack on CubeHash, a SHA-3 candidate. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3198

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Doughty, Philip, Jr. “A Generic attack on CubeHash, a SHA-3 candidate.” 2010. Thesis, Rochester Institute of Technology. Accessed October 21, 2019. https://scholarworks.rit.edu/theses/3198.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Doughty, Philip, Jr. “A Generic attack on CubeHash, a SHA-3 candidate.” 2010. Web. 21 Oct 2019.

Vancouver:

Doughty, Philip J. A Generic attack on CubeHash, a SHA-3 candidate. [Internet] [Thesis]. Rochester Institute of Technology; 2010. [cited 2019 Oct 21]. Available from: https://scholarworks.rit.edu/theses/3198.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Doughty, Philip J. A Generic attack on CubeHash, a SHA-3 candidate. [Thesis]. Rochester Institute of Technology; 2010. Available from: https://scholarworks.rit.edu/theses/3198

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Björnhager, Jens. CRL2ALF : En översättare från PowerPC till ALF.

Degree: Design and Engineering, 2011, Mälardalen University

Realtidssystem ställer hårda krav på dess ingående mjukvaras temporala beteende. Programmen måste bete sig deterministiskt och ge svar inom satta tidsgränser. Med hårda krav… (more)

Subjects/Keywords: ppc powerpc assembly alf wcet real-time cfg code conversion; Computer Engineering; Datorteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Björnhager, J. (2011). CRL2ALF : En översättare från PowerPC till ALF. (Thesis). Mälardalen University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-13373

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Björnhager, Jens. “CRL2ALF : En översättare från PowerPC till ALF.” 2011. Thesis, Mälardalen University. Accessed October 21, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-13373.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Björnhager, Jens. “CRL2ALF : En översättare från PowerPC till ALF.” 2011. Web. 21 Oct 2019.

Vancouver:

Björnhager J. CRL2ALF : En översättare från PowerPC till ALF. [Internet] [Thesis]. Mälardalen University; 2011. [cited 2019 Oct 21]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-13373.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Björnhager J. CRL2ALF : En översättare från PowerPC till ALF. [Thesis]. Mälardalen University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-13373

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Ku, Po-Yu. The Optimal Design for Face Detection Algorithm on Cell Processor Architecture.

Degree: Master, Electrical Engineering, 2011, NSYSU

 With the advance of facial recognition technology, many related applications such as the clearance of specific facilities, air port security, video camera surveillance, and personnel… (more)

Subjects/Keywords: Multiple Buffering; Modified Census Transform (MCT); SIMD; Synergistic Processor (SPE); Heterogeneous; PowerPC Processor Element (PPE)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ku, P. (2011). The Optimal Design for Face Detection Algorithm on Cell Processor Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ku, Po-Yu. “The Optimal Design for Face Detection Algorithm on Cell Processor Architecture.” 2011. Thesis, NSYSU. Accessed October 21, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ku, Po-Yu. “The Optimal Design for Face Detection Algorithm on Cell Processor Architecture.” 2011. Web. 21 Oct 2019.

Vancouver:

Ku P. The Optimal Design for Face Detection Algorithm on Cell Processor Architecture. [Internet] [Thesis]. NSYSU; 2011. [cited 2019 Oct 21]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ku P. The Optimal Design for Face Detection Algorithm on Cell Processor Architecture. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Σακελλαρίου, Παναγιώτης. Ανάπτυξη ενσωματωμένου συστήματος για χαρακτηρισμό τηλεπικοινωνιακών διατάξεων.

Degree: 2011, University of Patras

Στην παρούσα διπλωματική αναπτύσσεται ένα ενσωματωμένο σύστημα αποτελούμενο από υλικό και λογισμικό, για τον χαρακτηρισμό τηλεπικοινωνιακών διατάξεων. Ειδικότερα μελετάται ο έλεγχος εξειδικευμένης ενσωματωμένης τηλεπικοινωνιακής διάταξης,… (more)

Subjects/Keywords: Ενσωματωμένα συστήματα; Τηλεπικοινωνίες; Ενσωματωμένοι δικτυακοί εξυπηρετητές; 004.21; Embedded systems; Telecommunications; Embedded web servers; PowerPC; MicroBlaze; LwIP; Ethernet; ESPV-F

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Σακελλαρίου, . (2011). Ανάπτυξη ενσωματωμένου συστήματος για χαρακτηρισμό τηλεπικοινωνιακών διατάξεων. (Masters Thesis). University of Patras. Retrieved from http://hdl.handle.net/10889/5145

Chicago Manual of Style (16th Edition):

Σακελλαρίου, Παναγιώτης. “Ανάπτυξη ενσωματωμένου συστήματος για χαρακτηρισμό τηλεπικοινωνιακών διατάξεων.” 2011. Masters Thesis, University of Patras. Accessed October 21, 2019. http://hdl.handle.net/10889/5145.

MLA Handbook (7th Edition):

Σακελλαρίου, Παναγιώτης. “Ανάπτυξη ενσωματωμένου συστήματος για χαρακτηρισμό τηλεπικοινωνιακών διατάξεων.” 2011. Web. 21 Oct 2019.

Vancouver:

Σακελλαρίου . Ανάπτυξη ενσωματωμένου συστήματος για χαρακτηρισμό τηλεπικοινωνιακών διατάξεων. [Internet] [Masters thesis]. University of Patras; 2011. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/10889/5145.

Council of Science Editors:

Σακελλαρίου . Ανάπτυξη ενσωματωμένου συστήματος για χαρακτηρισμό τηλεπικοινωνιακών διατάξεων. [Masters Thesis]. University of Patras; 2011. Available from: http://hdl.handle.net/10889/5145


ITESO – Universidad Jesuita de Guadalajara

8. Vallejo-Ríos, José A. Mecanismo de cambio de contexto de tareas en una arquitectura PowerPC .

Degree: 2018, ITESO – Universidad Jesuita de Guadalajara

Subjects/Keywords: Body Controller Module; PowerPC; Automotive; Scheduler Preemptive

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vallejo-Ríos, J. A. (2018). Mecanismo de cambio de contexto de tareas en una arquitectura PowerPC . (Thesis). ITESO – Universidad Jesuita de Guadalajara. Retrieved from http://hdl.handle.net/11117/5551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vallejo-Ríos, José A. “Mecanismo de cambio de contexto de tareas en una arquitectura PowerPC .” 2018. Thesis, ITESO – Universidad Jesuita de Guadalajara. Accessed October 21, 2019. http://hdl.handle.net/11117/5551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vallejo-Ríos, José A. “Mecanismo de cambio de contexto de tareas en una arquitectura PowerPC .” 2018. Web. 21 Oct 2019.

Vancouver:

Vallejo-Ríos JA. Mecanismo de cambio de contexto de tareas en una arquitectura PowerPC . [Internet] [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2018. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/11117/5551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vallejo-Ríos JA. Mecanismo de cambio de contexto de tareas en una arquitectura PowerPC . [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2018. Available from: http://hdl.handle.net/11117/5551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Bordeaux I

9. Kthiri, Moez. Étude et implantation d'algorithmes de compression vidéo optimisés H.264/AVC dans un environnement conjoint matériel et logiciel : Study and Implementation of Algorithms for H.264/AVC Compression in a Hardware and Software Environment.

Degree: Docteur es, Electronique, 2012, Université de Bordeaux I

La contribution de cette thèse concerne le développement et la conception d’un système multimédia embarqué basé sur l’approche de conception conjointe matérielle/logicielle (codesign). Il en… (more)

Subjects/Keywords: Processeur PowerPC; HW/SW Codesign; Xenomai; Système Embarqué Multimédia; Compression d’Images; H.264/AVC; FPGA; ASIC; Embedded System for Multimedia; Image Compression; H.264/AVC; FPGA; ASIC; PowerPC Processor; Xenomai; HW/SW Codesign

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kthiri, M. (2012). Étude et implantation d'algorithmes de compression vidéo optimisés H.264/AVC dans un environnement conjoint matériel et logiciel : Study and Implementation of Algorithms for H.264/AVC Compression in a Hardware and Software Environment. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2012BOR14505

Chicago Manual of Style (16th Edition):

Kthiri, Moez. “Étude et implantation d'algorithmes de compression vidéo optimisés H.264/AVC dans un environnement conjoint matériel et logiciel : Study and Implementation of Algorithms for H.264/AVC Compression in a Hardware and Software Environment.” 2012. Doctoral Dissertation, Université de Bordeaux I. Accessed October 21, 2019. http://www.theses.fr/2012BOR14505.

MLA Handbook (7th Edition):

Kthiri, Moez. “Étude et implantation d'algorithmes de compression vidéo optimisés H.264/AVC dans un environnement conjoint matériel et logiciel : Study and Implementation of Algorithms for H.264/AVC Compression in a Hardware and Software Environment.” 2012. Web. 21 Oct 2019.

Vancouver:

Kthiri M. Étude et implantation d'algorithmes de compression vidéo optimisés H.264/AVC dans un environnement conjoint matériel et logiciel : Study and Implementation of Algorithms for H.264/AVC Compression in a Hardware and Software Environment. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2012. [cited 2019 Oct 21]. Available from: http://www.theses.fr/2012BOR14505.

Council of Science Editors:

Kthiri M. Étude et implantation d'algorithmes de compression vidéo optimisés H.264/AVC dans un environnement conjoint matériel et logiciel : Study and Implementation of Algorithms for H.264/AVC Compression in a Hardware and Software Environment. [Doctoral Dissertation]. Université de Bordeaux I; 2012. Available from: http://www.theses.fr/2012BOR14505


Universidade Estadual de Campinas

10. Souza, Maxwell Monteiro Andrade de. ISAMAP tradução binaria dinamica orientada a mapeamento de instruções .

Degree: 2008, Universidade Estadual de Campinas

 Resumo: Tradução binária dinâmica consiste em permitir que programas originalmente compilados para uma determinada arquitetura, executem sobre um nova arquitetura sem a necessidade de recompilação.… (more)

Subjects/Keywords: Tradução binária dinâmica; Processador PowerPC; Processador X86; Mapeamento de instruções

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Souza, M. M. A. d. (2008). ISAMAP tradução binaria dinamica orientada a mapeamento de instruções . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/276087

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Souza, Maxwell Monteiro Andrade de. “ISAMAP tradução binaria dinamica orientada a mapeamento de instruções .” 2008. Thesis, Universidade Estadual de Campinas. Accessed October 21, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/276087.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Souza, Maxwell Monteiro Andrade de. “ISAMAP tradução binaria dinamica orientada a mapeamento de instruções .” 2008. Web. 21 Oct 2019.

Vancouver:

Souza MMAd. ISAMAP tradução binaria dinamica orientada a mapeamento de instruções . [Internet] [Thesis]. Universidade Estadual de Campinas; 2008. [cited 2019 Oct 21]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/276087.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Souza MMAd. ISAMAP tradução binaria dinamica orientada a mapeamento de instruções . [Thesis]. Universidade Estadual de Campinas; 2008. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/276087

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

11. Bekker, Dmitriy. Hardware and software optimization of fourier transform infrared spectrometry on hybrid-FPGAs.

Degree: Computer Engineering, 2007, Rochester Institute of Technology

 With the increasing complexity of today’s spacecrafts, there exists a concern that the on-board flight computer may be overburdened with various processing tasks. Currently available… (more)

Subjects/Keywords: APU; Embedded processor; FTIR spectrometry; FPU; Hybrid-FPGA; PowerPC 405; Virtex-4 FX

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bekker, D. (2007). Hardware and software optimization of fourier transform infrared spectrometry on hybrid-FPGAs. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bekker, Dmitriy. “Hardware and software optimization of fourier transform infrared spectrometry on hybrid-FPGAs.” 2007. Thesis, Rochester Institute of Technology. Accessed October 21, 2019. https://scholarworks.rit.edu/theses/3193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bekker, Dmitriy. “Hardware and software optimization of fourier transform infrared spectrometry on hybrid-FPGAs.” 2007. Web. 21 Oct 2019.

Vancouver:

Bekker D. Hardware and software optimization of fourier transform infrared spectrometry on hybrid-FPGAs. [Internet] [Thesis]. Rochester Institute of Technology; 2007. [cited 2019 Oct 21]. Available from: https://scholarworks.rit.edu/theses/3193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bekker D. Hardware and software optimization of fourier transform infrared spectrometry on hybrid-FPGAs. [Thesis]. Rochester Institute of Technology; 2007. Available from: https://scholarworks.rit.edu/theses/3193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Bilen, Celal Can. Performance Evaluation of Embedded Microcomputers for Avionics Applications.

Degree: Computer and Electrical Engineering, 2010, Jönköping University

  Embedded microcomputers are used in a wide range of applications nowadays. Avionics is one of these areas and requires extra attention regarding reliability and… (more)

Subjects/Keywords: Microprocessor; Avionics; PowerPC; Performance Evaluation; Determinism; Embedded Systems; Computer Architecture; Computer Engineering; Datorteknik

…47 2.9. POWERPC… …52 2.9.4. PowerPC Timeline… …DISABLE & DQM MASKING FIGURE 2-12: MEMORY TECHNOLOGIES TIMELINE FIGURE 2-13: POWERPC… …ARCHITECTURE FIGURE 2-14: POWERPC TIMELINE FIGURE 4-1: HARDWARE CONFIGURATION OF THE PROJECT FIGURE 4… …at roughly 30 percent as well as PowerPC and M IPS with fairly smaller shares [1]… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bilen, C. C. (2010). Performance Evaluation of Embedded Microcomputers for Avionics Applications. (Thesis). Jönköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11955

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bilen, Celal Can. “Performance Evaluation of Embedded Microcomputers for Avionics Applications.” 2010. Thesis, Jönköping University. Accessed October 21, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11955.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bilen, Celal Can. “Performance Evaluation of Embedded Microcomputers for Avionics Applications.” 2010. Web. 21 Oct 2019.

Vancouver:

Bilen CC. Performance Evaluation of Embedded Microcomputers for Avionics Applications. [Internet] [Thesis]. Jönköping University; 2010. [cited 2019 Oct 21]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11955.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bilen CC. Performance Evaluation of Embedded Microcomputers for Avionics Applications. [Thesis]. Jönköping University; 2010. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11955

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Dudebout, Nicolas. Multigigabit multimedia processor for 60GHz WPAN: a hardware software codesign implementation.

Degree: MS, Electrical and Computer Engineering, 2008, Georgia Tech

 The emergence of a multitude of bandwidth hungry multimedia applications has ex- acerbated the need for multi-gigabit wireless solutions and made it out of the… (more)

Subjects/Keywords: PowerPC; Virtex2Pro; FPGA; Multimedia systems; Computer architecture; Parallel processing (Electronic computers); High performance computing

…these boards contains a system centered around an embedded PowerPC processor. This processor… …kernel running on a PowerPC on top of which I had installed a BusyBox utility. The kernel is… …FPGA PowerPC Hardware configuration file Bitstream Software stack JavaScript GUI Web… …Figure 9: Localization of the software stack 12 PowerPC My first steps as a system designer… …3.2 3.2.1 System on Chip Using an embedded PowerPC... Let’s now describe with a little… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dudebout, N. (2008). Multigigabit multimedia processor for 60GHz WPAN: a hardware software codesign implementation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26677

Chicago Manual of Style (16th Edition):

Dudebout, Nicolas. “Multigigabit multimedia processor for 60GHz WPAN: a hardware software codesign implementation.” 2008. Masters Thesis, Georgia Tech. Accessed October 21, 2019. http://hdl.handle.net/1853/26677.

MLA Handbook (7th Edition):

Dudebout, Nicolas. “Multigigabit multimedia processor for 60GHz WPAN: a hardware software codesign implementation.” 2008. Web. 21 Oct 2019.

Vancouver:

Dudebout N. Multigigabit multimedia processor for 60GHz WPAN: a hardware software codesign implementation. [Internet] [Masters thesis]. Georgia Tech; 2008. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/1853/26677.

Council of Science Editors:

Dudebout N. Multigigabit multimedia processor for 60GHz WPAN: a hardware software codesign implementation. [Masters Thesis]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26677

.