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You searched for subject:(Post silicon optimization). Showing records 1 – 4 of 4 total matches.

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University of Minnesota

1. Liu, Qunzeng. Statistical analysis techniques for logic and memory circuits.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

 Process variations have become increasingly important as feature sizes enter the sub- 100nm regime and continue to shrink. Both logic and memory circuits have seen… (more)

Subjects/Keywords: Embedded DRAM; Post-silicon optimization; SSTA; Statistical analysis; Electrical Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, Q. (2010). Statistical analysis techniques for logic and memory circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/95019

Chicago Manual of Style (16th Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Doctoral Dissertation, University of Minnesota. Accessed April 04, 2020. http://purl.umn.edu/95019.

MLA Handbook (7th Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Web. 04 Apr 2020.

Vancouver:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2020 Apr 04]. Available from: http://purl.umn.edu/95019.

Council of Science Editors:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://purl.umn.edu/95019


ITESO – Universidad Jesuita de Guadalajara

2. Rangel-Patiño, Francisco E. Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation .

Degree: 2018, ITESO – Universidad Jesuita de Guadalajara

Subjects/Keywords: Eye Diagram; Artificial Neural Network; Broyden; Post-Silicon Validation; Receptor HSIO; Kriging; Space Mapping; Surrogate Models; Support Vector Machines; System Margining; Optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rangel-Patiño, F. E. (2018). Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation . (Thesis). ITESO – Universidad Jesuita de Guadalajara. Retrieved from http://hdl.handle.net/11117/5527

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rangel-Patiño, Francisco E. “Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation .” 2018. Thesis, ITESO – Universidad Jesuita de Guadalajara. Accessed April 04, 2020. http://hdl.handle.net/11117/5527.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rangel-Patiño, Francisco E. “Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation .” 2018. Web. 04 Apr 2020.

Vancouver:

Rangel-Patiño FE. Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation . [Internet] [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2018. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/11117/5527.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rangel-Patiño FE. Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation . [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2018. Available from: http://hdl.handle.net/11117/5527

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Campbell, Keith A. Low-cost error detection through high-level synthesis.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a… (more)

Subjects/Keywords: High-level synthesis; Automation; error detection; scheduling; binding; compiler transformation; compiler optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath, control logic; shadow logic; low cost; high performance; electrical bugs; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback; recovery; post-silicon validation; Accelerators; system on a chip; signature generation; execution signatures; execution hashing; logic bugs; nondeterministic bugs; masked errors; circuit reliability; hot spots; wear out; silent data corruption; observability; detection latency; mixed datapath; diversity; checkpoint corruption; error injection; error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); hybrid hardware/software; execution tracing; address conversion; undefined behavior; High-Level Synthesis (HLS) engine bugs; detection coverage

…Transistor MSB Most Significant Bit MUX MUltipleXer PSV Post-Silicon Validation QED Quick… …Design Fabrication Post-Silicon Testing Soft Errors Permanent Faults Hardware Deployment… …Hardware that passes post-silicon testing is sent to end-users who deploy it in their systems… …can make it into the physical design. Some of those bugs evade detection in post-silicon… …14, 15, 16, 17], which is a software technique for the post-silicon validation of… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2015). Low-cost error detection through high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 04, 2020. http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Web. 04 Apr 2020.

Vancouver:

Campbell KA. Low-cost error detection through high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Campbell KA. Low-cost error detection through high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…52 54 60 60 61 62 CHAPTER 6 POST-SILICON VALIDATION: 6.1 Hybrid Hashing Framework… …P&R Place and Route PSV Post-Silicon Validation QA Quarter Adder QED Quick Error… …signature stream that captures the internal behavior of the design during post-silicon validation… …Hardware that passes post-silicon testing is sent to end-users who deploy it in their systems… …can make it into the physical design. Some of those bugs evade detection in post-silicon… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 04, 2020. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 04 Apr 2020.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

.