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You searched for subject:(Pipelining). Showing records 1 – 30 of 87 total matches.

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Washington State University

1. [No author]. High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures .

Degree: 2005, Washington State University

Subjects/Keywords: Pipelining (Electronics)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2005). High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/349

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures .” 2005. Thesis, Washington State University. Accessed February 28, 2021. http://hdl.handle.net/2376/349.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures .” 2005. Web. 28 Feb 2021.

Vancouver:

author] [. High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures . [Internet] [Thesis]. Washington State University; 2005. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2376/349.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures . [Thesis]. Washington State University; 2005. Available from: http://hdl.handle.net/2376/349

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Ugurdag, Hasan Fatih. Various perspectives of loop pipelining.

Degree: PhD, Electrical Engineering, 1995, Case Western Reserve University School of Graduate Studies

 Loops can be a bottle-neck in many computer applications. Examples of such applications include industrial inspection tasks, embedded system software, and DSP algorithms. Loop pipelining(more)

Subjects/Keywords: Loop pipelining

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APA (6th Edition):

Ugurdag, H. F. (1995). Various perspectives of loop pipelining. (Doctoral Dissertation). Case Western Reserve University School of Graduate Studies. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1061833352

Chicago Manual of Style (16th Edition):

Ugurdag, Hasan Fatih. “Various perspectives of loop pipelining.” 1995. Doctoral Dissertation, Case Western Reserve University School of Graduate Studies. Accessed February 28, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=case1061833352.

MLA Handbook (7th Edition):

Ugurdag, Hasan Fatih. “Various perspectives of loop pipelining.” 1995. Web. 28 Feb 2021.

Vancouver:

Ugurdag HF. Various perspectives of loop pipelining. [Internet] [Doctoral dissertation]. Case Western Reserve University School of Graduate Studies; 1995. [cited 2021 Feb 28]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1061833352.

Council of Science Editors:

Ugurdag HF. Various perspectives of loop pipelining. [Doctoral Dissertation]. Case Western Reserve University School of Graduate Studies; 1995. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1061833352


Universidade do Rio Grande do Norte

3. Medeiros, Aparecida Lopes de. Implementação da técnica de software pipelining na rede em chip IPNoSyS .

Degree: 2014, Universidade do Rio Grande do Norte

 Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors,… (more)

Subjects/Keywords: Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho; Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho

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APA (6th Edition):

Medeiros, A. L. d. (2014). Implementação da técnica de software pipelining na rede em chip IPNoSyS . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Thesis, Universidade do Rio Grande do Norte. Accessed February 28, 2021. http://repositorio.ufrn.br/handle/123456789/18100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Web. 28 Feb 2021.

Vancouver:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2014. [cited 2021 Feb 28]. Available from: http://repositorio.ufrn.br/handle/123456789/18100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Thesis]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/18100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

4. Medeiros, Aparecida Lopes de. Implementação da técnica de software pipelining na rede em chip IPNoSyS .

Degree: 2014, Universidade do Rio Grande do Norte

 Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors,… (more)

Subjects/Keywords: Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho; Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Medeiros, A. L. d. (2014). Implementação da técnica de software pipelining na rede em chip IPNoSyS . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18100

Chicago Manual of Style (16th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Masters Thesis, Universidade do Rio Grande do Norte. Accessed February 28, 2021. http://repositorio.ufrn.br/handle/123456789/18100.

MLA Handbook (7th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Web. 28 Feb 2021.

Vancouver:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2014. [cited 2021 Feb 28]. Available from: http://repositorio.ufrn.br/handle/123456789/18100.

Council of Science Editors:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Masters Thesis]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/18100


Brno University of Technology

5. Zlatohlávková, Lucie. Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU.

Degree: 2020, Brno University of Technology

 This masters thesis is focused on the issue of processor architecture. The ground of this project is a design of a simple processor, which is… (more)

Subjects/Keywords: Architektura; Počítač; Procesor; Instrukce; Pipelining; Predikce skoků; Paměť cache.; Architecture; Computer; Processor; Instruction; Pipelining; Branch prediction; Cache memory.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zlatohlávková, L. (2020). Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/187521

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zlatohlávková, Lucie. “Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU.” 2020. Thesis, Brno University of Technology. Accessed February 28, 2021. http://hdl.handle.net/11012/187521.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zlatohlávková, Lucie. “Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU.” 2020. Web. 28 Feb 2021.

Vancouver:

Zlatohlávková L. Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11012/187521.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zlatohlávková L. Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/187521

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

6. Sulistyo, Jos Budi. High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining.

Degree: PhD, Electrical and Computer Engineering, 2005, Virginia Tech

 The increasing capabilities of multimedia appliances demand arithmetic circuits with higher speed and reasonable power dissipation. A common technique to attain those goals is synchronous… (more)

Subjects/Keywords: high-speed CMOS VLSI; pipelining; wave pipelining; arithmetic circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sulistyo, J. B. (2005). High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29091

Chicago Manual of Style (16th Edition):

Sulistyo, Jos Budi. “High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining.” 2005. Doctoral Dissertation, Virginia Tech. Accessed February 28, 2021. http://hdl.handle.net/10919/29091.

MLA Handbook (7th Edition):

Sulistyo, Jos Budi. “High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining.” 2005. Web. 28 Feb 2021.

Vancouver:

Sulistyo JB. High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining. [Internet] [Doctoral dissertation]. Virginia Tech; 2005. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10919/29091.

Council of Science Editors:

Sulistyo JB. High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining. [Doctoral Dissertation]. Virginia Tech; 2005. Available from: http://hdl.handle.net/10919/29091


Anna University

7. Kalavathi Devi T. Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;.

Degree: communication engineering, 2013, Anna University

Rapid developments in the field of wireless communication have newlinecreated a rising demand for Viterbi decoder with long battery life low power newlinedissipation and low… (more)

Subjects/Keywords: Low Power; Power Reduction; Viterbi Decoder; VlSI Architectures; wave pipelining

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APA (6th Edition):

T, K. D. (2013). Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/23861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

T, Kalavathi Devi. “Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;.” 2013. Thesis, Anna University. Accessed February 28, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/23861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

T, Kalavathi Devi. “Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;.” 2013. Web. 28 Feb 2021.

Vancouver:

T KD. Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;. [Internet] [Thesis]. Anna University; 2013. [cited 2021 Feb 28]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

T KD. Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;. [Thesis]. Anna University; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Ho, Calvin. Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers.

Degree: MS, Electrical and Computer Engineering, 2014, California State University – Northridge

 This report describes some the fundamentals of Bitcoin mining. It highlights some of the key aspects that are needed to create and operate a miner.… (more)

Subjects/Keywords: pipelining; Dissertations, Academic  – CSUN  – Engineering  – Electrical and Computer Engineering.

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APA (6th Edition):

Ho, C. (2014). Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.2/4996

Chicago Manual of Style (16th Edition):

Ho, Calvin. “Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers.” 2014. Masters Thesis, California State University – Northridge. Accessed February 28, 2021. http://hdl.handle.net/10211.2/4996.

MLA Handbook (7th Edition):

Ho, Calvin. “Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers.” 2014. Web. 28 Feb 2021.

Vancouver:

Ho C. Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers. [Internet] [Masters thesis]. California State University – Northridge; 2014. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10211.2/4996.

Council of Science Editors:

Ho C. Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers. [Masters Thesis]. California State University – Northridge; 2014. Available from: http://hdl.handle.net/10211.2/4996


Washington State University

9. [No author]. A high performance low power mesochronous pipeline architecture for computer systems .

Degree: 2006, Washington State University

Subjects/Keywords: Pipelining (Electronics); Computers, Pipeline.

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APA (6th Edition):

author], [. (2006). A high performance low power mesochronous pipeline architecture for computer systems . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/475

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “A high performance low power mesochronous pipeline architecture for computer systems .” 2006. Thesis, Washington State University. Accessed February 28, 2021. http://hdl.handle.net/2376/475.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “A high performance low power mesochronous pipeline architecture for computer systems .” 2006. Web. 28 Feb 2021.

Vancouver:

author] [. A high performance low power mesochronous pipeline architecture for computer systems . [Internet] [Thesis]. Washington State University; 2006. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2376/475.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. A high performance low power mesochronous pipeline architecture for computer systems . [Thesis]. Washington State University; 2006. Available from: http://hdl.handle.net/2376/475

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Santa Cruz

10. Trapani Possignolo, Rafael. Improving the Productivity of Hardware Design.

Degree: Computer Engineering, 2018, University of California – Santa Cruz

 Current hardware development techniques contrast with agile methods that became popular in modern software development. This has been mitigated with technology scaling, when performance gains… (more)

Subjects/Keywords: Computer engineering; Computer science; Digital Design; Electronic Design Automation; Pipelining; Productivity

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APA (6th Edition):

Trapani Possignolo, R. (2018). Improving the Productivity of Hardware Design. (Thesis). University of California – Santa Cruz. Retrieved from http://www.escholarship.org/uc/item/6bd5n1c7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Trapani Possignolo, Rafael. “Improving the Productivity of Hardware Design.” 2018. Thesis, University of California – Santa Cruz. Accessed February 28, 2021. http://www.escholarship.org/uc/item/6bd5n1c7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Trapani Possignolo, Rafael. “Improving the Productivity of Hardware Design.” 2018. Web. 28 Feb 2021.

Vancouver:

Trapani Possignolo R. Improving the Productivity of Hardware Design. [Internet] [Thesis]. University of California – Santa Cruz; 2018. [cited 2021 Feb 28]. Available from: http://www.escholarship.org/uc/item/6bd5n1c7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Trapani Possignolo R. Improving the Productivity of Hardware Design. [Thesis]. University of California – Santa Cruz; 2018. Available from: http://www.escholarship.org/uc/item/6bd5n1c7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


IUPUI

11. Mao, Linyong. Application of Data Pipelining Technology in Cheminformatics and Bioinformatics.

Degree: 2002, IUPUI

Submitted to the faculty of the University Graduate School in partial fulfillment of the requirements for the degree Master of Sciences in the School of… (more)

Subjects/Keywords: data pipelining technology; cheminformatics; bioinformatics

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APA (6th Edition):

Mao, L. (2002). Application of Data Pipelining Technology in Cheminformatics and Bioinformatics. (Thesis). IUPUI. Retrieved from http://hdl.handle.net/1805/322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mao, Linyong. “Application of Data Pipelining Technology in Cheminformatics and Bioinformatics.” 2002. Thesis, IUPUI. Accessed February 28, 2021. http://hdl.handle.net/1805/322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mao, Linyong. “Application of Data Pipelining Technology in Cheminformatics and Bioinformatics.” 2002. Web. 28 Feb 2021.

Vancouver:

Mao L. Application of Data Pipelining Technology in Cheminformatics and Bioinformatics. [Internet] [Thesis]. IUPUI; 2002. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1805/322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mao L. Application of Data Pipelining Technology in Cheminformatics and Bioinformatics. [Thesis]. IUPUI; 2002. Available from: http://hdl.handle.net/1805/322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

12. Klass, E.F. Wave pipelining: Theoretical and practical issues in CMOS.

Degree: 1994, Delft University of Technology

Subjects/Keywords: Computer architecture; wave pipelining

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Klass, E. F. (1994). Wave pipelining: Theoretical and practical issues in CMOS. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765

Chicago Manual of Style (16th Edition):

Klass, E F. “Wave pipelining: Theoretical and practical issues in CMOS.” 1994. Doctoral Dissertation, Delft University of Technology. Accessed February 28, 2021. http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765.

MLA Handbook (7th Edition):

Klass, E F. “Wave pipelining: Theoretical and practical issues in CMOS.” 1994. Web. 28 Feb 2021.

Vancouver:

Klass EF. Wave pipelining: Theoretical and practical issues in CMOS. [Internet] [Doctoral dissertation]. Delft University of Technology; 1994. [cited 2021 Feb 28]. Available from: http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765.

Council of Science Editors:

Klass EF. Wave pipelining: Theoretical and practical issues in CMOS. [Doctoral Dissertation]. Delft University of Technology; 1994. Available from: http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765


Brno University of Technology

13. Hájek, Radek. Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language.

Degree: 2019, Brno University of Technology

 The diploma thesis contains theoretical basis, classification and function of processors. It summarizes the principle of pipelined instruction processing and the types of hazards in… (more)

Subjects/Keywords: Procesor; CodAL; MicroBlaze; zřetězené zpracování; hazardy; Processor; CodAL; MicroBlaze; pipelining; hazards

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hájek, R. (2019). Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/59746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hájek, Radek. “Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language.” 2019. Thesis, Brno University of Technology. Accessed February 28, 2021. http://hdl.handle.net/11012/59746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hájek, Radek. “Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language.” 2019. Web. 28 Feb 2021.

Vancouver:

Hájek R. Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11012/59746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hájek R. Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/59746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia State University

14. Wu, Xiaolong. Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform.

Degree: MS, Computer Science, 2015, Georgia State University

  Sparse Matrix-Matrix multiplication (SpMM) is a fundamental operation over irregular data, which is widely used in graph algorithms, such as finding minimum spanning trees… (more)

Subjects/Keywords: Sparse matrix-matrix multiplication; Data locality; Pipelining; GPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, X. (2015). Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform. (Thesis). Georgia State University. Retrieved from https://scholarworks.gsu.edu/cs_theses/84

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Xiaolong. “Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform.” 2015. Thesis, Georgia State University. Accessed February 28, 2021. https://scholarworks.gsu.edu/cs_theses/84.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Xiaolong. “Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform.” 2015. Web. 28 Feb 2021.

Vancouver:

Wu X. Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform. [Internet] [Thesis]. Georgia State University; 2015. [cited 2021 Feb 28]. Available from: https://scholarworks.gsu.edu/cs_theses/84.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu X. Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform. [Thesis]. Georgia State University; 2015. Available from: https://scholarworks.gsu.edu/cs_theses/84

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Karlstad University

15. Vilhelmsson, Lina. Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi.

Degree: Karlstad University, 2020, Karlstad University

  In the last few years, the popularity of Industrial IoT has grown a lot, and it is expected to have an impact of over… (more)

Subjects/Keywords: Data pipelining; Apache NiFi; IIoT; Industrial IoT; Computer Sciences; Datavetenskap (datalogi)

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APA (6th Edition):

Vilhelmsson, L. (2020). Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi. (Thesis). Karlstad University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-78032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vilhelmsson, Lina. “Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi.” 2020. Thesis, Karlstad University. Accessed February 28, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-78032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vilhelmsson, Lina. “Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi.” 2020. Web. 28 Feb 2021.

Vancouver:

Vilhelmsson L. Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi. [Internet] [Thesis]. Karlstad University; 2020. [cited 2021 Feb 28]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-78032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vilhelmsson L. Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi. [Thesis]. Karlstad University; 2020. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-78032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

16. Aleen, Farhana Afroz. Dynamic execution prediction and pipeline balancing of streaming applications.

Degree: MS, Computing, 2010, Georgia Tech

 The number and scope of data driven streaming applications is growing. Such streaming applications are promising targets for effectively utilizing multi-cores because of their inherent… (more)

Subjects/Keywords: Dynamic scheduling; Software pipelining; Streaming technology (Telecommunications); Multimedia systems; Computers, Pipeline; Pipelining (Electronics)

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APA (6th Edition):

Aleen, F. A. (2010). Dynamic execution prediction and pipeline balancing of streaming applications. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37192

Chicago Manual of Style (16th Edition):

Aleen, Farhana Afroz. “Dynamic execution prediction and pipeline balancing of streaming applications.” 2010. Masters Thesis, Georgia Tech. Accessed February 28, 2021. http://hdl.handle.net/1853/37192.

MLA Handbook (7th Edition):

Aleen, Farhana Afroz. “Dynamic execution prediction and pipeline balancing of streaming applications.” 2010. Web. 28 Feb 2021.

Vancouver:

Aleen FA. Dynamic execution prediction and pipeline balancing of streaming applications. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1853/37192.

Council of Science Editors:

Aleen FA. Dynamic execution prediction and pipeline balancing of streaming applications. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37192


University of Utah

17. Gebhardt, Daniel J. Energy-efficient design of an asynchronous network-on-chip.

Degree: PhD, Computer Science, 2011, University of Utah

 Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are… (more)

Subjects/Keywords: Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gebhardt, D. J. (2011). Energy-efficient design of an asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Chicago Manual of Style (16th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed February 28, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

MLA Handbook (7th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Web. 28 Feb 2021.

Vancouver:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2021 Feb 28]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

Council of Science Editors:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871


Anna University

18. Kumar, V. Design of an efficient medium access protocol for wireless networks using pipelining methods.

Degree: 2013, Anna University

 In this work, new techniques for cross layer design of wireless network has been proposed for improving the Quality of Service in wireless networks by… (more)

Subjects/Keywords: Medium Access Protocol; Wireless Networks; Pipelining methods; MAC layer; CSMA/CD algorithm; passive nodes

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APA (6th Edition):

Kumar, V. (2013). Design of an efficient medium access protocol for wireless networks using pipelining methods. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/13417

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kumar, V. “Design of an efficient medium access protocol for wireless networks using pipelining methods.” 2013. Thesis, Anna University. Accessed February 28, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/13417.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kumar, V. “Design of an efficient medium access protocol for wireless networks using pipelining methods.” 2013. Web. 28 Feb 2021.

Vancouver:

Kumar V. Design of an efficient medium access protocol for wireless networks using pipelining methods. [Internet] [Thesis]. Anna University; 2013. [cited 2021 Feb 28]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13417.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumar V. Design of an efficient medium access protocol for wireless networks using pipelining methods. [Thesis]. Anna University; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13417

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

19. Ming, Jiang. Pipelined Symbolic Taint Analysis.

Degree: 2016, Penn State University

 The multifaceted benefits of taint analysis have led to its wide adoption in security applications, such as software attack detection, attack provenance investigation, and data… (more)

Subjects/Keywords: taint analysis; pipelining taint analysis; offline symbolic taint analysis; multi-core architectures

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APA (6th Edition):

Ming, J. (2016). Pipelined Symbolic Taint Analysis. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/v979v304g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ming, Jiang. “Pipelined Symbolic Taint Analysis.” 2016. Thesis, Penn State University. Accessed February 28, 2021. https://submit-etda.libraries.psu.edu/catalog/v979v304g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ming, Jiang. “Pipelined Symbolic Taint Analysis.” 2016. Web. 28 Feb 2021.

Vancouver:

Ming J. Pipelined Symbolic Taint Analysis. [Internet] [Thesis]. Penn State University; 2016. [cited 2021 Feb 28]. Available from: https://submit-etda.libraries.psu.edu/catalog/v979v304g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ming J. Pipelined Symbolic Taint Analysis. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/v979v304g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. Chen, Yi-Chang. The Study of Double Level Branch Buffer.

Degree: Master, Electrical Engineering, 2001, NSYSU

Pipelining is the major organizational technique by which computers can execute several instructions simultaneously to reach higher single-processor performance. Branches are recognized as a major… (more)

Subjects/Keywords: Pipelining; Branch Penalty; Branch Prediction; Branch Target Buffer

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APA (6th Edition):

Chen, Y. (2001). The Study of Double Level Branch Buffer. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012101-091101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yi-Chang. “The Study of Double Level Branch Buffer.” 2001. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012101-091101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yi-Chang. “The Study of Double Level Branch Buffer.” 2001. Web. 28 Feb 2021.

Vancouver:

Chen Y. The Study of Double Level Branch Buffer. [Internet] [Thesis]. NSYSU; 2001. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012101-091101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. The Study of Double Level Branch Buffer. [Thesis]. NSYSU; 2001. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012101-091101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. 池田, 吉朗. ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

Supervisor:日比野 靖

情報科学研究科

修士

Subjects/Keywords: マルチスレッド型プロセッサ、ウェーブパイプライン; multi-threaded processor, wave pipelining

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

池田, . (n.d.). ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/1288

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

池田, 吉朗. “ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed February 28, 2021. http://hdl.handle.net/10119/1288.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

池田, 吉朗. “ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究.” Web. 28 Feb 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

池田 . ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10119/1288.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

池田 . ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/1288

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

22. Tsakiris, Nicholas. Enabling Gigabit IP for Embedded Systems.

Degree: 2009, Flinders University

 For any practical implementation of chip design, there needs to be a hardware platform available for the purpose of prototyping and implementation of FPGA-based programs,… (more)

Subjects/Keywords: embedded; vhdl; fpga; jpeg; jpeg2000; pipelining; xilinx

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APA (6th Edition):

Tsakiris, N. (2009). Enabling Gigabit IP for Embedded Systems. (Thesis). Flinders University. Retrieved from http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsakiris, Nicholas. “Enabling Gigabit IP for Embedded Systems.” 2009. Thesis, Flinders University. Accessed February 28, 2021. http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsakiris, Nicholas. “Enabling Gigabit IP for Embedded Systems.” 2009. Web. 28 Feb 2021.

Vancouver:

Tsakiris N. Enabling Gigabit IP for Embedded Systems. [Internet] [Thesis]. Flinders University; 2009. [cited 2021 Feb 28]. Available from: http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsakiris N. Enabling Gigabit IP for Embedded Systems. [Thesis]. Flinders University; 2009. Available from: http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

23. Bao, Bin (1982 - ). Peer-aware program optimization.

Degree: PhD, 2013, University of Rochester

 Most existing program optimization techniques are based on the code or the behavior of the target program, which means they can be characterized as self-aware.… (more)

Subjects/Keywords: Defensive loop tiling; Dynamic computation and communication pipelining; Peer-aware; Program collaboration; Program interference; Program optimization.

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APA (6th Edition):

Bao, B. (. -. ). (2013). Peer-aware program optimization. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/26831

Chicago Manual of Style (16th Edition):

Bao, Bin (1982 - ). “Peer-aware program optimization.” 2013. Doctoral Dissertation, University of Rochester. Accessed February 28, 2021. http://hdl.handle.net/1802/26831.

MLA Handbook (7th Edition):

Bao, Bin (1982 - ). “Peer-aware program optimization.” 2013. Web. 28 Feb 2021.

Vancouver:

Bao B(-). Peer-aware program optimization. [Internet] [Doctoral dissertation]. University of Rochester; 2013. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1802/26831.

Council of Science Editors:

Bao B(-). Peer-aware program optimization. [Doctoral Dissertation]. University of Rochester; 2013. Available from: http://hdl.handle.net/1802/26831


University of Michigan

24. Dundas, James David. Improving processor performance by dynamically pre-processing the instruction stream.

Degree: PhD, Electrical engineering, 1998, University of Michigan

 The exponentially increasing gap between processors and off-chip memory, as measured in processor cycles, is rapidly turning memory latency into a major processor performance bottleneck.… (more)

Subjects/Keywords: Dynamically; Improving; Instruction; Performance; Pipelining; Pre; Processing; Processor; Stream

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APA (6th Edition):

Dundas, J. D. (1998). Improving processor performance by dynamically pre-processing the instruction stream. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/130943

Chicago Manual of Style (16th Edition):

Dundas, James David. “Improving processor performance by dynamically pre-processing the instruction stream.” 1998. Doctoral Dissertation, University of Michigan. Accessed February 28, 2021. http://hdl.handle.net/2027.42/130943.

MLA Handbook (7th Edition):

Dundas, James David. “Improving processor performance by dynamically pre-processing the instruction stream.” 1998. Web. 28 Feb 2021.

Vancouver:

Dundas JD. Improving processor performance by dynamically pre-processing the instruction stream. [Internet] [Doctoral dissertation]. University of Michigan; 1998. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2027.42/130943.

Council of Science Editors:

Dundas JD. Improving processor performance by dynamically pre-processing the instruction stream. [Doctoral Dissertation]. University of Michigan; 1998. Available from: http://hdl.handle.net/2027.42/130943


McMaster University

25. Thaller, Wolfgang. Explicitly Staged Software Pipelining.

Degree: MSc, 2006, McMaster University

Software Pipelining is a method of instruction scheduling where loops are scheduled more efficiently by executing operations from more than one iteration of the… (more)

Subjects/Keywords: software pipelining; optimal software; pipeline schedule; computing

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APA (6th Edition):

Thaller, W. (2006). Explicitly Staged Software Pipelining. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/20357

Chicago Manual of Style (16th Edition):

Thaller, Wolfgang. “Explicitly Staged Software Pipelining.” 2006. Masters Thesis, McMaster University. Accessed February 28, 2021. http://hdl.handle.net/11375/20357.

MLA Handbook (7th Edition):

Thaller, Wolfgang. “Explicitly Staged Software Pipelining.” 2006. Web. 28 Feb 2021.

Vancouver:

Thaller W. Explicitly Staged Software Pipelining. [Internet] [Masters thesis]. McMaster University; 2006. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11375/20357.

Council of Science Editors:

Thaller W. Explicitly Staged Software Pipelining. [Masters Thesis]. McMaster University; 2006. Available from: http://hdl.handle.net/11375/20357


North Carolina State University

26. Sudarsanam, Yasaswini. Implementation of Double Precision Floating Point Arithmetic.

Degree: MS, Computer Engineering, 2007, North Carolina State University

 Floating Point Arithmetic is extensively used in the field of medical imaging, biometrics, motion capture and audio applications, including broadcast, conferencing, musical instruments and professional… (more)

Subjects/Keywords: IEEE 754 format; power analysis; pipelining; double precision

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APA (6th Edition):

Sudarsanam, Y. (2007). Implementation of Double Precision Floating Point Arithmetic. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/862

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sudarsanam, Yasaswini. “Implementation of Double Precision Floating Point Arithmetic.” 2007. Thesis, North Carolina State University. Accessed February 28, 2021. http://www.lib.ncsu.edu/resolver/1840.16/862.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sudarsanam, Yasaswini. “Implementation of Double Precision Floating Point Arithmetic.” 2007. Web. 28 Feb 2021.

Vancouver:

Sudarsanam Y. Implementation of Double Precision Floating Point Arithmetic. [Internet] [Thesis]. North Carolina State University; 2007. [cited 2021 Feb 28]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/862.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sudarsanam Y. Implementation of Double Precision Floating Point Arithmetic. [Thesis]. North Carolina State University; 2007. Available from: http://www.lib.ncsu.edu/resolver/1840.16/862

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

27. Dalal, Ishita. An Efficient FPGA Implementation of the Discrete Wavelet Transform.

Degree: MS, Electrical Engineering, 2008, North Carolina State University

Subjects/Keywords: discrete wavelet transform; interleaving; pipelining; optimizations; polyphase; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dalal, I. (2008). An Efficient FPGA Implementation of the Discrete Wavelet Transform. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dalal, Ishita. “An Efficient FPGA Implementation of the Discrete Wavelet Transform.” 2008. Thesis, North Carolina State University. Accessed February 28, 2021. http://www.lib.ncsu.edu/resolver/1840.16/1713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dalal, Ishita. “An Efficient FPGA Implementation of the Discrete Wavelet Transform.” 2008. Web. 28 Feb 2021.

Vancouver:

Dalal I. An Efficient FPGA Implementation of the Discrete Wavelet Transform. [Internet] [Thesis]. North Carolina State University; 2008. [cited 2021 Feb 28]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dalal I. An Efficient FPGA Implementation of the Discrete Wavelet Transform. [Thesis]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

28. Gupte, Ruchir. Interval Arithmetic Logic Unit for DSP and Control Applications.

Degree: MS, Electrical Engineering, 2006, North Carolina State University

 There are many applications in the field of digital signal processing (DSP) and controls that require the user to know how various numerical errors (uncertainty)… (more)

Subjects/Keywords: Pipelining; Signal Processing; Arithmetic Logic Unit; Interval Arithmetic

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APA (6th Edition):

Gupte, R. (2006). Interval Arithmetic Logic Unit for DSP and Control Applications. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1225

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gupte, Ruchir. “Interval Arithmetic Logic Unit for DSP and Control Applications.” 2006. Thesis, North Carolina State University. Accessed February 28, 2021. http://www.lib.ncsu.edu/resolver/1840.16/1225.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gupte, Ruchir. “Interval Arithmetic Logic Unit for DSP and Control Applications.” 2006. Web. 28 Feb 2021.

Vancouver:

Gupte R. Interval Arithmetic Logic Unit for DSP and Control Applications. [Internet] [Thesis]. North Carolina State University; 2006. [cited 2021 Feb 28]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1225.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gupte R. Interval Arithmetic Logic Unit for DSP and Control Applications. [Thesis]. North Carolina State University; 2006. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1225

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Morvan, Antoine. Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model.

Degree: Docteur es, Informatique, 2013, Cachan, Ecole normale supérieure

Grâce aux progrès réalisés dans le domaine des semi-conducteurs, les plateformes matérielles embarquées sont capables de satisfaire les contraintes de performances d'applications de plus en… (more)

Subjects/Keywords: Synthèse de haut niveau; Pipeline de nid de boucles; High level synthesis; Loop pipelining; Optimizing compilation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Morvan, A. (2013). Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model. (Doctoral Dissertation). Cachan, Ecole normale supérieure. Retrieved from http://www.theses.fr/2013DENS0022

Chicago Manual of Style (16th Edition):

Morvan, Antoine. “Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model.” 2013. Doctoral Dissertation, Cachan, Ecole normale supérieure. Accessed February 28, 2021. http://www.theses.fr/2013DENS0022.

MLA Handbook (7th Edition):

Morvan, Antoine. “Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model.” 2013. Web. 28 Feb 2021.

Vancouver:

Morvan A. Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model. [Internet] [Doctoral dissertation]. Cachan, Ecole normale supérieure; 2013. [cited 2021 Feb 28]. Available from: http://www.theses.fr/2013DENS0022.

Council of Science Editors:

Morvan A. Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model. [Doctoral Dissertation]. Cachan, Ecole normale supérieure; 2013. Available from: http://www.theses.fr/2013DENS0022


Université Paris-Sud – Paris XI

30. Fellahi, Mohammed. Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining.

Degree: Docteur es, Informatique, 2011, Université Paris-Sud – Paris XI

Les applications de flux de données sont des cibles importantes de l’optimisation de programme en raison de leur haute exigence de calcul et la diversité… (more)

Subjects/Keywords: Applications de flux de données; Boucles imbriquées; Pipeline logiciel; Ordonnancement multidimentionnel; Streaming applications; Nested loops; Multidimensional scheduling; Software Pipelining

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fellahi, M. (2011). Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2011PA112046

Chicago Manual of Style (16th Edition):

Fellahi, Mohammed. “Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining.” 2011. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed February 28, 2021. http://www.theses.fr/2011PA112046.

MLA Handbook (7th Edition):

Fellahi, Mohammed. “Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining.” 2011. Web. 28 Feb 2021.

Vancouver:

Fellahi M. Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2011. [cited 2021 Feb 28]. Available from: http://www.theses.fr/2011PA112046.

Council of Science Editors:

Fellahi M. Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2011. Available from: http://www.theses.fr/2011PA112046

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