subject:(Pipelining)

Washington State University

1. [No author]. High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures .

Degree: 2005, Washington State University

URL: http://hdl.handle.net/2376/349

Subjects/Keywords: Pipelining (Electronics)

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APA (6^th Edition):

author], [. (2005). High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/349

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

author], [No. “High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures .” 2005. Thesis, Washington State University. Accessed February 28, 2021. http://hdl.handle.net/2376/349.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

author], [No. “High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures .” 2005. Web. 28 Feb 2021.

Vancouver:

author] [. High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures . [Internet] [Thesis]. Washington State University; 2005. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2376/349.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. High-performance hybrid wave-pipeline scheme as it applies to adder micro-architectures . [Thesis]. Washington State University; 2005. Available from: http://hdl.handle.net/2376/349

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Ugurdag, Hasan Fatih. Various perspectives of loop pipelining.

Degree: PhD, Electrical Engineering, 1995, Case Western Reserve University School of Graduate Studies

URL: http://rave.ohiolink.edu/etdc/view?acc_num=case1061833352

► Loops can be a bottle-neck in many computer applications. Examples of such applications include industrial inspection tasks, embedded system software, and DSP algorithms. Loop pipelining… (more)

Subjects/Keywords: Loop pipelining

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APA (6^th Edition):

Ugurdag, H. F. (1995). Various perspectives of loop pipelining. (Doctoral Dissertation). Case Western Reserve University School of Graduate Studies. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1061833352

Chicago Manual of Style (16^th Edition):

Ugurdag, Hasan Fatih. “Various perspectives of loop pipelining.” 1995. Doctoral Dissertation, Case Western Reserve University School of Graduate Studies. Accessed February 28, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=case1061833352.

MLA Handbook (7^th Edition):

Ugurdag, Hasan Fatih. “Various perspectives of loop pipelining.” 1995. Web. 28 Feb 2021.

Vancouver:

Ugurdag HF. Various perspectives of loop pipelining. [Internet] [Doctoral dissertation]. Case Western Reserve University School of Graduate Studies; 1995. [cited 2021 Feb 28]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1061833352.

Council of Science Editors:

Ugurdag HF. Various perspectives of loop pipelining. [Doctoral Dissertation]. Case Western Reserve University School of Graduate Studies; 1995. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1061833352

Universidade do Rio Grande do Norte

3. Medeiros, Aparecida Lopes de. Implementação da técnica de software pipelining na rede em chip IPNoSyS .

Degree: 2014, Universidade do Rio Grande do Norte

URL: http://repositorio.ufrn.br/handle/123456789/18100

► Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors,… (more)

Subjects/Keywords: Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho; Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho

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APA (6^th Edition):

Medeiros, A. L. d. (2014). Implementação da técnica de software pipelining na rede em chip IPNoSyS . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Thesis, Universidade do Rio Grande do Norte. Accessed February 28, 2021. http://repositorio.ufrn.br/handle/123456789/18100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Web. 28 Feb 2021.

Vancouver:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2014. [cited 2021 Feb 28]. Available from: http://repositorio.ufrn.br/handle/123456789/18100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Thesis]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/18100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade do Rio Grande do Norte

4. Medeiros, Aparecida Lopes de. Implementação da técnica de software pipelining na rede em chip IPNoSyS .

Degree: 2014, Universidade do Rio Grande do Norte

URL: http://repositorio.ufrn.br/handle/123456789/18100

► Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors,… (more)

Subjects/Keywords: Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho; Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Medeiros, A. L. d. (2014). Implementação da técnica de software pipelining na rede em chip IPNoSyS . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18100

Chicago Manual of Style (16^th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Masters Thesis, Universidade do Rio Grande do Norte. Accessed February 28, 2021. http://repositorio.ufrn.br/handle/123456789/18100.

MLA Handbook (7^th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Web. 28 Feb 2021.

Vancouver:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2014. [cited 2021 Feb 28]. Available from: http://repositorio.ufrn.br/handle/123456789/18100.

Council of Science Editors:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Masters Thesis]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/18100

Brno University of Technology

5. Zlatohlávková, Lucie. Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU.

Degree: 2020, Brno University of Technology

URL: http://hdl.handle.net/11012/187521

► This masters thesis is focused on the issue of processor architecture. The ground of this project is a design of a simple processor, which is… (more)

Subjects/Keywords: Architektura; Počítač; Procesor; Instrukce; Pipelining; Predikce skoků; Paměť cache.; Architecture; Computer; Processor; Instruction; Pipelining; Branch prediction; Cache memory.

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APA (6^th Edition):

Zlatohlávková, L. (2020). Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/187521

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zlatohlávková, Lucie. “Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU.” 2020. Thesis, Brno University of Technology. Accessed February 28, 2021. http://hdl.handle.net/11012/187521.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zlatohlávková, Lucie. “Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU.” 2020. Web. 28 Feb 2021.

Vancouver:

Zlatohlávková L. Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11012/187521.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zlatohlávková L. Návrh a implementace prostředků pro zvýšení výkonu procesoru: Design and Implementation of Mechanisms for Enhancing Performance of CPU. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/187521

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Virginia Tech

6. Sulistyo, Jos Budi. High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining.

Degree: PhD, Electrical and Computer Engineering, 2005, Virginia Tech

URL: http://hdl.handle.net/10919/29091

► The increasing capabilities of multimedia appliances demand arithmetic circuits with higher speed and reasonable power dissipation. A common technique to attain those goals is synchronous… (more)

▼ The increasing capabilities of multimedia appliances demand arithmetic circuits with higher speed and reasonable power dissipation. A common technique to attain those goals is synchronous pipelining, which increases the throughput of a circuit at the expense of longer latency, and it is therefore suitable where throughput takes priority over latency. Two synchronous pipelining approaches, conventional pipelining and wave pipelining, are commonly employed. Conventional pipelining uses registers to divide the circuit into shorter paths and synchronize among sub-blocks, while wave pipelining uses the delay of combinational elements to perform those tasks. As wave pipelining does not introduce additional registers, in principle, it can attain a higher throughput and lower power consumption. However, its throughput is limited by delay variations, while delay balancing often leads to increased power dissipation. This dissertation proposes a hybrid pipelining method called HyPipe, which divides the circuit into sub-blocks using conventional pipelining, and applies wave pipelining to each sub-block. Each sub-block is derived from a single base circuit, leading to a better delay balance and greater throughput than with heterogeneous circuits. Another requirement for wave pipelining to achieve high speed is short signal rise and fall times. Since CMOS wide-NAND and wide-NOR gates exhibit long rise and fall times and large delay variations, they should be decomposed. We show that the straightforward decomposition using alternating levels of NAND and NOR gates results in large delay variations. Therefore, we propose a new decomposition method using only one gate type. Our method reduces delay variations by up to 39%, and it is appropriate for wave pipelining based on standard-cells or sea-of-gates. We laid out a 4x4 HyPipe multiplier as a proof of concept and performed a post-layout SPICE simulation. The multiplier achieves a throughput of 4.17 billion multiplications per second or a clock period of 2.52 four-load inverter delays, which is almost twice the speed of any existing multiplier in the open literature. When the supply voltage is reduced to 1.2 V from 1.8 V, its power consumption is reduced from 76.2 mW to 18.2 mW while performing 2.33 billion multiplications per second. Advisors/Committee Members: Ha, Dong Sam (committeechair), Reed, Jeffrey Hugh (committee member), Lu, Guo-Quan (committee member), Gray, Festus Gail (committee member), Armstrong, James R. (committee member).

Subjects/Keywords: high-speed CMOS VLSI; pipelining; wave pipelining; arithmetic circuits

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APA (6^th Edition):

Sulistyo, J. B. (2005). High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29091

Chicago Manual of Style (16^th Edition):

Sulistyo, Jos Budi. “High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining.” 2005. Doctoral Dissertation, Virginia Tech. Accessed February 28, 2021. http://hdl.handle.net/10919/29091.

MLA Handbook (7^th Edition):

Sulistyo, Jos Budi. “High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining.” 2005. Web. 28 Feb 2021.

Vancouver:

Sulistyo JB. High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining. [Internet] [Doctoral dissertation]. Virginia Tech; 2005. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10919/29091.

Council of Science Editors:

Sulistyo JB. High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining. [Doctoral Dissertation]. Virginia Tech; 2005. Available from: http://hdl.handle.net/10919/29091

Anna University

7. Kalavathi Devi T. Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;.

Degree: communication engineering, 2013, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/23861

►

Rapid developments in the field of wireless communication have newlinecreated a rising demand for Viterbi decoder with long battery life low power newlinedissipation and low… (more)

▼

Rapid developments in the field of wireless communication have newlinecreated a rising demand for Viterbi decoder with long battery life low power newlinedissipation and low weight Despite the significant progress in the last decade newlinethe problems of power dissipation in the Viterbi decoder still remains newlinechallenging and require further technical solutions Hence this research newlinefocuses on designing low power VLSI Very Large Scale Integration newlinearchitectures for the Viterbi decoder for a constraint length of K3 and newlinediscuss their performances in terms of power speed and area The newlineconvolutional encoders are designed for constraint length of K3 to7 Thus newlinethe performance of the Viterbi decoder is improved by low power VLSI newlinetechniques newlineIn order to reduce the power consumption and to increase the speed newlineof the Viterbi decoder repeated iterations are performed at the same clock newlinetransition by unfolding algorithm This unfolding algorithm is applied at the newlinebit level to generate digitserial architecture which processes multiple words newlineper clock cycle The obtained results are compared with the existing 2 bit newlinelevel pipelined look ahead technique It is observed that the proposed method newlinereduced power consumption by 2576 with 1009 increase in speed The newlinelimitation of this method is addressed by wave pipelining technique and it is newlineimplemented to increase the speed of the architecture as the idle time of the newlinenon critical paths is reduced newlineThe combined technique of Self Reset Logic SRL with wave newlinepipelining is used to design the architecture for the Viterbi decoder to reduce newlinethe power dissipation Power consumption of the wave pipelining work is newlinereduced by a factor of 7231 when compared to the existing single rail newlinedomino logic The area of the decoder increases with respect to its advantage newlineof increase in speed newlineVLSI architecture for a Viterbi decoder based on GDI Gate newlineDiffusion Input is designed to minimize the number of transistors and newlinetransitions Thus the problem of high gate density in SRL based design is newlineaddressed by the GDI approach newline newline

Advisors/Committee Members: Venkatesh C.

Subjects/Keywords: Low Power; Power Reduction; Viterbi Decoder; VlSI Architectures; wave pipelining

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APA (6^th Edition):

T, K. D. (2013). Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/23861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

T, Kalavathi Devi. “Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;.” 2013. Thesis, Anna University. Accessed February 28, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/23861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

T, Kalavathi Devi. “Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;.” 2013. Web. 28 Feb 2021.

Vancouver:

T KD. Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;. [Internet] [Thesis]. Anna University; 2013. [cited 2021 Feb 28]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

T KD. Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures;. [Thesis]. Anna University; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/23861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Ho, Calvin. Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers.

Degree: MS, Electrical and Computer Engineering, 2014, California State University – Northridge

URL: http://hdl.handle.net/10211.2/4996

► This report describes some the fundamentals of Bitcoin mining. It highlights some of the key aspects that are needed to create and operate a miner.… (more)

Subjects/Keywords: pipelining; Dissertations, Academic – CSUN – Engineering – Electrical and Computer Engineering.

10 more images…

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APA (6^th Edition):

Ho, C. (2014). Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.2/4996

Chicago Manual of Style (16^th Edition):

Ho, Calvin. “Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers.” 2014. Masters Thesis, California State University – Northridge. Accessed February 28, 2021. http://hdl.handle.net/10211.2/4996.

MLA Handbook (7^th Edition):

Ho, Calvin. “Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers.” 2014. Web. 28 Feb 2021.

Vancouver:

Ho C. Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers. [Internet] [Masters thesis]. California State University – Northridge; 2014. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10211.2/4996.

Council of Science Editors:

Ho C. Adaptation of all-programmable SoC to hardware Bitcoin miners and mining servers. [Masters Thesis]. California State University – Northridge; 2014. Available from: http://hdl.handle.net/10211.2/4996

Washington State University

9. [No author]. A high performance low power mesochronous pipeline architecture for computer systems .

Degree: 2006, Washington State University

URL: http://hdl.handle.net/2376/475

Subjects/Keywords: Pipelining (Electronics); Computers, Pipeline.

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APA (6^th Edition):

author], [. (2006). A high performance low power mesochronous pipeline architecture for computer systems . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/475

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

author], [No. “A high performance low power mesochronous pipeline architecture for computer systems .” 2006. Thesis, Washington State University. Accessed February 28, 2021. http://hdl.handle.net/2376/475.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

author], [No. “A high performance low power mesochronous pipeline architecture for computer systems .” 2006. Web. 28 Feb 2021.

Vancouver:

author] [. A high performance low power mesochronous pipeline architecture for computer systems . [Internet] [Thesis]. Washington State University; 2006. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2376/475.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. A high performance low power mesochronous pipeline architecture for computer systems . [Thesis]. Washington State University; 2006. Available from: http://hdl.handle.net/2376/475

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of California – Santa Cruz

10. Trapani Possignolo, Rafael. Improving the Productivity of Hardware Design.

Degree: Computer Engineering, 2018, University of California – Santa Cruz

URL: http://www.escholarship.org/uc/item/6bd5n1c7

► Current hardware development techniques contrast with agile methods that became popular in modern software development. This has been mitigated with technology scaling, when performance gains… (more)

Subjects/Keywords: Computer engineering; Computer science; Digital Design; Electronic Design Automation; Pipelining; Productivity

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APA (6^th Edition):

Trapani Possignolo, R. (2018). Improving the Productivity of Hardware Design. (Thesis). University of California – Santa Cruz. Retrieved from http://www.escholarship.org/uc/item/6bd5n1c7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Trapani Possignolo, Rafael. “Improving the Productivity of Hardware Design.” 2018. Thesis, University of California – Santa Cruz. Accessed February 28, 2021. http://www.escholarship.org/uc/item/6bd5n1c7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Trapani Possignolo, Rafael. “Improving the Productivity of Hardware Design.” 2018. Web. 28 Feb 2021.

Vancouver:

Trapani Possignolo R. Improving the Productivity of Hardware Design. [Internet] [Thesis]. University of California – Santa Cruz; 2018. [cited 2021 Feb 28]. Available from: http://www.escholarship.org/uc/item/6bd5n1c7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Trapani Possignolo R. Improving the Productivity of Hardware Design. [Thesis]. University of California – Santa Cruz; 2018. Available from: http://www.escholarship.org/uc/item/6bd5n1c7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

IUPUI

11. Mao, Linyong. Application of Data Pipelining Technology in Cheminformatics and Bioinformatics.

Degree: 2002, IUPUI

URL: http://hdl.handle.net/1805/322

►

Submitted to the faculty of the University Graduate School in partial fulfillment of the requirements for the degree Master of Sciences in the School of… (more)

Subjects/Keywords: data pipelining technology; cheminformatics; bioinformatics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mao, L. (2002). Application of Data Pipelining Technology in Cheminformatics and Bioinformatics. (Thesis). IUPUI. Retrieved from http://hdl.handle.net/1805/322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Mao, Linyong. “Application of Data Pipelining Technology in Cheminformatics and Bioinformatics.” 2002. Thesis, IUPUI. Accessed February 28, 2021. http://hdl.handle.net/1805/322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Mao, Linyong. “Application of Data Pipelining Technology in Cheminformatics and Bioinformatics.” 2002. Web. 28 Feb 2021.

Vancouver:

Mao L. Application of Data Pipelining Technology in Cheminformatics and Bioinformatics. [Internet] [Thesis]. IUPUI; 2002. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1805/322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mao L. Application of Data Pipelining Technology in Cheminformatics and Bioinformatics. [Thesis]. IUPUI; 2002. Available from: http://hdl.handle.net/1805/322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Delft University of Technology

12. Klass, E.F. Wave pipelining: Theoretical and practical issues in CMOS.

Degree: 1994, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765

Subjects/Keywords: Computer architecture; wave pipelining

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APA (6^th Edition):

Klass, E. F. (1994). Wave pipelining: Theoretical and practical issues in CMOS. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765

Chicago Manual of Style (16^th Edition):

Klass, E F. “Wave pipelining: Theoretical and practical issues in CMOS.” 1994. Doctoral Dissertation, Delft University of Technology. Accessed February 28, 2021. http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765.

MLA Handbook (7^th Edition):

Klass, E F. “Wave pipelining: Theoretical and practical issues in CMOS.” 1994. Web. 28 Feb 2021.

Vancouver:

Klass EF. Wave pipelining: Theoretical and practical issues in CMOS. [Internet] [Doctoral dissertation]. Delft University of Technology; 1994. [cited 2021 Feb 28]. Available from: http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765.

Council of Science Editors:

Klass EF. Wave pipelining: Theoretical and practical issues in CMOS. [Doctoral Dissertation]. Delft University of Technology; 1994. Available from: http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; urn:NBN:nl:ui:24-uuid:2d257c85-3d5c-4d43-9439-21ff16de5765 ; http://resolver.tudelft.nl/uuid:2d257c85-3d5c-4d43-9439-21ff16de5765

Brno University of Technology

13. Hájek, Radek. Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/59746

► The diploma thesis contains theoretical basis, classification and function of processors. It summarizes the principle of pipelined instruction processing and the types of hazards in… (more)

Subjects/Keywords: Procesor; CodAL; MicroBlaze; zřetězené zpracování; hazardy; Processor; CodAL; MicroBlaze; pipelining; hazards

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APA (6^th Edition):

Hájek, R. (2019). Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/59746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hájek, Radek. “Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language.” 2019. Thesis, Brno University of Technology. Accessed February 28, 2021. http://hdl.handle.net/11012/59746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hájek, Radek. “Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language.” 2019. Web. 28 Feb 2021.

Vancouver:

Hájek R. Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11012/59746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hájek R. Implementace procesoru MicroBlaze v jazyce CodAL: MicroBlaze processor implementation using CodAL language. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/59746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Georgia State University

14. Wu, Xiaolong. Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform.

Degree: MS, Computer Science, 2015, Georgia State University

URL: https://scholarworks.gsu.edu/cs_theses/84

► Sparse Matrix-Matrix multiplication (SpMM) is a fundamental operation over irregular data, which is widely used in graph algorithms, such as finding minimum spanning trees… (more)

Subjects/Keywords: Sparse matrix-matrix multiplication; Data locality; Pipelining; GPU

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APA (6^th Edition):

Wu, X. (2015). Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform. (Thesis). Georgia State University. Retrieved from https://scholarworks.gsu.edu/cs_theses/84

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Xiaolong. “Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform.” 2015. Thesis, Georgia State University. Accessed February 28, 2021. https://scholarworks.gsu.edu/cs_theses/84.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Xiaolong. “Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform.” 2015. Web. 28 Feb 2021.

Vancouver:

Wu X. Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform. [Internet] [Thesis]. Georgia State University; 2015. [cited 2021 Feb 28]. Available from: https://scholarworks.gsu.edu/cs_theses/84.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu X. Optimizing Sparse Matrix-Matrix Multiplication on a Heterogeneous CPU-GPU Platform. [Thesis]. Georgia State University; 2015. Available from: https://scholarworks.gsu.edu/cs_theses/84

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Karlstad University

15. Vilhelmsson, Lina. Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi.

Degree: Karlstad University, 2020, Karlstad University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-78032

► In the last few years, the popularity of Industrial IoT has grown a lot, and it is expected to have an impact of over… (more)

Subjects/Keywords: Data pipelining; Apache NiFi; IIoT; Industrial IoT; Computer Sciences; Datavetenskap (datalogi)

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APA (6^th Edition):

Vilhelmsson, L. (2020). Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi. (Thesis). Karlstad University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-78032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Vilhelmsson, Lina. “Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi.” 2020. Thesis, Karlstad University. Accessed February 28, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-78032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Vilhelmsson, Lina. “Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi.” 2020. Web. 28 Feb 2021.

Vancouver:

Vilhelmsson L. Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi. [Internet] [Thesis]. Karlstad University; 2020. [cited 2021 Feb 28]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-78032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vilhelmsson L. Implementation and Evaluation of a DataPipeline for Industrial IoT Using ApacheNiFi. [Thesis]. Karlstad University; 2020. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-78032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Georgia Tech

16. Aleen, Farhana Afroz. Dynamic execution prediction and pipeline balancing of streaming applications.

Degree: MS, Computing, 2010, Georgia Tech

URL: http://hdl.handle.net/1853/37192

► The number and scope of data driven streaming applications is growing. Such streaming applications are promising targets for effectively utilizing multi-cores because of their inherent… (more)

▼ The number and scope of data driven streaming applications is growing. Such streaming applications are promising targets for effectively utilizing multi-cores because of their inherent amenability to pipelined parallelism. While existing methods of orchestrating streaming programs on multi-cores have mostly been static, real-world applications show ample variations in execution time that may cause the achieved speedup and throughput to be sub-optimal. One of the principle challenges for moving towards dynamic pipeline balancing has been the lack of approaches that can predict upcoming dynamic variations in execution efficiently, well before they occur. In this thesis, we propose an automated dynamic execution behavior prediction approach based on compiler analysis that can be used to efficiently estimate the time to be spent in different pipeline stages for upcoming inputs. Our approach first uses dynamic taint analysis to automatically generate an input-based execution characterization of the streaming program, which identifies the key control points where variation in execution might occur with respect to the associated input elements. We then automatically generate a light-weight emulator from the program using this characterization that can predict the execution paths taken for new streaming inputs and provide execution time estimates and possible dynamic variations. The main challenge in devising such an approach is the essential trade-off between accuracy and overhead of dynamic analysis. We present experimental evidence that our technique can accurately and efficiently estimate dynamic execution behaviors for several benchmarks with a small error rate. We also showed that the error rate could be lowered with the trade-off of execution overhead by implementing a selective symbolic expression generation for each of the complex conditions of control-flow operations. Our experiments show that dynamic pipeline balancing using our predicted execution behavior can achieve considerably higher speedup and throughput along with more effective utilization of multi-cores than static balancing approaches. Advisors/Committee Members: Santosh Pande (Committee Chair), Kim, Hyesoon (Committee Member), Yalamanchilli, Sudhakar (Committee Member).

Subjects/Keywords: Dynamic scheduling; Software pipelining; Streaming technology (Telecommunications); Multimedia systems; Computers, Pipeline; Pipelining (Electronics)

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APA (6^th Edition):

Aleen, F. A. (2010). Dynamic execution prediction and pipeline balancing of streaming applications. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37192

Chicago Manual of Style (16^th Edition):

Aleen, Farhana Afroz. “Dynamic execution prediction and pipeline balancing of streaming applications.” 2010. Masters Thesis, Georgia Tech. Accessed February 28, 2021. http://hdl.handle.net/1853/37192.

MLA Handbook (7^th Edition):

Aleen, Farhana Afroz. “Dynamic execution prediction and pipeline balancing of streaming applications.” 2010. Web. 28 Feb 2021.

Vancouver:

Aleen FA. Dynamic execution prediction and pipeline balancing of streaming applications. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1853/37192.

Council of Science Editors:

Aleen FA. Dynamic execution prediction and pipeline balancing of streaming applications. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37192

University of Utah

17. Gebhardt, Daniel J. Energy-efficient design of an asynchronous network-on-chip.

Degree: PhD, Computer Science, 2011, University of Utah

URL: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

► Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are… (more)

Subjects/Keywords: Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Gebhardt, D. J. (2011). Energy-efficient design of an asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Chicago Manual of Style (16^th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed February 28, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

MLA Handbook (7^th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Web. 28 Feb 2021.

Vancouver:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2021 Feb 28]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

Council of Science Editors:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Anna University

18. Kumar, V. Design of an efficient medium access protocol for wireless networks using pipelining methods.

Degree: 2013, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/13417

► In this work, new techniques for cross layer design of wireless network has been proposed for improving the Quality of Service in wireless networks by… (more)

▼ In this work, new techniques for cross layer design of wireless network has been proposed for improving the Quality of Service in wireless networks by considering the MAC and network layers. For this purpose, pipelining techniques have been used at the MAC layer that improves the channel utilization. In wireless MAC protocols, packet scheduling is carried out based on a channel allocation algorithm in which the channel is allotted based on the CSMA/CD algorithm. However, this algorithm is useful only for contention resolution. When the network traffic is increased, it is necessary to service many nodes at a time in order to send multiple packets at the same time. For this purpose, a parallel scheduling algorithm using pipelining has been proposed and implemented in this research work. In this algorithm, a MAC job is split into multiple stages and the execution of various stages is allowed to overlap using pipelining mechanism. In this thesis work, a novel proactive maintenance scheme is followed where a set of 1-hop neighbours called passive nodes around the path between source and destination are maintained. Moreover, the combinations of active and passive nodes maintain a mesh of optimal and sub-optimal paths where sub-optimal paths are backups and activated only when all optimal paths fail. This research work includes an ant based proactive route discovery to increase the connectivity between the nodes. In this ant based proactive route discovery, every node maintains a pheromone table and a probability routing table. Forward ants are used by the source to find the path to the destination and the optimal path is returned in the form of backward ants. In this way, route optimization techniques have been proposed in this thesis. The major contributions of this thesis are the proposal of an architectural frame work for cross layer design, pipelining at the MAC layer, and clustering and ant colony optimization at the network layer for improving the overall performance of the network. newline newline newline Advisors/Committee Members: Balasubramanie, P.

Subjects/Keywords: Medium Access Protocol; Wireless Networks; Pipelining methods; MAC layer; CSMA/CD algorithm; passive nodes

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APA (6^th Edition):

Kumar, V. (2013). Design of an efficient medium access protocol for wireless networks using pipelining methods. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/13417

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kumar, V. “Design of an efficient medium access protocol for wireless networks using pipelining methods.” 2013. Thesis, Anna University. Accessed February 28, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/13417.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kumar, V. “Design of an efficient medium access protocol for wireless networks using pipelining methods.” 2013. Web. 28 Feb 2021.

Vancouver:

Kumar V. Design of an efficient medium access protocol for wireless networks using pipelining methods. [Internet] [Thesis]. Anna University; 2013. [cited 2021 Feb 28]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13417.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumar V. Design of an efficient medium access protocol for wireless networks using pipelining methods. [Thesis]. Anna University; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13417

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Penn State University

19. Ming, Jiang. Pipelined Symbolic Taint Analysis.

Degree: 2016, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/v979v304g

► The multifaceted benefits of taint analysis have led to its wide adoption in security applications, such as software attack detection, attack provenance investigation, and data… (more)

▼ The multifaceted benefits of taint analysis have led to its wide adoption in security applications, such as software attack detection, attack provenance investigation, and data lifetime analysis. Static taint analysis propagates taint values following all possible paths with no need for concrete execution but is generally less accurate than dynamic analysis. Unfortunately, the high runtime overhead imposed by dynamic taint analysis makes it impractical in many scenarios. The key obstacle is the strict coupling of program execution and taint tracking logic code. To alleviate this performance bottleneck, recent work seeks to offload taint analysis from program execution and run it on a different CPU offline or a spare core in parallel. However, since the taint analysis has heavy data and control dependencies on the program execution, the massive data in recording or transformation overshadows the benefit of decoupling. In this thesis, we continue this line of research to take advantage of ubiquitous multi-core platforms. First, we propose StraightTaint, a hybrid taint analysis tool that completely decouples the program execution and taint analysis. StraightTaint allows very lightweight logging, resulting in much lower execution slowdown, while still permitting us to perform full-featured offline taint analysis, including bit-level and multi-tag taint analysis. StraightTaint relies on very lightweight logging of the execution information to reconstruct a straight-line code, enabling an offline symbolic taint analysis without frequent data communication with the application. While StraightTaint does not log complete runtime or input values, it is able to precisely identify the causal relationships between sources and sinks, for example. Our experimental results show that on average StraightTaint can speed up application execution performance 3.32 times on a set of utility programs and 3.25 times on SPEC2006. The collected data during online logging for some long running program could be still too large to be saved up for offline analysis. To address this limitation, we propose TaintPipe, a novel technique for parallelizing and pipelining taint analysis. TaintPipe produces compact control flow profiles and spawns multiple threads as different stages of a pipeline to carry out symbolic taint analysis in parallel. Our experiments show that TaintPipe imposes low overhead on application runtime performance and accelerates taint analysis significantly. Compared to a state-of-the-art inlined dynamic data flow tracking tool, TaintPipe achieves 2.38 times speedup for taint analysis on SPEC2006 and 2.43 times for a set of common utilities, respectively. In addition, we demonstrate the strength of TaintPipe with a set of security applications. Last but not least, due to the design, both StraightTaint and TaintPipe are an ideal fit for ex post facto security applications, such as computer forensic analysis and reverse engineering. To make the techniques described in this thesis apply to a broader range of such applications, we… Advisors/Committee Members: Dinghao Wu, Dissertation Advisor/Co-Advisor, Dinghao Wu, Committee Chair/Co-Chair, Peng Liu, Committee Member, Sencun Zhu, Committee Member, Patrick Drew Mcdaniel, Outside Member.

Subjects/Keywords: taint analysis; pipelining taint analysis; offline symbolic taint analysis; multi-core architectures

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APA (6^th Edition):

Ming, J. (2016). Pipelined Symbolic Taint Analysis. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/v979v304g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ming, Jiang. “Pipelined Symbolic Taint Analysis.” 2016. Thesis, Penn State University. Accessed February 28, 2021. https://submit-etda.libraries.psu.edu/catalog/v979v304g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ming, Jiang. “Pipelined Symbolic Taint Analysis.” 2016. Web. 28 Feb 2021.

Vancouver:

Ming J. Pipelined Symbolic Taint Analysis. [Internet] [Thesis]. Penn State University; 2016. [cited 2021 Feb 28]. Available from: https://submit-etda.libraries.psu.edu/catalog/v979v304g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ming J. Pipelined Symbolic Taint Analysis. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/v979v304g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

20. Chen, Yi-Chang. The Study of Double Level Branch Buffer.

Degree: Master, Electrical Engineering, 2001, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012101-091101

► Pipelining is the major organizational technique by which computers can execute several instructions simultaneously to reach higher single-processor performance. Branches are recognized as a major… (more)

Subjects/Keywords: Pipelining; Branch Penalty; Branch Prediction; Branch Target Buffer

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APA (6^th Edition):

Chen, Y. (2001). The Study of Double Level Branch Buffer. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012101-091101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Yi-Chang. “The Study of Double Level Branch Buffer.” 2001. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012101-091101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Yi-Chang. “The Study of Double Level Branch Buffer.” 2001. Web. 28 Feb 2021.

Vancouver:

Chen Y. The Study of Double Level Branch Buffer. [Internet] [Thesis]. NSYSU; 2001. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012101-091101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. The Study of Double Level Branch Buffer. [Thesis]. NSYSU; 2001. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012101-091101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. 池田, 吉朗. ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

URL: http://hdl.handle.net/10119/1288

Supervisor:日比野靖

情報科学研究科

修士

Subjects/Keywords: マルチスレッド型プロセッサ、ウェーブパイプライン; multi-threaded processor, wave pipelining

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

池田, �. (n.d.). ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/1288

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

池田, 吉朗. “ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed February 28, 2021. http://hdl.handle.net/10119/1288.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

池田, 吉朗. “ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究.” Web. 28 Feb 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

池田 �. ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10119/1288.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

池田 �. ウェーブパイプラインを用いたマルチスレッド型プロセッサアーキテクチャに関する研究. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/1288

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

22. Tsakiris, Nicholas. Enabling Gigabit IP for Embedded Systems.

Degree: 2009, Flinders University

URL: http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821

► For any practical implementation of chip design, there needs to be a hardware platform available for the purpose of prototyping and implementation of FPGA-based programs,… (more)

▼ For any practical implementation of chip design, there needs to be a hardware platform available for the purpose of prototyping and implementation of FPGA-based programs, whether they are written in VHDL or Verilog. Communication between the platform and a computer is a useful feature of many hardware solutions as it allows for the capability of regular data transmission between the two devices. Furthermore, the ability to communicate between the platform and a computer at high-speeds requires a specially constructed interface, one that can be modified by the designer at their choosing. There are a number of commercial packages which provide a hardware platform to perform this task, however there are drawbacks to many of the available options. Some may require special hardware to connect to a computer using proprietary connectors or boards, which increases the cost and reduces the flexibility of any solution. Other options may have limited access to the internal structure of the interface, limiting the ability of the developer to modify the interface to suit their needs. There may be an extra cost to provide the code to the interface, separate from the board, which can also tax design budgets. This dissertation provides a solution in the form of a Gigabit Ethernet connection with a custom IP/network layer written in VHDL to facilitate the connection. With an increasing number of IP-enabled devices available such as IPTV and set top boxes, the ability to link hardware using Ethernet is very useful and so the development of a lean and capable network layer was considered a suitable focus for the project. The overall goal has been to provide an interface which is cheap, open, robust and efficient, retaining the flexibility a developer might require to modify the code to their needs. After covering some basic background information about the project, the dissertation looks at the requirements of the board and interface, as well as the alternative interface solutions which were looked at before deciding on Gigabit Ethernet. The protocols used in Ethernet are then covered, with both an explanation of the structure of each and their relevance to the implementation. The Finite State Machines which control operation of the interface are covered in depth, with an explanation of their inter-connectivity to each other and how they fit in the data-flow between the computer and the board. Error correction and reliability is discussed, as well as any remaining components critical to the operation of the interface. Pipelining, the method of design which provides the speed required for Gigabit Ethernet, is covered along with the extra speed optimisation techniques used in the design such as RAM swinging buffers. Testing and synthesis are covered which ensure the design is as robust as possible, both in simulations and in real-world applications. The final design was implemented on a Xilinx Spartan 3 FPGA (XC3S5000-5FG900C) and capable of a maximum speed of 128.287 MHz, which is more than enough to…

Subjects/Keywords: embedded; vhdl; fpga; jpeg; jpeg2000; pipelining; xilinx

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APA (6^th Edition):

Tsakiris, N. (2009). Enabling Gigabit IP for Embedded Systems. (Thesis). Flinders University. Retrieved from http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tsakiris, Nicholas. “Enabling Gigabit IP for Embedded Systems.” 2009. Thesis, Flinders University. Accessed February 28, 2021. http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tsakiris, Nicholas. “Enabling Gigabit IP for Embedded Systems.” 2009. Web. 28 Feb 2021.

Vancouver:

Tsakiris N. Enabling Gigabit IP for Embedded Systems. [Internet] [Thesis]. Flinders University; 2009. [cited 2021 Feb 28]. Available from: http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsakiris N. Enabling Gigabit IP for Embedded Systems. [Thesis]. Flinders University; 2009. Available from: http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20090913.204821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Rochester

23. Bao, Bin (1982 - ). Peer-aware program optimization.

Degree: PhD, 2013, University of Rochester

URL: http://hdl.handle.net/1802/26831

► Most existing program optimization techniques are based on the code or the behavior of the target program, which means they can be characterized as self-aware.… (more)

Subjects/Keywords: Defensive loop tiling; Dynamic computation and communication pipelining; Peer-aware; Program collaboration; Program interference; Program optimization.

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APA (6^th Edition):

Bao, B. (. -. ). (2013). Peer-aware program optimization. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/26831

Chicago Manual of Style (16^th Edition):

Bao, Bin (1982 - ). “Peer-aware program optimization.” 2013. Doctoral Dissertation, University of Rochester. Accessed February 28, 2021. http://hdl.handle.net/1802/26831.

MLA Handbook (7^th Edition):

Bao, Bin (1982 - ). “Peer-aware program optimization.” 2013. Web. 28 Feb 2021.

Vancouver:

Bao B(-). Peer-aware program optimization. [Internet] [Doctoral dissertation]. University of Rochester; 2013. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1802/26831.

Council of Science Editors:

Bao B(-). Peer-aware program optimization. [Doctoral Dissertation]. University of Rochester; 2013. Available from: http://hdl.handle.net/1802/26831

University of Michigan

24. Dundas, James David. Improving processor performance by dynamically pre-processing the instruction stream.

Degree: PhD, Electrical engineering, 1998, University of Michigan

URL: http://hdl.handle.net/2027.42/130943

► The exponentially increasing gap between processors and off-chip memory, as measured in processor cycles, is rapidly turning memory latency into a major processor performance bottleneck.… (more)

▼ The exponentially increasing gap between processors and off-chip memory, as measured in processor cycles, is rapidly turning memory latency into a major processor performance bottleneck. Traditional solutions, such as employing multiple levels of caches, are expensive and do not work well with some applications. We evaluate a technique, called runahead pre-processing, that can significantly improve processor performance. The basic idea behind runahead is to use the processor pipeline to pre-process instructions during cache miss cycles, instead of stalling. The pre-processed instructions are used to generate highly accurate instruction and data stream prefetches, while all of the pre-processed instruction results are discarded after the cache miss has been serviced: this allows us to achieve a form of very aggressive speculation with a simple in-order pipeline. The principal hardware cost is a means of checkpointing the sequential state of the register file and memory hierarchy while instructions are pre-processed. As we discard all pre-processed instruction results, the checkpointing can be accomplished with a modest amount of hardware. The instruction and data stream prefetches generated during runahead episodes led to a significant performance improvement for all of the benchmarks we examined. We found that runahead typically led to about a 30% reduction in CPI for the four Spec95 integer benchmarks that we simulated, while runahead was able to reduce CPI by 77% for the STREAM benchmark. This is for a five stage pipeline with two levels of split instruction and data caches: 8KB each of L1, and 1MB each of L2. A significant result is that when the latency to off-chip memory increases, or if the caching performance for a particular bench-mark is poor, runahead is especially effective as the processor has more opportunities in which to pre-process instructions. Finally, runahead appears particularly well suited for use with high clock-rate in-order processors that employ relatively inexpensive memory hierarchies. Advisors/Committee Members: Mudge, Trevor (advisor).

Subjects/Keywords: Dynamically; Improving; Instruction; Performance; Pipelining; Pre; Processing; Processor; Stream

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APA (6^th Edition):

Dundas, J. D. (1998). Improving processor performance by dynamically pre-processing the instruction stream. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/130943

Chicago Manual of Style (16^th Edition):

Dundas, James David. “Improving processor performance by dynamically pre-processing the instruction stream.” 1998. Doctoral Dissertation, University of Michigan. Accessed February 28, 2021. http://hdl.handle.net/2027.42/130943.

MLA Handbook (7^th Edition):

Dundas, James David. “Improving processor performance by dynamically pre-processing the instruction stream.” 1998. Web. 28 Feb 2021.

Vancouver:

Dundas JD. Improving processor performance by dynamically pre-processing the instruction stream. [Internet] [Doctoral dissertation]. University of Michigan; 1998. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2027.42/130943.

Council of Science Editors:

Dundas JD. Improving processor performance by dynamically pre-processing the instruction stream. [Doctoral Dissertation]. University of Michigan; 1998. Available from: http://hdl.handle.net/2027.42/130943

McMaster University

25. Thaller, Wolfgang. Explicitly Staged Software Pipelining.

Degree: MSc, 2006, McMaster University

URL: http://hdl.handle.net/11375/20357

►

Software Pipelining is a method of instruction scheduling where loops are scheduled more efficiently by executing operations from more than one iteration of the… (more)

Subjects/Keywords: software pipelining; optimal software; pipeline schedule; computing

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APA (6^th Edition):

Thaller, W. (2006). Explicitly Staged Software Pipelining. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/20357

Chicago Manual of Style (16^th Edition):

Thaller, Wolfgang. “Explicitly Staged Software Pipelining.” 2006. Masters Thesis, McMaster University. Accessed February 28, 2021. http://hdl.handle.net/11375/20357.

MLA Handbook (7^th Edition):

Thaller, Wolfgang. “Explicitly Staged Software Pipelining.” 2006. Web. 28 Feb 2021.

Vancouver:

Thaller W. Explicitly Staged Software Pipelining. [Internet] [Masters thesis]. McMaster University; 2006. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11375/20357.

Council of Science Editors:

Thaller W. Explicitly Staged Software Pipelining. [Masters Thesis]. McMaster University; 2006. Available from: http://hdl.handle.net/11375/20357

North Carolina State University

26. Sudarsanam, Yasaswini. Implementation of Double Precision Floating Point Arithmetic.

Degree: MS, Computer Engineering, 2007, North Carolina State University

URL: http://www.lib.ncsu.edu/resolver/1840.16/862

► Floating Point Arithmetic is extensively used in the field of medical imaging, biometrics, motion capture and audio applications, including broadcast, conferencing, musical instruments and professional… (more)

Subjects/Keywords: IEEE 754 format; power analysis; pipelining; double precision

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APA (6^th Edition):

Sudarsanam, Y. (2007). Implementation of Double Precision Floating Point Arithmetic. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/862

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Sudarsanam, Yasaswini. “Implementation of Double Precision Floating Point Arithmetic.” 2007. Thesis, North Carolina State University. Accessed February 28, 2021. http://www.lib.ncsu.edu/resolver/1840.16/862.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Sudarsanam, Yasaswini. “Implementation of Double Precision Floating Point Arithmetic.” 2007. Web. 28 Feb 2021.

Vancouver:

Sudarsanam Y. Implementation of Double Precision Floating Point Arithmetic. [Internet] [Thesis]. North Carolina State University; 2007. [cited 2021 Feb 28]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/862.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sudarsanam Y. Implementation of Double Precision Floating Point Arithmetic. [Thesis]. North Carolina State University; 2007. Available from: http://www.lib.ncsu.edu/resolver/1840.16/862

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

North Carolina State University

27. Dalal, Ishita. An Efficient FPGA Implementation of the Discrete Wavelet Transform.

Degree: MS, Electrical Engineering, 2008, North Carolina State University

URL: http://www.lib.ncsu.edu/resolver/1840.16/1713

Subjects/Keywords: discrete wavelet transform; interleaving; pipelining; optimizations; polyphase; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Dalal, I. (2008). An Efficient FPGA Implementation of the Discrete Wavelet Transform. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Dalal, Ishita. “An Efficient FPGA Implementation of the Discrete Wavelet Transform.” 2008. Thesis, North Carolina State University. Accessed February 28, 2021. http://www.lib.ncsu.edu/resolver/1840.16/1713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Dalal, Ishita. “An Efficient FPGA Implementation of the Discrete Wavelet Transform.” 2008. Web. 28 Feb 2021.

Vancouver:

Dalal I. An Efficient FPGA Implementation of the Discrete Wavelet Transform. [Internet] [Thesis]. North Carolina State University; 2008. [cited 2021 Feb 28]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dalal I. An Efficient FPGA Implementation of the Discrete Wavelet Transform. [Thesis]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

North Carolina State University

28. Gupte, Ruchir. Interval Arithmetic Logic Unit for DSP and Control Applications.

Degree: MS, Electrical Engineering, 2006, North Carolina State University

URL: http://www.lib.ncsu.edu/resolver/1840.16/1225

► There are many applications in the field of digital signal processing (DSP) and controls that require the user to know how various numerical errors (uncertainty)… (more)

▼ There are many applications in the field of digital signal processing (DSP) and controls that require the user to know how various numerical errors (uncertainty) affect the result. Interval Arithmetic (IA) eliminates this uncertainty by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are needed. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. This thesis proposes a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equivalent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed efficiently. This design has two independent modules operating in parallel to calculate the lower bound and upper bound of the output interval. The functional unit of the ALU performs the basic fixed-point interval arithmetic operations of addition, subtraction, multiplication and the interval set operations of union and intersection. In addition, the ALU is optimized to perform dot products through the multiply-accumulate instruction. Division is not implemented on digital signal processors traditionally unless computed with a shift operation. In this design, division by shifting is implemented. One of the prime design goals is to maximize the throughput of the ALU for an optimum value of area. Pipelining is implemented to achieve this design goal. Power dissipation analysis of different ALU architectures is done. Since it required to obtain maximum throughput for the least power dissipation, throughput per unit power dissipation is used as the most critical performance metric. This thesis studies several architectures for the ALU and concludes with the one with the highest performance amongst the ones which are studied. Advisors/Committee Members: Dr. William W. Edmonson, Committee Chair (advisor), Dr. William Rhett Davis, Committee Member (advisor), Dr. Winser E. Alexander, Committee Member (advisor).

Subjects/Keywords: Pipelining; Signal Processing; Arithmetic Logic Unit; Interval Arithmetic

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APA (6^th Edition):

Gupte, R. (2006). Interval Arithmetic Logic Unit for DSP and Control Applications. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1225

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Gupte, Ruchir. “Interval Arithmetic Logic Unit for DSP and Control Applications.” 2006. Thesis, North Carolina State University. Accessed February 28, 2021. http://www.lib.ncsu.edu/resolver/1840.16/1225.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Gupte, Ruchir. “Interval Arithmetic Logic Unit for DSP and Control Applications.” 2006. Web. 28 Feb 2021.

Vancouver:

Gupte R. Interval Arithmetic Logic Unit for DSP and Control Applications. [Internet] [Thesis]. North Carolina State University; 2006. [cited 2021 Feb 28]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1225.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gupte R. Interval Arithmetic Logic Unit for DSP and Control Applications. [Thesis]. North Carolina State University; 2006. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1225

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Morvan, Antoine. Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model.

Degree: Docteur es, Informatique, 2013, Cachan, Ecole normale supérieure

URL: http://www.theses.fr/2013DENS0022

►

Grâce aux progrès réalisés dans le domaine des semi-conducteurs, les plateformes matérielles embarquées sont capables de satisfaire les contraintes de performances d'applications de plus en… (more)

▼

Grâce aux progrès réalisés dans le domaine des semi-conducteurs, les plateformes matérielles embarquées sont capables de satisfaire les contraintes de performances d'applications de plus en plus complexes. Cette augmentation conduit à une explosion des coûts de conception, ce qui pousse les concepteurs de ces plateformes à utiliser des outils travaillant à des niveaux d’abstraction plus élevés. Aujourd’hui, les outils de synthèse de haut niveau opèrent sur des descriptions C/C++ pour en générer des accélérateurs matériels spécialisés. Ces outils offrent des gains en productivité significatifs par rapport à la génération précédente, qui opérait sur des descriptions structurelles de l’architecture en VHDL ou Verilog. Ces descriptions algorithmiques doivent être retravaillées pour que les outils puissent générer des circuits performants. Pour faciliter cette tâche, une solution consiste à mettre en œuvre une boite à outils pour des transformations source-à-source orientées synthèse de haut niveau. En particulier, cette thèse s’intéresse aux transformations de boucles, avec pour objectif d’améliorer les performances en exposant des boucles parallèles et en améliorant la localité des accès mémoire. En nous appuyant sur une représentation des boucles dans le modèle polyédrique, nous proposons une approche qui améliore l’applicabilité du pipeline de nids de boucles en vérifiant sa légalité de manière plus précise que les approches existantes. De plus, lorsque la vérification échoue, nous proposons une technique de correction qui insère statiquement des états d’attente pour assurer la légalité du pipeline. Enfin, ce pipeline est mis en œuvre en utilisant une technique de génération de code qui met les nids de boucles à plat. Ces contributions ont été implémentées dans l’infrastructure de compilation source-à-source Gecos, avant d’être appliquées à un ensemble de benchmarks représentatifs des noyaux de calculs cibles de la synthèse de haut niveau. Les résultats montrent un gain en performances significatif, avec un surcoût en surface modéré.

Due to the advances in semiconductor technologies, embedded hardware is capable of satisfying the performance constraints of increasingly complex applications. This leads to a design cost explosion, thus pushing the hardware designers to use tools working with higher levels of abstractions. High-Level Synthesis tools generate custom hardware accelerators out of C/C++ specifications. They offer significant productivity gains compared to the previous generation of tools that worked at the level of hardware description languages, such as VHDL or Verilog. These higher level specifications have to be reworked in order for the High-Level Synthesis tools to generate efficient hardware accelerators. To ease this task, one solution is to provide a source-to-source transformation toolbox targeting High-Level Synthesis. Specifically, this thesis explores loop transformations in order to improve performance by exposing parallel loops and improving the locality of memory accesses. Using polyhedral…

Advisors/Committee Members: Quinton, Patrice (thesis director).

Subjects/Keywords: Synthèse de haut niveau; Pipeline de nid de boucles; High level synthesis; Loop pipelining; Optimizing compilation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Morvan, A. (2013). Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model. (Doctoral Dissertation). Cachan, Ecole normale supérieure. Retrieved from http://www.theses.fr/2013DENS0022

Chicago Manual of Style (16^th Edition):

Morvan, Antoine. “Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model.” 2013. Doctoral Dissertation, Cachan, Ecole normale supérieure. Accessed February 28, 2021. http://www.theses.fr/2013DENS0022.

MLA Handbook (7^th Edition):

Morvan, Antoine. “Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model.” 2013. Web. 28 Feb 2021.

Vancouver:

Morvan A. Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model. [Internet] [Doctoral dissertation]. Cachan, Ecole normale supérieure; 2013. [cited 2021 Feb 28]. Available from: http://www.theses.fr/2013DENS0022.

Council of Science Editors:

Morvan A. Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées : Synthesis of pipelined architectures using the polyhedral model. [Doctoral Dissertation]. Cachan, Ecole normale supérieure; 2013. Available from: http://www.theses.fr/2013DENS0022

Université Paris-Sud – Paris XI

30. Fellahi, Mohammed. Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining.

Degree: Docteur es, Informatique, 2011, Université Paris-Sud – Paris XI

URL: http://www.theses.fr/2011PA112046

►

Les applications de flux de données sont des cibles importantes de l’optimisation de programme en raison de leur haute exigence de calcul et la diversité… (more)

▼

Les applications de flux de données sont des cibles importantes de l’optimisation de programme en raison de leur haute exigence de calcul et la diversité de leurs domaines d’application: communication, systèmes embarqués, multimédia, etc. L’un des problèmes les plus importants et difficiles dans la conception des langages de programmation destinés à ce genre d’applications est comment les ordonnancer à grain fin à fin d’exploiter les ressources disponibles de la machine.Dans cette thèse on propose un "framework" pour l’ordonnancement à grain fin des applications de flux de données et des boucles imbriquées en général. Premièrement on essaye de paralléliser le nombre maximum de boucles en appliquant le pipeline logiciel. Après on merge le prologue et l’épilogue de chaque boucle (phase) parallélisée pour éviter l’augmentation de la taille du code. Ce processus est un pipeline multidimensionnel, quelques occurrences (ou instructions) sont décalées par des iterations de la boucle interne et d’autres occurrences (instructions) par des iterationsde la boucle externe. Les expériences montrent que l’application de cette technique permet l’amélioration des performances, extraction du parallélisme sans augmenter la taille du code, à la fois dans le cas des applications de flux des donnée et des boucles imbriquées en général.

Applications based on streams, ordered sequences of data values, are important targets of program optimization because of their high computational requirements and the diversity of their application domains: communication, embedded systems, multimedia, etc. One of the most important and difficult problems in special purpose stream language design and implementation is how to schedule these applications in a fine-grain way to exploit available machine resources In this thesis we propose a framework for fine-grain scheduling of streaming applications and nested loops in general. First, we try to pipeline steady state phases (inner loops), by finding the repeated kernel pattern, and executing actor occurrences in parallel as much as possible. Then we merge the kernel prolog and epilog of pipelined phases to move them out of the outer loop. Merging the kernel prolog and epilog means that we shift acotor occurrences, or instructions, from one phase iteration to another and from one outer loop iteration to another, a multidimensional shifting. Experimental shows that our framwork can imporove perfomance, prallelism extraction without increasing the code size, in streaming applications and nested loops in general.

Advisors/Committee Members: Cohen, Albert Henri (thesis director).

Subjects/Keywords: Applications de flux de données; Boucles imbriquées; Pipeline logiciel; Ordonnancement multidimentionnel; Streaming applications; Nested loops; Multidimensional scheduling; Software Pipelining

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APA (6^th Edition):

Fellahi, M. (2011). Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2011PA112046

Chicago Manual of Style (16^th Edition):

Fellahi, Mohammed. “Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining.” 2011. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed February 28, 2021. http://www.theses.fr/2011PA112046.

MLA Handbook (7^th Edition):

Fellahi, Mohammed. “Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining.” 2011. Web. 28 Feb 2021.

Vancouver:

Fellahi M. Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2011. [cited 2021 Feb 28]. Available from: http://www.theses.fr/2011PA112046.

Council of Science Editors:

Fellahi M. Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel : From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2011. Available from: http://www.theses.fr/2011PA112046

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Open Access Theses and Dissertations