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You searched for subject:(Pipelined). Showing records 1 – 30 of 82 total matches.

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1. Rao, P Prasada. Studies on Design and Implementation of 10-Bit, 50 Ms/Sec Pipelined Analog to Digital Converter; -.

Degree: Electrical and communication engineering, 2013, Jawaharlal Nehru Technological University, Hyderabad

All electrical signals in nature are analog and since most of the signal processing is done in the digital domain, Analog to Digital (ADC) and… (more)

Subjects/Keywords: Analog; Design; Digital; Pipelined; Studies

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rao, P. P. (2013). Studies on Design and Implementation of 10-Bit, 50 Ms/Sec Pipelined Analog to Digital Converter; -. (Thesis). Jawaharlal Nehru Technological University, Hyderabad. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/19321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rao, P Prasada. “Studies on Design and Implementation of 10-Bit, 50 Ms/Sec Pipelined Analog to Digital Converter; -.” 2013. Thesis, Jawaharlal Nehru Technological University, Hyderabad. Accessed October 30, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/19321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rao, P Prasada. “Studies on Design and Implementation of 10-Bit, 50 Ms/Sec Pipelined Analog to Digital Converter; -.” 2013. Web. 30 Oct 2020.

Vancouver:

Rao PP. Studies on Design and Implementation of 10-Bit, 50 Ms/Sec Pipelined Analog to Digital Converter; -. [Internet] [Thesis]. Jawaharlal Nehru Technological University, Hyderabad; 2013. [cited 2020 Oct 30]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/19321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rao PP. Studies on Design and Implementation of 10-Bit, 50 Ms/Sec Pipelined Analog to Digital Converter; -. [Thesis]. Jawaharlal Nehru Technological University, Hyderabad; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/19321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

2. Gulati, Paridhi. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.

Degree: MSin Engineering, Electrical and Computer Engineering, 2016, University of Texas – Austin

 A pipelined ADC is generally used for high speeds and high resolutions in applications where latency is not a major concern. This project involves the… (more)

Subjects/Keywords: Pipelined ADC; SAR ADC

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APA (6th Edition):

Gulati, P. (2016). A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65964

Chicago Manual of Style (16th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Masters Thesis, University of Texas – Austin. Accessed October 30, 2020. http://hdl.handle.net/2152/65964.

MLA Handbook (7th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Web. 30 Oct 2020.

Vancouver:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Internet] [Masters thesis]. University of Texas – Austin; 2016. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/2152/65964.

Council of Science Editors:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Masters Thesis]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/65964

3. 小松, 直樹. ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture.

Degree: 2012, Hosei University / 法政大学

 A novel background calibration technique for capacitor mismatches is proposed in this paper. The capacitor mismatch is one of the non-ideal factors in the pipelined(more)

Subjects/Keywords: Capacitor mismatch; Digital Calibration; NSDEM; Pipelined ADC

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APA (6th Edition):

小松, . (2012). ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture. (Thesis). Hosei University / 法政大学. Retrieved from http://hdl.handle.net/10114/7619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

小松, 直樹. “ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture.” 2012. Thesis, Hosei University / 法政大学. Accessed October 30, 2020. http://hdl.handle.net/10114/7619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

小松, 直樹. “ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture.” 2012. Web. 30 Oct 2020.

Vancouver:

小松 . ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture. [Internet] [Thesis]. Hosei University / 法政大学; 2012. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/10114/7619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

小松 . ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture. [Thesis]. Hosei University / 法政大学; 2012. Available from: http://hdl.handle.net/10114/7619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

4. Fung, Sheung Wai. Low power pipelined ADC with non-linear calibration.

Degree: 2010, Hong Kong University of Science and Technology

Pipelined analog-to-digital converter (ADC) design is popular for high speed data conversion (10-100 MS/s) with medium-to-high resolution (8-14bits). Moreover, low power pipelined ADC is important… (more)

Subjects/Keywords: Pipelined ADCs  – Calibration

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APA (6th Edition):

Fung, S. W. (2010). Low power pipelined ADC with non-linear calibration. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-6958 ; https://doi.org/10.14711/thesis-b1114797 ; http://repository.ust.hk/ir/bitstream/1783.1-6958/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fung, Sheung Wai. “Low power pipelined ADC with non-linear calibration.” 2010. Thesis, Hong Kong University of Science and Technology. Accessed October 30, 2020. http://repository.ust.hk/ir/Record/1783.1-6958 ; https://doi.org/10.14711/thesis-b1114797 ; http://repository.ust.hk/ir/bitstream/1783.1-6958/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fung, Sheung Wai. “Low power pipelined ADC with non-linear calibration.” 2010. Web. 30 Oct 2020.

Vancouver:

Fung SW. Low power pipelined ADC with non-linear calibration. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2010. [cited 2020 Oct 30]. Available from: http://repository.ust.hk/ir/Record/1783.1-6958 ; https://doi.org/10.14711/thesis-b1114797 ; http://repository.ust.hk/ir/bitstream/1783.1-6958/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fung SW. Low power pipelined ADC with non-linear calibration. [Thesis]. Hong Kong University of Science and Technology; 2010. Available from: http://repository.ust.hk/ir/Record/1783.1-6958 ; https://doi.org/10.14711/thesis-b1114797 ; http://repository.ust.hk/ir/bitstream/1783.1-6958/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Chen, Bang-Cyuan. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 A high speed and low power Pipelined-SAR ADC is proposed in this thesis. The Flash ADC which is often found in traditional Pipelined ADC is… (more)

Subjects/Keywords: SAR; ADC; Low Power; Pipelined-SAR ADC; Pipelined; Analog-to-Digital Converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, B. (2013). A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Bang-Cyuan. “A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.” 2013. Thesis, NSYSU. Accessed October 30, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Bang-Cyuan. “A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.” 2013. Web. 30 Oct 2020.

Vancouver:

Chen B. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Oct 30]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen B. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McMaster University

6. Chen, Jing. A Pipelined, Single Precision Floating-Point Logarithm Computation Unit in Hardware.

Degree: MSc, 2012, McMaster University

This thesis is funded by the IBM Center for Advanced Studies

A large number of scientific applications rely on the computing of logarithm.… (more)

Subjects/Keywords: logarithm computation unit; look-up table based approximation; parabolic interpolation; pipelined adder; pipelined multiplier; pipelined ROM; Digital Circuits; Numerical Analysis and Scientific Computing; Digital Circuits

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APA (6th Edition):

Chen, J. (2012). A Pipelined, Single Precision Floating-Point Logarithm Computation Unit in Hardware. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/12364

Chicago Manual of Style (16th Edition):

Chen, Jing. “A Pipelined, Single Precision Floating-Point Logarithm Computation Unit in Hardware.” 2012. Masters Thesis, McMaster University. Accessed October 30, 2020. http://hdl.handle.net/11375/12364.

MLA Handbook (7th Edition):

Chen, Jing. “A Pipelined, Single Precision Floating-Point Logarithm Computation Unit in Hardware.” 2012. Web. 30 Oct 2020.

Vancouver:

Chen J. A Pipelined, Single Precision Floating-Point Logarithm Computation Unit in Hardware. [Internet] [Masters thesis]. McMaster University; 2012. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/11375/12364.

Council of Science Editors:

Chen J. A Pipelined, Single Precision Floating-Point Logarithm Computation Unit in Hardware. [Masters Thesis]. McMaster University; 2012. Available from: http://hdl.handle.net/11375/12364


Wright State University

7. Sampath, Sowrirajan. FPGA based Hardware Implementation of Advanced Encryption Standard.

Degree: MSEgr, Electrical Engineering, 2007, Wright State University

 Sampath, Sowrirajan. M.S.E., Department of Electrical Engineering, Wright State University, 2007 FPGA based Hardware Implementation of Advanced Encryption Standard On October, 2, 2000, The National… (more)

Subjects/Keywords: AES; Basic iterative; Key Expansion; ENCRYPTION; sub pipelined; stage sub pipelined; pipelined

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APA (6th Edition):

Sampath, S. (2007). FPGA based Hardware Implementation of Advanced Encryption Standard. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1189835736

Chicago Manual of Style (16th Edition):

Sampath, Sowrirajan. “FPGA based Hardware Implementation of Advanced Encryption Standard.” 2007. Masters Thesis, Wright State University. Accessed October 30, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189835736.

MLA Handbook (7th Edition):

Sampath, Sowrirajan. “FPGA based Hardware Implementation of Advanced Encryption Standard.” 2007. Web. 30 Oct 2020.

Vancouver:

Sampath S. FPGA based Hardware Implementation of Advanced Encryption Standard. [Internet] [Masters thesis]. Wright State University; 2007. [cited 2020 Oct 30]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1189835736.

Council of Science Editors:

Sampath S. FPGA based Hardware Implementation of Advanced Encryption Standard. [Masters Thesis]. Wright State University; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1189835736


NSYSU

8. Chuang, Yuan-chih. Design of Low-Power Pipelined Multipliers with Various Output Precision.

Degree: Master, Computer Science and Engineering, 2006, NSYSU

 With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, multipliers are always… (more)

Subjects/Keywords: pipelined; generator; low-power; multiplier

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APA (6th Edition):

Chuang, Y. (2006). Design of Low-Power Pipelined Multipliers with Various Output Precision. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721106-143851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chuang, Yuan-chih. “Design of Low-Power Pipelined Multipliers with Various Output Precision.” 2006. Thesis, NSYSU. Accessed October 30, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721106-143851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chuang, Yuan-chih. “Design of Low-Power Pipelined Multipliers with Various Output Precision.” 2006. Web. 30 Oct 2020.

Vancouver:

Chuang Y. Design of Low-Power Pipelined Multipliers with Various Output Precision. [Internet] [Thesis]. NSYSU; 2006. [cited 2020 Oct 30]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721106-143851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chuang Y. Design of Low-Power Pipelined Multipliers with Various Output Precision. [Thesis]. NSYSU; 2006. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721106-143851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Shang, Yao-Yung. Pipelined Forwarding with Energy Balance in Cluster-based Wireless Sensor Networks.

Degree: Master, Electrical Engineering, 2011, NSYSU

 Wireless Sensor Network (WSN) is composed of sink and sensors. Sensors transmit data to sink through wireless network after collecting data. Because multi-hop routing and… (more)

Subjects/Keywords: Pipelined forwarding; WSN; Energy balance; Mobile sink; Cluster-based

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APA (6th Edition):

Shang, Y. (2011). Pipelined Forwarding with Energy Balance in Cluster-based Wireless Sensor Networks. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816111-152900

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shang, Yao-Yung. “Pipelined Forwarding with Energy Balance in Cluster-based Wireless Sensor Networks.” 2011. Thesis, NSYSU. Accessed October 30, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816111-152900.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shang, Yao-Yung. “Pipelined Forwarding with Energy Balance in Cluster-based Wireless Sensor Networks.” 2011. Web. 30 Oct 2020.

Vancouver:

Shang Y. Pipelined Forwarding with Energy Balance in Cluster-based Wireless Sensor Networks. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Oct 30]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816111-152900.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shang Y. Pipelined Forwarding with Energy Balance in Cluster-based Wireless Sensor Networks. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816111-152900

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

10. Gregoire, B. Robert. Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps.

Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University

 This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution… (more)

Subjects/Keywords: Correlated Level Shifting; Pipelined ADCs  – Noise  – Mathematical models

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APA (6th Edition):

Gregoire, B. R. (2008). Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/9948

Chicago Manual of Style (16th Edition):

Gregoire, B Robert. “Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps.” 2008. Doctoral Dissertation, Oregon State University. Accessed October 30, 2020. http://hdl.handle.net/1957/9948.

MLA Handbook (7th Edition):

Gregoire, B Robert. “Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps.” 2008. Web. 30 Oct 2020.

Vancouver:

Gregoire BR. Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/1957/9948.

Council of Science Editors:

Gregoire BR. Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/9948


Oregon State University

11. Gubbins, David Patrick. Continuous time input pipeline ADCs.

Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University

 Analog-to-digital converters (ADCs) convert analog continuous time signals into discrete time, digital format. One precondition that must be met for conventional nyquist rate ADCs is… (more)

Subjects/Keywords: analog; Pipelined ADCs  – Design and construction  – Mathematical models

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APA (6th Edition):

Gubbins, D. P. (2008). Continuous time input pipeline ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/10160

Chicago Manual of Style (16th Edition):

Gubbins, David Patrick. “Continuous time input pipeline ADCs.” 2008. Doctoral Dissertation, Oregon State University. Accessed October 30, 2020. http://hdl.handle.net/1957/10160.

MLA Handbook (7th Edition):

Gubbins, David Patrick. “Continuous time input pipeline ADCs.” 2008. Web. 30 Oct 2020.

Vancouver:

Gubbins DP. Continuous time input pipeline ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/1957/10160.

Council of Science Editors:

Gubbins DP. Continuous time input pipeline ADCs. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/10160


Oregon State University

12. Lingam, Naga Sasidhar. Low power design techniques for high speed pipelined ADCs.

Degree: PhD, Electrical and Computer Engineering, 2009, Oregon State University

 Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is… (more)

Subjects/Keywords: ADC; Pipelined ADCs  – Design and construction  – Mathematical models

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lingam, N. S. (2009). Low power design techniques for high speed pipelined ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/10294

Chicago Manual of Style (16th Edition):

Lingam, Naga Sasidhar. “Low power design techniques for high speed pipelined ADCs.” 2009. Doctoral Dissertation, Oregon State University. Accessed October 30, 2020. http://hdl.handle.net/1957/10294.

MLA Handbook (7th Edition):

Lingam, Naga Sasidhar. “Low power design techniques for high speed pipelined ADCs.” 2009. Web. 30 Oct 2020.

Vancouver:

Lingam NS. Low power design techniques for high speed pipelined ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2009. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/1957/10294.

Council of Science Editors:

Lingam NS. Low power design techniques for high speed pipelined ADCs. [Doctoral Dissertation]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/10294


Rochester Institute of Technology

13. Marsaw, Nicholas J. UVM Verification of a Floating Point Multiplier.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  Increased design complexity has resulted in the need for efficient verification. The verification process is crucial for discovering and fixing bugs prior to fabrication… (more)

Subjects/Keywords: UVM; Verification; Layering protocols; Pipeline; Pipelined architecture; Testing

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APA (6th Edition):

Marsaw, N. J. (2019). UVM Verification of a Floating Point Multiplier. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10327

Chicago Manual of Style (16th Edition):

Marsaw, Nicholas J. “UVM Verification of a Floating Point Multiplier.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed October 30, 2020. https://scholarworks.rit.edu/theses/10327.

MLA Handbook (7th Edition):

Marsaw, Nicholas J. “UVM Verification of a Floating Point Multiplier.” 2019. Web. 30 Oct 2020.

Vancouver:

Marsaw NJ. UVM Verification of a Floating Point Multiplier. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Oct 30]. Available from: https://scholarworks.rit.edu/theses/10327.

Council of Science Editors:

Marsaw NJ. UVM Verification of a Floating Point Multiplier. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10327


Anna University

14. Gummadi, Sudhakar. A study of multicore processor performance for network applications; -.

Degree: Information and Communication Engineering, 2014, Anna University

Multicore processors have become the new approach for increase newlinein the performance of the processor based systems General purpose multicore newlineprocessors that are also multithreaded… (more)

Subjects/Keywords: Information and Communication engineering; multicore processor; pipelined processes

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APA (6th Edition):

Gummadi, S. (2014). A study of multicore processor performance for network applications; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/24727

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gummadi, Sudhakar. “A study of multicore processor performance for network applications; -.” 2014. Thesis, Anna University. Accessed October 30, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/24727.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gummadi, Sudhakar. “A study of multicore processor performance for network applications; -.” 2014. Web. 30 Oct 2020.

Vancouver:

Gummadi S. A study of multicore processor performance for network applications; -. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Oct 30]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24727.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gummadi S. A study of multicore processor performance for network applications; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24727

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

15. Chan, Kai Yin. A digital nonlinear background calibration for pipeline analog-to-digital converters.

Degree: 2010, Hong Kong University of Science and Technology

Pipelined ADCs are widely used in portable devices because of its fast speed and medium resolution. In a pipelined ADC, capacitor mismatch and finite amplifier… (more)

Subjects/Keywords: Pipelined ADCs  – Calibration ; Calibration

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APA (6th Edition):

Chan, K. Y. (2010). A digital nonlinear background calibration for pipeline analog-to-digital converters. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-6963 ; https://doi.org/10.14711/thesis-b1115035 ; http://repository.ust.hk/ir/bitstream/1783.1-6963/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chan, Kai Yin. “A digital nonlinear background calibration for pipeline analog-to-digital converters.” 2010. Thesis, Hong Kong University of Science and Technology. Accessed October 30, 2020. http://repository.ust.hk/ir/Record/1783.1-6963 ; https://doi.org/10.14711/thesis-b1115035 ; http://repository.ust.hk/ir/bitstream/1783.1-6963/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chan, Kai Yin. “A digital nonlinear background calibration for pipeline analog-to-digital converters.” 2010. Web. 30 Oct 2020.

Vancouver:

Chan KY. A digital nonlinear background calibration for pipeline analog-to-digital converters. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2010. [cited 2020 Oct 30]. Available from: http://repository.ust.hk/ir/Record/1783.1-6963 ; https://doi.org/10.14711/thesis-b1115035 ; http://repository.ust.hk/ir/bitstream/1783.1-6963/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chan KY. A digital nonlinear background calibration for pipeline analog-to-digital converters. [Thesis]. Hong Kong University of Science and Technology; 2010. Available from: http://repository.ust.hk/ir/Record/1783.1-6963 ; https://doi.org/10.14711/thesis-b1115035 ; http://repository.ust.hk/ir/bitstream/1783.1-6963/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Washington

16. Shin, Soonkyun. A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter.

Degree: PhD, 2014, University of Washington

 In this dissertation, techniques with zero-crossing based circuits (ZCBC) to achieve high speed and high resolution in scaled technologies with very low intrinsic gain are… (more)

Subjects/Keywords: 55nm; ADC; CMOS; Pipelined; ZCBC; Electrical engineering; electrical engineering

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APA (6th Edition):

Shin, S. (2014). A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter. (Doctoral Dissertation). University of Washington. Retrieved from http://hdl.handle.net/1773/27154

Chicago Manual of Style (16th Edition):

Shin, Soonkyun. “A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter.” 2014. Doctoral Dissertation, University of Washington. Accessed October 30, 2020. http://hdl.handle.net/1773/27154.

MLA Handbook (7th Edition):

Shin, Soonkyun. “A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter.” 2014. Web. 30 Oct 2020.

Vancouver:

Shin S. A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter. [Internet] [Doctoral dissertation]. University of Washington; 2014. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/1773/27154.

Council of Science Editors:

Shin S. A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter. [Doctoral Dissertation]. University of Washington; 2014. Available from: http://hdl.handle.net/1773/27154


Brno University of Technology

17. Kledrowetz, Vilém. Vliv rozlišení MDAC na bloky řetězového převodníku AD: The influence of MDAC resolution on basic blocks of pipelined AD converter.

Degree: 2018, Brno University of Technology

 This work deals with the influence of MDAC (multiplying DAC) resolution on basic blocks of pipelined AD converter. The MDAC was designed with 1,5 and… (more)

Subjects/Keywords: řetězový převodník AD; MDAC; rozlišení; pipelined ADC; MDAC; resolution

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APA (6th Edition):

Kledrowetz, V. (2018). Vliv rozlišení MDAC na bloky řetězového převodníku AD: The influence of MDAC resolution on basic blocks of pipelined AD converter. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/9586

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kledrowetz, Vilém. “Vliv rozlišení MDAC na bloky řetězového převodníku AD: The influence of MDAC resolution on basic blocks of pipelined AD converter.” 2018. Thesis, Brno University of Technology. Accessed October 30, 2020. http://hdl.handle.net/11012/9586.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kledrowetz, Vilém. “Vliv rozlišení MDAC na bloky řetězového převodníku AD: The influence of MDAC resolution on basic blocks of pipelined AD converter.” 2018. Web. 30 Oct 2020.

Vancouver:

Kledrowetz V. Vliv rozlišení MDAC na bloky řetězového převodníku AD: The influence of MDAC resolution on basic blocks of pipelined AD converter. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/11012/9586.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kledrowetz V. Vliv rozlišení MDAC na bloky řetězového převodníku AD: The influence of MDAC resolution on basic blocks of pipelined AD converter. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/9586

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ohio University

18. Chen, Chao-Wu. Design and NMOS implementation of parallel pipelined multiplier.

Degree: MS, Electrical Engineering & Computer Science (Engineering and Technology), 1988, Ohio University

Subjects/Keywords: NMOS; Parallel Pipelined Multiplier

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APA (6th Edition):

Chen, C. (1988). Design and NMOS implementation of parallel pipelined multiplier. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1182779741

Chicago Manual of Style (16th Edition):

Chen, Chao-Wu. “Design and NMOS implementation of parallel pipelined multiplier.” 1988. Masters Thesis, Ohio University. Accessed October 30, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1182779741.

MLA Handbook (7th Edition):

Chen, Chao-Wu. “Design and NMOS implementation of parallel pipelined multiplier.” 1988. Web. 30 Oct 2020.

Vancouver:

Chen C. Design and NMOS implementation of parallel pipelined multiplier. [Internet] [Masters thesis]. Ohio University; 1988. [cited 2020 Oct 30]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1182779741.

Council of Science Editors:

Chen C. Design and NMOS implementation of parallel pipelined multiplier. [Masters Thesis]. Ohio University; 1988. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1182779741


Princeton University

19. Fix, Jordan Samuel. HARDWARE MULTITHREADED TRANSACTIONS: ENABLING SPECULATIVE MULTITHREADED PIPELINE PARALLELIZATION FOR COMPLEX PROGRAMS .

Degree: PhD, 2020, Princeton University

 Speculation with transactional memory systems helps programmers and compilers produce profitable thread-level parallel programs. Prior work shows that supporting transactions that can span multiple threads,… (more)

Subjects/Keywords: hardware transactional memory; multithreaded transactions; pipelined parallelism; thread-level speculation

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APA (6th Edition):

Fix, J. S. (2020). HARDWARE MULTITHREADED TRANSACTIONS: ENABLING SPECULATIVE MULTITHREADED PIPELINE PARALLELIZATION FOR COMPLEX PROGRAMS . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp018k71nm05g

Chicago Manual of Style (16th Edition):

Fix, Jordan Samuel. “HARDWARE MULTITHREADED TRANSACTIONS: ENABLING SPECULATIVE MULTITHREADED PIPELINE PARALLELIZATION FOR COMPLEX PROGRAMS .” 2020. Doctoral Dissertation, Princeton University. Accessed October 30, 2020. http://arks.princeton.edu/ark:/88435/dsp018k71nm05g.

MLA Handbook (7th Edition):

Fix, Jordan Samuel. “HARDWARE MULTITHREADED TRANSACTIONS: ENABLING SPECULATIVE MULTITHREADED PIPELINE PARALLELIZATION FOR COMPLEX PROGRAMS .” 2020. Web. 30 Oct 2020.

Vancouver:

Fix JS. HARDWARE MULTITHREADED TRANSACTIONS: ENABLING SPECULATIVE MULTITHREADED PIPELINE PARALLELIZATION FOR COMPLEX PROGRAMS . [Internet] [Doctoral dissertation]. Princeton University; 2020. [cited 2020 Oct 30]. Available from: http://arks.princeton.edu/ark:/88435/dsp018k71nm05g.

Council of Science Editors:

Fix JS. HARDWARE MULTITHREADED TRANSACTIONS: ENABLING SPECULATIVE MULTITHREADED PIPELINE PARALLELIZATION FOR COMPLEX PROGRAMS . [Doctoral Dissertation]. Princeton University; 2020. Available from: http://arks.princeton.edu/ark:/88435/dsp018k71nm05g


NSYSU

20. Lee, Kuan-Hui. An Efficient Pipelined Architecture for the Multi-precision Texture Unit.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 As technology advances and the fully developed technology for 3-D graphics processing units, it has been widely applied in wearable devices. For wearable devices, the… (more)

Subjects/Keywords: multi-precision; pipelined architecture; texture unit; low-power design; 3-D graphics processing unit

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APA (6th Edition):

Lee, K. (2016). An Efficient Pipelined Architecture for the Multi-precision Texture Unit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710116-140815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Kuan-Hui. “An Efficient Pipelined Architecture for the Multi-precision Texture Unit.” 2016. Thesis, NSYSU. Accessed October 30, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710116-140815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Kuan-Hui. “An Efficient Pipelined Architecture for the Multi-precision Texture Unit.” 2016. Web. 30 Oct 2020.

Vancouver:

Lee K. An Efficient Pipelined Architecture for the Multi-precision Texture Unit. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Oct 30]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710116-140815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee K. An Efficient Pipelined Architecture for the Multi-precision Texture Unit. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710116-140815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Liao, Yen-Qun. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 In this thesis, the circuits are designing with TSMC.18μm CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100MS/s and… (more)

Subjects/Keywords: Symmetry Bootstrap-switch; Dynamic comparator; Switched-Opamp; Successive Approximation ADC; Pipelined ADC

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APA (6th Edition):

Liao, Y. (2013). High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Yen-Qun. “High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.” 2013. Thesis, NSYSU. Accessed October 30, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Yen-Qun. “High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.” 2013. Web. 30 Oct 2020.

Vancouver:

Liao Y. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Oct 30]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao Y. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Chen , Hsin-cheng. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 A high speed and low power Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter is proposed in this thesis. Using only two stage in the proposed ADC… (more)

Subjects/Keywords: Successive Approximation ADC; Error correction; Dynamic comparator; Pipelined ADC; Additional comparator for MSB

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APA (6th Edition):

Chen , H. (2015). Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen , Hsin-cheng. “Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.” 2015. Thesis, NSYSU. Accessed October 30, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen , Hsin-cheng. “Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.” 2015. Web. 30 Oct 2020.

Vancouver:

Chen H. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Oct 30]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Pedrino, Emerson Carlos. Arquitetura pipeline reconfigurável através de instruções geradas por programação genética para processamento morfológico de imagens digitais utilizando FPGAs.

Degree: PhD, Engenharia Elétrica, 2008, University of São Paulo

A morfologia matemática fornece ferramentas poderosas para a realização de análise de imagens em baixo nível e tem encontrado aplicações em diversas áreas, tais como:… (more)

Subjects/Keywords: Arquitetura pipeline; FPGAs; FPGAs; Genetic programming; Mathematical morphology; Morfologia matemática; Pipelined architecture; Programação genética

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APA (6th Edition):

Pedrino, E. C. (2008). Arquitetura pipeline reconfigurável através de instruções geradas por programação genética para processamento morfológico de imagens digitais utilizando FPGAs. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/18/18133/tde-17032009-151610/ ;

Chicago Manual of Style (16th Edition):

Pedrino, Emerson Carlos. “Arquitetura pipeline reconfigurável através de instruções geradas por programação genética para processamento morfológico de imagens digitais utilizando FPGAs.” 2008. Doctoral Dissertation, University of São Paulo. Accessed October 30, 2020. http://www.teses.usp.br/teses/disponiveis/18/18133/tde-17032009-151610/ ;.

MLA Handbook (7th Edition):

Pedrino, Emerson Carlos. “Arquitetura pipeline reconfigurável através de instruções geradas por programação genética para processamento morfológico de imagens digitais utilizando FPGAs.” 2008. Web. 30 Oct 2020.

Vancouver:

Pedrino EC. Arquitetura pipeline reconfigurável através de instruções geradas por programação genética para processamento morfológico de imagens digitais utilizando FPGAs. [Internet] [Doctoral dissertation]. University of São Paulo; 2008. [cited 2020 Oct 30]. Available from: http://www.teses.usp.br/teses/disponiveis/18/18133/tde-17032009-151610/ ;.

Council of Science Editors:

Pedrino EC. Arquitetura pipeline reconfigurável através de instruções geradas por programação genética para processamento morfológico de imagens digitais utilizando FPGAs. [Doctoral Dissertation]. University of São Paulo; 2008. Available from: http://www.teses.usp.br/teses/disponiveis/18/18133/tde-17032009-151610/ ;


Oregon State University

24. Carnes, Joshua Kenneth. Low voltage techniques for pipelined analog-to-digital converters.

Degree: MS, Electrical and Computer Engineering, 2007, Oregon State University

 To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the… (more)

Subjects/Keywords: ADC; Pipelined ADCs  – Design and construction

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APA (6th Edition):

Carnes, J. K. (2007). Low voltage techniques for pipelined analog-to-digital converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/4026

Chicago Manual of Style (16th Edition):

Carnes, Joshua Kenneth. “Low voltage techniques for pipelined analog-to-digital converters.” 2007. Masters Thesis, Oregon State University. Accessed October 30, 2020. http://hdl.handle.net/1957/4026.

MLA Handbook (7th Edition):

Carnes, Joshua Kenneth. “Low voltage techniques for pipelined analog-to-digital converters.” 2007. Web. 30 Oct 2020.

Vancouver:

Carnes JK. Low voltage techniques for pipelined analog-to-digital converters. [Internet] [Masters thesis]. Oregon State University; 2007. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/1957/4026.

Council of Science Editors:

Carnes JK. Low voltage techniques for pipelined analog-to-digital converters. [Masters Thesis]. Oregon State University; 2007. Available from: http://hdl.handle.net/1957/4026


University of New South Wales

25. Javaid, Haris. Design methodologies for pipelined MPSoCs targeting multimedia applications.

Degree: Computer Science & Engineering, 2009, University of New South Wales

 The semiconductor industry has seen a paradigm shift from Application Specific Integrated Circuits to Multiprocessor System on Chip systems over the last decade, primarily due… (more)

Subjects/Keywords: Streaming Applications; Design Automation; Pipelined MPSoCs

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APA (6th Edition):

Javaid, H. (2009). Design methodologies for pipelined MPSoCs targeting multimedia applications. (Masters Thesis). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/44597 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:7894/SOURCE1?view=true

Chicago Manual of Style (16th Edition):

Javaid, Haris. “Design methodologies for pipelined MPSoCs targeting multimedia applications.” 2009. Masters Thesis, University of New South Wales. Accessed October 30, 2020. http://handle.unsw.edu.au/1959.4/44597 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:7894/SOURCE1?view=true.

MLA Handbook (7th Edition):

Javaid, Haris. “Design methodologies for pipelined MPSoCs targeting multimedia applications.” 2009. Web. 30 Oct 2020.

Vancouver:

Javaid H. Design methodologies for pipelined MPSoCs targeting multimedia applications. [Internet] [Masters thesis]. University of New South Wales; 2009. [cited 2020 Oct 30]. Available from: http://handle.unsw.edu.au/1959.4/44597 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:7894/SOURCE1?view=true.

Council of Science Editors:

Javaid H. Design methodologies for pipelined MPSoCs targeting multimedia applications. [Masters Thesis]. University of New South Wales; 2009. Available from: http://handle.unsw.edu.au/1959.4/44597 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:7894/SOURCE1?view=true


NSYSU

26. Yang, Chih-yu. Implementation of Pipeline Floating-Point CORDIC Processor and its Error Analysis and Applications.

Degree: Master, Computer Science and Engineering, 2007, NSYSU

 In this thesis, the traditional fixed-point CORDIC algorithm is extended to floating-point version in order to calculate transcendental functions (such as sine/cosine, logarithm, powering function,… (more)

Subjects/Keywords: error analysis; 3D; CORDIC; floating-point; pipelined

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APA (6th Edition):

Yang, C. (2007). Implementation of Pipeline Floating-Point CORDIC Processor and its Error Analysis and Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0819107-224652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Chih-yu. “Implementation of Pipeline Floating-Point CORDIC Processor and its Error Analysis and Applications.” 2007. Thesis, NSYSU. Accessed October 30, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0819107-224652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Chih-yu. “Implementation of Pipeline Floating-Point CORDIC Processor and its Error Analysis and Applications.” 2007. Web. 30 Oct 2020.

Vancouver:

Yang C. Implementation of Pipeline Floating-Point CORDIC Processor and its Error Analysis and Applications. [Internet] [Thesis]. NSYSU; 2007. [cited 2020 Oct 30]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0819107-224652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang C. Implementation of Pipeline Floating-Point CORDIC Processor and its Error Analysis and Applications. [Thesis]. NSYSU; 2007. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0819107-224652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

27. Liang, shish-chang. Design and Implementation of Reconfigurable Low-Power Pipelined Booth Multiplier.

Degree: Master, Computer Science and Engineering, 2007, NSYSU

 With the portable computing devices and wireless communication systems are popularly used, the power consumption became one of the major targets of VLSI design. However,… (more)

Subjects/Keywords: truncated multiplier; multiplier; reconfigurable; pipelined; low-power

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liang, s. (2007). Design and Implementation of Reconfigurable Low-Power Pipelined Booth Multiplier. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822107-173322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liang, shish-chang. “Design and Implementation of Reconfigurable Low-Power Pipelined Booth Multiplier.” 2007. Thesis, NSYSU. Accessed October 30, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822107-173322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liang, shish-chang. “Design and Implementation of Reconfigurable Low-Power Pipelined Booth Multiplier.” 2007. Web. 30 Oct 2020.

Vancouver:

Liang s. Design and Implementation of Reconfigurable Low-Power Pipelined Booth Multiplier. [Internet] [Thesis]. NSYSU; 2007. [cited 2020 Oct 30]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822107-173322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liang s. Design and Implementation of Reconfigurable Low-Power Pipelined Booth Multiplier. [Thesis]. NSYSU; 2007. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822107-173322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

28. Ardalan, Shahab. A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter.

Degree: 2002, Ryerson University

 A 1.2 V, 8 bit, 100 MSample/Sec Pipeline Analog-to-Digital Converter is designed in 0.18-μm standard CMOS technology. An emphasis was placed on observing the low… (more)

Subjects/Keywords: Analog-to-digital converters; Pipelined ADCs; Electronic circuit design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ardalan, S. (2002). A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A616

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ardalan, Shahab. “A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter.” 2002. Thesis, Ryerson University. Accessed October 30, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A616.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ardalan, Shahab. “A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter.” 2002. Web. 30 Oct 2020.

Vancouver:

Ardalan S. A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter. [Internet] [Thesis]. Ryerson University; 2002. [cited 2020 Oct 30]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A616.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ardalan S. A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter. [Thesis]. Ryerson University; 2002. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A616

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

29. Golden, Michael Leonard. Reducing the penalty of branch and load hazards in pipelined microprocessors.

Degree: PhD, Computer science, 1995, University of Michigan

Pipelined microprocessors allow the simultaneous execution of several machine instructions at a time, increasing the total throughput of instructions. Because an instruction being executed by… (more)

Subjects/Keywords: Branch Instructions; Hazards; Load; Microprocessors; Penalty; Pipelined; Reducing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Golden, M. L. (1995). Reducing the penalty of branch and load hazards in pipelined microprocessors. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/129692

Chicago Manual of Style (16th Edition):

Golden, Michael Leonard. “Reducing the penalty of branch and load hazards in pipelined microprocessors.” 1995. Doctoral Dissertation, University of Michigan. Accessed October 30, 2020. http://hdl.handle.net/2027.42/129692.

MLA Handbook (7th Edition):

Golden, Michael Leonard. “Reducing the penalty of branch and load hazards in pipelined microprocessors.” 1995. Web. 30 Oct 2020.

Vancouver:

Golden ML. Reducing the penalty of branch and load hazards in pipelined microprocessors. [Internet] [Doctoral dissertation]. University of Michigan; 1995. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/2027.42/129692.

Council of Science Editors:

Golden ML. Reducing the penalty of branch and load hazards in pipelined microprocessors. [Doctoral Dissertation]. University of Michigan; 1995. Available from: http://hdl.handle.net/2027.42/129692


Oregon State University

30. Lee, Ho-Young. Power-efficient two-step pipelined analog-to-digital conversion.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance… (more)

Subjects/Keywords: ADC; Pipelined ADCs  – Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, H. (2011). Power-efficient two-step pipelined analog-to-digital conversion. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/26075

Chicago Manual of Style (16th Edition):

Lee, Ho-Young. “Power-efficient two-step pipelined analog-to-digital conversion.” 2011. Doctoral Dissertation, Oregon State University. Accessed October 30, 2020. http://hdl.handle.net/1957/26075.

MLA Handbook (7th Edition):

Lee, Ho-Young. “Power-efficient two-step pipelined analog-to-digital conversion.” 2011. Web. 30 Oct 2020.

Vancouver:

Lee H. Power-efficient two-step pipelined analog-to-digital conversion. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2020 Oct 30]. Available from: http://hdl.handle.net/1957/26075.

Council of Science Editors:

Lee H. Power-efficient two-step pipelined analog-to-digital conversion. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/26075

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