subject:(Phase Frequency Detector)

Wright State University

1. Suraparaju, Eswar Raju. Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology.

Degree: MSEE, Electrical Engineering, 2015, Wright State University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990

► This thesis presents wide tuning range in-phase and quad-phase (I/Q) output digital control oscillator (DCO) and voltage control oscillator (VCO) and a simple high performance… (more)

Subjects/Keywords: Electrical Engineering; In-phase and Quad-phase , Digital control oscillator , Voltage control oscillator , dead-zone, Phase Frequency Detector

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APA (6^th Edition):

Suraparaju, E. R. (2015). Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990

Chicago Manual of Style (16^th Edition):

Suraparaju, Eswar Raju. “Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology.” 2015. Masters Thesis, Wright State University. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990.

MLA Handbook (7^th Edition):

Suraparaju, Eswar Raju. “Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology.” 2015. Web. 20 Jan 2021.

Vancouver:

Suraparaju ER. Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology. [Internet] [Masters thesis]. Wright State University; 2015. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990.

Council of Science Editors:

Suraparaju ER. Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology. [Masters Thesis]. Wright State University; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990

Brno University of Technology

2. Florián, Antonín. Synchronizované zdroje časových signálů: Synchronized sources of clock signals.

Degree: 2018, Brno University of Technology

URL: http://hdl.handle.net/11012/25847

► This thesis deals with design of synchronized sources of time signal. The first part of the thesis deals with the theory the crystal resonators, crystal… (more)

Subjects/Keywords: Krystalový rezonátor; krystalový oscilátor; frekvenční stabilita; fázový závěs; fázový detektor.; Crystal resonator; crystal oscillator; frequency stability; phase locked loop; phase detector.

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APA (6^th Edition):

Florián, A. (2018). Synchronizované zdroje časových signálů: Synchronized sources of clock signals. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/25847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Florián, Antonín. “Synchronizované zdroje časových signálů: Synchronized sources of clock signals.” 2018. Thesis, Brno University of Technology. Accessed January 20, 2021. http://hdl.handle.net/11012/25847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Florián, Antonín. “Synchronizované zdroje časových signálů: Synchronized sources of clock signals.” 2018. Web. 20 Jan 2021.

Vancouver:

Florián A. Synchronizované zdroje časových signálů: Synchronized sources of clock signals. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/11012/25847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Florián A. Synchronizované zdroje časových signálů: Synchronized sources of clock signals. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/25847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arkansas

3. Joshi, Phaniraj. Design of an 866 MHz On-chip Frequency Synthesizer.

Degree: MSEE, 2011, University of Arkansas

URL: https://scholarworks.uark.edu/etd/143

► There is a strong need for stable frequency references with large tuning ranges in today's communication systems. While the crystal oscillators assure good frequency… (more)

Subjects/Keywords: Communication and the arts; Applied sciences; Charge pump; Closed loop; Frequency synthesizer; Phase locked loop; Pll; Tristate phase frequency detector; Electrical and Electronics

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APA (6^th Edition):

Joshi, P. (2011). Design of an 866 MHz On-chip Frequency Synthesizer. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/143

Chicago Manual of Style (16^th Edition):

Joshi, Phaniraj. “Design of an 866 MHz On-chip Frequency Synthesizer.” 2011. Masters Thesis, University of Arkansas. Accessed January 20, 2021. https://scholarworks.uark.edu/etd/143.

MLA Handbook (7^th Edition):

Joshi, Phaniraj. “Design of an 866 MHz On-chip Frequency Synthesizer.” 2011. Web. 20 Jan 2021.

Vancouver:

Joshi P. Design of an 866 MHz On-chip Frequency Synthesizer. [Internet] [Masters thesis]. University of Arkansas; 2011. [cited 2021 Jan 20]. Available from: https://scholarworks.uark.edu/etd/143.

Council of Science Editors:

Joshi P. Design of an 866 MHz On-chip Frequency Synthesizer. [Masters Thesis]. University of Arkansas; 2011. Available from: https://scholarworks.uark.edu/etd/143

NSYSU

4. Juan, Sung-lin. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614

► This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power; digitally controlled oscillator; successive approximation register; digital frequency detector; all digital phase-locked loop

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APA (6^th Edition):

Juan, S. (2015). Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Juan, Sung-lin. “Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.” 2015. Thesis, NSYSU. Accessed January 20, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Juan, Sung-lin. “Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.” 2015. Web. 20 Jan 2021.

Vancouver:

Juan S. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Jan 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Juan S. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

5. Xie, Shan-yang. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

► This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power schmitt trigger inverter; digitally controlled oscillator; all digital phase-locked loop; digital frequency detector; successive approximation register

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Xie, S. (2018). Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Thesis, NSYSU. Accessed January 20, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Web. 20 Jan 2021.

Vancouver:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Jan 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of California – Irvine

6. Sedighzadeh Yazdi, Siavash. A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS.

Degree: Electrical and Computer Engineering, 2017, University of California – Irvine

URL: http://www.escholarship.org/uc/item/3k36t3tv

► Frequency-domain diffuse optical imaging (fd-DOI) systems require accurate phase and amplitude measurement of the modulating signal for precise calculation of optical properties of a medium.… (more)

Subjects/Keywords: Electrical engineering; Biomedical engineering; Medical imaging; CMOS; Diffuse Optical Imaging; frequency domain; Near infrared; n-path; phase detector

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Sedighzadeh Yazdi, S. (2017). A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/3k36t3tv

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Sedighzadeh Yazdi, Siavash. “A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS.” 2017. Thesis, University of California – Irvine. Accessed January 20, 2021. http://www.escholarship.org/uc/item/3k36t3tv.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Sedighzadeh Yazdi, Siavash. “A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS.” 2017. Web. 20 Jan 2021.

Vancouver:

Sedighzadeh Yazdi S. A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS. [Internet] [Thesis]. University of California – Irvine; 2017. [cited 2021 Jan 20]. Available from: http://www.escholarship.org/uc/item/3k36t3tv.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sedighzadeh Yazdi S. A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS. [Thesis]. University of California – Irvine; 2017. Available from: http://www.escholarship.org/uc/item/3k36t3tv

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toronto

7. Samarah, Amer. Improved Phase Detection for Digital Phase-locked Loops.

Degree: PhD, 2016, University of Toronto

URL: http://hdl.handle.net/1807/78796

►

Digital PLLs (DPLLs) have emerged as reliable alternatives to analog PLLs since they are more robust in the presence of process variations and mismatch and… (more)

▼

Digital PLLs (DPLLs) have emerged as reliable alternatives to analog PLLs since they are more robust in the presence of process variations and mismatch and do not need a large on-chip capacitor to realize a loop ﬁlter. However, a DPLL employs a time to-digital converter (TDC) to resolve the phase error in quantized steps which shows up as deterministic jitter in the output clock. Similarly, a DPLL tunes a digitally controlled-oscillator (DCO) in discrete frequency steps which adds an extra source of jitter. Furthermore, the quantized response of the DPLL may cause chaotic limit cycles in some conﬁgurations. This thesis presents innovations to make DPLLs suitable for a wide range of applications. First, a novel low-power TDC with 4 ps resolution, approximately an order of magnitude better than an inverter delay in the 0.13 µm CMOS technology, is enabled by employing a highly digital coarse-ﬁne TDC with a calibrated coarse stage followed by a ﬁne stochastic stage. On power-up, on-chip calibration algorithm based on a balanced mean code density test is used to minimize nonlinearities in the coarse TDC, reducing worst-case spurs from -54.4 dBc to -70.55 dBc at 1.995 GHz operation. The thesis also investigates dead-zone behavior in DPLLs caused by the quantization eﬀect of the TDC. It results in chaotic limit cycle behavior; producing higher than expected in-band phase noise and strong spurious tones. To alleviate this problem, a noise-shaped oﬀset is added to the phase error to keep the TDC active and away from the dead-zone. The proposed solution is demonstrated in a 0.13 µm CMOS prototype achieving consistent low in-band noise. A binary bang-bang phase detector (BBPD) is a commonly used alternative to the power hungry TDC. However, BBPD based DPLLs have limited frequency pull-in and capture range that are traded oﬀ for steady-state jitter performance. The thesis proposes an alternative to BBPD by using a multi-phase bang-bang detector (MPBBD). Also, the thesis presents a rigorous mathematical analysis of the cycle slipping behavior to quantify the pull-in and capture range as well as the locking time for DPLL with either BBPD or MPBBD. The ﬁnal formula gives a useful insight into the eﬀect of various loop parameters on the cycle slipping behavior. A DPLL architecture with a MPBBD is presented and implemented in 28 nm CMOS technology to improve the pull-in and capture range while not aﬀecting the steady-state jitter performance.

2017-10-17 00:00:00

Advisors/Committee Members: Chan Carusone, Anthony, Electrical and Computer Engineering.

Subjects/Keywords: bang bang phase locked loop; dead zone of phase detector; Digital phase locked loop; frequency synthesizer; modulator dithering; time to digital converter; 0544

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APA (6^th Edition):

Samarah, A. (2016). Improved Phase Detection for Digital Phase-locked Loops. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/78796

Chicago Manual of Style (16^th Edition):

Samarah, Amer. “Improved Phase Detection for Digital Phase-locked Loops.” 2016. Doctoral Dissertation, University of Toronto. Accessed January 20, 2021. http://hdl.handle.net/1807/78796.

MLA Handbook (7^th Edition):

Samarah, Amer. “Improved Phase Detection for Digital Phase-locked Loops.” 2016. Web. 20 Jan 2021.

Vancouver:

Samarah A. Improved Phase Detection for Digital Phase-locked Loops. [Internet] [Doctoral dissertation]. University of Toronto; 2016. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1807/78796.

Council of Science Editors:

Samarah A. Improved Phase Detection for Digital Phase-locked Loops. [Doctoral Dissertation]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/78796

8. Ahola, Rami. Integrated Radio Frequency Synthesizers for Wireless Applications.

Degree: 2005, Helsinki University of Technology

URL: http://lib.tkk.fi/Diss/2005/isbn9512275635/

►

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in… (more)

Subjects/Keywords: analog integrated circuit; frequency synthesizer; phase-locked loop; CMOS; BiCMOS; wireless communication; radio transceiver; prescaler; phase detector; chargepump; integer-N; fractional-N

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APA (6^th Edition):

Ahola, R. (2005). Integrated Radio Frequency Synthesizers for Wireless Applications. (Thesis). Helsinki University of Technology. Retrieved from http://lib.tkk.fi/Diss/2005/isbn9512275635/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ahola, Rami. “Integrated Radio Frequency Synthesizers for Wireless Applications.” 2005. Thesis, Helsinki University of Technology. Accessed January 20, 2021. http://lib.tkk.fi/Diss/2005/isbn9512275635/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ahola, Rami. “Integrated Radio Frequency Synthesizers for Wireless Applications.” 2005. Web. 20 Jan 2021.

Vancouver:

Ahola R. Integrated Radio Frequency Synthesizers for Wireless Applications. [Internet] [Thesis]. Helsinki University of Technology; 2005. [cited 2021 Jan 20]. Available from: http://lib.tkk.fi/Diss/2005/isbn9512275635/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahola R. Integrated Radio Frequency Synthesizers for Wireless Applications. [Thesis]. Helsinki University of Technology; 2005. Available from: http://lib.tkk.fi/Diss/2005/isbn9512275635/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Anna University

9. Sujatha, V. Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -.

Degree: Information and Communication Engineering, 2014, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/24464

►

In a Phase Locked Loop PLL the Charge Pump CP circuit is newlineone of the key elements It receives Up and Down signals from the… (more)

Subjects/Keywords: Channel Metal Oxide Semiconductors; Charge Pump Phase Locked Loop; Complementary Metal Oxide Semiconductors; Gain Boosting Charge Pump; High output impedance; High Performance charge pump phase; Information and Communication engineering; Phase Frequency Detector; Phase Locked Loop; Voltage controlled oscillator

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APA (6^th Edition):

Sujatha, V. (2014). Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/24464

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Sujatha, V. “Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -.” 2014. Thesis, Anna University. Accessed January 20, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/24464.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Sujatha, V. “Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -.” 2014. Web. 20 Jan 2021.

Vancouver:

Sujatha V. Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -. [Internet] [Thesis]. Anna University; 2014. [cited 2021 Jan 20]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24464.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sujatha V. Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24464

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

10. Raghavendra, R G. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.

Degree: MSc Engg, Faculty of Engineering, 2011, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/1006

► Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture… (more)

▼ Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero determining capacitance (CZ). A low loop bandwidth CPPLL has a higher CZ value, and hence consumes a larger die area than a large loop bandwidth CPPLL. Literature survey shows that the problem of higher CZ value in low loop bandwidth CPPLL is addressed by using some form of emulation techniques. A relatively simpler emulation technique is the use of dual charge pump based loop filter. Existing dual charge pump based loop filter consume extra elements (such as summer that need opamps to realize the summer function) for achieving low CZ value. These extra elements consume extra area and additional power. We present two types of Summer-Less Dual Charge Pump (SDCP) based loop filter designs that do not need extra elements and still achieves low CZ value and this is achieved by using a second charge pump in an appropriate way. A test chip was implemented in 0.13µm UMC MMRFCMOS process to verify the presented circuits. The presented SDCP based loop filter circuits are particularly useful in designs employing multiple CPPLL’s and design employing low loop bandwidth CPPLL’s. Another challenge worth-mentioning is the frequency ranges over which the PLL can be locked. The Voltage Controlled Oscillator (VCO) of PLL mainly determines the frequency locking range of a PLL. A typical VCO has a frequency locking range of usually 1:2 to 1:3. The VCO frequency tuning range reduces with reduction in supply voltage. This poses a serious problem in low supply voltage applications that demand a wide frequency locking range, sometimes greater than 1:3. We have addressed this problem of wide PLL lock range, by using an Analog Frequency Detector. A wide frequency lock range is achieved, either by dynamically modifying the VCO or the feedback divider of PLL. Both the approaches are equally feasible. The frequency detector is used for dynamically modifying the VCO or the feedback divider of PLL. Two test chips were implemented to verify the presented Analog Frequency Detector scheme. A testchip implemented in 0.25µm CSM analog process achieves wide frequency lock range by dynamically modifying the feedback divider of PLL. Another testchip implemented in 0.13µm UMC MMRFCMOS process achieves wide frequency lock range by dynamically modifying the center frequency of the VCO. Presented analog frequency detection scheme is particularly useful in applications that demand wide PLL lock range from a single die. Advisors/Committee Members: Amrutur, Bharadwaj (advisor).

Subjects/Keywords: Special Devices (Computer Engineering); Analog Frequency Detector; Charge Pump Phase Locked Loop; Phase Locked Loop (PLL); Phase Locked Loop Filters; Phase Locked Loop Filter Design; Summer-Less Dual Charge Pump Based Loop Filters; Loop Filter Design; Computer Engineering

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APA (6^th Edition):

Raghavendra, R. G. (2011). Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/1006

Chicago Manual of Style (16^th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2011. Masters Thesis, Indian Institute of Science. Accessed January 20, 2021. http://etd.iisc.ac.in/handle/2005/1006.

MLA Handbook (7^th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2011. Web. 20 Jan 2021.

Vancouver:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Internet] [Masters thesis]. Indian Institute of Science; 2011. [cited 2021 Jan 20]. Available from: http://etd.iisc.ac.in/handle/2005/1006.

Council of Science Editors:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Masters Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ac.in/handle/2005/1006

Texas A&M University

11. Cheng, Shanfeng. Design of CMOS integrated phase-locked loops for multi-gigabits serial data links.

Degree: PhD, Electrical Engineering, 2007, Texas A&M University

URL: http://hdl.handle.net/1969.1/4954

► High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication… (more)

▼ High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 ÃÂ¼m CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 ÃÂ¼m CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 ÃÂ¼m CMOS technology. Advisors/Committee Members: Silva-Martinez, Jose (advisor), Karsilayan, Aydin Ilker (committee member), Li, Peng (committee member), Soriaga, Manuel P. (committee member).

Subjects/Keywords: Phase-locked Loops; PLL; Clock and Data Recovery; CDR; Jitter; Phase Noise; VCO; Charge Pump; Phase Detector; Frequency Detector; Voltage-Controlled Oscillator

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APA (6^th Edition):

Cheng, S. (2007). Design of CMOS integrated phase-locked loops for multi-gigabits serial data links. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/4954

Chicago Manual of Style (16^th Edition):

Cheng, Shanfeng. “Design of CMOS integrated phase-locked loops for multi-gigabits serial data links.” 2007. Doctoral Dissertation, Texas A&M University. Accessed January 20, 2021. http://hdl.handle.net/1969.1/4954.

MLA Handbook (7^th Edition):

Cheng, Shanfeng. “Design of CMOS integrated phase-locked loops for multi-gigabits serial data links.” 2007. Web. 20 Jan 2021.

Vancouver:

Cheng S. Design of CMOS integrated phase-locked loops for multi-gigabits serial data links. [Internet] [Doctoral dissertation]. Texas A&M University; 2007. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1969.1/4954.

Council of Science Editors:

Cheng S. Design of CMOS integrated phase-locked loops for multi-gigabits serial data links. [Doctoral Dissertation]. Texas A&M University; 2007. Available from: http://hdl.handle.net/1969.1/4954

University of Illinois – Urbana-Champaign

12. Elkholy, Ahmed Mostafa Mohamed Attia. Digital enhancement techniques for fractional-N frequency synthesizers.

Degree: PhD, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/95573

► Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing… (more)

▼ Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing the data traffic generated by trillions of such nodes also puts severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and clocking modules by exploring design techniques at both the architectural and circuit levels. In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1ps resolution. Fabricated in 65nm CMOS process, the prototype PLL achieves better than -106dBc/Hz in-band noise and 3MHz PLL bandwidth at 4.5GHz output frequency using 50MHz reference. The PLL achieves excellent jitter performance of 490fsrms, while consumes only 3.7mW. This translates to the best reported jitter-power figure-of-merit (FoM) of -240.5dB among previously reported FNPLLs. Phase noise performance of ring oscillator based digital FNPLLs is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the TDC, ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their FoM that quantifies the power-jitter tradeoff is at least 25dB worse than their LC-oscillator based FNPLL counterparts. In the second part of this thesis, we seek to close this performance gap by extending PLL bandwidth using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. A prototype was implemented in a 65nm CMOS process operating over a wide frequency range of 2.0GHz-5.5GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9psrms integrated jitter while consuming only 4mW at 5GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference and its FoM is -228.5dB, which is at about 20dB better than previously reported ring-based digital FNPLLs. In the third part, we propose a new multi-output clock generator architecture using open loop fractional dividers for system-on-chip (SoC) platforms. Modern multi-core processors use per core clocking, where each core runs at its own speed. The core frequency can be changed… Advisors/Committee Members: Hanumolu, Pavan K (advisor), Hanumolu, Pavan K (Committee Chair), Rosenbaum, Elyse (committee member), Viswanath, Pramod (committee member), Pilawa-Podgurski, Robert (committee member).

Subjects/Keywords: Phase-locked loops (PLLs); digital PLL; All-digital phase locked loop (ADPLL); fractional-N; Fractional divider, frequency synthesizer; Wide bandwidth; Bang-bang phase detector (BBPD); Digital-to-time converter (DTC); Least-mean square (LMS); Time-to-digtial converter (TDC); Time amplifier; Jitter; Digitally controlled oscillator (DCO); Frequency multiplier; Frequency tracking; Impulse sensitivity function (ISF); Injection locking; Multiplying injection-locked oscillator (MILO); Phase domain response (PDR); Phase noise; Pulse; Reference spur; Root mean square (rms) jitter; Sub-harmonic locking; Sub-sampling (SS)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Elkholy, A. M. M. A. (2016). Digital enhancement techniques for fractional-N frequency synthesizers. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95573

Chicago Manual of Style (16^th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 20, 2021. http://hdl.handle.net/2142/95573.

MLA Handbook (7^th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Web. 20 Jan 2021.

Vancouver:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2142/95573.

Council of Science Editors:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95573

University of Cincinnati

13. VIJAY, VIKAS. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.

Degree: MS, Engineering : Computer Engineering, 2004, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

► This thesis presents automated techniques for synthesis of high performance RF circuits. The top-down methodology developed encompasses all stages of RF design from circuit sizing,… (more)

Subjects/Keywords: Radio Frequency; Synthesis; Optimization; Automation; Layout Generation; RF; Analog; High Frequency; Module Generation; C++; SKILL; Extraction; Performance Analysis; Circuit Sizing; Radio Receiver; LNA; Mixer; VCO; Phase Frequency Detector

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APA (6^th Edition):

VIJAY, V. (2004). A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

Chicago Manual of Style (16^th Edition):

VIJAY, VIKAS. “A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.” 2004. Masters Thesis, University of Cincinnati. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

MLA Handbook (7^th Edition):

VIJAY, VIKAS. “A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.” 2004. Web. 20 Jan 2021.

Vancouver:

VIJAY V. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2004. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

Council of Science Editors:

VIJAY V. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. [Masters Thesis]. University of Cincinnati; 2004. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

Queens University

14. Carr, John. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .

Degree: Electrical and Computer Engineering, 2009, Queens University

URL: http://hdl.handle.net/1974/1796

► This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use… (more)

▼ This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails.

Subjects/Keywords: phase-locked loop ; frequency multiplier ; CMOS ; integrated circuit ; voltage controlled oscillator ; injection locked frequency divider ; phase detector ; phase noise ; Accumulation MOS varactor ; monolithic integration ; static phase offset ; common mode rejection ; 26 GHz ; master-slave flip-flop divider ; direct injection ; differential ; phase plane

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APA (6^th Edition):

Carr, J. (2009). A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/1796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Carr, John. “A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .” 2009. Thesis, Queens University. Accessed January 20, 2021. http://hdl.handle.net/1974/1796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Carr, John. “A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .” 2009. Web. 20 Jan 2021.

Vancouver:

Carr J. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . [Internet] [Thesis]. Queens University; 2009. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1974/1796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carr J. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . [Thesis]. Queens University; 2009. Available from: http://hdl.handle.net/1974/1796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Mishra, Satyabh. Design of charge pump phase locked loop.

Degree: 2012, Texas Tech University

URL: http://hdl.handle.net/2346/46975

► Phase Locked Loop system is around since 1932. The versatility of PLL systems and where it can apply makes it very useful. It can be… (more)

Subjects/Keywords: Phase locked loop; Pump frequency detector (PFD); Charge pump; Low pass filter; Voltage-controlled oscillator (VCO); Ring oscillator; Frequency divider; Current mode logic; Lock time

…Phase Frequency Detector 2. Loop Filter (low pass) 3. Voltage Controlled Oscillator… …Phase Detector (PD) part to become Phase Frequency Detector (PFD). In this… …having a Phase Frequency Detector instead of Phase Detector, a Charge Pump, and a divide by N… …CHAPTER II PHASE FREQUENCY DETECTOR A Phase Frequency Detector (PFD) is typically an… …level. This basic form of Phase Detector is not capable to detect large frequency differences…

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APA (6^th Edition):

Mishra, S. (2012). Design of charge pump phase locked loop. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/46975

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Mishra, Satyabh. “Design of charge pump phase locked loop.” 2012. Thesis, Texas Tech University. Accessed January 20, 2021. http://hdl.handle.net/2346/46975.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Mishra, Satyabh. “Design of charge pump phase locked loop.” 2012. Web. 20 Jan 2021.

Vancouver:

Mishra S. Design of charge pump phase locked loop. [Internet] [Thesis]. Texas Tech University; 2012. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2346/46975.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mishra S. Design of charge pump phase locked loop. [Thesis]. Texas Tech University; 2012. Available from: http://hdl.handle.net/2346/46975

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

16. Balssubramanian, Suresh. Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models.

Degree: MSc Engg, Faculty of Engineering, 2011, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/1127

Subjects/Keywords: Computer Aided Design; Integrated Circuits; Phased Locked Loop; Phased Locked Loop Design - Behavioral Models; PLL Design; Digital Signal Processing (DSP); Application Specific Integrated Circuits (ASIC); Phase Frequency Detector (PFD); Voltage Controlled Oscillators (VCO); Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Balssubramanian, S. (2011). Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/1127

Chicago Manual of Style (16^th Edition):

Balssubramanian, Suresh. “Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models.” 2011. Masters Thesis, Indian Institute of Science. Accessed January 20, 2021. http://etd.iisc.ac.in/handle/2005/1127.

MLA Handbook (7^th Edition):

Balssubramanian, Suresh. “Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models.” 2011. Web. 20 Jan 2021.

Vancouver:

Balssubramanian S. Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models. [Internet] [Masters thesis]. Indian Institute of Science; 2011. [cited 2021 Jan 20]. Available from: http://etd.iisc.ac.in/handle/2005/1127.

Council of Science Editors:

Balssubramanian S. Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models. [Masters Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ac.in/handle/2005/1127

17. Laha, Soumyasanta. Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs.

Degree: PhD, Electrical Engineering & Computer Science (Engineering and Technology), 2015, Ohio University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974

► Today's nanochips contain billions of transistors on a single die that integrates whole electronic systems as opposed to sub-system parts. Together with ever higher frequency… (more)

Subjects/Keywords: Electrical Engineering; Radio Frequency Integrated Circuit Design; Wireless Communication; Double Gate MOSFET; 60 GHz; OOK Modulation and Demodulation; Oscillator; Power Amplifier; Low Noise Amplifier; RF Mixer; Phase Frequency Detector; 65 nm RF CMOS TRx Design

…Phase Frequency Detector 5.3.1 DG-MOSFET NOR Gate . . . . . 5.3.2 Charge Pump PFD… …Ampliﬁers • RF Mixers • OOK Demodulator/Envelope Detectors • Charge Pump Phase Frequency Detector… …bias optimization technique for DG-MOSFET RF Mixer. Charge Pump Phase Frequency Detector… …receivers. It also reports the research on DG-MOSFET Charge Pump Phase Frequency detector which is… …2.5.1.2 Phase Shift Keying . . . . . . . . . . . . . . 2.5.1.3 Orthogonal Frequency Division…

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APA (6^th Edition):

Laha, S. (2015). Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs. (Doctoral Dissertation). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974

Chicago Manual of Style (16^th Edition):

Laha, Soumyasanta. “Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs.” 2015. Doctoral Dissertation, Ohio University. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974.

MLA Handbook (7^th Edition):

Laha, Soumyasanta. “Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs.” 2015. Web. 20 Jan 2021.

Vancouver:

Laha S. Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs. [Internet] [Doctoral dissertation]. Ohio University; 2015. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974.

Council of Science Editors:

Laha S. Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs. [Doctoral Dissertation]. Ohio University; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974

Queensland University of Technology

18. Hussain, Zahir M. Adaptive instantaneous frequency estimation: Techniques and algorithms.

Degree: 2002, Queensland University of Technology

URL: https://eprints.qut.edu.au/36137/

► This thesis deals with the problem of the instantaneous frequency (IF) estimation of sinusoidal signals. This topic plays significant role in signal processing and communications.… (more)

▼ This thesis deals with the problem of the instantaneous frequency (IF) estimation of sinusoidal signals. This topic plays significant role in signal processing and communications. Depending on the type of the signal, two major approaches are considered. For IF estimation of single-tone or digitally-modulated sinusoidal signals (like frequency shift keying signals) the approach of digital phase-locked loops (DPLLs) is considered, and this is Part-I of this thesis. For FM signals the approach of time-frequency analysis is considered, and this is Part-II of the thesis. In part-I we have utilized sinusoidal DPLLs with non-uniform sampling scheme as this type is widely used in communication systems. The digital tanlock loop (DTL) has introduced significant advantages over other existing DPLLs. In the last 10 years many efforts have been made to improve DTL performance. However, this loop and all of its modifications utilizes Hilbert transformer (HT) to produce a signal-independent 90-degree phase-shifted version of the input signal. Hilbert transformer can be realized approximately using a finite impulse response (FIR) digital filter. This realization introduces further complexity in the loop in addition to approximations and frequency limitations on the input signal. We have tried to avoid practical difficulties associated with the conventional tanlock scheme while keeping its advantages. A time-delay is utilized in the tanlock scheme of DTL to produce a signal-dependent phase shift. This gave rise to the time-delay digital tanlock loop (TDTL). Fixed point theorems are used to analyze the behavior of the new loop. As such TDTL combines the two major approaches in DPLLs: the non-linear approach of sinusoidal DPLL based on fixed point analysis, and the linear tanlock approach based on the arctan phase detection. TDTL preserves the main advantages of the DTL despite its reduced structure. An application of TDTL in FSK demodulation is also considered. This idea of replacing HT by a time-delay may be of interest in other signal processing systems. Hence we have analyzed and compared the behaviors of the HT and the time-delay in the presence of additive Gaussian noise. Based on the above analysis, the behavior of the first and second-order TDTLs has been analyzed in additive Gaussian noise. Since DPLLs need time for locking, they are normally not efficient in tracking the continuously changing frequencies of non-stationary signals, i.e. signals with time-varying spectra. Nonstationary signals are of importance in synthetic and real life applications. An example is the frequency-modulated (FM) signals widely used in communication systems. Part-II of this thesis is dedicated for the IF estimation of non-stationary signals. For such signals the classical spectral techniques break down, due to the time-varying nature of their spectra, and more advanced techniques should be utilized. For the purpose of instantaneous frequency estimation of non-stationary signals there are two major approaches: parametric and…

Subjects/Keywords: Signal processing; Time series analysis; Frequency spectra; instantaneous frequency; stationary signals; non-stationary signals; communication systems; multicomponent signals; frequency modulated (FM) signals; frequency shift keying (FSK) signals; sinusoidal signals; analytic signals; digital phase-locked loops; Hilbert transform; time-delay; phase shifter; difference equation; sinusoidal digital phase locked loops; digital tanlock loop; tanlock; lock range; independent locking; digital filters; nonuniform sampling; additive Gaussian noise; signal-to-noise-ratio (SNR); locking speed; phase error detector; Cramer-Rao bounds; time-frequency analysis; ambiguity function; time-frequency distribution (TFD); the quadratic class; resolution; cross-terms; Fourier transform; estimation; amplitude estimation; instantaneous frequency estimation; mean square error; simulation; algorithms; adaptive algorithms; adaptive estimation; bias; variance; asymptotic analysis; thesis; doctoral

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APA (6^th Edition):

Hussain, Z. M. (2002). Adaptive instantaneous frequency estimation: Techniques and algorithms. (Thesis). Queensland University of Technology. Retrieved from https://eprints.qut.edu.au/36137/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hussain, Zahir M. “Adaptive instantaneous frequency estimation: Techniques and algorithms.” 2002. Thesis, Queensland University of Technology. Accessed January 20, 2021. https://eprints.qut.edu.au/36137/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hussain, Zahir M. “Adaptive instantaneous frequency estimation: Techniques and algorithms.” 2002. Web. 20 Jan 2021.

Vancouver:

Hussain ZM. Adaptive instantaneous frequency estimation: Techniques and algorithms. [Internet] [Thesis]. Queensland University of Technology; 2002. [cited 2021 Jan 20]. Available from: https://eprints.qut.edu.au/36137/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hussain ZM. Adaptive instantaneous frequency estimation: Techniques and algorithms. [Thesis]. Queensland University of Technology; 2002. Available from: https://eprints.qut.edu.au/36137/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Ellinger, John David. Multi-Carrier Radar for Target Detection and Communications.

Degree: PhD, Electrical Engineering, 2016, Wright State University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=wright1463839176

► This dissertation considers the optimization of radar performance within the structure imposed by a coded Orthogonal Frequency Division Multiplexing (OFDM) format required to achieve an… (more)

▼ This dissertation considers the optimization of radar performance within the structure imposed by a coded Orthogonal Frequency Division Multiplexing (OFDM) format required to achieve an acceptable communication link. The dual goal of achieving both satisfactory radar and communication performance raises challenges that can be substantively addressed by combining phase coding and modulation techniques to provide the temporal and spectral structure necessary to implement simultaneous radar and communication operations.In particular, the specific techniques, as introduced within this dissertation, of using the Multi-Frequency Complementary Phase Coded (MCPC) sequences, as prescribed by Levanon and Mozeson, for simultaneous radar and wireless communication operations represent a novel contribution and offers a significant improvement in the study, implementation, and performance of dual use radar and communication waveforms and signal processing techniques. Specific contributions of this dissertation include: 1) as will be demonstrated, not all valid MCPC sequences can be used for data transmission, and, therefore, a subset of MCPC sequences are chosen with consideration to radar detection performance, 2) communication operation is improved through the introduction of an algorithm that enables Gray codes to be applied to MCPC sequences, 3) the orthogonality of MCPC sequences is exploited to overcome the effects of multipath fading and intercarrier interference, 4) a new detector type, termed the Beta detector, is developed for both communications operations and radar detection, 5) a radar detection method, termed Polar Signal Detection, is developed that combines the Beta detector with a traditional matched filter detector to achieve superior detection performance as compared to traditional Cell-Averaging Constant False Alarm Rate (CA-CFAR) detectors in multi-target environments, and 6) a novel method of measuring Doppler frequencies is introduced that is superior to the measurement performance of traditional radar systems. Advisors/Committee Members: Wu, Zhiqiang (Advisor).

Subjects/Keywords: Electrical Engineering; radar; communications; orthogonal frequency division multiplexing; OFDM; MCPC; multi-carrier; multi-carrier complementary phase codes; MCPC; polar signal detection; intercarrier interference; ICI; fading; multipath fading; beta detector; doppler

…digital phase modulated system or a wider frequency spread in an analog frequency modulated… …of a simple radar pulse with a pulse-width τ and non-varying frequency and phase. Assuming… …bandwidth by applying a frequency or phase modulation. 2.3 Pulse Compression Pulse compression… …also called a phase coded waveform, has a constant frequency, 10 and a phase that is… …demonstrates the range resolution performance improvement when using frequency and phase modulated…

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APA (6^th Edition):

Ellinger, J. D. (2016). Multi-Carrier Radar for Target Detection and Communications. (Doctoral Dissertation). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1463839176

Chicago Manual of Style (16^th Edition):

Ellinger, John David. “Multi-Carrier Radar for Target Detection and Communications.” 2016. Doctoral Dissertation, Wright State University. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1463839176.

MLA Handbook (7^th Edition):

Ellinger, John David. “Multi-Carrier Radar for Target Detection and Communications.” 2016. Web. 20 Jan 2021.

Vancouver:

Ellinger JD. Multi-Carrier Radar for Target Detection and Communications. [Internet] [Doctoral dissertation]. Wright State University; 2016. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1463839176.

Council of Science Editors:

Ellinger JD. Multi-Carrier Radar for Target Detection and Communications. [Doctoral Dissertation]. Wright State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1463839176

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