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You searched for subject:(Phase Frequency Detector). Showing records 1 – 19 of 19 total matches.

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Wright State University

1. Suraparaju, Eswar Raju. Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology.

Degree: MSEE, Electrical Engineering, 2015, Wright State University

 This thesis presents wide tuning range in-phase and quad-phase (I/Q) output digital control oscillator (DCO) and voltage control oscillator (VCO) and a simple high performance… (more)

Subjects/Keywords: Electrical Engineering; In-phase and Quad-phase , Digital control oscillator , Voltage control oscillator , dead-zone, Phase Frequency Detector

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Suraparaju, E. R. (2015). Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990

Chicago Manual of Style (16th Edition):

Suraparaju, Eswar Raju. “Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology.” 2015. Masters Thesis, Wright State University. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990.

MLA Handbook (7th Edition):

Suraparaju, Eswar Raju. “Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology.” 2015. Web. 20 Jan 2021.

Vancouver:

Suraparaju ER. Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology. [Internet] [Masters thesis]. Wright State University; 2015. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990.

Council of Science Editors:

Suraparaju ER. Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology. [Masters Thesis]. Wright State University; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1451488990


Brno University of Technology

2. Florián, Antonín. Synchronizované zdroje časových signálů: Synchronized sources of clock signals.

Degree: 2018, Brno University of Technology

 This thesis deals with design of synchronized sources of time signal. The first part of the thesis deals with the theory the crystal resonators, crystal… (more)

Subjects/Keywords: Krystalový rezonátor; krystalový oscilátor; frekvenční stabilita; fázový závěs; fázový detektor.; Crystal resonator; crystal oscillator; frequency stability; phase locked loop; phase detector.

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APA (6th Edition):

Florián, A. (2018). Synchronizované zdroje časových signálů: Synchronized sources of clock signals. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/25847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Florián, Antonín. “Synchronizované zdroje časových signálů: Synchronized sources of clock signals.” 2018. Thesis, Brno University of Technology. Accessed January 20, 2021. http://hdl.handle.net/11012/25847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Florián, Antonín. “Synchronizované zdroje časových signálů: Synchronized sources of clock signals.” 2018. Web. 20 Jan 2021.

Vancouver:

Florián A. Synchronizované zdroje časových signálů: Synchronized sources of clock signals. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/11012/25847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Florián A. Synchronizované zdroje časových signálů: Synchronized sources of clock signals. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/25847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

3. Joshi, Phaniraj. Design of an 866 MHz On-chip Frequency Synthesizer.

Degree: MSEE, 2011, University of Arkansas

  There is a strong need for stable frequency references with large tuning ranges in today's communication systems. While the crystal oscillators assure good frequency(more)

Subjects/Keywords: Communication and the arts; Applied sciences; Charge pump; Closed loop; Frequency synthesizer; Phase locked loop; Pll; Tristate phase frequency detector; Electrical and Electronics

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APA (6th Edition):

Joshi, P. (2011). Design of an 866 MHz On-chip Frequency Synthesizer. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/143

Chicago Manual of Style (16th Edition):

Joshi, Phaniraj. “Design of an 866 MHz On-chip Frequency Synthesizer.” 2011. Masters Thesis, University of Arkansas. Accessed January 20, 2021. https://scholarworks.uark.edu/etd/143.

MLA Handbook (7th Edition):

Joshi, Phaniraj. “Design of an 866 MHz On-chip Frequency Synthesizer.” 2011. Web. 20 Jan 2021.

Vancouver:

Joshi P. Design of an 866 MHz On-chip Frequency Synthesizer. [Internet] [Masters thesis]. University of Arkansas; 2011. [cited 2021 Jan 20]. Available from: https://scholarworks.uark.edu/etd/143.

Council of Science Editors:

Joshi P. Design of an 866 MHz On-chip Frequency Synthesizer. [Masters Thesis]. University of Arkansas; 2011. Available from: https://scholarworks.uark.edu/etd/143


NSYSU

4. Juan, Sung-lin. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power; digitally controlled oscillator; successive approximation register; digital frequency detector; all digital phase-locked loop

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APA (6th Edition):

Juan, S. (2015). Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Juan, Sung-lin. “Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.” 2015. Thesis, NSYSU. Accessed January 20, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Juan, Sung-lin. “Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.” 2015. Web. 20 Jan 2021.

Vancouver:

Juan S. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Jan 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Juan S. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Xie, Shan-yang. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power schmitt trigger inverter; digitally controlled oscillator; all digital phase-locked loop; digital frequency detector; successive approximation register

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APA (6th Edition):

Xie, S. (2018). Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Thesis, NSYSU. Accessed January 20, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Web. 20 Jan 2021.

Vancouver:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Jan 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Irvine

6. Sedighzadeh Yazdi, Siavash. A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS.

Degree: Electrical and Computer Engineering, 2017, University of California – Irvine

Frequency-domain diffuse optical imaging (fd-DOI) systems require accurate phase and amplitude measurement of the modulating signal for precise calculation of optical properties of a medium.… (more)

Subjects/Keywords: Electrical engineering; Biomedical engineering; Medical imaging; CMOS; Diffuse Optical Imaging; frequency domain; Near infrared; n-path; phase detector

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APA (6th Edition):

Sedighzadeh Yazdi, S. (2017). A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/3k36t3tv

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sedighzadeh Yazdi, Siavash. “A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS.” 2017. Thesis, University of California – Irvine. Accessed January 20, 2021. http://www.escholarship.org/uc/item/3k36t3tv.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sedighzadeh Yazdi, Siavash. “A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS.” 2017. Web. 20 Jan 2021.

Vancouver:

Sedighzadeh Yazdi S. A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS. [Internet] [Thesis]. University of California – Irvine; 2017. [cited 2021 Jan 20]. Available from: http://www.escholarship.org/uc/item/3k36t3tv.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sedighzadeh Yazdi S. A Fully Integrated Frequency-Domain Diffuse Optical Imaging System in 180 nm Standard CMOS. [Thesis]. University of California – Irvine; 2017. Available from: http://www.escholarship.org/uc/item/3k36t3tv

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

7. Samarah, Amer. Improved Phase Detection for Digital Phase-locked Loops.

Degree: PhD, 2016, University of Toronto

Digital PLLs (DPLLs) have emerged as reliable alternatives to analog PLLs since they are more robust in the presence of process variations and mismatch and… (more)

Subjects/Keywords: bang bang phase locked loop; dead zone of phase detector; Digital phase locked loop; frequency synthesizer; modulator dithering; time to digital converter; 0544

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APA (6th Edition):

Samarah, A. (2016). Improved Phase Detection for Digital Phase-locked Loops. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/78796

Chicago Manual of Style (16th Edition):

Samarah, Amer. “Improved Phase Detection for Digital Phase-locked Loops.” 2016. Doctoral Dissertation, University of Toronto. Accessed January 20, 2021. http://hdl.handle.net/1807/78796.

MLA Handbook (7th Edition):

Samarah, Amer. “Improved Phase Detection for Digital Phase-locked Loops.” 2016. Web. 20 Jan 2021.

Vancouver:

Samarah A. Improved Phase Detection for Digital Phase-locked Loops. [Internet] [Doctoral dissertation]. University of Toronto; 2016. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1807/78796.

Council of Science Editors:

Samarah A. Improved Phase Detection for Digital Phase-locked Loops. [Doctoral Dissertation]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/78796

8. Ahola, Rami. Integrated Radio Frequency Synthesizers for Wireless Applications.

Degree: 2005, Helsinki University of Technology

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in… (more)

Subjects/Keywords: analog integrated circuit; frequency synthesizer; phase-locked loop; CMOS; BiCMOS; wireless communication; radio transceiver; prescaler; phase detector; chargepump; integer-N; fractional-N

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APA (6th Edition):

Ahola, R. (2005). Integrated Radio Frequency Synthesizers for Wireless Applications. (Thesis). Helsinki University of Technology. Retrieved from http://lib.tkk.fi/Diss/2005/isbn9512275635/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ahola, Rami. “Integrated Radio Frequency Synthesizers for Wireless Applications.” 2005. Thesis, Helsinki University of Technology. Accessed January 20, 2021. http://lib.tkk.fi/Diss/2005/isbn9512275635/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ahola, Rami. “Integrated Radio Frequency Synthesizers for Wireless Applications.” 2005. Web. 20 Jan 2021.

Vancouver:

Ahola R. Integrated Radio Frequency Synthesizers for Wireless Applications. [Internet] [Thesis]. Helsinki University of Technology; 2005. [cited 2021 Jan 20]. Available from: http://lib.tkk.fi/Diss/2005/isbn9512275635/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahola R. Integrated Radio Frequency Synthesizers for Wireless Applications. [Thesis]. Helsinki University of Technology; 2005. Available from: http://lib.tkk.fi/Diss/2005/isbn9512275635/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

9. Sujatha, V. Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -.

Degree: Information and Communication Engineering, 2014, Anna University

In a Phase Locked Loop PLL the Charge Pump CP circuit is newlineone of the key elements It receives Up and Down signals from the… (more)

Subjects/Keywords: Channel Metal Oxide Semiconductors; Charge Pump Phase Locked Loop; Complementary Metal Oxide Semiconductors; Gain Boosting Charge Pump; High output impedance; High Performance charge pump phase; Information and Communication engineering; Phase Frequency Detector; Phase Locked Loop; Voltage controlled oscillator

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APA (6th Edition):

Sujatha, V. (2014). Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/24464

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sujatha, V. “Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -.” 2014. Thesis, Anna University. Accessed January 20, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/24464.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sujatha, V. “Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -.” 2014. Web. 20 Jan 2021.

Vancouver:

Sujatha V. Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -. [Internet] [Thesis]. Anna University; 2014. [cited 2021 Jan 20]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24464.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sujatha V. Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24464

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

10. Raghavendra, R G. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.

Degree: MSc Engg, Faculty of Engineering, 2011, Indian Institute of Science

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture… (more)

Subjects/Keywords: Special Devices (Computer Engineering); Analog Frequency Detector; Charge Pump Phase Locked Loop; Phase Locked Loop (PLL); Phase Locked Loop Filters; Phase Locked Loop Filter Design; Summer-Less Dual Charge Pump Based Loop Filters; Loop Filter Design; Computer Engineering

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APA (6th Edition):

Raghavendra, R. G. (2011). Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/1006

Chicago Manual of Style (16th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2011. Masters Thesis, Indian Institute of Science. Accessed January 20, 2021. http://etd.iisc.ac.in/handle/2005/1006.

MLA Handbook (7th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2011. Web. 20 Jan 2021.

Vancouver:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Internet] [Masters thesis]. Indian Institute of Science; 2011. [cited 2021 Jan 20]. Available from: http://etd.iisc.ac.in/handle/2005/1006.

Council of Science Editors:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Masters Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ac.in/handle/2005/1006


Texas A&M University

11. Cheng, Shanfeng. Design of CMOS integrated phase-locked loops for multi-gigabits serial data links.

Degree: PhD, Electrical Engineering, 2007, Texas A&M University

 High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication… (more)

Subjects/Keywords: Phase-locked Loops; PLL; Clock and Data Recovery; CDR; Jitter; Phase Noise; VCO; Charge Pump; Phase Detector; Frequency Detector; Voltage-Controlled Oscillator

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APA (6th Edition):

Cheng, S. (2007). Design of CMOS integrated phase-locked loops for multi-gigabits serial data links. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/4954

Chicago Manual of Style (16th Edition):

Cheng, Shanfeng. “Design of CMOS integrated phase-locked loops for multi-gigabits serial data links.” 2007. Doctoral Dissertation, Texas A&M University. Accessed January 20, 2021. http://hdl.handle.net/1969.1/4954.

MLA Handbook (7th Edition):

Cheng, Shanfeng. “Design of CMOS integrated phase-locked loops for multi-gigabits serial data links.” 2007. Web. 20 Jan 2021.

Vancouver:

Cheng S. Design of CMOS integrated phase-locked loops for multi-gigabits serial data links. [Internet] [Doctoral dissertation]. Texas A&M University; 2007. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1969.1/4954.

Council of Science Editors:

Cheng S. Design of CMOS integrated phase-locked loops for multi-gigabits serial data links. [Doctoral Dissertation]. Texas A&M University; 2007. Available from: http://hdl.handle.net/1969.1/4954


University of Illinois – Urbana-Champaign

12. Elkholy, Ahmed Mostafa Mohamed Attia. Digital enhancement techniques for fractional-N frequency synthesizers.

Degree: PhD, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing… (more)

Subjects/Keywords: Phase-locked loops (PLLs); digital PLL; All-digital phase locked loop (ADPLL); fractional-N; Fractional divider, frequency synthesizer; Wide bandwidth; Bang-bang phase detector (BBPD); Digital-to-time converter (DTC); Least-mean square (LMS); Time-to-digtial converter (TDC); Time amplifier; Jitter; Digitally controlled oscillator (DCO); Frequency multiplier; Frequency tracking; Impulse sensitivity function (ISF); Injection locking; Multiplying injection-locked oscillator (MILO); Phase domain response (PDR); Phase noise; Pulse; Reference spur; Root mean square (rms) jitter; Sub-harmonic locking; Sub-sampling (SS)

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APA (6th Edition):

Elkholy, A. M. M. A. (2016). Digital enhancement techniques for fractional-N frequency synthesizers. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95573

Chicago Manual of Style (16th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 20, 2021. http://hdl.handle.net/2142/95573.

MLA Handbook (7th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Web. 20 Jan 2021.

Vancouver:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2142/95573.

Council of Science Editors:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95573


University of Cincinnati

13. VIJAY, VIKAS. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.

Degree: MS, Engineering : Computer Engineering, 2004, University of Cincinnati

 This thesis presents automated techniques for synthesis of high performance RF circuits. The top-down methodology developed encompasses all stages of RF design from circuit sizing,… (more)

Subjects/Keywords: Radio Frequency; Synthesis; Optimization; Automation; Layout Generation; RF; Analog; High Frequency; Module Generation; C++; SKILL; Extraction; Performance Analysis; Circuit Sizing; Radio Receiver; LNA; Mixer; VCO; Phase Frequency Detector

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APA (6th Edition):

VIJAY, V. (2004). A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

Chicago Manual of Style (16th Edition):

VIJAY, VIKAS. “A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.” 2004. Masters Thesis, University of Cincinnati. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

MLA Handbook (7th Edition):

VIJAY, VIKAS. “A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.” 2004. Web. 20 Jan 2021.

Vancouver:

VIJAY V. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2004. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

Council of Science Editors:

VIJAY V. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. [Masters Thesis]. University of Cincinnati; 2004. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283


Queens University

14. Carr, John. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .

Degree: Electrical and Computer Engineering, 2009, Queens University

 This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use… (more)

Subjects/Keywords: phase-locked loop ; frequency multiplier ; CMOS ; integrated circuit ; voltage controlled oscillator ; injection locked frequency divider ; phase detector ; phase noise ; Accumulation MOS varactor ; monolithic integration ; static phase offset ; common mode rejection ; 26 GHz ; master-slave flip-flop divider ; direct injection ; differential ; phase plane

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carr, J. (2009). A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/1796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Carr, John. “A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .” 2009. Thesis, Queens University. Accessed January 20, 2021. http://hdl.handle.net/1974/1796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Carr, John. “A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .” 2009. Web. 20 Jan 2021.

Vancouver:

Carr J. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . [Internet] [Thesis]. Queens University; 2009. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1974/1796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carr J. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . [Thesis]. Queens University; 2009. Available from: http://hdl.handle.net/1974/1796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Mishra, Satyabh. Design of charge pump phase locked loop.

Degree: 2012, Texas Tech University

Phase Locked Loop system is around since 1932. The versatility of PLL systems and where it can apply makes it very useful. It can be… (more)

Subjects/Keywords: Phase locked loop; Pump frequency detector (PFD); Charge pump; Low pass filter; Voltage-controlled oscillator (VCO); Ring oscillator; Frequency divider; Current mode logic; Lock time

Phase Frequency Detector 2. Loop Filter (low pass) 3. Voltage Controlled Oscillator… …Phase Detector (PD) part to become Phase Frequency Detector (PFD). In this… …having a Phase Frequency Detector instead of Phase Detector, a Charge Pump, and a divide by N… …CHAPTER II PHASE FREQUENCY DETECTOR A Phase Frequency Detector (PFD) is typically an… …level. This basic form of Phase Detector is not capable to detect large frequency differences… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mishra, S. (2012). Design of charge pump phase locked loop. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/46975

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mishra, Satyabh. “Design of charge pump phase locked loop.” 2012. Thesis, Texas Tech University. Accessed January 20, 2021. http://hdl.handle.net/2346/46975.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mishra, Satyabh. “Design of charge pump phase locked loop.” 2012. Web. 20 Jan 2021.

Vancouver:

Mishra S. Design of charge pump phase locked loop. [Internet] [Thesis]. Texas Tech University; 2012. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2346/46975.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mishra S. Design of charge pump phase locked loop. [Thesis]. Texas Tech University; 2012. Available from: http://hdl.handle.net/2346/46975

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

16. Balssubramanian, Suresh. Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models.

Degree: MSc Engg, Faculty of Engineering, 2011, Indian Institute of Science

Subjects/Keywords: Computer Aided Design; Integrated Circuits; Phased Locked Loop; Phased Locked Loop Design - Behavioral Models; PLL Design; Digital Signal Processing (DSP); Application Specific Integrated Circuits (ASIC); Phase Frequency Detector (PFD); Voltage Controlled Oscillators (VCO); Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Balssubramanian, S. (2011). Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/1127

Chicago Manual of Style (16th Edition):

Balssubramanian, Suresh. “Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models.” 2011. Masters Thesis, Indian Institute of Science. Accessed January 20, 2021. http://etd.iisc.ac.in/handle/2005/1127.

MLA Handbook (7th Edition):

Balssubramanian, Suresh. “Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models.” 2011. Web. 20 Jan 2021.

Vancouver:

Balssubramanian S. Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models. [Internet] [Masters thesis]. Indian Institute of Science; 2011. [cited 2021 Jan 20]. Available from: http://etd.iisc.ac.in/handle/2005/1127.

Council of Science Editors:

Balssubramanian S. Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models. [Masters Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ac.in/handle/2005/1127

17. Laha, Soumyasanta. Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs.

Degree: PhD, Electrical Engineering & Computer Science (Engineering and Technology), 2015, Ohio University

 Today's nanochips contain billions of transistors on a single die that integrates whole electronic systems as opposed to sub-system parts. Together with ever higher frequency(more)

Subjects/Keywords: Electrical Engineering; Radio Frequency Integrated Circuit Design; Wireless Communication; Double Gate MOSFET; 60 GHz; OOK Modulation and Demodulation; Oscillator; Power Amplifier; Low Noise Amplifier; RF Mixer; Phase Frequency Detector; 65 nm RF CMOS TRx Design

Phase Frequency Detector 5.3.1 DG-MOSFET NOR Gate . . . . . 5.3.2 Charge Pump PFD… …Amplifiers • RF Mixers • OOK Demodulator/Envelope Detectors • Charge Pump Phase Frequency Detector… …bias optimization technique for DG-MOSFET RF Mixer. Charge Pump Phase Frequency Detector… …receivers. It also reports the research on DG-MOSFET Charge Pump Phase Frequency detector which is… …2.5.1.2 Phase Shift Keying . . . . . . . . . . . . . . 2.5.1.3 Orthogonal Frequency Division… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Laha, S. (2015). Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs. (Doctoral Dissertation). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974

Chicago Manual of Style (16th Edition):

Laha, Soumyasanta. “Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs.” 2015. Doctoral Dissertation, Ohio University. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974.

MLA Handbook (7th Edition):

Laha, Soumyasanta. “Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs.” 2015. Web. 20 Jan 2021.

Vancouver:

Laha S. Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs. [Internet] [Doctoral dissertation]. Ohio University; 2015. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974.

Council of Science Editors:

Laha S. Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs. [Doctoral Dissertation]. Ohio University; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974


Queensland University of Technology

18. Hussain, Zahir M. Adaptive instantaneous frequency estimation: Techniques and algorithms.

Degree: 2002, Queensland University of Technology

 This thesis deals with the problem of the instantaneous frequency (IF) estimation of sinusoidal signals. This topic plays significant role in signal processing and communications.… (more)

Subjects/Keywords: Signal processing; Time series analysis; Frequency spectra; instantaneous frequency; stationary signals; non-stationary signals; communication systems; multicomponent signals; frequency modulated (FM) signals; frequency shift keying (FSK) signals; sinusoidal signals; analytic signals; digital phase-locked loops; Hilbert transform; time-delay; phase shifter; difference equation; sinusoidal digital phase locked loops; digital tanlock loop; tanlock; lock range; independent locking; digital filters; nonuniform sampling; additive Gaussian noise; signal-to-noise-ratio (SNR); locking speed; phase error detector; Cramer-Rao bounds; time-frequency analysis; ambiguity function; time-frequency distribution (TFD); the quadratic class; resolution; cross-terms; Fourier transform; estimation; amplitude estimation; instantaneous frequency estimation; mean square error; simulation; algorithms; adaptive algorithms; adaptive estimation; bias; variance; asymptotic analysis; thesis; doctoral

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hussain, Z. M. (2002). Adaptive instantaneous frequency estimation: Techniques and algorithms. (Thesis). Queensland University of Technology. Retrieved from https://eprints.qut.edu.au/36137/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hussain, Zahir M. “Adaptive instantaneous frequency estimation: Techniques and algorithms.” 2002. Thesis, Queensland University of Technology. Accessed January 20, 2021. https://eprints.qut.edu.au/36137/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hussain, Zahir M. “Adaptive instantaneous frequency estimation: Techniques and algorithms.” 2002. Web. 20 Jan 2021.

Vancouver:

Hussain ZM. Adaptive instantaneous frequency estimation: Techniques and algorithms. [Internet] [Thesis]. Queensland University of Technology; 2002. [cited 2021 Jan 20]. Available from: https://eprints.qut.edu.au/36137/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hussain ZM. Adaptive instantaneous frequency estimation: Techniques and algorithms. [Thesis]. Queensland University of Technology; 2002. Available from: https://eprints.qut.edu.au/36137/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Ellinger, John David. Multi-Carrier Radar for Target Detection and Communications.

Degree: PhD, Electrical Engineering, 2016, Wright State University

 This dissertation considers the optimization of radar performance within the structure imposed by a coded <i>Orthogonal Frequency Division Multiplexing</i> (OFDM) format required to achieve an… (more)

Subjects/Keywords: Electrical Engineering; radar; communications; orthogonal frequency division multiplexing; OFDM; MCPC; multi-carrier; multi-carrier complementary phase codes; MCPC; polar signal detection; intercarrier interference; ICI; fading; multipath fading; beta detector; doppler

…digital phase modulated system or a wider frequency spread in an analog frequency modulated… …of a simple radar pulse with a pulse-width τ and non-varying frequency and phase. Assuming… …bandwidth by applying a frequency or phase modulation. 2.3 Pulse Compression Pulse compression… …also called a phase coded waveform, has a constant frequency, 10 and a phase that is… …demonstrates the range resolution performance improvement when using frequency and phase modulated… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ellinger, J. D. (2016). Multi-Carrier Radar for Target Detection and Communications. (Doctoral Dissertation). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1463839176

Chicago Manual of Style (16th Edition):

Ellinger, John David. “Multi-Carrier Radar for Target Detection and Communications.” 2016. Doctoral Dissertation, Wright State University. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1463839176.

MLA Handbook (7th Edition):

Ellinger, John David. “Multi-Carrier Radar for Target Detection and Communications.” 2016. Web. 20 Jan 2021.

Vancouver:

Ellinger JD. Multi-Carrier Radar for Target Detection and Communications. [Internet] [Doctoral dissertation]. Wright State University; 2016. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1463839176.

Council of Science Editors:

Ellinger JD. Multi-Carrier Radar for Target Detection and Communications. [Doctoral Dissertation]. Wright State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1463839176

.