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You searched for subject:(Performance bug). Showing records 1 – 5 of 5 total matches.

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Texas A&M University

1. Rajagopalan, Arun Krishnakumar. Fast and Precise On-The-Fly Data Race Detection.

Degree: MS, Computer Science, 2016, Texas A&M University

 While concurrent programming is quickly gaining popularity lately, developing bug-free programs is still challenging. Although developers have a wide choice of race detection tools available,… (more)

Subjects/Keywords: bug detection; concurrency; debugging; dynamic analysis; parallelism; performance analysis; runtime monitoring; software engineering; redundancy; data race; missing events; precise detection; happens-before; maximal thread causality

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APA (6th Edition):

Rajagopalan, A. K. (2016). Fast and Precise On-The-Fly Data Race Detection. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/157131

Chicago Manual of Style (16th Edition):

Rajagopalan, Arun Krishnakumar. “Fast and Precise On-The-Fly Data Race Detection.” 2016. Masters Thesis, Texas A&M University. Accessed January 22, 2021. http://hdl.handle.net/1969.1/157131.

MLA Handbook (7th Edition):

Rajagopalan, Arun Krishnakumar. “Fast and Precise On-The-Fly Data Race Detection.” 2016. Web. 22 Jan 2021.

Vancouver:

Rajagopalan AK. Fast and Precise On-The-Fly Data Race Detection. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/1969.1/157131.

Council of Science Editors:

Rajagopalan AK. Fast and Precise On-The-Fly Data Race Detection. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/157131

2. -2178-1988. Program analysis techniques for algorithmic complexity and relational properties.

Degree: PhD, Computer Science, 2019, University of Texas – Austin

 Analyzing standard safety properties of a given program has traditionally been the primary focus of the program analysis community. Unfortunately, there are still many interesting… (more)

Subjects/Keywords: Complexity testing; Optimal program synthesis; Fuzzing; Genetic programming; Performance bug; Vulnerability detection; Side channel; Static analysis; Relational verification; Reinforcement learning; Policy gradient

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APA (6th Edition):

-2178-1988. (2019). Program analysis techniques for algorithmic complexity and relational properties. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2181

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-2178-1988. “Program analysis techniques for algorithmic complexity and relational properties.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed January 22, 2021. http://dx.doi.org/10.26153/tsw/2181.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-2178-1988. “Program analysis techniques for algorithmic complexity and relational properties.” 2019. Web. 22 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-2178-1988. Program analysis techniques for algorithmic complexity and relational properties. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Jan 22]. Available from: http://dx.doi.org/10.26153/tsw/2181.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-2178-1988. Program analysis techniques for algorithmic complexity and relational properties. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/2181

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Central Florida

3. Garland, Dennis. Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders.

Degree: 2013, University of Central Florida

 Due to a multitude of convergent circumstances, students labeled in the disability category of emotional and behavioral disorders (EBD) experience high rates of academic and… (more)

Subjects/Keywords: Emotional and behavioral disorders; students with disabilities; evidence based practices; three term contingency trials; teacher preparation; novice educators; science education; bug in the ear technology; inclusion; Education; Special Education and Teaching; Dissertations, Academic  – Education and Human Performance, Education and Human Performance  – Dissertations, Academic

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APA (6th Edition):

Garland, D. (2013). Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders. (Doctoral Dissertation). University of Central Florida. Retrieved from https://stars.library.ucf.edu/etd/2629

Chicago Manual of Style (16th Edition):

Garland, Dennis. “Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders.” 2013. Doctoral Dissertation, University of Central Florida. Accessed January 22, 2021. https://stars.library.ucf.edu/etd/2629.

MLA Handbook (7th Edition):

Garland, Dennis. “Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders.” 2013. Web. 22 Jan 2021.

Vancouver:

Garland D. Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders. [Internet] [Doctoral dissertation]. University of Central Florida; 2013. [cited 2021 Jan 22]. Available from: https://stars.library.ucf.edu/etd/2629.

Council of Science Editors:

Garland D. Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders. [Doctoral Dissertation]. University of Central Florida; 2013. Available from: https://stars.library.ucf.edu/etd/2629

4. Cao, Man. Efficient, Practical Dynamic Program Analyses for Concurrency Correctness.

Degree: PhD, Computer Science and Engineering, 2017, The Ohio State University

 Shared-memory parallel programs are notoriously difficult to be both scalable and correct. One of the most problematic concurrency bugs is data race. Data races are… (more)

Subjects/Keywords: Computer Science; Computer Engineering; concurrency, runtime, parallelism, correctness, bug detection, performance, data race, dynamic analysis

…Arnab Nandi High Performance Computing Prof. P. Sadayappan viii Table of Contents Page… …3.6.5 Performance of Tracking Alone . . . . . . . . 3.6.6 Performance of Runtime Support… …4.4.3 Performance . . . . . . . . . . . . . . . . . . . . . . . Contributions and Impact… …5.7.4 Run-Time Performance . . . . . . . . . . . . . . . Contributions and Impact… …for flexible support for high-performance implementations that require various compiler… 

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APA (6th Edition):

Cao, M. (2017). Efficient, Practical Dynamic Program Analyses for Concurrency Correctness. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986

Chicago Manual of Style (16th Edition):

Cao, Man. “Efficient, Practical Dynamic Program Analyses for Concurrency Correctness.” 2017. Doctoral Dissertation, The Ohio State University. Accessed January 22, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986.

MLA Handbook (7th Edition):

Cao, Man. “Efficient, Practical Dynamic Program Analyses for Concurrency Correctness.” 2017. Web. 22 Jan 2021.

Vancouver:

Cao M. Efficient, Practical Dynamic Program Analyses for Concurrency Correctness. [Internet] [Doctoral dissertation]. The Ohio State University; 2017. [cited 2021 Jan 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986.

Council of Science Editors:

Cao M. Efficient, Practical Dynamic Program Analyses for Concurrency Correctness. [Doctoral Dissertation]. The Ohio State University; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986

5. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…Simulation Breakpoint Trigger . . . . . . . . . . . . . 5.4 Bug Example… …solution is inadequate for power consumption and/or performance reasons. Thus problems that… …require a hardware solution already come with demanding power and performance constraints. With… …the end of Dennard scaling, improvements in power consumption and performance for… …with a software version generated to produce the same result, we show that logic bug… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 22, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 22 Jan 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

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