You searched for subject:(Performance bug).
Showing records 1 – 5 of
5 total matches.
No search limiters apply to these results.
Texas A&M University
1.
Rajagopalan, Arun Krishnakumar.
Fast and Precise On-The-Fly Data Race Detection.
Degree: MS, Computer Science, 2016, Texas A&M University
URL: http://hdl.handle.net/1969.1/157131 
► While concurrent programming is quickly gaining popularity lately, developing bug-free programs is still challenging. Although developers have a wide choice of race detection tools available,…
(more)
▼ While concurrent programming is quickly gaining popularity lately, developing
bug-free programs is still challenging. Although developers have a wide choice of race detection tools available, we have found that the majority of these techniques do not scale well and developers are often forced to balance precision with speed. Additionally, various practical issues force even precise race detectors to produce spurious warnings, defeating their purpose and burdening their users. We design and implement a novel race detection technique that is both fast and precise, even in the face of missing program source information. Towards this goal, we have developed two separate tools, TREE and RDIT, that respectively improve
performance and precision over existing techniques.
TREE, implemented in the RoadRunner framework, acts as a filter and sends through only those events that might add value to race detection while eliminating those events which are deemed redundant for this purpose. All the while, removing these redundant events does not affect its race detection capability. We have evaluated TREE against a whole set of standard benchmarks, including two large real-world applications. We have found that there exists a significant number of redundant events in all these applications and on an average, TREE saves somewhere between 15-25% of analysis time as compared to the state-of-the-art techniques.
Meanwhile, our next tool, RDIT, is able to precisely detect races in programs with incomplete source information, generating no false positives. RDIT is also maximal in the sense that it detects a maximal set of true races from the observed incomplete trace. It is underpinned by a sound BarrierPair model that abstracts away the missing events by capturing the invocation data of their enclosing methods. By making the least conservative assumption that a missing method introduces synchronization only when its invocation data overlaps with other missing methods, and by formulating maximal thread causality as a set of logical constraints, RDIT guarantees to precisely detect races with maximal capability. We tested RDIT against seven real-world large concurrent systems and have detected dozens of true races with zero false alarm. Comparatively, existing algorithms such as Happens-Before, Causal-Precede, and Maximal-Causality, which are all known to be precise, were observed reporting hundreds of false alarms due to trace incompleteness.
Advisors/Committee Members: Huang, Jeff (advisor), Welch, Jennifer L (committee member), Ji, Jim (committee member).
Subjects/Keywords: bug detection; concurrency; debugging; dynamic analysis; parallelism; performance analysis; runtime monitoring; software engineering; redundancy; data race; missing events; precise detection; happens-before; maximal thread causality
Record Details
Similar Records
Cite
Share »
Record Details
Similar Records
Cite
« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Rajagopalan, A. K. (2016). Fast and Precise On-The-Fly Data Race Detection. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/157131
Chicago Manual of Style (16th Edition):
Rajagopalan, Arun Krishnakumar. “Fast and Precise On-The-Fly Data Race Detection.” 2016. Masters Thesis, Texas A&M University. Accessed January 22, 2021.
http://hdl.handle.net/1969.1/157131.
MLA Handbook (7th Edition):
Rajagopalan, Arun Krishnakumar. “Fast and Precise On-The-Fly Data Race Detection.” 2016. Web. 22 Jan 2021.
Vancouver:
Rajagopalan AK. Fast and Precise On-The-Fly Data Race Detection. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2021 Jan 22].
Available from: http://hdl.handle.net/1969.1/157131.
Council of Science Editors:
Rajagopalan AK. Fast and Precise On-The-Fly Data Race Detection. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/157131
2.
-2178-1988.
Program analysis techniques for algorithmic complexity and relational properties.
Degree: PhD, Computer Science, 2019, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/2181
► Analyzing standard safety properties of a given program has traditionally been the primary focus of the program analysis community. Unfortunately, there are still many interesting…
(more)
▼ Analyzing standard safety properties of a given program has traditionally been
the primary focus of the program analysis community. Unfortunately, there are
still many interesting analysis tasks that cannot be effectively expressed with
standard safety properties. One such example is to derive the asymptotic
complexity of a given program. Another example is to verify relational
properties, i.e. properties that must be satisfied jointly by multiple programs
of multiple runs of one program. Existing program analysis techniques for
standard safety properties are usually not immediately applicable to asymptotic
complexity analysis problems and relational verification problems. New
approaches are therefore needed to solve these unconventional problems.
This thesis studies techniques for algorithmic complexity analysis as well as
relational verification. To that end, we present three case studies: (1) We
propose a new fuzzing technique for automatically finding inputs that trigger a
program's worst-case resource usage. (2) We show how to build a scalable,
end-to-end side channel detection tool by combining static taint analysis and a
program logic designed for verifying non-interference of a given program. (3) We
propose a general and effective relational verification algorithm that combines
reinforcement learning with backtracking search. A common theme
among all these solutions is to exploit problem-specific structures and adapt
existing techniques to exploit those structures accordingly.
Advisors/Committee Members: Dillig, Isil (advisor), Lin, Calvin (committee member), Chidambaram, Vijay (committee member), Tiwari, Mohit (committee member).
Subjects/Keywords: Complexity testing; Optimal program synthesis; Fuzzing; Genetic
programming; Performance bug; Vulnerability detection; Side channel; Static analysis; Relational verification; Reinforcement learning; Policy gradient
Record Details
Similar Records
Cite
Share »
Record Details
Similar Records
Cite
« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
-2178-1988. (2019). Program analysis techniques for algorithmic complexity and relational properties. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2181
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-2178-1988. “Program analysis techniques for algorithmic complexity and relational properties.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed January 22, 2021.
http://dx.doi.org/10.26153/tsw/2181.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-2178-1988. “Program analysis techniques for algorithmic complexity and relational properties.” 2019. Web. 22 Jan 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-2178-1988. Program analysis techniques for algorithmic complexity and relational properties. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Jan 22].
Available from: http://dx.doi.org/10.26153/tsw/2181.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-2178-1988. Program analysis techniques for algorithmic complexity and relational properties. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/2181
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
University of Central Florida
3.
Garland, Dennis.
Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders.
Degree: 2013, University of Central Florida
URL: https://stars.library.ucf.edu/etd/2629
► Due to a multitude of convergent circumstances, students labeled in the disability category of emotional and behavioral disorders (EBD) experience high rates of academic and…
(more)
▼ Due to a multitude of convergent circumstances, students labeled in the disability category of emotional and behavioral disorders (EBD) experience high rates of academic and behavioral failure. Such failure frequently leads to the students’ dropping out of school, involvement in the judicial system, or a combination of those outcomes. Science is an academic content area that has the potential to enhance behavioral and academic success of students with EBD. Researchers, nonprofits, and business leaders have provided an impetus for nationwide reform in science education. Concurrently, a corpus of legislation has influenced the preparation of new teachers to use evidence-based teaching practices while addressing the needs of an increasingly diverse student population. Using technology is one way that teacher educators are providing in-vivo learning experiences to new teachers during their classroom instruction. A multiple-baseline across-participants research study was used to examine the effectiveness of providing immediate feedback (within three seconds) to novice general science educators to increase their use of an evidence-based teaching strategy, known as a three-term contingency (TTC) trial while they taught. Feedback was delivered via
Bug-in-the-Ear (BIE) technology and during whole-class instruction in which students with EBD were included. The teacher participants wore a Bluetooth earpiece, which served as a vehicle for audio communication with the investigator. Teachers were observed via web camera over the Adobe®ConnectTM online conferencing platform. During the intervention, teachers increased iv their percentage of completed TTC trials, opportunities to respond, and praise or error correction. Student responses also increased, and maladaptive behaviors decreased.
Advisors/Committee Members: Dieker, Lisa.
Subjects/Keywords: Emotional and behavioral disorders; students with disabilities; evidence based practices; three term contingency trials; teacher preparation; novice educators; science education; bug in the ear technology; inclusion; Education; Special Education and Teaching; Dissertations, Academic – Education and Human Performance, Education and Human Performance – Dissertations, Academic
Record Details
Similar Records
Cite
Share »
Record Details
Similar Records
Cite
« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Garland, D. (2013). Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders. (Doctoral Dissertation). University of Central Florida. Retrieved from https://stars.library.ucf.edu/etd/2629
Chicago Manual of Style (16th Edition):
Garland, Dennis. “Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders.” 2013. Doctoral Dissertation, University of Central Florida. Accessed January 22, 2021.
https://stars.library.ucf.edu/etd/2629.
MLA Handbook (7th Edition):
Garland, Dennis. “Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders.” 2013. Web. 22 Jan 2021.
Vancouver:
Garland D. Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders. [Internet] [Doctoral dissertation]. University of Central Florida; 2013. [cited 2021 Jan 22].
Available from: https://stars.library.ucf.edu/etd/2629.
Council of Science Editors:
Garland D. Virtual Coaching Of Novice Science Educators To Support Students With Emotional And Behavioral Disorders. [Doctoral Dissertation]. University of Central Florida; 2013. Available from: https://stars.library.ucf.edu/etd/2629
4.
Cao, Man.
Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness.
Degree: PhD, Computer Science and Engineering, 2017, The Ohio State University
URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986
► Shared-memory parallel programs are notoriously difficult to be both scalable and correct. One of the most problematic concurrency bugs is data race. Data races are…
(more)
▼ Shared-memory parallel programs are notoriously
difficult to be both scalable and correct. One of the most
problematic concurrency bugs is data race. Data races are difficult
to avoid, find, fix, reproduce, and eliminate. A fundamental
problem is that language and hardware memory models provide few or
no guarantees for executions containing data races. Researchers
have developed various program analyses and runtime tools for
concurrency correctness properties. Examples includes data race
detectors, multithreaded record & replay, transactional memory,
and enforcement of stronger memory models. However, in the presence
of data races, many of these tools suffer from limitations that
impede their widespread use.The first challenge in handling racy
executions is the high overhead for tracking (i.e., detect or
control) cross-thread dependences, which is a necessary requirement
to ensure the soundness of many analyses. The second limitation is
that existing work has not covered the full range of possible
behaviors for racy executions in weak memory models. This thesis
explores several efficient and practical dynamic program analyses
that aim to overcome these two key limitations, advancing the state
of the art for detecting, enforcing, and exposing issues related to
concurrency correctness.We present hybrid tracking and RegPlay to
address the first challenge. Hybrid tracking is a generalized
framework for tracking dependences, which hybridizes pessimistic
and optimistic tracking in order to get the best of both world. We
build hybrid-tracking-based versions of a dependence recorder and a
region serializability enforcer to demonstrate the usefulness of
hybrid tracking. RegPlay shows an analysis-specifc way of
optimizing dependence tracking in the context of multithreaded
record & replay. RegPlay avoids recording read – write
dependences and many transitively implied dependences in order to
reduce run-time overhead, and enforces replay determinism by
detecting and resolving violations of read – write dependences.
Experiments show that hybrid tracking enables runtime support to
overcome the
performance limitations of both pessimistic and
optimistic tracking alone, and RegPlay records much fewer
dependences than existing approach while preserves replay
determinism.To address the second limitation, we introduce
prescient memory (PM), a novel dynamic analysis that exposes
behaviors due to future values – a value written by a store that
executes after the load that uses the value. A load could return a
future value in a racy execution in weak memory models, but
existing analyses fail to expose such behaviors. PM speculatively
returns a future value at a program load, and tries to validate the
speculative value at a later store. PM applies a novel approach
that profiles future values and guides execution to increase the
chances of successfully validating future values in real
application executions. Experiments shows that PM uncovers a few
previously unknown behaviors due to future values in real
applications.Overall, this thesis…
Advisors/Committee Members: Bond, Michael (Advisor).
Subjects/Keywords: Computer Science; Computer Engineering; concurrency, runtime, parallelism, correctness, bug
detection, performance, data race, dynamic analysis
…Arnab Nandi
High Performance Computing
Prof. P. Sadayappan
viii
Table of Contents
Page… …3.6.5 Performance of Tracking Alone . . . . . . . .
3.6.6 Performance of Runtime Support… …4.4.3 Performance . . . . . . . . . . . . . . . . . . . . . . .
Contributions and Impact… …5.7.4 Run-Time Performance . . . . . . . . . . . . . . .
Contributions and Impact… …for flexible support for high-performance
implementations that require various compiler…
Record Details
Similar Records
Cite
Share »
Record Details
Similar Records
Cite
« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Cao, M. (2017). Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986
Chicago Manual of Style (16th Edition):
Cao, Man. “Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness.” 2017. Doctoral Dissertation, The Ohio State University. Accessed January 22, 2021.
http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986.
MLA Handbook (7th Edition):
Cao, Man. “Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness.” 2017. Web. 22 Jan 2021.
Vancouver:
Cao M. Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness. [Internet] [Doctoral dissertation]. The Ohio State University; 2017. [cited 2021 Jan 22].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986.
Council of Science Editors:
Cao M. Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness. [Doctoral Dissertation]. The Ohio State University; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986
5.
Campbell, Keith A.
Robust and reliable hardware accelerator design through high-level synthesis.
Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign
URL: http://hdl.handle.net/2142/99294
► System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety…
(more)
▼ System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system
performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable.
High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This dissertation shows that high-level synthesis also has the power to address validation and reliability challenges through three automated solutions targeting three key stages in the hardware design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment error detection.
Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software implementation at a fine temporal and spatial granularity to detect logic bugs. An integrated backtrace process delivers source-code meaning to the hardware designer, pinpointing the location of
bug activation and providing a strong hint for potential
bug fixes. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself.
A variation of this solution tailored for rapid post-silicon validation of accelerator designs is hybrid hashing: inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using hybrid hashing, we demonstrate an improvement in error detection latency (time elapsed from when a
bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in
bug coverage compared to traditional post-silicon validation techniques. Hybrid hashing also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. Hybrid hashing incurs less than 10% area overhead for the accelerator it validates with negligible
performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by hybrid hashing.
Finally, our solution for post-deployment error detection is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling…
Advisors/Committee Members: Chen, Deming (advisor), Chen, Deming (Committee Chair), Hwu, Wen-Mei W (committee member), Wong, Martin D F (committee member), Kim, Nam Sung (committee member).
Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency
…Simulation Breakpoint Trigger . . . . . . . . . . . . .
5.4 Bug Example… …solution is inadequate for power consumption
and/or performance reasons. Thus problems that… …require a hardware solution
already come with demanding power and performance constraints. With… …the
end of Dennard scaling, improvements in power consumption and performance
for… …with a software version generated to produce the
same result, we show that logic bug…
Record Details
Similar Records
Cite
Share »
Record Details
Similar Records
Cite
« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294
Chicago Manual of Style (16th Edition):
Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 22, 2021.
http://hdl.handle.net/2142/99294.
MLA Handbook (7th Edition):
Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 22 Jan 2021.
Vancouver:
Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Jan 22].
Available from: http://hdl.handle.net/2142/99294.
Council of Science Editors:
Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294
. 
Open Access Theses and Dissertations
