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You searched for subject:(PLL). Showing records 1 – 30 of 237 total matches.

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Texas A&M University

1. Park, Joohwan. Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter.

Degree: 2006, Texas A&M University

 Phase locked loops (PLL) are used in a variety of RF integrated applications because of their ability to generate precise clock signals. These applications include… (more)

Subjects/Keywords: PLL

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APA (6th Edition):

Park, J. (2006). Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/4194

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Joohwan. “Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter.” 2006. Thesis, Texas A&M University. Accessed October 20, 2019. http://hdl.handle.net/1969.1/4194.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Joohwan. “Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter.” 2006. Web. 20 Oct 2019.

Vancouver:

Park J. Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter. [Internet] [Thesis]. Texas A&M University; 2006. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1969.1/4194.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park J. Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter. [Thesis]. Texas A&M University; 2006. Available from: http://hdl.handle.net/1969.1/4194

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Dalhousie University

2. Ren, Jie. Design of Low-Voltage Wide Tuning Range CMOS Multipass Voltage-Controlled Ring Oscillator.

Degree: Master of Applied Science, Department of Electrical & Computer Engineering, 2011, Dalhousie University

 This thesis introduces a multipass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The… (more)

Subjects/Keywords: VCO; PLL; CMOS

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APA (6th Edition):

Ren, J. (2011). Design of Low-Voltage Wide Tuning Range CMOS Multipass Voltage-Controlled Ring Oscillator. (Masters Thesis). Dalhousie University. Retrieved from http://hdl.handle.net/10222/13341

Chicago Manual of Style (16th Edition):

Ren, Jie. “Design of Low-Voltage Wide Tuning Range CMOS Multipass Voltage-Controlled Ring Oscillator.” 2011. Masters Thesis, Dalhousie University. Accessed October 20, 2019. http://hdl.handle.net/10222/13341.

MLA Handbook (7th Edition):

Ren, Jie. “Design of Low-Voltage Wide Tuning Range CMOS Multipass Voltage-Controlled Ring Oscillator.” 2011. Web. 20 Oct 2019.

Vancouver:

Ren J. Design of Low-Voltage Wide Tuning Range CMOS Multipass Voltage-Controlled Ring Oscillator. [Internet] [Masters thesis]. Dalhousie University; 2011. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/10222/13341.

Council of Science Editors:

Ren J. Design of Low-Voltage Wide Tuning Range CMOS Multipass Voltage-Controlled Ring Oscillator. [Masters Thesis]. Dalhousie University; 2011. Available from: http://hdl.handle.net/10222/13341


Texas A&M University

3. Li, Jinghua. Design of clock data recovery IC for high speed data communication systems.

Degree: 2009, Texas A&M University

 Demand for low cost Serializer and De-serializer (SerDes) integrated circuits has increased due to the widespread use of Synchronous Optical Network (SONET)/Gigabit Ethernet network and… (more)

Subjects/Keywords: VCO; pll; clock recovery

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APA (6th Edition):

Li, J. (2009). Design of clock data recovery IC for high speed data communication systems. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2396

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Jinghua. “Design of clock data recovery IC for high speed data communication systems.” 2009. Thesis, Texas A&M University. Accessed October 20, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2396.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Jinghua. “Design of clock data recovery IC for high speed data communication systems.” 2009. Web. 20 Oct 2019.

Vancouver:

Li J. Design of clock data recovery IC for high speed data communication systems. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2396.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li J. Design of clock data recovery IC for high speed data communication systems. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2396

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Sacramento

4. Dabhi, Chirag V. Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS.

Degree: MS, Electrical and Electronic Engineering, 2011, California State University – Sacramento

 The aim of this project was to design, simulate and layout a charge pump for a phase locked loop (PLL) FM synthesizer in a 0.5um… (more)

Subjects/Keywords: PLL; Charge pump; Differential amplifier

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APA (6th Edition):

Dabhi, C. V. (2011). Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/859

Chicago Manual of Style (16th Edition):

Dabhi, Chirag V. “Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS.” 2011. Masters Thesis, California State University – Sacramento. Accessed October 20, 2019. http://hdl.handle.net/10211.9/859.

MLA Handbook (7th Edition):

Dabhi, Chirag V. “Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS.” 2011. Web. 20 Oct 2019.

Vancouver:

Dabhi CV. Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2011. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/10211.9/859.

Council of Science Editors:

Dabhi CV. Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS. [Masters Thesis]. California State University – Sacramento; 2011. Available from: http://hdl.handle.net/10211.9/859


Oregon State University

5. Yin, Wenjing. Design techniques for high-performance digital PLLs and CDRs.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as… (more)

Subjects/Keywords: digital PLL; Phase-locked loops

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APA (6th Edition):

Yin, W. (2010). Design techniques for high-performance digital PLLs and CDRs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19407

Chicago Manual of Style (16th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 20, 2019. http://hdl.handle.net/1957/19407.

MLA Handbook (7th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Web. 20 Oct 2019.

Vancouver:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1957/19407.

Council of Science Editors:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/19407


Oregon State University

6. Inti, Rajesh. Highly digital power efficient techniques for serial links.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable… (more)

Subjects/Keywords: Digital PLL; Radio  – Transmitter-receivers

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APA (6th Edition):

Inti, R. (2011). Highly digital power efficient techniques for serial links. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/25855

Chicago Manual of Style (16th Edition):

Inti, Rajesh. “Highly digital power efficient techniques for serial links.” 2011. Doctoral Dissertation, Oregon State University. Accessed October 20, 2019. http://hdl.handle.net/1957/25855.

MLA Handbook (7th Edition):

Inti, Rajesh. “Highly digital power efficient techniques for serial links.” 2011. Web. 20 Oct 2019.

Vancouver:

Inti R. Highly digital power efficient techniques for serial links. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1957/25855.

Council of Science Editors:

Inti R. Highly digital power efficient techniques for serial links. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/25855


UCLA

7. Wong, Chien-Heng. DPLL and Energy Harvesting Circuit for Low-Power and Miniaturized System Applications.

Degree: Electrical Engineering, 2018, UCLA

 As fabrication technology improves, computation ability has increased accordingly and enables new applications such as biomedical and health monitoring system, internet of things (IoT) and… (more)

Subjects/Keywords: Electrical engineering; Energy Harvester; PLL

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APA (6th Edition):

Wong, C. (2018). DPLL and Energy Harvesting Circuit for Low-Power and Miniaturized System Applications. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9fc192n9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wong, Chien-Heng. “DPLL and Energy Harvesting Circuit for Low-Power and Miniaturized System Applications.” 2018. Thesis, UCLA. Accessed October 20, 2019. http://www.escholarship.org/uc/item/9fc192n9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wong, Chien-Heng. “DPLL and Energy Harvesting Circuit for Low-Power and Miniaturized System Applications.” 2018. Web. 20 Oct 2019.

Vancouver:

Wong C. DPLL and Energy Harvesting Circuit for Low-Power and Miniaturized System Applications. [Internet] [Thesis]. UCLA; 2018. [cited 2019 Oct 20]. Available from: http://www.escholarship.org/uc/item/9fc192n9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wong C. DPLL and Energy Harvesting Circuit for Low-Power and Miniaturized System Applications. [Thesis]. UCLA; 2018. Available from: http://www.escholarship.org/uc/item/9fc192n9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Butt, Hadiyah. Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  A phase-locked loop commonly known as PLL is widely used in communication systems. A PLL is used in radio, telecommunications, modulation and demodulation. It… (more)

Subjects/Keywords: ADPLL; PLL; DCO; TDC

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APA (6th Edition):

Butt, H. (2013). Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87158

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Butt, Hadiyah. “Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band.” 2013. Thesis, Linköping UniversityLinköping University. Accessed October 20, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87158.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Butt, Hadiyah. “Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band.” 2013. Web. 20 Oct 2019.

Vancouver:

Butt H. Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2019 Oct 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87158.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Butt H. Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87158

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

9. Donmez, A. WideBand PLL as a clock multiplier:.

Degree: 2009, Delft University of Technology

 In this study, the theory, design and analysis of PLL circuits are examined and a 4.9GHz ~ 5.9GHz Wideband CMOS PLL Frequency Synthesizer is designed… (more)

Subjects/Keywords: Wide Band; PLL; Clock Multiplier

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APA (6th Edition):

Donmez, A. (2009). WideBand PLL as a clock multiplier:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:026c9807-3632-4272-b69f-a3b6f5452607

Chicago Manual of Style (16th Edition):

Donmez, A. “WideBand PLL as a clock multiplier:.” 2009. Masters Thesis, Delft University of Technology. Accessed October 20, 2019. http://resolver.tudelft.nl/uuid:026c9807-3632-4272-b69f-a3b6f5452607.

MLA Handbook (7th Edition):

Donmez, A. “WideBand PLL as a clock multiplier:.” 2009. Web. 20 Oct 2019.

Vancouver:

Donmez A. WideBand PLL as a clock multiplier:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2019 Oct 20]. Available from: http://resolver.tudelft.nl/uuid:026c9807-3632-4272-b69f-a3b6f5452607.

Council of Science Editors:

Donmez A. WideBand PLL as a clock multiplier:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:026c9807-3632-4272-b69f-a3b6f5452607


Texas A&M University

10. Attah, Hubert. A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL).

Degree: MS, Electrical Engineering, 2016, Texas A&M University

 Frequency synthesizers have become a crucial building block in the evolution of modern communication systems and consumer electronics. The spectral purity performance of frequency synthesizers… (more)

Subjects/Keywords: CMOS RF; PLL; Wideband; Fractional-N PLL; SSPLL; DTC; DCL; DILF

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APA (6th Edition):

Attah, H. (2016). A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL). (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156859

Chicago Manual of Style (16th Edition):

Attah, Hubert. “A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL).” 2016. Masters Thesis, Texas A&M University. Accessed October 20, 2019. http://hdl.handle.net/1969.1/156859.

MLA Handbook (7th Edition):

Attah, Hubert. “A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL).” 2016. Web. 20 Oct 2019.

Vancouver:

Attah H. A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL). [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1969.1/156859.

Council of Science Editors:

Attah H. A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL). [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156859


University of Alberta

11. Woinowsky-Krieger, Alexis. Adaptive phase synchronization techniques for unbalanced and distorted three-phase voltage system.

Degree: PhD, Department of Electrical and Computer Engineering, 2010, University of Alberta

 Interfacing and operating AC power electronic systems requires rapid and accurate estimation of the phase angle of the power source, and specifically of the positive… (more)

Subjects/Keywords: unbalance; ASAE; H-NSASAE-PLL; adaptive; synchronization; PLL; PNSF

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APA (6th Edition):

Woinowsky-Krieger, A. (2010). Adaptive phase synchronization techniques for unbalanced and distorted three-phase voltage system. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/pc289k02c

Chicago Manual of Style (16th Edition):

Woinowsky-Krieger, Alexis. “Adaptive phase synchronization techniques for unbalanced and distorted three-phase voltage system.” 2010. Doctoral Dissertation, University of Alberta. Accessed October 20, 2019. https://era.library.ualberta.ca/files/pc289k02c.

MLA Handbook (7th Edition):

Woinowsky-Krieger, Alexis. “Adaptive phase synchronization techniques for unbalanced and distorted three-phase voltage system.” 2010. Web. 20 Oct 2019.

Vancouver:

Woinowsky-Krieger A. Adaptive phase synchronization techniques for unbalanced and distorted three-phase voltage system. [Internet] [Doctoral dissertation]. University of Alberta; 2010. [cited 2019 Oct 20]. Available from: https://era.library.ualberta.ca/files/pc289k02c.

Council of Science Editors:

Woinowsky-Krieger A. Adaptive phase synchronization techniques for unbalanced and distorted three-phase voltage system. [Doctoral Dissertation]. University of Alberta; 2010. Available from: https://era.library.ualberta.ca/files/pc289k02c


Universidade Federal de Santa Maria

12. Evandro Palma. A PRECISÃO POSSÍVEL COM GPS L1-C/A EM GEORREFERENCIAMENTO: O DESAFIO DO MULTICAMINHO.

Degree: 2005, Universidade Federal de Santa Maria

Desde a criação do sistema Navstar/GPS, várias fontes de erros nas observáveis foram sendo identificadas e estudadas pela comunidade científica, tais como a solução de… (more)

Subjects/Keywords: GPS; multicaminho; DLL; PLL; GEOCIENCIAS; GPS; multipath; DLL; PLL

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APA (6th Edition):

Palma, E. (2005). A PRECISÃO POSSÍVEL COM GPS L1-C/A EM GEORREFERENCIAMENTO: O DESAFIO DO MULTICAMINHO. (Thesis). Universidade Federal de Santa Maria. Retrieved from http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=1652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Palma, Evandro. “A PRECISÃO POSSÍVEL COM GPS L1-C/A EM GEORREFERENCIAMENTO: O DESAFIO DO MULTICAMINHO.” 2005. Thesis, Universidade Federal de Santa Maria. Accessed October 20, 2019. http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=1652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Palma, Evandro. “A PRECISÃO POSSÍVEL COM GPS L1-C/A EM GEORREFERENCIAMENTO: O DESAFIO DO MULTICAMINHO.” 2005. Web. 20 Oct 2019.

Vancouver:

Palma E. A PRECISÃO POSSÍVEL COM GPS L1-C/A EM GEORREFERENCIAMENTO: O DESAFIO DO MULTICAMINHO. [Internet] [Thesis]. Universidade Federal de Santa Maria; 2005. [cited 2019 Oct 20]. Available from: http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=1652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Palma E. A PRECISÃO POSSÍVEL COM GPS L1-C/A EM GEORREFERENCIAMENTO: O DESAFIO DO MULTICAMINHO. [Thesis]. Universidade Federal de Santa Maria; 2005. Available from: http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=1652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. 町田, 秀和. PLLを用いた高精度モーション制御とそのディジタル実現 : High-precision Motion Control Using PLL and Its Digital Implementation.

Degree: 博士(情報工学), 2017, Kyushu Institute of Technology / 九州工業大学

九州工業大学博士学位論文 学位記番号:情工博甲第267号 学位授与年月日:平成24年6月30日

第1章 序論|第2章 PLL|第3章 PLLモータ速度制御系|第4章 2重PLLモータ速度制御系|第5章 PLLとD繰返しによる高精度回転速度制御|第6章 結論

平成24年度

Advisors/Committee Members: 延山, 英沢.

Subjects/Keywords: PLL; Dual-loop PLL; Repetitive control; Motion control; FPGA

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APA (6th Edition):

町田, . (2017). PLLを用いた高精度モーション制御とそのディジタル実現 : High-precision Motion Control Using PLL and Its Digital Implementation. (Thesis). Kyushu Institute of Technology / 九州工業大学. Retrieved from http://hdl.handle.net/10228/4956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

町田, 秀和. “PLLを用いた高精度モーション制御とそのディジタル実現 : High-precision Motion Control Using PLL and Its Digital Implementation.” 2017. Thesis, Kyushu Institute of Technology / 九州工業大学. Accessed October 20, 2019. http://hdl.handle.net/10228/4956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

町田, 秀和. “PLLを用いた高精度モーション制御とそのディジタル実現 : High-precision Motion Control Using PLL and Its Digital Implementation.” 2017. Web. 20 Oct 2019.

Vancouver:

町田 . PLLを用いた高精度モーション制御とそのディジタル実現 : High-precision Motion Control Using PLL and Its Digital Implementation. [Internet] [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/10228/4956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

町田 . PLLを用いた高精度モーション制御とそのディジタル実現 : High-precision Motion Control Using PLL and Its Digital Implementation. [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. Available from: http://hdl.handle.net/10228/4956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ITESO – Universidad Jesuita de Guadalajara

14. Guzmán-Rosales, Gustavo. Formación complementaria en área de concentración de diseño de circuitos integrados analógicos .

Degree: 2015, ITESO – Universidad Jesuita de Guadalajara

Subjects/Keywords: PLL; Interpolador; Layout

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APA (6th Edition):

Guzmán-Rosales, G. (2015). Formación complementaria en área de concentración de diseño de circuitos integrados analógicos . (Thesis). ITESO – Universidad Jesuita de Guadalajara. Retrieved from http://hdl.handle.net/11117/3748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guzmán-Rosales, Gustavo. “Formación complementaria en área de concentración de diseño de circuitos integrados analógicos .” 2015. Thesis, ITESO – Universidad Jesuita de Guadalajara. Accessed October 20, 2019. http://hdl.handle.net/11117/3748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guzmán-Rosales, Gustavo. “Formación complementaria en área de concentración de diseño de circuitos integrados analógicos .” 2015. Web. 20 Oct 2019.

Vancouver:

Guzmán-Rosales G. Formación complementaria en área de concentración de diseño de circuitos integrados analógicos . [Internet] [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2015. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/11117/3748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guzmán-Rosales G. Formación complementaria en área de concentración de diseño de circuitos integrados analógicos . [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2015. Available from: http://hdl.handle.net/11117/3748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Ferruzzo Correa, Diego Paolo. Malha síncrona digital \"Tanlock\" com estimação de frequência e ganho adaptativo para convergência rápida.

Degree: Mestrado, Engenharia de Sistemas, 2011, University of São Paulo

Nas últimas três décadas os phase locked loops (PLLs) totalmente digitais têm recebido muita atenção devido, principalmente, às vantagens que eles oferecem em comparação aos… (more)

Subjects/Keywords: Adaptive PLL; Digital PLL; Digital Tanlock loop; Dinâmica não-linear; Fixed-point theorems; Malha Digital "Tanlock"; Non-linear dynamic; PLL adaptativo; PLL digital; Teoremas de ponto fixo

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ferruzzo Correa, D. P. (2011). Malha síncrona digital \"Tanlock\" com estimação de frequência e ganho adaptativo para convergência rápida. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3139/tde-11042011-141428/ ;

Chicago Manual of Style (16th Edition):

Ferruzzo Correa, Diego Paolo. “Malha síncrona digital \"Tanlock\" com estimação de frequência e ganho adaptativo para convergência rápida.” 2011. Masters Thesis, University of São Paulo. Accessed October 20, 2019. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-11042011-141428/ ;.

MLA Handbook (7th Edition):

Ferruzzo Correa, Diego Paolo. “Malha síncrona digital \"Tanlock\" com estimação de frequência e ganho adaptativo para convergência rápida.” 2011. Web. 20 Oct 2019.

Vancouver:

Ferruzzo Correa DP. Malha síncrona digital \"Tanlock\" com estimação de frequência e ganho adaptativo para convergência rápida. [Internet] [Masters thesis]. University of São Paulo; 2011. [cited 2019 Oct 20]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3139/tde-11042011-141428/ ;.

Council of Science Editors:

Ferruzzo Correa DP. Malha síncrona digital \"Tanlock\" com estimação de frequência e ganho adaptativo para convergência rápida. [Masters Thesis]. University of São Paulo; 2011. Available from: http://www.teses.usp.br/teses/disponiveis/3/3139/tde-11042011-141428/ ;

16. Luis Claudio Gambôa Lopes. EXPERIMENTAL PHOTOVOLTAIC SYSTEM OF ELECTRIC ENERGY GENERATION SHUNT CONNECTED TO THE AC NETWORK.

Degree: 2006, Universidade Federal de Juiz de Fora

Esta dissertação descreve as etapas de desenvolvimento de um sistema experimental de geração de energia elétrica de 30 kW baseado em painéis solares fotovoltaicos montado… (more)

Subjects/Keywords: emulador; geração elétrica fotovoltáica; DSP; Engenharias; PLL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lopes, L. C. G. (2006). EXPERIMENTAL PHOTOVOLTAIC SYSTEM OF ELECTRIC ENERGY GENERATION SHUNT CONNECTED TO THE AC NETWORK. (Thesis). Universidade Federal de Juiz de Fora. Retrieved from http://www.bdtd.ufjf.br/tde_busca/arquivo.php?codArquivo=3

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lopes, Luis Claudio Gambôa. “EXPERIMENTAL PHOTOVOLTAIC SYSTEM OF ELECTRIC ENERGY GENERATION SHUNT CONNECTED TO THE AC NETWORK.” 2006. Thesis, Universidade Federal de Juiz de Fora. Accessed October 20, 2019. http://www.bdtd.ufjf.br/tde_busca/arquivo.php?codArquivo=3.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lopes, Luis Claudio Gambôa. “EXPERIMENTAL PHOTOVOLTAIC SYSTEM OF ELECTRIC ENERGY GENERATION SHUNT CONNECTED TO THE AC NETWORK.” 2006. Web. 20 Oct 2019.

Vancouver:

Lopes LCG. EXPERIMENTAL PHOTOVOLTAIC SYSTEM OF ELECTRIC ENERGY GENERATION SHUNT CONNECTED TO THE AC NETWORK. [Internet] [Thesis]. Universidade Federal de Juiz de Fora; 2006. [cited 2019 Oct 20]. Available from: http://www.bdtd.ufjf.br/tde_busca/arquivo.php?codArquivo=3.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lopes LCG. EXPERIMENTAL PHOTOVOLTAIC SYSTEM OF ELECTRIC ENERGY GENERATION SHUNT CONNECTED TO THE AC NETWORK. [Thesis]. Universidade Federal de Juiz de Fora; 2006. Available from: http://www.bdtd.ufjf.br/tde_busca/arquivo.php?codArquivo=3

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

17. Thomas, Renji George. A Full Digital Phase Locked Loop.

Degree: MS, Electrical and Computer Engineering, 2010, The Ohio State University

 In this thesis a Full Digital Phase Locked Loop is designed and implemented in 0.13um technology node from TSMC. This full digital PLL is more… (more)

Subjects/Keywords: Electrical Engineering; Digital PLL; DPLL; Clock Distribution

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Thomas, R. G. (2010). A Full Digital Phase Locked Loop. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406

Chicago Manual of Style (16th Edition):

Thomas, Renji George. “A Full Digital Phase Locked Loop.” 2010. Masters Thesis, The Ohio State University. Accessed October 20, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.

MLA Handbook (7th Edition):

Thomas, Renji George. “A Full Digital Phase Locked Loop.” 2010. Web. 20 Oct 2019.

Vancouver:

Thomas RG. A Full Digital Phase Locked Loop. [Internet] [Masters thesis]. The Ohio State University; 2010. [cited 2019 Oct 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.

Council of Science Editors:

Thomas RG. A Full Digital Phase Locked Loop. [Masters Thesis]. The Ohio State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406


University of Toronto

18. Fard, Miad. An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters.

Degree: 2016, University of Toronto

In this thesis, two Phase-Locked-Loop (PLL) based synchronization schemes are introduced and applied to a bi-directional Dual-Active-Bridge (DAB) dc-dc converter with an input voltage up… (more)

Subjects/Keywords: DAB; Isolated; Photovoltaics; PLL; Programmable; Synchronization; 0544

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APA (6th Edition):

Fard, M. (2016). An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/72693

Chicago Manual of Style (16th Edition):

Fard, Miad. “An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters.” 2016. Masters Thesis, University of Toronto. Accessed October 20, 2019. http://hdl.handle.net/1807/72693.

MLA Handbook (7th Edition):

Fard, Miad. “An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters.” 2016. Web. 20 Oct 2019.

Vancouver:

Fard M. An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters. [Internet] [Masters thesis]. University of Toronto; 2016. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1807/72693.

Council of Science Editors:

Fard M. An Integrated Programmable Wide-range PLL for Switching Synchronization in Isolated DC-DC Converters. [Masters Thesis]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/72693


Texas A&M University

19. Lee, Sang Hun. A Fully Integrated Multi-Band Multi-Output Synthesizer with Wide-Locking-Range 1/3 Injection Locked Divider Utilizing Self-Injection Technique for Multi-Band Microwave Systems.

Degree: 2012, Texas A&M University

 This dissertation reports the development of a new multi-band multi-output synthesizer, 1/2 dual-injection locked divider, 1/3 injection-locked divider with phase-tuning, and 1/3 injection-locked divider with… (more)

Subjects/Keywords: Multi-Output PLL; Self-Injection; Multi-Band PLL; 1/3 Injection Locked Divider; ILFD

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APA (6th Edition):

Lee, S. H. (2012). A Fully Integrated Multi-Band Multi-Output Synthesizer with Wide-Locking-Range 1/3 Injection Locked Divider Utilizing Self-Injection Technique for Multi-Band Microwave Systems. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11477

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Sang Hun. “A Fully Integrated Multi-Band Multi-Output Synthesizer with Wide-Locking-Range 1/3 Injection Locked Divider Utilizing Self-Injection Technique for Multi-Band Microwave Systems.” 2012. Thesis, Texas A&M University. Accessed October 20, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11477.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Sang Hun. “A Fully Integrated Multi-Band Multi-Output Synthesizer with Wide-Locking-Range 1/3 Injection Locked Divider Utilizing Self-Injection Technique for Multi-Band Microwave Systems.” 2012. Web. 20 Oct 2019.

Vancouver:

Lee SH. A Fully Integrated Multi-Band Multi-Output Synthesizer with Wide-Locking-Range 1/3 Injection Locked Divider Utilizing Self-Injection Technique for Multi-Band Microwave Systems. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11477.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee SH. A Fully Integrated Multi-Band Multi-Output Synthesizer with Wide-Locking-Range 1/3 Injection Locked Divider Utilizing Self-Injection Technique for Multi-Band Microwave Systems. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11477

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Grenoble

20. Kieffer, Julien. Contribution au dimensionnement des PLL pour des modulations polaires larges bandes : Contribution to PLLs' sizing for wideband polar modulations.

Degree: Docteur es, Optique et radiofréquence, 2014, Université de Grenoble

Les problématiques d'intégrabilité et de consommation des circuits sont au centre des spécifications des émetteurs pour la téléphonie mobile. L'architecture polaire est une alternative intéressante… (more)

Subjects/Keywords: Modulation polaire; Large bande; PLL; LTE; Polar modulation; Wideband; PLL; LTE; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kieffer, J. (2014). Contribution au dimensionnement des PLL pour des modulations polaires larges bandes : Contribution to PLLs' sizing for wideband polar modulations. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2014GRENT026

Chicago Manual of Style (16th Edition):

Kieffer, Julien. “Contribution au dimensionnement des PLL pour des modulations polaires larges bandes : Contribution to PLLs' sizing for wideband polar modulations.” 2014. Doctoral Dissertation, Université de Grenoble. Accessed October 20, 2019. http://www.theses.fr/2014GRENT026.

MLA Handbook (7th Edition):

Kieffer, Julien. “Contribution au dimensionnement des PLL pour des modulations polaires larges bandes : Contribution to PLLs' sizing for wideband polar modulations.” 2014. Web. 20 Oct 2019.

Vancouver:

Kieffer J. Contribution au dimensionnement des PLL pour des modulations polaires larges bandes : Contribution to PLLs' sizing for wideband polar modulations. [Internet] [Doctoral dissertation]. Université de Grenoble; 2014. [cited 2019 Oct 20]. Available from: http://www.theses.fr/2014GRENT026.

Council of Science Editors:

Kieffer J. Contribution au dimensionnement des PLL pour des modulations polaires larges bandes : Contribution to PLLs' sizing for wideband polar modulations. [Doctoral Dissertation]. Université de Grenoble; 2014. Available from: http://www.theses.fr/2014GRENT026


Brno University of Technology

21. Sabol, Martin. FM vysílač APRS telemetrických dat v pásmu 144MHz .

Degree: 2010, Brno University of Technology

 Tato práce se zabývá rozborem protokolu automatického pozičního systému APRS pro účely telemetrie. Je rozebrána struktura nejdůležitějších rámců a jejich použití. Věnuje se zpracování GPS… (more)

Subjects/Keywords: APRS; AFSK; Mikropočítač; PLL; VCO; GPS; APRS; AFSK; Microcontroller; PLL; VCO; GPS

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APA (6th Edition):

Sabol, M. (2010). FM vysílač APRS telemetrických dat v pásmu 144MHz . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/2303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sabol, Martin. “FM vysílač APRS telemetrických dat v pásmu 144MHz .” 2010. Thesis, Brno University of Technology. Accessed October 20, 2019. http://hdl.handle.net/11012/2303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sabol, Martin. “FM vysílač APRS telemetrických dat v pásmu 144MHz .” 2010. Web. 20 Oct 2019.

Vancouver:

Sabol M. FM vysílač APRS telemetrických dat v pásmu 144MHz . [Internet] [Thesis]. Brno University of Technology; 2010. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/11012/2303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sabol M. FM vysílač APRS telemetrických dat v pásmu 144MHz . [Thesis]. Brno University of Technology; 2010. Available from: http://hdl.handle.net/11012/2303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

22. Turker, Didem 1981-. Frequency Synthesis in Wireless and Wireline Systems.

Degree: 2010, Texas A&M University

 First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is… (more)

Subjects/Keywords: wireline systems; wireless systems; TDC; DCO; DPLL; ADPLL; digital PLL; all digital PLL; delay model; DCVSL; VCO; ring oscillator; prescaler; dual modulus prescaler; frequency divider; PLL; frequency synthesizer; Frequency Synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Turker, D. 1. (2010). Frequency Synthesis in Wireless and Wireline Systems. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148459

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Turker, Didem 1981-. “Frequency Synthesis in Wireless and Wireline Systems.” 2010. Thesis, Texas A&M University. Accessed October 20, 2019. http://hdl.handle.net/1969.1/148459.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Turker, Didem 1981-. “Frequency Synthesis in Wireless and Wireline Systems.” 2010. Web. 20 Oct 2019.

Vancouver:

Turker D1. Frequency Synthesis in Wireless and Wireline Systems. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/1969.1/148459.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Turker D1. Frequency Synthesis in Wireless and Wireline Systems. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/148459

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kyoto University / 京都大学

23. Kim, Sinnyoung. Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計.

Degree: 博士(情報学), 2014, Kyoto University / 京都大学

新制・課程博士

甲第18413号

情博第528号

Subjects/Keywords: Phase-Locked Loop (PLL); Soft error; Radiation-Hardened PLL (RH-PLL)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, S. (2014). Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/188872 ; http://dx.doi.org/10.14989/doctor.k18413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Sinnyoung. “Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計.” 2014. Thesis, Kyoto University / 京都大学. Accessed October 20, 2019. http://hdl.handle.net/2433/188872 ; http://dx.doi.org/10.14989/doctor.k18413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Sinnyoung. “Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計.” 2014. Web. 20 Oct 2019.

Vancouver:

Kim S. Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計. [Internet] [Thesis]. Kyoto University / 京都大学; 2014. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/2433/188872 ; http://dx.doi.org/10.14989/doctor.k18413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim S. Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計. [Thesis]. Kyoto University / 京都大学; 2014. Available from: http://hdl.handle.net/2433/188872 ; http://dx.doi.org/10.14989/doctor.k18413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Melo, José Luís Lisboa Brandão de. Malhas de captura de fase para a sincronização e processamento de sinais da rede elétrica.

Degree: 2017, Repositório Científico do Instituto Politécnico de Lisboa

Dissertação para a obtenção do grau de Mestre em Engenharia Eletrotécnica Ramo de Automação e Eletrónica Industrial

O presente trabalho focou-se no desenvolvimento de uma… (more)

Subjects/Keywords: Malha de captura de fase (PLL); Detetores de fase; Oscilador controlado por tensão (VCO); Dimensionamento do PLL; Implementação

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APA (6th Edition):

Melo, J. L. L. B. d. (2017). Malhas de captura de fase para a sincronização e processamento de sinais da rede elétrica. (Thesis). Repositório Científico do Instituto Politécnico de Lisboa. Retrieved from https://www.rcaap.pt/detail.jsp?id=oai:repositorio.ipl.pt:10400.21/7046

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Melo, José Luís Lisboa Brandão de. “Malhas de captura de fase para a sincronização e processamento de sinais da rede elétrica.” 2017. Thesis, Repositório Científico do Instituto Politécnico de Lisboa. Accessed October 20, 2019. https://www.rcaap.pt/detail.jsp?id=oai:repositorio.ipl.pt:10400.21/7046.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Melo, José Luís Lisboa Brandão de. “Malhas de captura de fase para a sincronização e processamento de sinais da rede elétrica.” 2017. Web. 20 Oct 2019.

Vancouver:

Melo JLLBd. Malhas de captura de fase para a sincronização e processamento de sinais da rede elétrica. [Internet] [Thesis]. Repositório Científico do Instituto Politécnico de Lisboa; 2017. [cited 2019 Oct 20]. Available from: https://www.rcaap.pt/detail.jsp?id=oai:repositorio.ipl.pt:10400.21/7046.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Melo JLLBd. Malhas de captura de fase para a sincronização e processamento de sinais da rede elétrica. [Thesis]. Repositório Científico do Instituto Politécnico de Lisboa; 2017. Available from: https://www.rcaap.pt/detail.jsp?id=oai:repositorio.ipl.pt:10400.21/7046

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Orsatti, Fernando Moya. Redes mutuamente conectadas de DPLLs: modelagem, simulação e otimização.

Degree: PhD, Engenharia de Sistemas, 2007, University of São Paulo

A distribuição de sinais de tempo é um fator essencial em muitas aplicações de engenharia como, por exemplo, redes de telecomunicações, circuitos digitais integrados e… (more)

Subjects/Keywords: Dynamical systems; Mutually connected networks; PLL; PLL; Redes de sincronismo; Redes mutuamente conectadas; Sistemas dinâmicos; Synchronization networks

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Orsatti, F. M. (2007). Redes mutuamente conectadas de DPLLs: modelagem, simulação e otimização. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3139/tde-04072007-150219/ ;

Chicago Manual of Style (16th Edition):

Orsatti, Fernando Moya. “Redes mutuamente conectadas de DPLLs: modelagem, simulação e otimização.” 2007. Doctoral Dissertation, University of São Paulo. Accessed October 20, 2019. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-04072007-150219/ ;.

MLA Handbook (7th Edition):

Orsatti, Fernando Moya. “Redes mutuamente conectadas de DPLLs: modelagem, simulação e otimização.” 2007. Web. 20 Oct 2019.

Vancouver:

Orsatti FM. Redes mutuamente conectadas de DPLLs: modelagem, simulação e otimização. [Internet] [Doctoral dissertation]. University of São Paulo; 2007. [cited 2019 Oct 20]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3139/tde-04072007-150219/ ;.

Council of Science Editors:

Orsatti FM. Redes mutuamente conectadas de DPLLs: modelagem, simulação e otimização. [Doctoral Dissertation]. University of São Paulo; 2007. Available from: http://www.teses.usp.br/teses/disponiveis/3/3139/tde-04072007-150219/ ;


Université de Bordeaux I

26. Regimbal, Nicolas. Study of fractional frequency synthesizers for high data rate applications : Contribution à l'étude de synthétiseurs de fréquence fractionnaires pour applications à haut débit.

Degree: Docteur es, Electronique, 2011, Université de Bordeaux I

Cette thèse traite de synthétiseurs de fréquence, et plus précisément de diviseurs de fréquence fractionnaires qui sont des blocs critiques en radiocommunications. Une nouvelle méthode… (more)

Subjects/Keywords: Synthèse de fréquence; Pll; Diviseur de fréquence fractionnaire; Modulation directe; Fractional frequency synthesis; Pll; Fractional frequency divider; Direct modulation

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APA (6th Edition):

Regimbal, N. (2011). Study of fractional frequency synthesizers for high data rate applications : Contribution à l'étude de synthétiseurs de fréquence fractionnaires pour applications à haut débit. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2011BOR14292

Chicago Manual of Style (16th Edition):

Regimbal, Nicolas. “Study of fractional frequency synthesizers for high data rate applications : Contribution à l'étude de synthétiseurs de fréquence fractionnaires pour applications à haut débit.” 2011. Doctoral Dissertation, Université de Bordeaux I. Accessed October 20, 2019. http://www.theses.fr/2011BOR14292.

MLA Handbook (7th Edition):

Regimbal, Nicolas. “Study of fractional frequency synthesizers for high data rate applications : Contribution à l'étude de synthétiseurs de fréquence fractionnaires pour applications à haut débit.” 2011. Web. 20 Oct 2019.

Vancouver:

Regimbal N. Study of fractional frequency synthesizers for high data rate applications : Contribution à l'étude de synthétiseurs de fréquence fractionnaires pour applications à haut débit. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2011. [cited 2019 Oct 20]. Available from: http://www.theses.fr/2011BOR14292.

Council of Science Editors:

Regimbal N. Study of fractional frequency synthesizers for high data rate applications : Contribution à l'étude de synthétiseurs de fréquence fractionnaires pour applications à haut débit. [Doctoral Dissertation]. Université de Bordeaux I; 2011. Available from: http://www.theses.fr/2011BOR14292


Université de Bordeaux I

27. Béraud-Sudreau, Quentin. Étude, conception optimisée et réalisation d’un prototype ASIC d’une extraction d’horloge haut débit pour une nouvelle génération de liaison à 80 Gbit/sec. : Analysis and design of an 80 Gbit/sec clock and data recovery prototype.

Degree: Docteur es, Electronique, 2013, Université de Bordeaux I

La demande croissante de toujours plus de débit pour les télécommunications entraine une augmentation de la fréquence de fonctionnement des liaisons séries. Cette demande se… (more)

Subjects/Keywords: CDR; Oscillateur verrouillé en injection; Restitution d'horloge et de données; PLL; CDR; Injection locked oscillator; Clock and data recovery; PLL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Béraud-Sudreau, Q. (2013). Étude, conception optimisée et réalisation d’un prototype ASIC d’une extraction d’horloge haut débit pour une nouvelle génération de liaison à 80 Gbit/sec. : Analysis and design of an 80 Gbit/sec clock and data recovery prototype. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2013BOR14765

Chicago Manual of Style (16th Edition):

Béraud-Sudreau, Quentin. “Étude, conception optimisée et réalisation d’un prototype ASIC d’une extraction d’horloge haut débit pour une nouvelle génération de liaison à 80 Gbit/sec. : Analysis and design of an 80 Gbit/sec clock and data recovery prototype.” 2013. Doctoral Dissertation, Université de Bordeaux I. Accessed October 20, 2019. http://www.theses.fr/2013BOR14765.

MLA Handbook (7th Edition):

Béraud-Sudreau, Quentin. “Étude, conception optimisée et réalisation d’un prototype ASIC d’une extraction d’horloge haut débit pour une nouvelle génération de liaison à 80 Gbit/sec. : Analysis and design of an 80 Gbit/sec clock and data recovery prototype.” 2013. Web. 20 Oct 2019.

Vancouver:

Béraud-Sudreau Q. Étude, conception optimisée et réalisation d’un prototype ASIC d’une extraction d’horloge haut débit pour une nouvelle génération de liaison à 80 Gbit/sec. : Analysis and design of an 80 Gbit/sec clock and data recovery prototype. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2013. [cited 2019 Oct 20]. Available from: http://www.theses.fr/2013BOR14765.

Council of Science Editors:

Béraud-Sudreau Q. Étude, conception optimisée et réalisation d’un prototype ASIC d’une extraction d’horloge haut débit pour une nouvelle génération de liaison à 80 Gbit/sec. : Analysis and design of an 80 Gbit/sec clock and data recovery prototype. [Doctoral Dissertation]. Université de Bordeaux I; 2013. Available from: http://www.theses.fr/2013BOR14765


Université de Grenoble

28. El Issati, Oussama. Oscillateurs asynchrones en anneau : de la théorie à la pratique : Ring oscillators and asynchronous delay lines : applications to PLLs and "Clock recovery" systems.

Degree: Docteur es, Micro et nanoélectronique, 2011, Université de Grenoble

Les oscillateurs sont des blocs qui figurent dans presque tous les circuits. En effet,ils sont utilisés pour générer les signaux de synchronisation (les horloges), les… (more)

Subjects/Keywords: PLL; VCO; Oscillateurs asynchrones; Faible bruit de phase; PLL; VCO; Asynchronous rings; Low phase noise; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

El Issati, O. (2011). Oscillateurs asynchrones en anneau : de la théorie à la pratique : Ring oscillators and asynchronous delay lines : applications to PLLs and "Clock recovery" systems. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2011GRENT081

Chicago Manual of Style (16th Edition):

El Issati, Oussama. “Oscillateurs asynchrones en anneau : de la théorie à la pratique : Ring oscillators and asynchronous delay lines : applications to PLLs and "Clock recovery" systems.” 2011. Doctoral Dissertation, Université de Grenoble. Accessed October 20, 2019. http://www.theses.fr/2011GRENT081.

MLA Handbook (7th Edition):

El Issati, Oussama. “Oscillateurs asynchrones en anneau : de la théorie à la pratique : Ring oscillators and asynchronous delay lines : applications to PLLs and "Clock recovery" systems.” 2011. Web. 20 Oct 2019.

Vancouver:

El Issati O. Oscillateurs asynchrones en anneau : de la théorie à la pratique : Ring oscillators and asynchronous delay lines : applications to PLLs and "Clock recovery" systems. [Internet] [Doctoral dissertation]. Université de Grenoble; 2011. [cited 2019 Oct 20]. Available from: http://www.theses.fr/2011GRENT081.

Council of Science Editors:

El Issati O. Oscillateurs asynchrones en anneau : de la théorie à la pratique : Ring oscillators and asynchronous delay lines : applications to PLLs and "Clock recovery" systems. [Doctoral Dissertation]. Université de Grenoble; 2011. Available from: http://www.theses.fr/2011GRENT081

29. Fonseca, Alexandre. Conception et réalisation de circuits de génération de fréquence en technologie FDSOI 28nm : Design and implementation of frequency generating circuits in FDSOI 28nm.

Degree: Docteur es, Électronique pour objets connectés, 2015, Nice

Le déploiement à grande échelle de l’internet des objets nécessite le développement de systèmes de radiocommunication plus économes en énergie, dont le circuit de génération… (more)

Subjects/Keywords: PLL Fractionnaire; TDC-Less; Phase-Switching; RO; FDSOI; Fractional PLL; TDC-Less; Phase-Switching; RO; FDSOI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fonseca, A. (2015). Conception et réalisation de circuits de génération de fréquence en technologie FDSOI 28nm : Design and implementation of frequency generating circuits in FDSOI 28nm. (Doctoral Dissertation). Nice. Retrieved from http://www.theses.fr/2015NICE4100

Chicago Manual of Style (16th Edition):

Fonseca, Alexandre. “Conception et réalisation de circuits de génération de fréquence en technologie FDSOI 28nm : Design and implementation of frequency generating circuits in FDSOI 28nm.” 2015. Doctoral Dissertation, Nice. Accessed October 20, 2019. http://www.theses.fr/2015NICE4100.

MLA Handbook (7th Edition):

Fonseca, Alexandre. “Conception et réalisation de circuits de génération de fréquence en technologie FDSOI 28nm : Design and implementation of frequency generating circuits in FDSOI 28nm.” 2015. Web. 20 Oct 2019.

Vancouver:

Fonseca A. Conception et réalisation de circuits de génération de fréquence en technologie FDSOI 28nm : Design and implementation of frequency generating circuits in FDSOI 28nm. [Internet] [Doctoral dissertation]. Nice; 2015. [cited 2019 Oct 20]. Available from: http://www.theses.fr/2015NICE4100.

Council of Science Editors:

Fonseca A. Conception et réalisation de circuits de génération de fréquence en technologie FDSOI 28nm : Design and implementation of frequency generating circuits in FDSOI 28nm. [Doctoral Dissertation]. Nice; 2015. Available from: http://www.theses.fr/2015NICE4100


Brno University of Technology

30. Málek, Miroslav. Počítačem řízený PLL syntezátor .

Degree: 2011, Brno University of Technology

 Cílem této práce je realizovat počítačem řízený PLL syntezátor využívající rozhraní USB. Pro připojení PLL syntezátoru k počítači byl použit integrovaný obvod FT232RL. Následně byl… (more)

Subjects/Keywords: Kmitočtový syntezátor; napětím řízený oscilátor; USB; C#; PLL; Frequency synthesizer; voltage-controlled ocsillator; USB; C#; PLL.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Málek, M. (2011). Počítačem řízený PLL syntezátor . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/6589

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Málek, Miroslav. “Počítačem řízený PLL syntezátor .” 2011. Thesis, Brno University of Technology. Accessed October 20, 2019. http://hdl.handle.net/11012/6589.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Málek, Miroslav. “Počítačem řízený PLL syntezátor .” 2011. Web. 20 Oct 2019.

Vancouver:

Málek M. Počítačem řízený PLL syntezátor . [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2019 Oct 20]. Available from: http://hdl.handle.net/11012/6589.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Málek M. Počítačem řízený PLL syntezátor . [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/6589

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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