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You searched for subject:(PBTI). Showing records 1 – 3 of 3 total matches.

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1. Ahmed, Fahad. Invasive and non-invasive detection of bias temperature instability.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

Invasive and non-invasive methods of BTI monitoring and wearout preemption have been proposed. We propose a novel, simple to use, test structure for NBTI /PBTI monitoring. The proposed structure has an AC and a DC stress mode. Although during stress mode, both PMOS and NMOS devices are stressed, the proposed structure isolates the PBTI and NBTI degradation during test mode. A methodology of converting any data-path into ring oscillator (DPRO) is also presented. To avoid the performance overhead of attaching monitoring circuitry to functional block, a non-invasive scheme for BTI monitoring is presented for sleep transistor based logic families. Since, BTI is a critical issue for memories, a scheme for BTI monitoring of 6T SRAM cell based memories is also presented. We make use of the concept of a DPRO and show how a memory system can be made to oscillate in test mode. The frequency of oscillation is a function of the devices in the cell. After validation of the proposed schemes using extensive simulations, we have also validated the results on silicon. We also introduce the concept of wearout mitigation at the compiler level. Using an example of a register file, we present a preemptive method of wearout mitigation using a compiler directed scheme. Advisors/Committee Members: Milor, Linda S. (advisor), Chatterjee, Abhijit (committee member), Ghovanloo, Maysam (committee member), Orso, Alessandro (committee member), Lim, Sung K. (committee member).

Subjects/Keywords: Wearout; BTI; NBTI; PBTI; Compiler; Monitor; Sensor

…58 FIGURE 35: PBTI DEGRADATION ACROSS DIFFERENT BENCHMARKS… …71 FIGURE 45: NBTI/PBTI TEST FOR BITCELL AND THE ACCESS TIME TEST… …preemption have been proposed. We propose a novel, simple to use, test structure for NBTI /PBTI… …both PMOS and NMOS devices are stressed, the proposed structure isolates the PBTI and NBTI… …instability (NBTI) and in NMOS due to positive bias temperature instability (PBTI… 

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APA (6th Edition):

Ahmed, F. (2014). Invasive and non-invasive detection of bias temperature instability. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52227

Chicago Manual of Style (16th Edition):

Ahmed, Fahad. “Invasive and non-invasive detection of bias temperature instability.” 2014. Doctoral Dissertation, Georgia Tech. Accessed October 17, 2019. http://hdl.handle.net/1853/52227.

MLA Handbook (7th Edition):

Ahmed, Fahad. “Invasive and non-invasive detection of bias temperature instability.” 2014. Web. 17 Oct 2019.

Vancouver:

Ahmed F. Invasive and non-invasive detection of bias temperature instability. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/1853/52227.

Council of Science Editors:

Ahmed F. Invasive and non-invasive detection of bias temperature instability. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/52227


Penn State University

2. Agrawal, Nidhi. Variation Study on Advanced Cmos Systems for Low Voltage Applications.

Degree: PhD, Electrical Engineering, 2015, Penn State University

One of the key challenges in scaling beyond 10nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage (VT) inhibits supply voltage (VCC) scaling. In this work, a comprehensive study of process variations and line edge roughness (LER)/sidewall roughness (SWR) effects in advanced CMOS devices namely Silicon (Si) Bulk n-/p-FinFETs, In0.53Ga0.47As Bulk n-FinFETs, Germanium (Ge) Bulk p-FinFETs and Gallium Antimonide-Indium Arsenide (GaSb-InAs) staggered-gap Heterojunction n-/p-Tunnel FETs (HTFETs) is presented. This study is done using three-dimensional (3D) Technology Computer Aided Design (TCAD) numerical simulations. According to the sensitivity study, FinFET and Tunnel FET (TFET) device parameters are highly susceptible to n width, WFIN, and ultra-thin body thickness, Tb, variations, respectively. Moreover, TFETs show higher variation in device than FinFETs. Additionally, a Monte Carlo study of SWR variation on n- and p-FinFETs show higher 3sigma(VTLin) of In0.53Ga0.47As Bulk n- and Ge Bulk p-FinFETs than their Si counterparts. Further, to study the variation impact on memory circuits, we also simulate 6T and 10T SRAM cells with FinFETs and HTFETs, respectively. Another key challenge with advanced CMOS devices is time-dependent VT degradation due to BTI reliability. Thus, in the second part of this work, a comparative study of Positive Bias Temperature Instability (PBTI) reliability on n-type III-V devices and Negative Bias Temperature Instability (NBTI) reliability on p-type Ge devices is presented. PBTI reliability is studied in InxGa1

Subjects/Keywords: FinFET; TFET; Line Edge Roughness (LER); Line Width Roughness (LWR); SRAM; Rean Static Noise Margin (RSNM); NBTI; PBTI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Agrawal, N. (2015). Variation Study on Advanced Cmos Systems for Low Voltage Applications. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/26674

Chicago Manual of Style (16th Edition):

Agrawal, Nidhi. “Variation Study on Advanced Cmos Systems for Low Voltage Applications.” 2015. Doctoral Dissertation, Penn State University. Accessed October 17, 2019. https://etda.libraries.psu.edu/catalog/26674.

MLA Handbook (7th Edition):

Agrawal, Nidhi. “Variation Study on Advanced Cmos Systems for Low Voltage Applications.” 2015. Web. 17 Oct 2019.

Vancouver:

Agrawal N. Variation Study on Advanced Cmos Systems for Low Voltage Applications. [Internet] [Doctoral dissertation]. Penn State University; 2015. [cited 2019 Oct 17]. Available from: https://etda.libraries.psu.edu/catalog/26674.

Council of Science Editors:

Agrawal N. Variation Study on Advanced Cmos Systems for Low Voltage Applications. [Doctoral Dissertation]. Penn State University; 2015. Available from: https://etda.libraries.psu.edu/catalog/26674

3. Santos, Hugo Fernandes da Silva. Aging sensor for CMOS memory cells.

Degree: 2016, RCAAP

Dissertação de Mestrado, Engenharia e Tecnologia, Instituto Superior de Engenharia, Universidade do Algarve, 2016

As memórias Complementary Metal Oxide Semiconductor (CMOS) ocupam uma percentagem de área significativa nos circuitos integrados e, com o desenvolvimento de tecnologias de fabrico a uma escala cada vez mais reduzida, surgem problemas de performance e de fiabilidade. Efeitos como o BTI (Bias Thermal Instability), TDDB (Time Dependent Dielectric Breakdown), HCI (Hot Carrier Injection), EM (Electromigration), degradam os parâmetros físicos dos transístores de efeito de campo (MOSFET), alterando as suas propriedades elétricas ao longo do tempo. O efeito BTI pode ser subdividido em NBTI (Negative BTI) e PBTI (Positive BTI). O efeito NBTI é dominante no processo de degradação e envelhecimento dos transístores CMOS, afetando os transístores PMOS, enquanto o efeito PBTI assume especial relevância na degradação dos transístores NMOS. A degradação provocada por estes efeitos, manifesta-se nos transístores através do incremento do módulo da tensão de limiar de condução |ℎ| ao longo do tempo. A degradação dos transístores é designada por envelhecimento, sendo estes efeitos cumulativos e possuindo um grande impacto na performance do circuito, em particular se ocorrerem outras variações paramétricas. Outras variações paramétricas adicionais que podem ocorrer são as variações de processo (P), tensão (V) e temperatura (T), ou considerando todas estas variações, e de uma forma genérica, PVTA (Process, Voltage, Temperature and Aging). As células de memória de acesso aleatório (RAM, Random Access Memory), em particular as memórias estáticas (SRAM, Static Random Access Memory) e dinâmicas (DRAM, Dynamic Random Access Memory), possuem tempos de leitura e escrita precisos. Quando ao longo do tempo ocorre o envelhecimento das células de memória, devido à degradação das propriedades dos transístores MOSFET, ocorre também uma degradação da performance das células de memória. A degradação de performance é, portanto, resultado das transições lentas que ocorrem, devido ao envelhecimento dos transístores MOSFET que comutam mais tarde, comparativamente a transístores novos. A degradação de performance nas memórias devido às transições lentas pode traduzir-se em leituras e escritas mais lentas, bem como em alterações na capacidade de armazenamento da memória. Esta propriedade pode ser expressa através da margem de sinal ruído (SNM). O SNM é reduzido com o envelhecimento dos transístores MOSFET e, quando o valor do SNM é baixo, a célula perde a sua capacidade de armazenamento, tornando-se mais vulnerável a fontes de ruído. O SNM é, portanto, um valor que permite efetuar a aferição (benchmarking) e comparar as características da memória perante o envelhecimento ou outras variações paramétricas que possam ocorrer. O envelhecimento das memórias CMOS traduz-se portanto na ocorrência de erros nas memórias ao longo do tempo, o que é indesejável especialmente em sistemas críticos. O trabalho apresentado nesta dissertação tem como objetivo o…

Advisors/Committee Members: Semião, Jorge Filipe Leal Costa.

Subjects/Keywords: Sensor de Envelhecimento e Performance; NBTI; PBTI; SNM; Memórias CMOS; SRAM; Transições Lentas; Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Santos, H. F. d. S. (2016). Aging sensor for CMOS memory cells. (Thesis). RCAAP. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:sapientia.ualg.pt:10400.1/8028

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Santos, Hugo Fernandes da Silva. “Aging sensor for CMOS memory cells.” 2016. Thesis, RCAAP. Accessed October 17, 2019. http://www.rcaap.pt/detail.jsp?id=oai:sapientia.ualg.pt:10400.1/8028.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Santos, Hugo Fernandes da Silva. “Aging sensor for CMOS memory cells.” 2016. Web. 17 Oct 2019.

Vancouver:

Santos HFdS. Aging sensor for CMOS memory cells. [Internet] [Thesis]. RCAAP; 2016. [cited 2019 Oct 17]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:sapientia.ualg.pt:10400.1/8028.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santos HFdS. Aging sensor for CMOS memory cells. [Thesis]. RCAAP; 2016. Available from: http://www.rcaap.pt/detail.jsp?id=oai:sapientia.ualg.pt:10400.1/8028

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.