subject:(Oxide TFTs circuit integration)

University of Manchester

1. Jin, Jidong. Metal-oxide-based electronic devices.

Degree: PhD, 2013, University of Manchester

URL: https://www.research.manchester.ac.uk/portal/en/theses/metaloxidebased-electronic-devices(2ccabdd1-398b-4787-9455-e034f9001867).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.574311

► Metal oxides exhibit a wide range of chemical and electronic properties, making them an extremely interesting subject for numerous applications in modern electronics. The primary… (more)

▼ Metal oxides exhibit a wide range of chemical and electronic properties, making them an extremely interesting subject for numerous applications in modern electronics. The primary goal of this research is to develop metal-oxide-based electronic devices, including thin-film transistors (TFTs), resistance random-access memory (RRAM) and planar nano-devices. This research requires different processing techniques, novel device design concepts and optimisation of materials and devices. The first experiments were carried out to optimise the properties of zinc oxide (ZnO) semiconductors, in particular the carrier concentration, which determines the threshold voltage of the TFTs. Thermal annealing is one common method to affect carrier concentration and most work in the literature reports performing this process in a single-gas environment. In this work, however, annealing was carried out in a combination of air and nitrogen, and it was found that the threshold voltage could be tuned over a wide range of pre-determined values.Further experiments were undertaken to enhance the carrier mobility of ZnO TFTs, which is the most important material quality parameter. By optimising deposition conditions and incorporating a high-k gate dielectric layer, the devices showed saturation mobility values over 50 cm2/Vs at a low operating voltage of 4 V. This is, to our knowledge, one of the highest field-effect mobility values achieved in ZnO-based TFTs by room temperature sputtering. As an important type of metal-oxide-based novel memory devices, which have been studied intensively in the last few years, RRAM devices were also explored. New materials, such as tin oxide (SnOx), were tested, exhibiting bipolar-switching operations and a relatively large resistance ratio. As a novel process variation, anodisation was performed, which yielded less impressive results than SnOx, but with a potential for ultra-low-cost manufacturing. Finally, novel planar nano-devices were explored, which have much simpler structures than conventional multi-layered transistors and diodes. Three types of ZnO-based nano-devices (a side-gated transistor, a self-switching diode and a planar inverter) were fabricated using both e-beam lithography and chemical wet etching. After optimisation of the challenging wet etching procedure at nanometre scale, ZnO nano-devices with good reproducibility and reliability have been demonstrated.

Subjects/Keywords: 621.39732; metal oxide; TFTs; ZnO; Tin oxide; RRAM; SSD; SGT

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APA (6^th Edition):

Jin, J. (2013). Metal-oxide-based electronic devices. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/metaloxidebased-electronic-devices(2ccabdd1-398b-4787-9455-e034f9001867).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.574311

Chicago Manual of Style (16^th Edition):

Jin, Jidong. “Metal-oxide-based electronic devices.” 2013. Doctoral Dissertation, University of Manchester. Accessed March 01, 2021. https://www.research.manchester.ac.uk/portal/en/theses/metaloxidebased-electronic-devices(2ccabdd1-398b-4787-9455-e034f9001867).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.574311.

MLA Handbook (7^th Edition):

Jin, Jidong. “Metal-oxide-based electronic devices.” 2013. Web. 01 Mar 2021.

Vancouver:

Jin J. Metal-oxide-based electronic devices. [Internet] [Doctoral dissertation]. University of Manchester; 2013. [cited 2021 Mar 01]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/metaloxidebased-electronic-devices(2ccabdd1-398b-4787-9455-e034f9001867).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.574311.

Council of Science Editors:

Jin J. Metal-oxide-based electronic devices. [Doctoral Dissertation]. University of Manchester; 2013. Available from: https://www.research.manchester.ac.uk/portal/en/theses/metaloxidebased-electronic-devices(2ccabdd1-398b-4787-9455-e034f9001867).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.574311

Universidade Nova

2. Santos, Ângelo Emanuel Neves dos. Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology.

Degree: 2016, Universidade Nova

URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19593

► Packaging is an important element responsible for brand growth and one of the main rea-sons for producers to gain competitive advantages through technological innovation. In… (more)

Subjects/Keywords: Packaging is an important element responsible for brand growth and one of the main rea-sons for producers to gain competitive advantages through technological innovation. In this re-gard, the aim of this work is to design a fully autonomous electronic system for a smart bottle packaging, being integrated in a European project named ROLL-OUT. The desired application for the smart bottle is to act as a fill-level sensor system in order to determine the liquid content level that exists inside an opaque bottle, so the consumer can exactly know the remaining quantity of the product inside. An in-house amorphous indium–gallium–zinc oxide thin-film transistor (a-IGZO TFT) model, previously developed, was used for circuit designing purposes. This model was based in an artificial neural network (ANN) equivalent circuit approach. Taking into account that only n-type oxide TFTs were used, plenty of electronic building-blocks have been designed: clock generator, non-overlapping phase generator, a capacitance-to-voltage converter and a comparator. As it was demonstrated by electrical simulations, it has been achieved good functionality for each block, having a final system with a power dissipation of 2.3 mW (VDD=10 V) not considering the clock generator. Four printed circuit boards (PCBs) have been also designed in order to help in the testing phase. Mask layouts were already designed and are currently in fabrication, foreseeing a suc-cessful circuit fabrication, and a major step towards the design and integration of complex trans-ducer systems using oxide TFTs technology; Capacitance-to-voltage converter; Comparator; Oxide TFTs circuit integration; Domínio/Área Científica::Engenharia e Tecnologia::Engenharia dos Materiais

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APA (6^th Edition):

Santos, �. E. N. d. (2016). Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19593

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Santos, Ângelo Emanuel Neves dos. “Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology.” 2016. Thesis, Universidade Nova. Accessed March 01, 2021. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19593.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Santos, Ângelo Emanuel Neves dos. “Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology.” 2016. Web. 01 Mar 2021.

Vancouver:

Santos �ENd. Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology. [Internet] [Thesis]. Universidade Nova; 2016. [cited 2021 Mar 01]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19593.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santos �ENd. Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology. [Thesis]. Universidade Nova; 2016. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19593

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Penn State University

3. Liu, Yi-chun. Experimentally Calibrated Simulation Of Zno Thin Film Transistors Including Traps.

Degree: 2014, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/21318

► Oxide based semiconductor thin film transistors are of interest because of their high mobility, and compatibility with flexible substrates. The role of contact barriers and… (more)

▼ Oxide based semiconductor thin film transistors are of interest because of their high mobility, and compatibility with flexible substrates. The role of contact barriers and carrier traps on these devices are unclear. In this work we have self-consistently connected simulations of the effect of contact barrier and traps to experimental results. For this work, we fabricated zinc oxide thin film transistors (TFTs) on glass substrates. We used Al2O3 and ZnO deposited by weak reactant plasma enhanced atomic layer deposition (PEALD) at 200◦C with process details reported earlier [25]. After device fabrication we measured the device drain current versus gate bias and drain current versus drain bias for several values of gate bias, from room temperature to 200 C. We also measured gated transmission line characteristics and quasi-static capacitance voltage (QSCV) characteristics for large geometry TFTs. The QSCV characteristics show a large capacitance overshoot near the channel accumulation voltage. Capacitance overshoot is expected in TFTs due to the transmission line structure of the channel resistance – gate capacitance combination [26]. However, the overshoot is observed in these devices even for sweep speeds as low as 10-2 V/S, much slower (several orders of magnitudes) than would be expected for a device with no contact barrier. Two-dimensional device simulation using Synopsis TCAD Sentaurus Device also predicts a capacitance overshoot only for a much faster gate voltage sweep (> 102 V/S). This suggests the presence of a contact barrier or trap. Transmission line characteristics are also strongly influenced by contact barriers. However, simulations of gated transmission lines even with large contact barriers do not reproduce the experimentally observed slow turn-on of the total channel resistance. To reproduce this characteristic we found we must add a significant deep level trap and some tailing near the conduction band edge. This distribution explains the exponential dependence of the transfer length method (TLM), the variable temperature IDVG measurements, the thickness dependence, and the transient current overshoot. The self heating of TFT on glass substrates is a well known effect. The threshold voltage of our device is already changing with temperature, and it is likely to be enhanced due to self-heating. Hence, pulse measurements were performed to remove contamination of self-heating. The data can be fit with four different small traps. With the experience of characterization of PEALD ZnO TFTs, a systematic characterization approach was used to find the trap density of state of devices with several different processes. Those includes: tri-layer processed PEALD ZnO TFTs and Air Force Research Laboratory (AFRL) pulsed laser deposited (PLD) zinc oxide TFTs. The trap DOS of tri-layer processed devices is similar to PEALD baseline devices. The temperature dependent measurements of AFRL high mobility devices, which has a completely different trap distribution, was fit by a single Gaussian distribution, and optical… Advisors/Committee Members: Thomas Nelson Jackson, Dissertation Advisor/Co-Advisor, Kultegin Aydin, Committee Member, Joan Marie Redwing, Committee Member, Jerzy Ruzyllo, Committee Member, Clive A Randall, Committee Member.

Subjects/Keywords: Thin film transistor simulation; oxide TFT simulation; oxide thin film transistor; oxide TFTs; oxide semiconductor traps.

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APA (6^th Edition):

Liu, Y. (2014). Experimentally Calibrated Simulation Of Zno Thin Film Transistors Including Traps. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/21318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liu, Yi-chun. “Experimentally Calibrated Simulation Of Zno Thin Film Transistors Including Traps.” 2014. Thesis, Penn State University. Accessed March 01, 2021. https://submit-etda.libraries.psu.edu/catalog/21318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liu, Yi-chun. “Experimentally Calibrated Simulation Of Zno Thin Film Transistors Including Traps.” 2014. Web. 01 Mar 2021.

Vancouver:

Liu Y. Experimentally Calibrated Simulation Of Zno Thin Film Transistors Including Traps. [Internet] [Thesis]. Penn State University; 2014. [cited 2021 Mar 01]. Available from: https://submit-etda.libraries.psu.edu/catalog/21318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Experimentally Calibrated Simulation Of Zno Thin Film Transistors Including Traps. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/21318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

4. Chen, Min-Chen. Study on the Fabrication and Electrical Characteristics of the Advanced Metal-oxide-based Resistive Random Access Memory and Thin-Film Transistors Devices.

Degree: PhD, Physics, 2011, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714111-132055

► In first part, the supercritical CO2 (SCCO2) fluid technology is employed to improve the device properties of ZnO TFT. The SCCO2 fluid exhibits liquid-like property,… (more)

▼ In first part, the supercritical CO2 (SCCO2) fluid technology is employed to improve the device properties of ZnO TFT. The SCCO2 fluid exhibits liquid-like property, which has excellent transport ability. Furthermore, the SCCO2 fluid has gas-like and high-pressure properties to diffuse into the nanoscale structures without damage. Hence, the SCCO2 fluid can carry the H2O molecule effectively into the ZnO films at low temperature and passivate traps by H2O molecule at low temperature. The experimental results show that the on current, sub-threshold slope, and threshold voltage of the device were improved significantly. Next, the electrical degradation behaviors and mechanisms under drain bias stress of a-IGZO TFTs were investigated. A current crowding effect and an obvious capacitance-voltage stretch-out were observed after stress. During the drain-bias stress, the oxygen would be absorbed on the back channel near the drain region of IGZO film. Therefore, the carrier transport is impeded by the additional energy barrier near drain region induced by the adsorbed oxygen, which forms a depletion layer to generate the parasitism resistance. We also investigated the RRAM device based on IGZO film, and proposed the related physical mechanism models. The IGZO RRAM will be very promising for integration with IGZO TFTs for advanced system-on-panel display applications to be a transparent embedded system. In this part, the transparent RRAM device with ITO/IGZO/ITO structure was fabricated. The proposed device presents an excellent bipolar resistive switching characteristic and good reliability. The bipolar switching mechanism of our device is dominated by the formation and rupture of the oxygen vacancies in a conduction path. The influence of electrode material on resistance switching characteristic is investigated through Pt/IGZO/TiN and Ti/IGZO/TiN structure. As the bias applied on the Ti or TiN, the Ti or TiN electrode can play the role of oxygen reservoir to absorb/discharge oxygen ions. Therefore, the device presents a bipolar resistive switching characteristic. However, as the bias applied on the Pt electrode, the device presents a unipolar resistive switching characteristic. Because the Pt electrode canât store the oxygen ion, the device should use the joule heating mode to rupture the conduction path and present the unipolar resistive switching characteristic. Finally, the resistive switching properties of IGZO film deposited at different oxygen content were investigated, since the resistance switching behaviors are related to the formation and rupture of filaments composed of oxygen vacancies in the IGZO matrix. Experiment results show that the HRS current decreases when the oxygen partial pressure gradually increases. Based on the XPS analysis, these phenomena are related to the non-lattice oxygen concentration. With increasing oxygen ratio, the filaments will rupture completely through the abundant non-lattice oxygen inducing oxidation, which leads to HRS current decrease and an increase in the memory window. Advisors/Committee Members: Tsung-Ming Tsai (chair), Ying-Chung Chen (chair), Jen-Sue Chen (chair), Ying-Lang,Wang (chair), Ting-Chang Chang (committee member).

Subjects/Keywords: Thin-Film Transistors (TFTs); Oxide thin film; Resistive Random Access Memory (RRAM)

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APA (6^th Edition):

Chen, M. (2011). Study on the Fabrication and Electrical Characteristics of the Advanced Metal-oxide-based Resistive Random Access Memory and Thin-Film Transistors Devices. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714111-132055

Chicago Manual of Style (16^th Edition):

Chen, Min-Chen. “Study on the Fabrication and Electrical Characteristics of the Advanced Metal-oxide-based Resistive Random Access Memory and Thin-Film Transistors Devices.” 2011. Doctoral Dissertation, NSYSU. Accessed March 01, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714111-132055.

MLA Handbook (7^th Edition):

Chen, Min-Chen. “Study on the Fabrication and Electrical Characteristics of the Advanced Metal-oxide-based Resistive Random Access Memory and Thin-Film Transistors Devices.” 2011. Web. 01 Mar 2021.

Vancouver:

Chen M. Study on the Fabrication and Electrical Characteristics of the Advanced Metal-oxide-based Resistive Random Access Memory and Thin-Film Transistors Devices. [Internet] [Doctoral dissertation]. NSYSU; 2011. [cited 2021 Mar 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714111-132055.

Council of Science Editors:

Chen M. Study on the Fabrication and Electrical Characteristics of the Advanced Metal-oxide-based Resistive Random Access Memory and Thin-Film Transistors Devices. [Doctoral Dissertation]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714111-132055

5. 乾, 京介. 液相法による低温酸化物TFTを用いたデバイスに関する研究.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

URL: http://hdl.handle.net/10119/15218

Supervisor:下田　達也

先端科学技術研究科

修士（マテリアルサイエンス）

Subjects/Keywords: 酸化物TFT; oxide-TFTs

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APA (6^th Edition):

乾, �. (n.d.). 液相法による低温酸化物TFTを用いたデバイスに関する研究. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/15218

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

乾, 京介. “液相法による低温酸化物TFTを用いたデバイスに関する研究.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed March 01, 2021. http://hdl.handle.net/10119/15218.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

乾, 京介. “液相法による低温酸化物TFTを用いたデバイスに関する研究.” Web. 01 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

乾 �. 液相法による低温酸化物TFTを用いたデバイスに関する研究. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2021 Mar 01]. Available from: http://hdl.handle.net/10119/15218.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

乾 �. 液相法による低温酸化物TFTを用いたデバイスに関する研究. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/15218

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Penn State University

6. Li, Haoyu. Functional Flexible Thin Film Electronics.

Degree: 2015, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/27080

► The field of flexible electronics has advanced rapidly in recent years. This dissertation reports progress on a few components for flexible electronics with a special… (more)

▼ The field of flexible electronics has advanced rapidly in recent years. This dissertation reports progress on a few components for flexible electronics with a special focus on process development, system integration, flexibility testing, and improvements in flexibility. In this dissertation, a rigid-substrate-compatible, lamination- and transfer-free process is developed to fabricate ZnO thin film transistors (TFTs) on very thin (~5 μm) solution-cast polyimide substrates. The flexible ZnO TFTs have very similar electrical characteristics to ZnO TFTs fabricated on rigid glass substrates. Typical TFT mobility is > 12 cm2/V∙s for a gate electric field of 2 MV/cm. Inverters and 51-stage ring oscillators have been demonstrated using ZnO TFTs on thin flexible substrates. After a simple mechanical release, most TFTs show unchanged electrical characteristics on the freestanding flexible substrates. The performance of the flexible TFTs also remains the same when bent to radii between 7 mm concavely and 5 mm convexly. Vanadium oxide (VOX) films have been studied as a temperature sensing material. Motivated by its potential of high-rate and uniform deposition, we investigated using RF diode sputtering to deposit VOX films as an alternative to the currently most commonly used ion-beam deposition. We found that process control for bolometer-grade VOX is very difficult. Small changes in oxygen-to-argon inlet ratio result in dramatic changes in the resistivity of the deposited VOX films, and a positive feedback mechanism drives depositions performed without active control to become either metallic or high resistivity films. We found that the local oxygen partial pressure near the reactively sputtered target varies with the oxidation of the target and is thus a strong candidate for an active control mechanism for reproducible reactive RF diode sputtering of VOX thin films. As efforts have taken place towards integrating more functions into flexible electronic systems, flexible organic light emitting diodes (OLEDs) have been demonstrated on the same thin flexible substrate as for the aforementioned flexible ZnO TFTs. The OLEDs use sputtered ITO anodes, evaporated organic layers, and evaporated Al top cathodes. Green light emission is confirmed for both on-rigid-carrier and freestanding flexible OLEDs. A direct patterning technique based on substrate surface energy contrast for parylene films as an encapsulation layer for electronic devices, including OLEDs, is also reported. The mechanical flexibility of flexible electronics is investigated in the context of testing strategies and the experimental results of different types of measurements. Besides the commonly reported static bending test, the strategies and apparatuses for repeated bending tests by push-to-flex and roller-flex are developed with the capability of in-situ electrical measurement while bending or flexing. Our flexible ZnO TFTs survive more than 50,000 repeated bending cycles with a bending radius of 3.5 mm with very little change in electrical characteristics.… Advisors/Committee Members: Thomas Nelson Jackson, Dissertation Advisor/Co-Advisor, Srinivas A Tadigadapa, Committee Member, Noel Christopher Giebink, Committee Member, Enrique Daniel Gomez, Committee Member.

Subjects/Keywords: Flexible electronics; thin film transistors (TFTs); oxide semiconductors; polymeric substrate; mechanical flexibility; VOx; OLED

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Li, H. (2015). Functional Flexible Thin Film Electronics. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/27080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Haoyu. “Functional Flexible Thin Film Electronics.” 2015. Thesis, Penn State University. Accessed March 01, 2021. https://submit-etda.libraries.psu.edu/catalog/27080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Haoyu. “Functional Flexible Thin Film Electronics.” 2015. Web. 01 Mar 2021.

Vancouver:

Li H. Functional Flexible Thin Film Electronics. [Internet] [Thesis]. Penn State University; 2015. [cited 2021 Mar 01]. Available from: https://submit-etda.libraries.psu.edu/catalog/27080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li H. Functional Flexible Thin Film Electronics. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/27080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

7. Raghuraman, Mathangi. Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface.

Degree: MSc Engg, Faculty of Engineering, 2018, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/3176

► Thin Film Transistors (TFTs) are widely used in large area electronics because they offer the advantage of low cost fabrication and wide substrate choice. TFTs… (more)

▼ Thin Film Transistors (TFTs) are widely used in large area electronics because they offer the advantage of low cost fabrication and wide substrate choice. TFTs have been conventionally used for switching applications in large area display arrays. But when it comes to designing a sensor actuator system on a flexible substrate comprising entirely of organic and inorganic TFTs, there are two main challenges – i) Fabrication of complementary TFT devices is difficult ii) TFTs have a drift in their threshold voltage (VT) on application of gate bias. Also currently there are no circuit simulators in the market which account for the effect of VT drift with time in TFT circuits. The first part of this thesis focuses on integrating the VT shift model in the commercially available AIM-Spice circuit simulator. This provides a new and powerful tool that would predict the effect of VT shift on nodal voltages and currents in circuits and also on parameters like small signal gain, bandwidth, hysteresis etc. Since the existing amorphous silicon TFT models (level 11 and level 15) of AIM-Spice are copyright protected, the open source BSIM4V4 model for the purpose of demonstration is used. The simulator is discussed in detail and an algorithm for integration is provided which is then supported by the data from the simulation plots and experimental results for popular TFT configurations. The second part of the thesis illustrates the idea of using negative feedback achieved via contact resistance modulation to minimize the effect of VT shift in the drain current of the TFT. Analytical expressions are derived for the exact value of resistance needed to compensate for the VT shift entirely. Circuit to realize this resistance using TFTs is also provided. All these are experimentally verified using fabricated organic P-type Copper Phthalocyanine (CuPc) and inorganic N-type Tin doped Zinc Oxide (ZTO) TFTs. The third part of the thesis focuses on building a robust amplifier using these TFTs which has time invariant DC voltage level and small signal gain at the output. A differential amplifier using ZTO TFTs has been built and is shown to fit all these criteria. Ideas on vertical routing in an actual sensor actuator interface using this amplifier have also been discussed such that the whole system may be “tearable” in any contour. Such a sensor actuator interface can have varied applications including wrap around thermometers and X-ray machines. Advisors/Committee Members: Sambandan, Sanjiv (advisor).

Subjects/Keywords: Sensor Actuator Interface; Non-Crystalline Semiconductors; Thin Film Transistor (TFT); Semiconductors; Threshold Voltage Shift (VT); Circuit Simulators; Tin Doped Zinc Oxide Thin Film Transistors; Copper Phthalocyanine Thin Film Transistors; Sensors and Actuators; Interface Circuits; VT Shift Model; Thin Film Transistors (TFTs); Sensor Actuator System; Threshold Voltage (VT); VT Shift Model; Electronics Engineering

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APA (6^th Edition):

Raghuraman, M. (2018). Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3176

Chicago Manual of Style (16^th Edition):

Raghuraman, Mathangi. “Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface.” 2018. Masters Thesis, Indian Institute of Science. Accessed March 01, 2021. http://etd.iisc.ac.in/handle/2005/3176.

MLA Handbook (7^th Edition):

Raghuraman, Mathangi. “Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface.” 2018. Web. 01 Mar 2021.

Vancouver:

Raghuraman M. Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface. [Internet] [Masters thesis]. Indian Institute of Science; 2018. [cited 2021 Mar 01]. Available from: http://etd.iisc.ac.in/handle/2005/3176.

Council of Science Editors:

Raghuraman M. Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface. [Masters Thesis]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3176

NSYSU

8. Tsao, Shu-Wei. Electrical Analysis & Fabricated Investigation of Amorphous Active Layer Thin Film Transistor for Large Size Display Application.

Degree: PhD, Electro-Optical Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1019110-225810

► In this dissertation, the electrical characteristics of generally used hydrogenated amorphous silicon (a-Si:H) TFTs in LCD and newly risen amorphous indium-gallium-zinc oxide (a-IGZO) TFTs were… (more)

▼ In this dissertation, the electrical characteristics of generally used hydrogenated amorphous silicon (a-Si:H) TFTs in LCD and newly risen amorphous indium-gallium-zinc oxide (a-IGZO) TFTs were studied. For modern mobile display and large-size flat panel display application, the traditional thin-film transistor-liquid crystal display (TFT-LCD) technology confronts with a lot of challenges and problems. In general, flexible displays must exhibit some bending ability; however, bending applies mechanical strain to electronic circuits and affects device characteristics. Therefore, the electrical characteristics of a-Si:H TFTs fabricated on stainless steel foil substrates with uniaxial bending were investigated at different temperatures. Experimental results showed that the on-state current and threshold voltage degraded under outward bending. This is because outward bending will induce the increase of band tail states, affecting the transport mechanism at different temperatures. In addition, for practical operation, the electrical characteristics of a-Si:H TFTs under flat and bending situations after AC/DC stress at different temperatures were studied. It was found that high temperature and mechanical bending played important roles under AC stress. The dependence between the accumulated sum of bias rising and falling time and the threshold voltage shifts under AC stress was also observed. Because a-Si:H is a photosensitive material, the high intensity backlight illumination will degrade the performance of a-Si:H TFTs. Thus, the photo-leakage current of a-Si:H TFTs under illumination was investigated at different temperatures. Experimental results showed that a-Si:H TFTs exhibited a pool performance at lower temperatures. The indirect recombination rate and the parasitic resistance (Rp) are responsible for the different photo-leakage-current trends of a-Si:H TFTs under varied temperature operations. To investigate the photo-leakage current, the a-Si:H TFTs were exposed to ultraviolet (UV) light irradiation. It was found that the photo current of a-Si:H TFTs was reduced after UV light irradiation. The detail mechanisms on reducing/increasing photo-leakage current by UV light irradiation were discussed. Recently, the oxide-based semiconductor TFT, especially a-IGZO TFT, is considered as one of promising candidates for active matrix flat-panel display. However, the a-IGZO TFT exists significant electrical instability issue and manufacturing problems. As a consequence, we investigated the effect of hydrogen incorporation on a-IGZO TFTs to reduce interface states between active layer and insulator. Experimental results showed that the electrical characteristics of hydrogen-incorporated a-IGZO TFTs were improved. The threshold voltage shift (ÎVth) in hysteresis loop is suppressed from 4 V to 2 V due to the hydrogen-induced passivation of the interface trap states. Finally, we reported the effect of ambient environment on a-IGZO TFT instability. As a-IGZO TFTs were stored in atmosphere environment for 40 days, the transfer… Advisors/Committee Members: Ting-Chang Chang (committee member), Tzu-Ming cheng (chair), Wen-Yao Huang (chair), Tsung-Ming Tsai (chair), Mei-Ying Chang (chair).

Subjects/Keywords: Mechanical Strain; UV Irradiation; amorphous indium-gallium-zinc oxide (a-IGZO) TFTs; Photo-leakage-current; Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tsao, S. (2010). Electrical Analysis & Fabricated Investigation of Amorphous Active Layer Thin Film Transistor for Large Size Display Application. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1019110-225810

Chicago Manual of Style (16^th Edition):

Tsao, Shu-Wei. “Electrical Analysis & Fabricated Investigation of Amorphous Active Layer Thin Film Transistor for Large Size Display Application.” 2010. Doctoral Dissertation, NSYSU. Accessed March 01, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1019110-225810.

MLA Handbook (7^th Edition):

Tsao, Shu-Wei. “Electrical Analysis & Fabricated Investigation of Amorphous Active Layer Thin Film Transistor for Large Size Display Application.” 2010. Web. 01 Mar 2021.

Vancouver:

Tsao S. Electrical Analysis & Fabricated Investigation of Amorphous Active Layer Thin Film Transistor for Large Size Display Application. [Internet] [Doctoral dissertation]. NSYSU; 2010. [cited 2021 Mar 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1019110-225810.

Council of Science Editors:

Tsao S. Electrical Analysis & Fabricated Investigation of Amorphous Active Layer Thin Film Transistor for Large Size Display Application. [Doctoral Dissertation]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1019110-225810

Penn State University

9. Ramirez, Jose Israel. Zno Thin Film Electronics For More Than Displays.

Degree: 2015, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/26550

► Zinc oxide thin film transistors (TFTs) are investigated in this work for large-area electronic applications outside of display technology. A constant pressure, constant flow, showerhead,… (more)

▼ Zinc oxide thin film transistors (TFTs) are investigated in this work for large-area electronic applications outside of display technology. A constant pressure, constant flow, showerhead, plasma-enhanced atomic layer deposition (PEALD) process has been developed to fabricate high mobility TFTs and circuits on rigid and flexible substrates at 200 °C. ZnO films and resulting devices prepared by PEALD and pulsed laser deposition (PLD) have been compared. Both PEALD and PLD ZnO films result in densely packed, polycrystalline ZnO thin films that were used to make high performance devices. PEALD ZnO TFTs deposited at 300 °C have a field-effect mobility of ~ 40 cm2/V-s (and > 20 cm2/V-S deposited at 200 °C). PLD ZnO TFTs, annealed at 400 °C, have a field-effect mobility of > 60 cm2/V-s (and up to 100 cm2/V-s). Devices, prepared by either technique, show high gamma-ray radiation tolerance of up to 100 Mrad(SiO2) with only a small radiation-induced threshold voltage shift (VT ~ -1.5 V). Electrical biasing during irradiation showed no enhanced radiation-induced effects. The study of the radiation effects as a function of material stack thicknesses revealed the majority of the radiation-induced charge collection happens at the semiconductor-passivation interface. A simple sheet-charge model at that interface can describe the radiation-induced charge in ZnO TFTs. By taking advantage of the substrate-agnostic process provided by PEALD, due to its low-temperature and excellent conformal coatings, ZnO electronics were monolithically integrated with thin-film complex oxides. Application-based examples where ZnO electronics provide added functionality to complex oxide-based devices are presented. In particular, the integration of arrayed lead zirconate titanate (Pb(Zr, Ti)O3 or PZT) thin films with ZnO electronics for microelectromechanical systems (MEMs) and deformable mirrors is demonstrated. ZnO switches can provide voltage to PZT capacitors with fast charging and slow discharging time constants. Finally, to circumvent fabrication challenges on predetermined complex shapes, like curved mirror optics, a technique to transfer electronics from a rigid substrate to a flexible substrate is used. This technique allows various thin films, regardless of their deposition temperature, to be transferred to flexible substrates. Finally, ultra-low power operation of ZnO TFT gas sensors was demonstrated. The ZnO ozone sensors were optimized to operate with excellent electrical stability in ambient conditions, without using elevated temperatures, while still providing good gas sensitivity. This was achieved by using a post-deposition anneal and by partially passivating the contact regions while leaving the semiconductor sensing area open to the ambient. A novel technique to reset the gas sensor using periodic pulsing of a UV light over the sensor results in less than 25 milliseconds recovery time. A pathway to achieve gas selectivity by using organic thin-film layers as filters deposited over the gas sensors tis demonstrated. The ZnO… Advisors/Committee Members: Thomas Nelson Jackson, Dissertation Advisor/Co-Advisor, Suman Datta, Committee Member, Susan E Trolier Mckinstry, Committee Member, Mark William Horn, Committee Member.

Subjects/Keywords: zno; thin film transistors (TFT); large-area electronics; radiation-hard ZnO TFTs; integration of ZnO electronics with PZT films

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APA (6^th Edition):

Ramirez, J. I. (2015). Zno Thin Film Electronics For More Than Displays. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/26550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ramirez, Jose Israel. “Zno Thin Film Electronics For More Than Displays.” 2015. Thesis, Penn State University. Accessed March 01, 2021. https://submit-etda.libraries.psu.edu/catalog/26550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ramirez, Jose Israel. “Zno Thin Film Electronics For More Than Displays.” 2015. Web. 01 Mar 2021.

Vancouver:

Ramirez JI. Zno Thin Film Electronics For More Than Displays. [Internet] [Thesis]. Penn State University; 2015. [cited 2021 Mar 01]. Available from: https://submit-etda.libraries.psu.edu/catalog/26550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ramirez JI. Zno Thin Film Electronics For More Than Displays. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/26550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Jin, Jidong. METAL-OXIDE-BASED ELECTRONIC DEVICES.

Degree: 2013, University of Manchester

URL: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:192842

► Metal oxides exhibit a wide range of chemical and electronic properties, making them an extremely interesting subject for numerous applications in modern electronics. The primary… (more)

▼ Metal oxides exhibit a wide range of chemical and electronic properties, making them an extremely interesting subject for numerous applications in modern electronics. The primary goal of this research is to develop metal-oxide-based electronic devices, including thin-film transistors (TFTs), resistance random-access memory (RRAM) and planar nano-devices. This research requires different processing techniques, novel device design concepts and optimisation of materials and devices. The first experiments were carried out to optimise the properties of zinc oxide (ZnO) semiconductors, in particular the carrier concentration, which determines the threshold voltage of the TFTs. Thermal annealing is one common method to affect carrier concentration and most work in the literature reports performing this process in a single-gas environment. In this work, however, annealing was carried out in a combination of air and nitrogen, and it was found that the threshold voltage could be tuned over a wide range of pre-determined values.Further experiments were undertaken to enhance the carrier mobility of ZnO TFTs, which is the most important material quality parameter. By optimising deposition conditions and incorporating a high-k gate dielectric layer, the devices showed saturation mobility values over 50 cm2/Vs at a low operating voltage of 4 V. This is, to our knowledge, one of the highest field-effect mobility values achieved in ZnO-based TFTs by room temperature sputtering. As an important type of metal-oxide-based novel memory devices, which have been studied intensively in the last few years, RRAM devices were also explored. New materials, such as tin oxide (SnOx), were tested, exhibiting bipolar-switching operations and a relatively large resistance ratio. As a novel process variation, anodisation was performed, which yielded less impressive results than SnOx, but with a potential for ultra-low-cost manufacturing. Finally, novel planar nano-devices were explored, which have much simpler structures than conventional multi-layered transistors and diodes. Three types of ZnO-based nano-devices (a side-gated transistor, a self-switching diode and a planar inverter) were fabricated using both e-beam lithography and chemical wet etching. After optimisation of the challenging wet etching procedure at nanometre scale, ZnO nano-devices with good reproducibility and reliability have been demonstrated. Advisors/Committee Members: Song, Aimin.

Subjects/Keywords: metal oxide; TFTs; ZnO; Tin oxide; RRAM; SSD; SGT

…develop metal-oxide-based electronic devices, including thin-film transistors (TFTs)… …undoubtedly the most important material in electronics so far. Recently, other circuit integration… …x5B;6, 8, 9]. Metal-oxide-based TFTs typically have a higher field-effect 18 Chapter… …including TFTs, RRAM and planar nano-devices. The successful implementation of metal-oxide-based… …but these devices showed very poor performance. Intensive research on metal-oxide-based TFTs…

10 more images…

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Jin, J. (2013). METAL-OXIDE-BASED ELECTRONIC DEVICES. (Doctoral Dissertation). University of Manchester. Retrieved from http://www.manchester.ac.uk/escholar/uk-ac-man-scw:192842

Chicago Manual of Style (16^th Edition):

Jin, Jidong. “METAL-OXIDE-BASED ELECTRONIC DEVICES.” 2013. Doctoral Dissertation, University of Manchester. Accessed March 01, 2021. http://www.manchester.ac.uk/escholar/uk-ac-man-scw:192842.

MLA Handbook (7^th Edition):

Jin, Jidong. “METAL-OXIDE-BASED ELECTRONIC DEVICES.” 2013. Web. 01 Mar 2021.

Vancouver:

Jin J. METAL-OXIDE-BASED ELECTRONIC DEVICES. [Internet] [Doctoral dissertation]. University of Manchester; 2013. [cited 2021 Mar 01]. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:192842.

Council of Science Editors:

Jin J. METAL-OXIDE-BASED ELECTRONIC DEVICES. [Doctoral Dissertation]. University of Manchester; 2013. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:192842

Universidade Nova

11. Carlos, Emanuel Abreu Antunes. Oxide transistors produced by solution: Influence of annealing parameters on properties of the insulator.

Degree: 2017, Universidade Nova

URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19799

► Solution processing of amorphous metal oxides has been lately used as an option to implement in flexible electronics allowing to reduce the associated costs and… (more)

Subjects/Keywords: Aluminum oxide; Combustion reaction; FUV irradiation; Low temperature; Solution TFTs; Low operating voltage; Domínio/Área Científica::Engenharia e Tecnologia::Engenharia dos Materiais

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APA (6^th Edition):

Carlos, E. A. A. (2017). Oxide transistors produced by solution: Influence of annealing parameters on properties of the insulator. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19799

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Carlos, Emanuel Abreu Antunes. “Oxide transistors produced by solution: Influence of annealing parameters on properties of the insulator.” 2017. Thesis, Universidade Nova. Accessed March 01, 2021. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19799.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Carlos, Emanuel Abreu Antunes. “Oxide transistors produced by solution: Influence of annealing parameters on properties of the insulator.” 2017. Web. 01 Mar 2021.

Vancouver:

Carlos EAA. Oxide transistors produced by solution: Influence of annealing parameters on properties of the insulator. [Internet] [Thesis]. Universidade Nova; 2017. [cited 2021 Mar 01]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19799.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carlos EAA. Oxide transistors produced by solution: Influence of annealing parameters on properties of the insulator. [Thesis]. Universidade Nova; 2017. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/19799

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade Nova

12. Trigo, Pedro Gil Dias. Oxide transistors produced by Combustion Synthesis: Influence of the PVP on the properties of the insulator.

Degree: 2017, Universidade Nova

URL: https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/42277

► Solution processing of amorphous metal oxides has been used as an option to implement in flexible electronics, allowing to reduce the associated costs, when compared… (more)

▼ Solution processing of amorphous metal oxides has been used as an option to implement in flexible electronics, allowing to reduce the associated costs, when compared with vacuum processes. Recent research has been more focused on the semiconductor layer; however, the dielectric layer is equally important since its responsible for the stability and electric performance of the device. This work aims to evaluate hybrid dielectric thin films, using aluminium oxide and different types of polyvinylpyrrolidone (PVP), both obtained by solution process using solution combustion synthesis (SCS), to study the influence of the amount of organic material used in the insulator layer, as well as to study the influence of the hybrid insulator obtained in oxide thin film transistors (TFTs) using indium-gallium-zinc-oxide (IGZO) and zinc-tin-oxide (ZTO) as semiconductor layer. The insulator layer was obtained using aluminium nitrate nonahydrate and polyvinylpyrrolidone (PVP) with different molecular weights (10000 and 40000) and different percentages as precursor solutions, using urea as fuel and 2-methoxyethanol as solvent. The best hybrid dielectric was obtained with 0.8 % PVP 40000 (weight per volume), showing a breakdown voltage of 1.1 MV/cm, low density leakage current of 9.6 × 10-5 A/cm2, capacitance per area of 123 nF/cm2, thickness of 49.35 nm, annealed at 200 °C for 30 minutes. Moreover, the roughness study obtained using atomic force microscopy showed highly smooth surface, resulting in improvement dielectric-semiconductor interface, while still maintaining an amorphous nature. These characteristics allowed this hybrid dielectric, lead to enhanced TFTs electrical properties. The best performing thin films were applied in IGZO TFTs as hybrid dielectrics. The optimized TFTs show good reproducibility with an average mobility of 40.24 ± 1.1 cm2∙V-1∙s-1, subthreshold slope of 0.169 ± 0.012 V∙dec-1, a turn-on voltage of 0.078 ± 0.004 V and a low operating voltage (maximum 2 V). Advisors/Committee Members: Branquinho, Rita.

Subjects/Keywords: aluminium oxide; polyvinylpyrrolidone; hybrid dielectrics; solution combustion synthesis; solution TFTs; low operating voltage; Domínio/Área Científica::Engenharia e Tecnologia::Engenharia dos Materiais

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Trigo, P. G. D. (2017). Oxide transistors produced by Combustion Synthesis: Influence of the PVP on the properties of the insulator. (Thesis). Universidade Nova. Retrieved from https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/42277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Trigo, Pedro Gil Dias. “Oxide transistors produced by Combustion Synthesis: Influence of the PVP on the properties of the insulator.” 2017. Thesis, Universidade Nova. Accessed March 01, 2021. https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/42277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Trigo, Pedro Gil Dias. “Oxide transistors produced by Combustion Synthesis: Influence of the PVP on the properties of the insulator.” 2017. Web. 01 Mar 2021.

Vancouver:

Trigo PGD. Oxide transistors produced by Combustion Synthesis: Influence of the PVP on the properties of the insulator. [Internet] [Thesis]. Universidade Nova; 2017. [cited 2021 Mar 01]. Available from: https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/42277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Trigo PGD. Oxide transistors produced by Combustion Synthesis: Influence of the PVP on the properties of the insulator. [Thesis]. Universidade Nova; 2017. Available from: https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/42277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Penn State University

13. Sun, Jie. PECVD, SPATIAL ALD, AND PEALD ZINC OXIDE THIN FILM TRANSISTORS .

Degree: 2008, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/8818

► This thesis describes low-temperature ZnO deposition and thin film transistor (TFT) fabrication for the fastest ZnO circuits reported to date. Using both plasma enhanced atomic… (more)

▼ This thesis describes low-temperature ZnO deposition and thin film transistor (TFT) fabrication for the fastest ZnO circuits reported to date. Using both plasma enhanced atomic layer deposition (PEALD) and, in collaboration with the Eastman Kodak Company, a novel spatial atomic layer deposition (ALD) process, we have fabricated circuits with 4 mm minimum channel length TFTs with propagation delay less than 30 ns/stage. For comparison, we also describe devices fabricated using plasma enhanced chemical vapor deposition that result in much slower circuits. A key problem in fabricating ZnO devices and circuits is control of the semiconductor trap density and the semiconductor/dielectric interface state density. We believe this strongly limits the performance of ZnO TFTs fabricated by plasma enhanced chemical vapor deposition (PECVD). ZnO TFTs using an Al2O3 gate dielectric deposited in situ by PECVD showed moderate gate leakage (< 105 A/cm2), field-effect mobility of ~10 cm2/V×s, and threshold voltage of 7.5 V. However, these devices are strongly limited by interface states and reducing the gate leakage results in TFTs with lower mobility. ZnO TFTs fabricated with low-leakage Al2O3 have mobility near 0.05 cm2/V×s, and five-stage ring oscillators fabricated using these TFTs have a 1.2 kHz oscillation frequency at 60 V, which is substantially slower than simulation results. ZnO TFTs with large gate leakage showed a higher field-effect mobility due to interface state charging through the leaky dielectric. Although the performance of PECVD ZnO TFTs may be limited by interface or bulk traps, PECVD provides flexibility in depositing low-temperature doped films. We demonstrated boron-doped ZnO thin films, grown at 200 °C by PECVD, with resistivity as low as 4 × 10-4 W×cm and with excellent optical transmission (>85% for visible spectrum). The free electron concentration, determined by Hall effect measurement was as high as 1 x 1021/cm3 with mobility of 13.5 cm2/V×s. In this doped ZnO work a low reactivity oxidant, CO2, is used to provide uniform growth over large-area and to simplify the system design. The boron source used was triethylboron (TEB), which is substantially less toxic than commonly used diborane. These results are among the lowest resistivities reported for doped ZnO thin films. In contrast to PECVD, spatial ALD, and PEALD may result in films with fewer stoichiometric defects and improved semiconductor/dielectric interface. ZnO TFTs fabricated using spatial ALD had a typical field effect mobility of ~15 cm2/V×s, a threshold voltage of 5 V, subthreshold slope of < 0.3 V/dec, and current on/off ratio > 108. Similarly, PEALD ZnO TFTs showed a typical field-effect mobility of ~16 cm2/V×s, a threshold voltage of 2.5 V, sub-threshold slope of 80 mV/decade, and current on/off ratio of 1010. Using both spatial ALD and PEALD ZnO TFTs, seven-stage ring oscillators with 4 mm minimum channel length TFTs oscillated at 2.3 MHz, corresponding to a propagation delay of ~30 ns/stage. These are the fastest ZnO TFT circuits… Advisors/Committee Members: Thomas Nelson Jackson, Committee Chair/Co-Chair, Jerzy Ruzyllo, Committee Member, Joan Marie Redwing, Committee Member, Mark William Horn, Committee Member.

Subjects/Keywords: Plasma Enhanced Atomic Layer Deposition; Atomic Layer Deposition; Plasma Enhanced Chemical Vapor Depostion; Thin Film Transistors (TFTs); Zinc Oxide (ZnO); ZnO TFTs Circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Sun, J. (2008). PECVD, SPATIAL ALD, AND PEALD ZINC OXIDE THIN FILM TRANSISTORS . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/8818

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Sun, Jie. “PECVD, SPATIAL ALD, AND PEALD ZINC OXIDE THIN FILM TRANSISTORS .” 2008. Thesis, Penn State University. Accessed March 01, 2021. https://submit-etda.libraries.psu.edu/catalog/8818.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Sun, Jie. “PECVD, SPATIAL ALD, AND PEALD ZINC OXIDE THIN FILM TRANSISTORS .” 2008. Web. 01 Mar 2021.

Vancouver:

Sun J. PECVD, SPATIAL ALD, AND PEALD ZINC OXIDE THIN FILM TRANSISTORS . [Internet] [Thesis]. Penn State University; 2008. [cited 2021 Mar 01]. Available from: https://submit-etda.libraries.psu.edu/catalog/8818.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun J. PECVD, SPATIAL ALD, AND PEALD ZINC OXIDE THIN FILM TRANSISTORS . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/8818

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Hong Kong University of Science and Technology

14. Raju, Salahuddin. Integration of low loss interconnects in CMOS.

Degree: 2016, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-86942 ; https://doi.org/10.14711/thesis-b1627112 ; http://repository.ust.hk/ir/bitstream/1783.1-86942/1/th_redirect.html

► In this work, an interlayer dielectric with an extremely low dielectric constant of 1.96 is achieved using SiO₂ with vertically aligned cylindrical pores. Vertically grown… (more)

Subjects/Keywords: Interconnects (Integrated circuit technology) ; Antennas (Electronics) ; Metal oxide semiconductors, Complementary

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Raju, S. (2016). Integration of low loss interconnects in CMOS. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-86942 ; https://doi.org/10.14711/thesis-b1627112 ; http://repository.ust.hk/ir/bitstream/1783.1-86942/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Raju, Salahuddin. “Integration of low loss interconnects in CMOS.” 2016. Thesis, Hong Kong University of Science and Technology. Accessed March 01, 2021. http://repository.ust.hk/ir/Record/1783.1-86942 ; https://doi.org/10.14711/thesis-b1627112 ; http://repository.ust.hk/ir/bitstream/1783.1-86942/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Raju, Salahuddin. “Integration of low loss interconnects in CMOS.” 2016. Web. 01 Mar 2021.

Vancouver:

Raju S. Integration of low loss interconnects in CMOS. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2016. [cited 2021 Mar 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-86942 ; https://doi.org/10.14711/thesis-b1627112 ; http://repository.ust.hk/ir/bitstream/1783.1-86942/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Raju S. Integration of low loss interconnects in CMOS. [Thesis]. Hong Kong University of Science and Technology; 2016. Available from: http://repository.ust.hk/ir/Record/1783.1-86942 ; https://doi.org/10.14711/thesis-b1627112 ; http://repository.ust.hk/ir/bitstream/1783.1-86942/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

15. Lin, Chun-Shou. Design and verification of an ARM10-like Processor and its System Integration.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

► With the advanced of the technique, we can design more IP in the same area space chip. The embedded system has more powerful about its… (more)

Subjects/Keywords: Integration; Embedded in circuit emulator (EICE); Microprocessor; Verification; Cache/MMU; Coprocessor

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APA (6^th Edition):

Lin, C. (2012). Design and verification of an ARM10-like Processor and its System Integration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Chun-Shou. “Design and verification of an ARM10-like Processor and its System Integration.” 2012. Thesis, NSYSU. Accessed March 01, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Chun-Shou. “Design and verification of an ARM10-like Processor and its System Integration.” 2012. Web. 01 Mar 2021.

Vancouver:

Lin C. Design and verification of an ARM10-like Processor and its System Integration. [Internet] [Thesis]. NSYSU; 2012. [cited 2021 Mar 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Design and verification of an ARM10-like Processor and its System Integration. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Ottawa

16. Lin, Yaoyao. Improvements in Obreshkov-based High-Order Circuit Simulation Method .

Degree: 2015, University of Ottawa

URL: http://hdl.handle.net/10393/32090

► The transient time-domain simulation, of the circuit response, is a fundamental component in the Computer-Aided Design tools of all integrated circuit and systems. It is… (more)

Subjects/Keywords: A-stable; Circuit simulation; Nonlinear memory elements; High-order integration methods

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APA (6^th Edition):

Lin, Y. (2015). Improvements in Obreshkov-based High-Order Circuit Simulation Method . (Thesis). University of Ottawa. Retrieved from http://hdl.handle.net/10393/32090

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Yaoyao. “Improvements in Obreshkov-based High-Order Circuit Simulation Method .” 2015. Thesis, University of Ottawa. Accessed March 01, 2021. http://hdl.handle.net/10393/32090.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Yaoyao. “Improvements in Obreshkov-based High-Order Circuit Simulation Method .” 2015. Web. 01 Mar 2021.

Vancouver:

Lin Y. Improvements in Obreshkov-based High-Order Circuit Simulation Method . [Internet] [Thesis]. University of Ottawa; 2015. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/10393/32090.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin Y. Improvements in Obreshkov-based High-Order Circuit Simulation Method . [Thesis]. University of Ottawa; 2015. Available from: http://hdl.handle.net/10393/32090

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Colorado State University

17. Tedjo, William. Biosensor system with an integrated CMOS microelectrode array for high spatio-temporal electrochemical imaging, A.

Degree: PhD, Electrical and Computer Engineering, 2019, Colorado State University

URL: http://hdl.handle.net/10217/199766

► The ability to view biological events in real time has contributed significantly to research in life sciences. While optical microscopy is important to observe anatomical… (more)

▼ The ability to view biological events in real time has contributed significantly to research in life sciences. While optical microscopy is important to observe anatomical and morphological changes, it is equally important to capture real-time two-dimensional (2D) chemical activities that drive the bio-sample behaviors. The existing chemical sensing methods (i.e. optical photoluminescence, magnetic resonance, and scanning electrochemical), are well-established and optimized for existing ex vivo or in vitro analyses. However, such methods also present various limitations in resolution, real-time performance, and costs. Electrochemical method has been advantageous to life sciences by supporting studies and discoveries in neurotransmitter signaling and metabolic activities in biological samples. In the meantime, the integration of Microelectrode Array (MEA) and Complementary-Metal-Oxide-Semiconductor (CMOS) technology to the electrochemical method provides biosensing capabilities with high spatial and temporal resolutions. This work discusses three related subtopics in this specific order: improvements to an electrochemical imaging system with 8,192 sensing points for neurotransmitter sensing; comprehensive design processes of an electrochemical imaging system with 16,064 sensing points based on the previous system; and the application of the system for imaging oxygen concentration gradients in metabolizing bovine oocytes. The first attempt of high spatial electrochemical imaging was based on an integrated CMOS microchip with 8,192 configurable Pt surface electrodes, on-chip potentiostat, on-chip control logic, and a microfluidic device designed to support ex vivo tissue experimentation. Using norepinephrine as a target analyte for proof of concept, the system is capable of differentiating concentrations of norepinephrine as low as 8µM and up to 1,024 µM with a linear response and a spatial resolution of 25.5×30.4μm. Electrochemical imaging was performed using murine adrenal tissue as a biological model and successfully showed caffeine-stimulated release of catecholamines from live slices of adrenal tissue with desired spatial and temporal resolutions. This system demonstrates the capability of an electrochemical imaging system capable of capturing changes in chemical gradients in live tissue slices. An enhanced system was designed and implemented in a CMOS microchip based on the previous generation. The enhanced CMOS microchip has an expanded sensing area of 3.6×3.6mm containing 16,064 Pt electrodes and the associated 16,064 integrated read channels. The novel three-electrode electrochemical sensor system designed at 27.5×27.5µm pitch enables spatially dense cellular level chemical gradient imaging. The noise level of the on-chip read channels allow amperometric linear detection of neurotransmitter (norepinephrine) concentrations from 4µM to 512µM with 4.7pA/µM sensitivity (R=0.98). Electrochemical response to dissolved oxygen concentration or oxygen partial pressure (pO2) was also characterized with deoxygenated… Advisors/Committee Members: Chen, Thomas (advisor), Tobet, Stuart (committee member), Collins, George (committee member), Wilson, Jesse (committee member).

Subjects/Keywords: CMOS circuit design; instrumentation integration; biosensor system; microelectrode array; electrochemical sensor

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APA (6^th Edition):

Tedjo, W. (2019). Biosensor system with an integrated CMOS microelectrode array for high spatio-temporal electrochemical imaging, A. (Doctoral Dissertation). Colorado State University. Retrieved from http://hdl.handle.net/10217/199766

Chicago Manual of Style (16^th Edition):

Tedjo, William. “Biosensor system with an integrated CMOS microelectrode array for high spatio-temporal electrochemical imaging, A.” 2019. Doctoral Dissertation, Colorado State University. Accessed March 01, 2021. http://hdl.handle.net/10217/199766.

MLA Handbook (7^th Edition):

Tedjo, William. “Biosensor system with an integrated CMOS microelectrode array for high spatio-temporal electrochemical imaging, A.” 2019. Web. 01 Mar 2021.

Vancouver:

Tedjo W. Biosensor system with an integrated CMOS microelectrode array for high spatio-temporal electrochemical imaging, A. [Internet] [Doctoral dissertation]. Colorado State University; 2019. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/10217/199766.

Council of Science Editors:

Tedjo W. Biosensor system with an integrated CMOS microelectrode array for high spatio-temporal electrochemical imaging, A. [Doctoral Dissertation]. Colorado State University; 2019. Available from: http://hdl.handle.net/10217/199766

18. Liu, Ting. Stability of Amorphous Silicon Thin Film Transistors and Circuits .

Degree: PhD, 2013, Princeton University

URL: http://arks.princeton.edu/ark:/88435/dsp01xs55mc14f

► Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used for the active-matrix addressing of flat panel displays, optical scanners and sensors. Extending the… (more)

▼ Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used for the active-matrix addressing of flat panel displays, optical scanners and sensors. Extending the application of the a-Si TFTs from switches to current sources, which requires continuous operation such as for active-matrix organic light-emitting-diode (AMOLED) pixels, makes stability a critical issue. This thesis first presents a two-stage model for the stability characterization and reliable lifetime prediction for highly stable a-Si TFTs under low gate-field stress. Two stages of the threshold voltage shift are identified from the decrease of the drain saturation current under low-gate field. The first initial stage dominates up to hours or days near room temperature. It can be characterized with a stretched-exponential model, with the underlying physical mechanism of charge trapping in the gate dielectric. The second stage dominates in the long term and then saturates. It corresponds to the breaking of weak bonds in the amorphous silicon. It can be modeled with a "unified stretched exponential fit," in which a thermalization energy is used to unify experimental measurements of drain current decay at different temperatures into a single curve. Two groups of experiments were conducted to reduce the drain current instability of a-Si TFTs under prolonged gate bias. Deposition conditions for the silicon nitride (SiNx) gate insulator and the a-Si channel layer were varied, and TFTs were fabricated with all reactive ion etching steps, or with all wet etching steps, the latter in a new process. The two-stage model that unites charge trapping in the SiNx gate dielectric and defect generation in the a-Si channel was used to interpret the experimental results. We identified the optimal substrate temperature, gas flow ratios, and RF deposition power densities. The stability of the a-Si channel depends also on the deposition conditions for the underlying SiNx gate insulator. TFTs made with wet etching are more stable than TFTs made with reactive ion etching. Combining the various improvements raised the extrapolated 50% decay time of the drain current of back channel passivated dry-etched TFTs under continuous operation at 20°C from 3.3 × 104 sec (9.2 hours) to 4.4 × 107 sec (1.4 years). The 50% lifetime can be further improved by ~2 times through wet etching process. Two assumptions in the two-stage model were revisited. First, the distribution of the gap state density in a-Si was obtained with the field-effect technique. The redistribution of the gap state density after low-gate field stress supports the idea that defect creation in a-Si dominates in the long term. Second, the drain-bias dependence of drain current degradation was measured and modeled. The unified stretched exponential was validated for a-Si TFTs operating in saturation. Finally, a new 3-TFT voltage-programmed pixel circuit with an in-pixel current source is presented. This circuit is largely insensitive to the TFT threshold voltage… Advisors/Committee Members: Sturm, James C (advisor).

Subjects/Keywords: a-Si TFTs; fabrication conditions; stability; two-stage model; voltage-programmed pixel circuit

…or rganic and metal m oxide TFTs T (F Fig. 1.3) [14 4] and make e a-Si… …circuit compensation for aSi TFTs. Chapter 2 introduces a basic knowledge of a-Si and a-Si TFTs… …Si TFTs ..................... 45 4.1. Instability mechanisms in a-Si TFTs… …52 4.1.3 Summary of instability models for a-Si TFTs… …65 Chapter 5 Optimization of Fabrication Conditions for Highly Stable a-Si TFTs…

10 more images…

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APA (6^th Edition):

Liu, T. (2013). Stability of Amorphous Silicon Thin Film Transistors and Circuits . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01xs55mc14f

Chicago Manual of Style (16^th Edition):

Liu, Ting. “Stability of Amorphous Silicon Thin Film Transistors and Circuits .” 2013. Doctoral Dissertation, Princeton University. Accessed March 01, 2021. http://arks.princeton.edu/ark:/88435/dsp01xs55mc14f.

MLA Handbook (7^th Edition):

Liu, Ting. “Stability of Amorphous Silicon Thin Film Transistors and Circuits .” 2013. Web. 01 Mar 2021.

Vancouver:

Liu T. Stability of Amorphous Silicon Thin Film Transistors and Circuits . [Internet] [Doctoral dissertation]. Princeton University; 2013. [cited 2021 Mar 01]. Available from: http://arks.princeton.edu/ark:/88435/dsp01xs55mc14f.

Council of Science Editors:

Liu T. Stability of Amorphous Silicon Thin Film Transistors and Circuits . [Doctoral Dissertation]. Princeton University; 2013. Available from: http://arks.princeton.edu/ark:/88435/dsp01xs55mc14f

Brno University of Technology

19. Chyťa, Filip. Optimalizace technologie a detekce defektů keramických struktur: Optimization of fabrication technology and defect detection for ceramics structures.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/81622

► This work deals with the problems of defects in ceramics structures and packages, their detection and subsequent optimization of the manufacturing process in order to… (more)

Subjects/Keywords: Pouzdro; oxidová keramika; čip; pouzdření; integrovaný obvod; oxid hlinitý; Package; oxide ceramics; chip; packaging; integrated circuit; aluminum oxide

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APA (6^th Edition):

Chyťa, F. (2019). Optimalizace technologie a detekce defektů keramických struktur: Optimization of fabrication technology and defect detection for ceramics structures. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/81622

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chyťa, Filip. “Optimalizace technologie a detekce defektů keramických struktur: Optimization of fabrication technology and defect detection for ceramics structures.” 2019. Thesis, Brno University of Technology. Accessed March 01, 2021. http://hdl.handle.net/11012/81622.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chyťa, Filip. “Optimalizace technologie a detekce defektů keramických struktur: Optimization of fabrication technology and defect detection for ceramics structures.” 2019. Web. 01 Mar 2021.

Vancouver:

Chyťa F. Optimalizace technologie a detekce defektů keramických struktur: Optimization of fabrication technology and defect detection for ceramics structures. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/11012/81622.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chyťa F. Optimalizace technologie a detekce defektů keramických struktur: Optimization of fabrication technology and defect detection for ceramics structures. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/81622

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Michigan State University

20. Li, Lin (Electrical engineer). Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem.

Degree: 2017, Michigan State University

URL: http://etd.lib.msu.edu/islandora/object/etd:4572

►

Thesis Ph. D. Michigan State University. Electrical Engineering 2017

"Miniaturized biosensor arrays are attractive for parallel analysis of multiple parameters and targets. Overcoming the need… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary; Interconnects (Integrated circuit technology); Metal oxide semiconductors, Complementary – Design and construction; Biosensors; Electrical engineering

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APA (6^th Edition):

Li, L. (. e. (2017). Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem. (Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:4572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Lin (Electrical engineer). “Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem.” 2017. Thesis, Michigan State University. Accessed March 01, 2021. http://etd.lib.msu.edu/islandora/object/etd:4572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Lin (Electrical engineer). “Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem.” 2017. Web. 01 Mar 2021.

Vancouver:

Li L(e. Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem. [Internet] [Thesis]. Michigan State University; 2017. [cited 2021 Mar 01]. Available from: http://etd.lib.msu.edu/islandora/object/etd:4572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li L(e. Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem. [Thesis]. Michigan State University; 2017. Available from: http://etd.lib.msu.edu/islandora/object/etd:4572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Neveu, Florian. Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence.

Degree: Docteur es, Génie électrique, 2015, INSA Lyon

URL: http://www.theses.fr/2015ISAL0133

►

L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche… (more)

▼

L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche est compatible avec une intégration totale sur silicium, mais limitée en terme de densité de puissance. Le second axe est l’utilisation de convertisseurs à inductances, qui pâtissent d’imposants composants passifs. Une augmentation de la fréquence permet de réduire les valeurs des composants passifs. Cependant une augmentation de la fréquence implique une augmentation des pertes par commutation, ce qui est contrebalancé par l’utilisation d’une technologie de fabrication plus avancée. Ces technologies plus avancées souffrent quant à elles de limitations au niveau de leur tension d’utilisation. Convertir une tension de 3,3V vers une tension de 1,2V apparait donc comme un objectif ambitieux, particulièrement dans le cas où les objectifs de taille minimale et de rendement supérieur à 90 % sont visés. Un assemblage 3D des composants actifs et passifs permet de minimiser la surface du système. Un fonctionnement à haute fréquence est aussi considéré, ce qui permet de réduire les valeurs requises pour les composants passifs. Dans le contexte de l’alimentation « on-chip », la technologie silicium est contrainte par les fonctions numériques. Une technologie 40 nm CMOS de type « bulk » est choisie comme cas d’étude pour une tension d’entrée de 3,3 V. Les transistors 3,3 V présentent une figure de mérite médiocre, les transistors 1,2 V sont donc choisis. Ce choix permet en outre de présenter une meilleure compatibilité avec une future intégration sur puce. Une structure cascode utilisant trois transistors en série est étudiée est confrontée à une structure standard à travers des simulations et mesures. Une fréquence de +100MHz est choisie. Une technologie de capacités en tranchées est sélectionnée, et fabriquée sur une puce séparée qui servira d’interposeur et recevra la puce active et les inductances. Les inductances doivent être aussi fabriquées de manière intégrée afin de limiter leur impact sur la surface du convertisseur. Ce travail fournit un objet contenant un convertisseur de type Buck à une phase, avec la puce active retournée (« flip-chip ») sur l’interposeur capacitif, sur lequel une inductance est rapportée. Le démonstrateur une phase est compatible pour une démonstration à phases couplées. Les configurations standard et cascode sont comparées expérimentalement aux fréquences de 100 MHz et 200 MHz. La conception de la puce active est l’élément central de ce travail, l’interposeur capacitif étant fabriqué par IPDiA et les inductances par Tyndall National Institute. L’assemblage des différents sous-éléments est réalisé via des procédés industriels. Un important ensemble de mesures ont été réalisées, montrant les performances du convertisseur DC-DC délivré, ainsi que ses limitations. Un rendement pic de 91,5 % à la fréquence de 100 MHz a été démontré.

Ultimate integration of power switch-mode converter relies on two research…

Advisors/Committee Members: Allard, Bruno (thesis director).

Subjects/Keywords: Electronique de puissance; Convertisseur DC-DC; Haute fréquence; Système embarqué; Circuit intégré Complementary Metal Oxide SemiConductor - CMOS; Power Electronics; DC-DC converters; High fraquency; Integrated circuit; CMOS circuit; 621.317 072

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APA (6^th Edition):

Neveu, F. (2015). Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2015ISAL0133

Chicago Manual of Style (16^th Edition):

Neveu, Florian. “Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence.” 2015. Doctoral Dissertation, INSA Lyon. Accessed March 01, 2021. http://www.theses.fr/2015ISAL0133.

MLA Handbook (7^th Edition):

Neveu, Florian. “Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence.” 2015. Web. 01 Mar 2021.

Vancouver:

Neveu F. Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence. [Internet] [Doctoral dissertation]. INSA Lyon; 2015. [cited 2021 Mar 01]. Available from: http://www.theses.fr/2015ISAL0133.

Council of Science Editors:

Neveu F. Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence. [Doctoral Dissertation]. INSA Lyon; 2015. Available from: http://www.theses.fr/2015ISAL0133

Indian Institute of Science

22. Harish, B P. Process Variability-Aware Performance Modeling In 65 nm CMOS.

Degree: PhD, Faculty of Engineering, 2011, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/1080

► With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all… (more)

▼ With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation. We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM). To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets. Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level. Advisors/Committee Members: Bhat, Navakanta (advisor).

Subjects/Keywords: Complementary Metal Oxide Semiconductors; Semiconductors; NAND Gate; Gate Delay Models; CMOS Digital Circuits; Circuit Design; Circuit Delay Performance; Circuit Delay Distribution; CMOS Designs; 65nm CMOS; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Harish, B. P. (2011). Process Variability-Aware Performance Modeling In 65 nm CMOS. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/1080

Chicago Manual of Style (16^th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2011. Doctoral Dissertation, Indian Institute of Science. Accessed March 01, 2021. http://etd.iisc.ac.in/handle/2005/1080.

MLA Handbook (7^th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2011. Web. 01 Mar 2021.

Vancouver:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2011. [cited 2021 Mar 01]. Available from: http://etd.iisc.ac.in/handle/2005/1080.

Council of Science Editors:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Doctoral Dissertation]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ac.in/handle/2005/1080

Hong Kong University of Science and Technology

23. Li, Suwen ECE. CMOS-compatible carbon nanotube via technology.

Degree: 2017, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-91057 ; https://doi.org/10.14711/thesis-991012554660903412 ; http://repository.ust.hk/ir/bitstream/1783.1-91057/1/th_redirect.html

► The continuous scaling of integrated circuit technology is challenging the Cu interconnect’s physical limit. The resistivity of Cu increases rapidly due to scattering, leading to… (more)

▼ The continuous scaling of integrated circuit technology is challenging the Cu interconnect’s physical limit. The resistivity of Cu increases rapidly due to scattering, leading to a large signal transmission delay. Furthermore, the increasing current density makes Cu interconnects unreliable due to electromigration. Carbon nanotubes (CNTs) are a promising alternative for vertical interconnects (vias) owing to their high current density capacity, electrical/thermal conductivity and high aspect ratios. We developed CMOS-compatible CNT synthesis approaches on Ti silicide and Ni silicide substrates. A multilayer (Ni/Al/Ni) catalyst design was proposed to enhance nanoparticle formation by suppressing the diffusion of Ni into silicide and sintering of the Ni nanoparticles. Owing to the stable, high-density and evenly distributed nanoparticle catalysts with the multilayer catalyst design, we have synthesized vertically aligned multiwall CNTs (MWCNTs) with a wall density of 5.2 X 10¹² cm^-2. The proposed catalyst design enables CNT synthesis at temperatures as low as 350°C. We developed a CNT via integration technology. To effectively preserve the surface properties of CNT tips and thus reduce the contact resistance of the CNT via, an integration process combining selective CNT growth and O₂ plasma-assisted post-CNT treatment was explored. A low CNT via resistance of 1.08 X 10^-6Ωcm² is obtained by preserving the CNT’s surface properties, enabling inner walls of MWCNTs for parallel current conduction and eliminating the side-wall CNT growth. The scalability of CNT via technology is studied through the fabrication of sub-100 nm CNT vias on Ni silicide and investigation on the scaling trend. The preliminary integration of submicron CNT vias with silicided Si transistors suggests the functionality of the transistor after integration. The CMOS-compatible CNT via technology developed in this thesis is a step forward towards the application of CNT interconnects in CMOS technology.

Subjects/Keywords: Carbon nanotubes ; Interconnects (Integrated circuit technology) ; Metal oxide semiconductors, Complementary ; Design and construction

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APA (6^th Edition):

Li, S. E. (2017). CMOS-compatible carbon nanotube via technology. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-91057 ; https://doi.org/10.14711/thesis-991012554660903412 ; http://repository.ust.hk/ir/bitstream/1783.1-91057/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Suwen ECE. “CMOS-compatible carbon nanotube via technology.” 2017. Thesis, Hong Kong University of Science and Technology. Accessed March 01, 2021. http://repository.ust.hk/ir/Record/1783.1-91057 ; https://doi.org/10.14711/thesis-991012554660903412 ; http://repository.ust.hk/ir/bitstream/1783.1-91057/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Suwen ECE. “CMOS-compatible carbon nanotube via technology.” 2017. Web. 01 Mar 2021.

Vancouver:

Li SE. CMOS-compatible carbon nanotube via technology. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2017. [cited 2021 Mar 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-91057 ; https://doi.org/10.14711/thesis-991012554660903412 ; http://repository.ust.hk/ir/bitstream/1783.1-91057/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li SE. CMOS-compatible carbon nanotube via technology. [Thesis]. Hong Kong University of Science and Technology; 2017. Available from: http://repository.ust.hk/ir/Record/1783.1-91057 ; https://doi.org/10.14711/thesis-991012554660903412 ; http://repository.ust.hk/ir/bitstream/1783.1-91057/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Iowa State University

24. Zhang, Xu. An integrated circuit solution to Johnson noise thermometry and high-speed three-stage amplifier design.

Degree: 2019, Iowa State University

URL: https://lib.dr.iastate.edu/etd/17816

► Temperature is fundamentally important not only to physics, but also to all sciences, industry, commerce, and everyday life. As a phenomenon related to the absolute… (more)

▼ Temperature is fundamentally important not only to physics, but also to all sciences, industry, commerce, and everyday life. As a phenomenon related to the absolute temperature, the random thermal motion of the electrons in a conductive resistor gives a voltage noise proportional to the temperature, and this phenomenon is called Johnson noise. The Johnson noise thermometry (JNT) is based on measuring the electronic noise spectrum or power of a resistor in thermal equilibrium. This method is extremely linear from a few kelvins to over one thousand kelvins. This powerful observation has motivated numerous scientists to develop accurate JNTs to rival those traditional primary thermometers, such as ideal gas thermometers and radiation thermometers. For example, for the last decade, the National Institute of Standards and Technology (NIST) has made great efforts on developing JNTs, which have a wide temperature range and minimal involvement of the material properties. However, even with all these contributions, most of the JNT solutions are still bulky and very slow. In this work, an integrated circuit (IC) solution to the JNTs in the complementary metal-oxide-semiconductor (CMOS) technology is discussed. By moving to an IC solution, the speed bottleneck is eliminated, and the proposed IC-based JNT can operate at the speed that is hundreds of times faster than the JNTs with discrete components. As an initial exploration of the CMOS JNT system, this work reviews the existing solutions and techniques as the JNT basics. The challenges of the existing designs, as well as the advantages of CMOS implementations, are discussed. In addition, as the main part of this project, the analyses of the JNT designs in the CMOS technology are emphasis and are firstly provided in this work. The analyses in this work include the noise analysis of the CMOS preamplifier, the speed requirement, and the resolution requirement on the analog-to-digital converter detection circuit. At last, the simulation results and test results are provided to verify the concept of this IC JNT solution.

Subjects/Keywords: Complementary metal–oxide–semiconductor; Integrated circuit; Johnson noise thermometry; Three-stage amplifier; Electrical and Electronics

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APA (6^th Edition):

Zhang, X. (2019). An integrated circuit solution to Johnson noise thermometry and high-speed three-stage amplifier design. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/17816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zhang, Xu. “An integrated circuit solution to Johnson noise thermometry and high-speed three-stage amplifier design.” 2019. Thesis, Iowa State University. Accessed March 01, 2021. https://lib.dr.iastate.edu/etd/17816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zhang, Xu. “An integrated circuit solution to Johnson noise thermometry and high-speed three-stage amplifier design.” 2019. Web. 01 Mar 2021.

Vancouver:

Zhang X. An integrated circuit solution to Johnson noise thermometry and high-speed three-stage amplifier design. [Internet] [Thesis]. Iowa State University; 2019. [cited 2021 Mar 01]. Available from: https://lib.dr.iastate.edu/etd/17816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang X. An integrated circuit solution to Johnson noise thermometry and high-speed three-stage amplifier design. [Thesis]. Iowa State University; 2019. Available from: https://lib.dr.iastate.edu/etd/17816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of California – San Diego

25. Zhuang, Hao. Exponential Time Integration for Transient Analysis of Large-Scale Circuits.

Degree: Computer Science, 2016, University of California – San Diego

URL: http://www.escholarship.org/uc/item/60d8c2r6

► Transient analysis of large-scale circuits relies on efficient numerical time integration algorithms. In this thesis, we focus on the high-order exponential integration and the explicit… (more)

Subjects/Keywords: Computer science; Applied mathematics; Electrical engineering; circuit simulation; dynamical systems; exponential time integration; Krylov subspace; numerical integration; power network

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APA (6^th Edition):

Zhuang, H. (2016). Exponential Time Integration for Transient Analysis of Large-Scale Circuits. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/60d8c2r6

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zhuang, Hao. “Exponential Time Integration for Transient Analysis of Large-Scale Circuits.” 2016. Thesis, University of California – San Diego. Accessed March 01, 2021. http://www.escholarship.org/uc/item/60d8c2r6.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zhuang, Hao. “Exponential Time Integration for Transient Analysis of Large-Scale Circuits.” 2016. Web. 01 Mar 2021.

Vancouver:

Zhuang H. Exponential Time Integration for Transient Analysis of Large-Scale Circuits. [Internet] [Thesis]. University of California – San Diego; 2016. [cited 2021 Mar 01]. Available from: http://www.escholarship.org/uc/item/60d8c2r6.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhuang H. Exponential Time Integration for Transient Analysis of Large-Scale Circuits. [Thesis]. University of California – San Diego; 2016. Available from: http://www.escholarship.org/uc/item/60d8c2r6

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Columbia University

26. Li, Jiangyi. Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications.

Degree: 2018, Columbia University

URL: https://doi.org/10.7916/D8BG45XN

► Heading towards the era of Internet-of-things (IoT) means both opportunity and challenge for the circuit-design community. In a system where billions of devices are equipped… (more)

▼ Heading towards the era of Internet-of-things (IoT) means both opportunity and challenge for the circuit-design community. In a system where billions of devices are equipped with the ability to sense, compute, communicate with each other and perform tasks in a coordinated manner, security and power management are among the most critical challenges. Physically unclonable function (PUF) emerges as an important security primitive in hardware-security applications; it provides an object-specific physical identifier hidden within the intrinsic device variations, which is hard to expose and reproduce by adversaries. Yet, designing a compact PUF robust to noise, temperature and voltage remains a challenge. This thesis presents a novel PUF design approach based on a pair of ultra-compact analog circuits whose output is proportional to absolute temperature. The proposed approach is demonstrated through two works: (1) an ultra-compact and robust PUF based on voltage-compensated proportional-to-absolute-temperature voltage generators that occupies 8.3× less area than the previous work with the similar robustness and twice the robustness of the previously most compact PUF design and (2) a technique to transform a 6T-SRAM array into a robust analog PUF with minimal overhead. In this work, similar circuit topology is used to transform a preexisting on-chip SRAM into a PUF, which further reduces the area in (1) with no robustness penalty. In this thesis, we also explore techniques for power management circuit design. Energy harvesting is an essential functionality in an IoT sensor node, where battery replacement is cost-prohibitive or impractical. Yet, existing energy-harvesting power management units (EH PMU) suffer from efficiency loss in the two-step voltage conversion: harvester-to-battery and battery-to-load. We propose an EH PMU architecture with hybrid energy storage, where a capacitor is introduced in addition to the battery to serve as an intermediate energy buffer to minimize the battery involvement in the system energy flow. Test-case measurements show as much as a 2.2× improvement in the end-to-end energy efficiency. In contrast, with the drastically reduced power consumption of IoT nodes that operates in the sub-threshold regime, adaptive dynamic voltage scaling (DVS) for supply-voltage margin removal, fully on-chip integration and high power conversion efficiency (PCE) are required in PMU designs. We present a PMU–load co-design based on a fully integrated switched-capacitor DC-DC converter (SC-DC) and hybrid error/replica-based regulation for a fully digital PMU control. The PMU is integrated with a neural spike processor (NSP) that achieves a record-low power consumption of 0.61 µW for 96 channels. A tunable replica circuit is added to assist the error regulation and prevent loss of regulation. With automatic energy-robustness co-optimization, the PMU can set the SC-DC’s optimal conversion ratio and switching frequency. The PMU achieves a PCE of 77.7% (72.2%) at VIN = 0.6 V (1 V) and…

Subjects/Keywords: Electrical engineering; Internet of things; Electronic circuit design; Integrated circuits – Very large scale integration

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APA (6^th Edition):

Li, J. (2018). Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8BG45XN

Chicago Manual of Style (16^th Edition):

Li, Jiangyi. “Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications.” 2018. Doctoral Dissertation, Columbia University. Accessed March 01, 2021. https://doi.org/10.7916/D8BG45XN.

MLA Handbook (7^th Edition):

Li, Jiangyi. “Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications.” 2018. Web. 01 Mar 2021.

Vancouver:

Li J. Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications. [Internet] [Doctoral dissertation]. Columbia University; 2018. [cited 2021 Mar 01]. Available from: https://doi.org/10.7916/D8BG45XN.

Council of Science Editors:

Li J. Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications. [Doctoral Dissertation]. Columbia University; 2018. Available from: https://doi.org/10.7916/D8BG45XN

The Ohio State University

27. Bonavita, Peter J. A Multiscale Finite Element Modeling Approach for Thermal Management in Heterogeneous Integrated Circuits.

Degree: MS, Mechanical Engineering, 2019, The Ohio State University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu155507820020889

► Modern radio frequency (RF) microsystems are challenged to deliver improved performance across an ever-changing landscape of applications and requirements. As the demand for high-power and… (more)

Subjects/Keywords: Engineering; Electrical Engineering; Mechanical Engineering; heterogeneous integration; thermal; simulation; multiscale; integrated circuit; finite element; submodel

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APA (6^th Edition):

Bonavita, P. J. (2019). A Multiscale Finite Element Modeling Approach for Thermal Management in Heterogeneous Integrated Circuits. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu155507820020889

Chicago Manual of Style (16^th Edition):

Bonavita, Peter J. “A Multiscale Finite Element Modeling Approach for Thermal Management in Heterogeneous Integrated Circuits.” 2019. Masters Thesis, The Ohio State University. Accessed March 01, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu155507820020889.

MLA Handbook (7^th Edition):

Bonavita, Peter J. “A Multiscale Finite Element Modeling Approach for Thermal Management in Heterogeneous Integrated Circuits.” 2019. Web. 01 Mar 2021.

Vancouver:

Bonavita PJ. A Multiscale Finite Element Modeling Approach for Thermal Management in Heterogeneous Integrated Circuits. [Internet] [Masters thesis]. The Ohio State University; 2019. [cited 2021 Mar 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu155507820020889.

Council of Science Editors:

Bonavita PJ. A Multiscale Finite Element Modeling Approach for Thermal Management in Heterogeneous Integrated Circuits. [Masters Thesis]. The Ohio State University; 2019. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu155507820020889

28. Michard, Audrey. Conception et caractérisation d’un transmetteur électro-optique dans une plateforme photonique sur silicium visant des communications très haut débit : Design and characterization of an electro-optic transmitter in a silicon photonics platform for high data rate communications.

Degree: Docteur es, Electronique et Optoélectronique, Nano- et Microtechnologies, 2018, Université Paris-Saclay (ComUE)

URL: http://www.theses.fr/2018SACLC087

►

La photonique sur silicium connaît depuis plusieurs années un fort développement avec la démonstration d’importants résultats concernant les interconnexions optiques. En effet, l’explosion du trafic… (more)

▼

La photonique sur silicium connaît depuis plusieurs années un fort développement avec la démonstration d’importants résultats concernant les interconnexions optiques. En effet, l’explosion du trafic de données au sein des centres de données a nécessité de trouver une solution annexe aux interconnexions métalliques afin de supporter de très hauts débits de transmission, tout en assurant une faible consommation énergétique et un coût raisonnable. Les applications de la photonique se situent d’une part dans le domaine des communications à longue distance entre équipements dont les standards actuels visent un débit de 400 Gb/s, et d’autre part dans le domaine des calculateurs à haute performance afin de réaliser les interconnexions courte distance entre un processeur et une banque de mémoires.STMicroelectronics s’est lancé depuis 2012 dans le développement d’une plateforme photonique sur silicium sur wafers de 300mm. Les principaux objectifs sont : la conception des composants optiques passifs et actifs pour réaliser un transceiver élémentaire à un débit de 20 Gb/s, l’intégration accrue des dispositifs électro-optiques afin de constituer un interposeur photonique, la capacité à gérer plusieurs longueurs d’onde.Dans ce contexte, le sujet de cette thèse porte sur la mise au point d’un circuit de qualification proposant l’intégration d’un transmetteur électro-optique à l’échelle de la puce.Cette solution tire bénéfice de l’architecture de l’assemblage en trois dimensions des éléments constitutifs au sein de l’interposeur et permet de traiter l’hétérogénéité des composants électriques et optiques.Dans ces travaux, nous proposons dans un premier temps d’étudier le modulateur optique. Celui-ci repose sur l’utilisation d’un anneau résonant dont la bande passante est optimisée afin de permettre des débits jusqu’à 50 Gb/s. Dans un second temps, nous décrivons la conception du driver électrique en technologie CMOS 55nm et expliquons le compromis mis en jeu entre la vitesse et la puissance consommée par le transmetteur. Les deux dispositifs sont fabriqués sur des plateformes distinctes, puis caractérisés et analysés par rapport à leur modèle respectif. Puis, nous réalisons une première intégration du transmetteur complet via un assemblage wire-bonding, ce qui nous permet de valider son fonctionnement et d’identifier les difficultés d’une telle co-intégration. Enfin, la dernière partie de la thèse est consacrée à la préparation d’un démonstrateur intégrant, dans un assemblage 3D à base de micro-piliers en cuivre, un lien électro-optique capable de transmettre 16 canaux à 20 Gb/s. Le multiplexage en longueurs d’onde déployé dans ce lien devrait permettre d’atteindre un débit total de 320 Gb/s. De plus, l’étude énergétique du système permet de s’assurer que l’interconnexion finale respectera les contraintes de consommation de puissance.

Stimulated by a series of important breakthrough, silicon photonics has been experiencing a significant development for several years. Indeed, due to exponential growth of data traffic inside…

Advisors/Committee Members: Bénabes, Philippe (thesis director).

Subjects/Keywords: Photonique sur silicium; Circuit de qualification; Microélectronique; Intégration hybride; Silicon photonics; Testchip; Microelectronics; Hybrid integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Michard, A. (2018). Conception et caractérisation d’un transmetteur électro-optique dans une plateforme photonique sur silicium visant des communications très haut débit : Design and characterization of an electro-optic transmitter in a silicon photonics platform for high data rate communications. (Doctoral Dissertation). Université Paris-Saclay (ComUE). Retrieved from http://www.theses.fr/2018SACLC087

Chicago Manual of Style (16^th Edition):

Michard, Audrey. “Conception et caractérisation d’un transmetteur électro-optique dans une plateforme photonique sur silicium visant des communications très haut débit : Design and characterization of an electro-optic transmitter in a silicon photonics platform for high data rate communications.” 2018. Doctoral Dissertation, Université Paris-Saclay (ComUE). Accessed March 01, 2021. http://www.theses.fr/2018SACLC087.

MLA Handbook (7^th Edition):

Michard, Audrey. “Conception et caractérisation d’un transmetteur électro-optique dans une plateforme photonique sur silicium visant des communications très haut débit : Design and characterization of an electro-optic transmitter in a silicon photonics platform for high data rate communications.” 2018. Web. 01 Mar 2021.

Vancouver:

Michard A. Conception et caractérisation d’un transmetteur électro-optique dans une plateforme photonique sur silicium visant des communications très haut débit : Design and characterization of an electro-optic transmitter in a silicon photonics platform for high data rate communications. [Internet] [Doctoral dissertation]. Université Paris-Saclay (ComUE); 2018. [cited 2021 Mar 01]. Available from: http://www.theses.fr/2018SACLC087.

Council of Science Editors:

Michard A. Conception et caractérisation d’un transmetteur électro-optique dans une plateforme photonique sur silicium visant des communications très haut débit : Design and characterization of an electro-optic transmitter in a silicon photonics platform for high data rate communications. [Doctoral Dissertation]. Université Paris-Saclay (ComUE); 2018. Available from: http://www.theses.fr/2018SACLC087

Anna University

29. Suveetha dhanaselvam P. Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;.

Degree: Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/43541

►

The steady down scaling of complementary metal oxide newlinesemiconductor CMOS device dimensions have lifted the era of micro newlineelectronics and computer aided ultra large scale… (more)

Subjects/Keywords: Complementary metal oxide semiconductor; Ultra large scale integration

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APA (6^th Edition):

P, S. d. (2015). Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/43541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

P, Suveetha dhanaselvam. “Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;.” 2015. Thesis, Anna University. Accessed March 01, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/43541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

P, Suveetha dhanaselvam. “Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;.” 2015. Web. 01 Mar 2021.

Vancouver:

P Sd. Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 01]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/43541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P Sd. Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/43541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

30. Ajayan, K R. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.

Degree: PhD, Faculty of Engineering, 2018, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/3516

► Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As… (more)

▼ Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model… Advisors/Committee Members: Bhat, Navakanta (advisor).

Subjects/Keywords: Metal Oxide Semiconductors (MOS); Digital Integrated Circuits; Complementary Metal Oxide Semiconductors (CMOS); N-type Metal-Oxide Semiconductors (NMOS); P-type Metal-Oxide Semiconductors (PMOS); Metal Oxode Semiconductor Device Modeling; Look Up Table Model (LUT); Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET); MOSFET Models; BSIM Models; Variability Aware Device Modeling; Integrated Circuit Modeling; Circuit Design; 45nm Analog CMOS Technology; Electrical Communication Engineering

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APA (6^th Edition):

Ajayan, K. R. (2018). Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3516

Chicago Manual of Style (16^th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed March 01, 2021. http://etd.iisc.ac.in/handle/2005/3516.

MLA Handbook (7^th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2018. Web. 01 Mar 2021.

Vancouver:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2021 Mar 01]. Available from: http://etd.iisc.ac.in/handle/2005/3516.

Council of Science Editors:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3516

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