Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Optical network on chip). Showing records 1 – 30 of 48728 total matches.

[1] [2] [3] [4] [5] … [1625]

Search Limiters

Last 2 Years | English Only

Degrees

Languages

Country

▼ Search Limiters


Texas A&M University

1. Wang, Lei. High Performance Interconnect System Design for Future Chip Multiprocessors.

Degree: 2013, Texas A&M University

Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP… (more)

Subjects/Keywords: Network-On-Chip; Chip Multiprocessors

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, L. (2013). High Performance Interconnect System Design for Future Chip Multiprocessors. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Lei. “High Performance Interconnect System Design for Future Chip Multiprocessors.” 2013. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/149541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Lei. “High Performance Interconnect System Design for Future Chip Multiprocessors.” 2013. Web. 24 Jan 2020.

Vancouver:

Wang L. High Performance Interconnect System Design for Future Chip Multiprocessors. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/149541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang L. High Performance Interconnect System Design for Future Chip Multiprocessors. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

2. Yang, Peng ECE. Rack-scale multi-domain optical networks for high-performance computing systems.

Degree: 2018, Hong Kong University of Science and Technology

 Rack-scale computing systems are expected to meet the computation and energy requirements of big data and emerging large-scale applications. They need to efficiently coordinate both… (more)

Subjects/Keywords: Optical communications ; Computer network architectures ; Networks on a chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, P. E. (2018). Rack-scale multi-domain optical networks for high-performance computing systems. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-96013 ; https://doi.org/10.14711/thesis-991012637269003412 ; http://repository.ust.hk/ir/bitstream/1783.1-96013/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Peng ECE. “Rack-scale multi-domain optical networks for high-performance computing systems.” 2018. Thesis, Hong Kong University of Science and Technology. Accessed January 24, 2020. http://repository.ust.hk/ir/Record/1783.1-96013 ; https://doi.org/10.14711/thesis-991012637269003412 ; http://repository.ust.hk/ir/bitstream/1783.1-96013/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Peng ECE. “Rack-scale multi-domain optical networks for high-performance computing systems.” 2018. Web. 24 Jan 2020.

Vancouver:

Yang PE. Rack-scale multi-domain optical networks for high-performance computing systems. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2018. [cited 2020 Jan 24]. Available from: http://repository.ust.hk/ir/Record/1783.1-96013 ; https://doi.org/10.14711/thesis-991012637269003412 ; http://repository.ust.hk/ir/bitstream/1783.1-96013/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang PE. Rack-scale multi-domain optical networks for high-performance computing systems. [Thesis]. Hong Kong University of Science and Technology; 2018. Available from: http://repository.ust.hk/ir/Record/1783.1-96013 ; https://doi.org/10.14711/thesis-991012637269003412 ; http://repository.ust.hk/ir/bitstream/1783.1-96013/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

3. Mandal, Ayan. Efficient Design and Clocking for a Network-on-Chip.

Degree: 2013, Texas A&M University

 As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC)… (more)

Subjects/Keywords: Network-on-Chip; Clock; VLSI

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mandal, A. (2013). Efficient Design and Clocking for a Network-on-Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/149325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Web. 24 Jan 2020.

Vancouver:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/149325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

4. Rasheed, Shalimar. A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.

Degree: 2014, Texas A&M University

 Networks-on-Chip (NoCs) offer a scalable means of on-chip communication for future many-core chips. As NoC size increases with core count in future many-core chips, NoC… (more)

Subjects/Keywords: Network-on-Chip; Router

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rasheed, S. (2014). A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rasheed, Shalimar. “A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.” 2014. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/152655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rasheed, Shalimar. “A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.” 2014. Web. 24 Jan 2020.

Vancouver:

Rasheed S. A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/152655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rasheed S. A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

5. Ieong, Ka Chon. A Virtual Prototype of Scalable Network-on-Chip Design.

Degree: 2014, Texas A&M University

 A Virtual Prototype of Network-on-Chip (NoC) that interconnects IPs in System-on-Chip is presented in this thesis. A Virtual Prototype is a software model describing various… (more)

Subjects/Keywords: Virtual Prototype; Network-on-Chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ieong, K. C. (2014). A Virtual Prototype of Scalable Network-on-Chip Design. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152730

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ieong, Ka Chon. “A Virtual Prototype of Scalable Network-on-Chip Design.” 2014. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/152730.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ieong, Ka Chon. “A Virtual Prototype of Scalable Network-on-Chip Design.” 2014. Web. 24 Jan 2020.

Vancouver:

Ieong KC. A Virtual Prototype of Scalable Network-on-Chip Design. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/152730.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ieong KC. A Virtual Prototype of Scalable Network-on-Chip Design. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152730

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

6. Elshennawy, Amr. An Asynchronous Network-On-Chip Router with Low Standby Power.

Degree: 2014, Texas A&M University

 The Network-on-Chip (NoC) paradigm is now widely used to interconnect the processing elements (PEs) in a chip multiprocessor (CMP). It has been reported that the… (more)

Subjects/Keywords: Network-on-Chip; Asynchronous; Leakage

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Elshennawy, A. (2014). An Asynchronous Network-On-Chip Router with Low Standby Power. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/153947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Elshennawy, Amr. “An Asynchronous Network-On-Chip Router with Low Standby Power.” 2014. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/153947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Elshennawy, Amr. “An Asynchronous Network-On-Chip Router with Low Standby Power.” 2014. Web. 24 Jan 2020.

Vancouver:

Elshennawy A. An Asynchronous Network-On-Chip Router with Low Standby Power. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/153947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Elshennawy A. An Asynchronous Network-On-Chip Router with Low Standby Power. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/153947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

7. Sudha S. Enhanced reliable and adaptive Routing models for networks on chip;.

Degree: Enhanced reliable and adaptive Routing models for networks on chip, 2014, Anna University

The main objective of this research is to develop a reliable and newlineCongestion aware adaptive routing model to improve the performance of the newlineNetwork on… (more)

Subjects/Keywords: Greedy algorithm; Network on Chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

S, S. (2014). Enhanced reliable and adaptive Routing models for networks on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/26114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

S, Sudha. “Enhanced reliable and adaptive Routing models for networks on chip;.” 2014. Thesis, Anna University. Accessed January 24, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/26114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

S, Sudha. “Enhanced reliable and adaptive Routing models for networks on chip;.” 2014. Web. 24 Jan 2020.

Vancouver:

S S. Enhanced reliable and adaptive Routing models for networks on chip;. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Jan 24]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

S S. Enhanced reliable and adaptive Routing models for networks on chip;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

8. Hu, Jianchen. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.

Degree: MS, Electrical Engineering, 2009, North Carolina State University

 As the complexity of SoC design grows, the traditional register transfer level (RTL) centric design flow cannot meet the time to market. In that case,… (more)

Subjects/Keywords: interconnect; TLM; Network-on-chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hu, J. (2009). Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hu, Jianchen. “Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.” 2009. Thesis, North Carolina State University. Accessed January 24, 2020. http://www.lib.ncsu.edu/resolver/1840.16/1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hu, Jianchen. “Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.” 2009. Web. 24 Jan 2020.

Vancouver:

Hu J. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. [Internet] [Thesis]. North Carolina State University; 2009. [cited 2020 Jan 24]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hu J. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. [Thesis]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

9. Kukreja, R.S. Modeling and performance analysis of a high bandwidth, low power ring interconnect:.

Degree: 2015, Delft University of Technology

 As technology is improving and the performance of a single core has reached its peak performance, Multicore Systems on Chip have emerged as the trend… (more)

Subjects/Keywords: Interconnect; Network on Chip; Ring

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kukreja, R. S. (2015). Modeling and performance analysis of a high bandwidth, low power ring interconnect:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c2831f45-8cc5-4e14-8065-c98d54665d7e

Chicago Manual of Style (16th Edition):

Kukreja, R S. “Modeling and performance analysis of a high bandwidth, low power ring interconnect:.” 2015. Masters Thesis, Delft University of Technology. Accessed January 24, 2020. http://resolver.tudelft.nl/uuid:c2831f45-8cc5-4e14-8065-c98d54665d7e.

MLA Handbook (7th Edition):

Kukreja, R S. “Modeling and performance analysis of a high bandwidth, low power ring interconnect:.” 2015. Web. 24 Jan 2020.

Vancouver:

Kukreja RS. Modeling and performance analysis of a high bandwidth, low power ring interconnect:. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2020 Jan 24]. Available from: http://resolver.tudelft.nl/uuid:c2831f45-8cc5-4e14-8065-c98d54665d7e.

Council of Science Editors:

Kukreja RS. Modeling and performance analysis of a high bandwidth, low power ring interconnect:. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:c2831f45-8cc5-4e14-8065-c98d54665d7e


Texas A&M University

10. Patra, Biplab. Hybrid Router Design for High Performance Photonic Network-On-Chip.

Degree: MS, Computer Engineering, 2015, Texas A&M University

 With rising density of cores in Chip-Multiprocessors, traditional metallic interconnects won't be able to cater to the high demand in communication bandwidth at lower power… (more)

Subjects/Keywords: Photonic; Network-on-chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patra, B. (2015). Hybrid Router Design for High Performance Photonic Network-On-Chip. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/186979

Chicago Manual of Style (16th Edition):

Patra, Biplab. “Hybrid Router Design for High Performance Photonic Network-On-Chip.” 2015. Masters Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/186979.

MLA Handbook (7th Edition):

Patra, Biplab. “Hybrid Router Design for High Performance Photonic Network-On-Chip.” 2015. Web. 24 Jan 2020.

Vancouver:

Patra B. Hybrid Router Design for High Performance Photonic Network-On-Chip. [Internet] [Masters thesis]. Texas A&M University; 2015. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/186979.

Council of Science Editors:

Patra B. Hybrid Router Design for High Performance Photonic Network-On-Chip. [Masters Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/186979


Texas A&M University

11. An, Baik Song. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.

Degree: 2012, Texas A&M University

 High performance systems have been widely adopted in many fields and the demand for better performance is constantly increasing. And the need of powerful yet… (more)

Subjects/Keywords: computer architecture; chip multiprocessor; network-on-chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

An, B. S. (2012). Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

An, Baik Song. “Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.” 2012. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

An, Baik Song. “Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.” 2012. Web. 24 Jan 2020.

Vancouver:

An BS. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

An BS. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

12. Carpenter, Aaron (1983 - ). The design and use of high-speed transmission line links for global on-chip communication.

Degree: PhD, 2012, University of Rochester

 As transistors approach the limits of traditional scaling, computer architects can no longer rely on the increase in density and core frequency to improve the… (more)

Subjects/Keywords: Interconnect; Chip multiprocessor; On-chip-network; On-chip communication; Transmission lines

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carpenter, A. (. -. ). (2012). The design and use of high-speed transmission line links for global on-chip communication. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/21272

Chicago Manual of Style (16th Edition):

Carpenter, Aaron (1983 - ). “The design and use of high-speed transmission line links for global on-chip communication.” 2012. Doctoral Dissertation, University of Rochester. Accessed January 24, 2020. http://hdl.handle.net/1802/21272.

MLA Handbook (7th Edition):

Carpenter, Aaron (1983 - ). “The design and use of high-speed transmission line links for global on-chip communication.” 2012. Web. 24 Jan 2020.

Vancouver:

Carpenter A(-). The design and use of high-speed transmission line links for global on-chip communication. [Internet] [Doctoral dissertation]. University of Rochester; 2012. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1802/21272.

Council of Science Editors:

Carpenter A(-). The design and use of high-speed transmission line links for global on-chip communication. [Doctoral Dissertation]. University of Rochester; 2012. Available from: http://hdl.handle.net/1802/21272

13. Magnos Roberto Pizzoni. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.

Degree: 2010, Universidade do Vale do Itajaí

Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos… (more)

Subjects/Keywords: System-on-Chip; Network-on-Chip; Avaliação de desempenho; CIENCIA DA COMPUTACAO; Circuitos integrados; System-on-Chip; Network-on-Chip; Performance

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pizzoni, M. R. (2010). PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Thesis, Universidade do Vale do Itajaí. Accessed January 24, 2020. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Web. 24 Jan 2020.

Vancouver:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2010. [cited 2020 Jan 24]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Thesis]. Universidade do Vale do Itajaí; 2010. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

14. Gebhardt, Daniel J. Energy-efficient design of an asynchronous network-on-chip.

Degree: PhD, Computer Science, 2011, University of Utah

 Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are… (more)

Subjects/Keywords: Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gebhardt, D. J. (2011). Energy-efficient design of an asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Chicago Manual of Style (16th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed January 24, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

MLA Handbook (7th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Web. 24 Jan 2020.

Vancouver:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2020 Jan 24]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

Council of Science Editors:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871


Anna University

15. Saravanakumar U. An investigation on macro and micro Architectures for network on chip;.

Degree: An investigation on macro and micro Architectures for network on chip, 2015, Anna University

As the technology scales down more processors or Processing newlineElements PEs are integrated in the same die and such technology is called as newlineMultiprocessor System… (more)

Subjects/Keywords: Microarchitectural aims; Multiprocessor System on Chip; Network on Chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

U, S. (2015). An investigation on macro and micro Architectures for network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Thesis, Anna University. Accessed January 24, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Web. 24 Jan 2020.

Vancouver:

U S. An investigation on macro and micro Architectures for network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Jan 24]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

U S. An investigation on macro and micro Architectures for network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

16. Malave-Bonet, Javier. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.

Degree: 2012, Texas A&M University

Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused… (more)

Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 24 Jan 2020.

Vancouver:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

17. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: 2012, Texas A&M University

 With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 24 Jan 2020.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Viswanathan N. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.

Degree: Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters, 2015, Anna University

Three dimensional integration is one of the emerging techniques newlineto find solution for the global interconnect delay challenges faced in the newlineadvanced VLSI ULSI technology… (more)

Subjects/Keywords: Network on Chip; System on Chip; Through Silicon Via

Page 1

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

N, V. (2015). Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Thesis, Anna University. Accessed January 24, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Web. 24 Jan 2020.

Vancouver:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Jan 24]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

19. Park, Dongkook. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures.

Degree: PhD, Computer Science and Engineering, 2008, Penn State University

 The notion of a Network-on-Chip (NoC) is rapidly gaining a foothold as the communication fabric in complex System-on-Chip (SoC) architectures including recent Multi-Core architectures. Scalability… (more)

Subjects/Keywords: Network-on-Chip; on-chip interconnection; low-power; reliability; router architecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, D. (2008). Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/8203

Chicago Manual of Style (16th Edition):

Park, Dongkook. “Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures.” 2008. Doctoral Dissertation, Penn State University. Accessed January 24, 2020. https://etda.libraries.psu.edu/catalog/8203.

MLA Handbook (7th Edition):

Park, Dongkook. “Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures.” 2008. Web. 24 Jan 2020.

Vancouver:

Park D. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures. [Internet] [Doctoral dissertation]. Penn State University; 2008. [cited 2020 Jan 24]. Available from: https://etda.libraries.psu.edu/catalog/8203.

Council of Science Editors:

Park D. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures. [Doctoral Dissertation]. Penn State University; 2008. Available from: https://etda.libraries.psu.edu/catalog/8203


Delft University of Technology

20. Escudero Martínez, M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.

Degree: 2010, Delft University of Technology

 Prototyping Systems on Chip (SoC) on FPGA technology improves the time that the de- signer needs to spend in the verification stage when developing new… (more)

Subjects/Keywords: network on chip; NoC; system on chip; SoC; bridge; FPGA; prototyping

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Escudero Martínez, M. (2010). An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847

Chicago Manual of Style (16th Edition):

Escudero Martínez, M. “An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.” 2010. Masters Thesis, Delft University of Technology. Accessed January 24, 2020. http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847.

MLA Handbook (7th Edition):

Escudero Martínez, M. “An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.” 2010. Web. 24 Jan 2020.

Vancouver:

Escudero Martínez M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 Jan 24]. Available from: http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847.

Council of Science Editors:

Escudero Martínez M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847


University of New South Wales

21. Hussain, Mubashir. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.

Degree: Computer Science & Engineering, 2018, University of New South Wales

 Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system… (more)

Subjects/Keywords: System-on-Chip; Hardware Trojan; Network-on-Chip; Hardware Security

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hussain, M. (2018). Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Doctoral Dissertation, University of New South Wales. Accessed January 24, 2020. http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

MLA Handbook (7th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Web. 24 Jan 2020.

Vancouver:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2020 Jan 24]. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

Council of Science Editors:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

22. Channoufi, Malèk. Modélisation et optimisation de la couche optique de réseaux sur puce : Modeling and optimization of optical layer networks on chip.

Degree: Docteur es, STIC (sciences et technologies de l'information et de la communication) - Cergy, 2014, Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie)

Dans le cadre du développement de SoC (Systems-on-Chip) complexes, l'interconnexion des différent IP matériels (Intellectual Property), très distants à l'échelle d'un circuit intégré (typiquement quelques… (more)

Subjects/Keywords: Réseau optique sur puce; Microrésonateur; Optique guidé; Configuration en 3D; Optical network on chip; Microring resonator; 3D-configuration; Power consumption

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Channoufi, M. (2014). Modélisation et optimisation de la couche optique de réseaux sur puce : Modeling and optimization of optical layer networks on chip. (Doctoral Dissertation). Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie). Retrieved from http://www.theses.fr/2014CERG0692

Chicago Manual of Style (16th Edition):

Channoufi, Malèk. “Modélisation et optimisation de la couche optique de réseaux sur puce : Modeling and optimization of optical layer networks on chip.” 2014. Doctoral Dissertation, Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie). Accessed January 24, 2020. http://www.theses.fr/2014CERG0692.

MLA Handbook (7th Edition):

Channoufi, Malèk. “Modélisation et optimisation de la couche optique de réseaux sur puce : Modeling and optimization of optical layer networks on chip.” 2014. Web. 24 Jan 2020.

Vancouver:

Channoufi M. Modélisation et optimisation de la couche optique de réseaux sur puce : Modeling and optimization of optical layer networks on chip. [Internet] [Doctoral dissertation]. Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie); 2014. [cited 2020 Jan 24]. Available from: http://www.theses.fr/2014CERG0692.

Council of Science Editors:

Channoufi M. Modélisation et optimisation de la couche optique de réseaux sur puce : Modeling and optimization of optical layer networks on chip. [Doctoral Dissertation]. Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie); 2014. Available from: http://www.theses.fr/2014CERG0692


University of Otago

23. Yang, Wen. Routing and Wavelength Assignment for Multicast Communication in Optical Network-on-Chip .

Degree: University of Otago

 An Optical Network-on-Chip (ONoC) is an emerging chip-level optical interconnection technology to realise high-performance and power-efficient inter-core communication for many-core processors. Within the field, multicast… (more)

Subjects/Keywords: Routing; Wavelength Assignment; Multicast; Optical Network-on-Chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, W. (n.d.). Routing and Wavelength Assignment for Multicast Communication in Optical Network-on-Chip . (Doctoral Dissertation). University of Otago. Retrieved from http://hdl.handle.net/10523/9679

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Chicago Manual of Style (16th Edition):

Yang, Wen. “Routing and Wavelength Assignment for Multicast Communication in Optical Network-on-Chip .” Doctoral Dissertation, University of Otago. Accessed January 24, 2020. http://hdl.handle.net/10523/9679.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

MLA Handbook (7th Edition):

Yang, Wen. “Routing and Wavelength Assignment for Multicast Communication in Optical Network-on-Chip .” Web. 24 Jan 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Yang W. Routing and Wavelength Assignment for Multicast Communication in Optical Network-on-Chip . [Internet] [Doctoral dissertation]. University of Otago; [cited 2020 Jan 24]. Available from: http://hdl.handle.net/10523/9679.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Council of Science Editors:

Yang W. Routing and Wavelength Assignment for Multicast Communication in Optical Network-on-Chip . [Doctoral Dissertation]. University of Otago; Available from: http://hdl.handle.net/10523/9679

Note: this citation may be lacking information needed for this citation format:
No year of publication.


Texas A&M University

24. Park, Sungho. A verilog-hdl implementation of virtual channels in a network-on-chip router.

Degree: 2009, Texas A&M University

 As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a… (more)

Subjects/Keywords: NoC; Virtual Channels; Network-on-Chip; router

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, S. (2009). A verilog-hdl implementation of virtual channels in a network-on-chip router. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2890

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Sungho. “A verilog-hdl implementation of virtual channels in a network-on-chip router.” 2009. Thesis, Texas A&M University. Accessed January 24, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2890.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Sungho. “A verilog-hdl implementation of virtual channels in a network-on-chip router.” 2009. Web. 24 Jan 2020.

Vancouver:

Park S. A verilog-hdl implementation of virtual channels in a network-on-chip router. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2890.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park S. A verilog-hdl implementation of virtual channels in a network-on-chip router. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2890

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

25. Sieber, Patrick. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.

Degree: Computer Engineering, 2013, Rochester Institute of Technology

Network-on-chip (NoC) has emerged as an enabling platform for connecting hundreds of cores on a single chip, allowing for a structured, scalable system when compared… (more)

Subjects/Keywords: Multi-core; Network-on-chip; Photonic

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sieber, P. (2013). Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sieber, Patrick. “Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.” 2013. Thesis, Rochester Institute of Technology. Accessed January 24, 2020. https://scholarworks.rit.edu/theses/3160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sieber, Patrick. “Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.” 2013. Web. 24 Jan 2020.

Vancouver:

Sieber P. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. [Internet] [Thesis]. Rochester Institute of Technology; 2013. [cited 2020 Jan 24]. Available from: https://scholarworks.rit.edu/theses/3160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sieber P. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. [Thesis]. Rochester Institute of Technology; 2013. Available from: https://scholarworks.rit.edu/theses/3160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

26. Ramakrishnan, Divya. Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System.

Degree: MS, Engineering : Computer Engineering, 2009, University of Cincinnati

  In recent years, the direction of research to improve the performance of computing systems is focused toward chip multiprocessor (CMP) designs with multiple cores… (more)

Subjects/Keywords: Engineering; location cache; network on chip; multiprocessor

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ramakrishnan, D. (2009). Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228441816

Chicago Manual of Style (16th Edition):

Ramakrishnan, Divya. “Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System.” 2009. Masters Thesis, University of Cincinnati. Accessed January 24, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228441816.

MLA Handbook (7th Edition):

Ramakrishnan, Divya. “Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System.” 2009. Web. 24 Jan 2020.

Vancouver:

Ramakrishnan D. Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System. [Internet] [Masters thesis]. University of Cincinnati; 2009. [cited 2020 Jan 24]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228441816.

Council of Science Editors:

Ramakrishnan D. Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System. [Masters Thesis]. University of Cincinnati; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228441816


University of Cincinnati

27. Hariharan, Sriram. Performance Evaluation of the On-Chip Communications in a Network-on-Chip System.

Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati

 Future system-on-chip (SoC) designs require predictable, scalable and reusable on-chip interconnect architecture to increase reliability and productivity. Current bus-based interconnect architectures are inherently non-scalable, less… (more)

Subjects/Keywords: Network-on-Chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hariharan, S. (2005). Performance Evaluation of the On-Chip Communications in a Network-on-Chip System. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109186550

Chicago Manual of Style (16th Edition):

Hariharan, Sriram. “Performance Evaluation of the On-Chip Communications in a Network-on-Chip System.” 2005. Masters Thesis, University of Cincinnati. Accessed January 24, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109186550.

MLA Handbook (7th Edition):

Hariharan, Sriram. “Performance Evaluation of the On-Chip Communications in a Network-on-Chip System.” 2005. Web. 24 Jan 2020.

Vancouver:

Hariharan S. Performance Evaluation of the On-Chip Communications in a Network-on-Chip System. [Internet] [Masters thesis]. University of Cincinnati; 2005. [cited 2020 Jan 24]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109186550.

Council of Science Editors:

Hariharan S. Performance Evaluation of the On-Chip Communications in a Network-on-Chip System. [Masters Thesis]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109186550

28. FARIAS, Max Santana Rolemberg. Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC .

Degree: 2014, Universidade Federal de Pernambuco

 O crescente número de tarefas em execução em plataformas Multiprocessor Systemson- Chips (MPSoC) exige mais e mais processadores e as plataformas MPSoC que utilizam o… (more)

Subjects/Keywords: Network on Chip; MPSoC; Mapeamento de Tarefas

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

FARIAS, M. S. R. (2014). Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/12432

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

FARIAS, Max Santana Rolemberg. “Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC .” 2014. Thesis, Universidade Federal de Pernambuco. Accessed January 24, 2020. http://repositorio.ufpe.br/handle/123456789/12432.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

FARIAS, Max Santana Rolemberg. “Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC .” 2014. Web. 24 Jan 2020.

Vancouver:

FARIAS MSR. Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2014. [cited 2020 Jan 24]. Available from: http://repositorio.ufpe.br/handle/123456789/12432.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

FARIAS MSR. Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC . [Thesis]. Universidade Federal de Pernambuco; 2014. Available from: http://repositorio.ufpe.br/handle/123456789/12432

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

29. Badr, Mario. Synthetic Traffic Models that Capture Cache Coherent Behaviour.

Degree: 2014, University of Toronto

Modern and future many-core systems represent large and complex architectures. The communication fabrics in these large systems play an important role in their performance and… (more)

Subjects/Keywords: Network on Chip; Performance Modelling; 0537

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Badr, M. (2014). Synthetic Traffic Models that Capture Cache Coherent Behaviour. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/65537

Chicago Manual of Style (16th Edition):

Badr, Mario. “Synthetic Traffic Models that Capture Cache Coherent Behaviour.” 2014. Masters Thesis, University of Toronto. Accessed January 24, 2020. http://hdl.handle.net/1807/65537.

MLA Handbook (7th Edition):

Badr, Mario. “Synthetic Traffic Models that Capture Cache Coherent Behaviour.” 2014. Web. 24 Jan 2020.

Vancouver:

Badr M. Synthetic Traffic Models that Capture Cache Coherent Behaviour. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1807/65537.

Council of Science Editors:

Badr M. Synthetic Traffic Models that Capture Cache Coherent Behaviour. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/65537


University of Toronto

30. Kannan, Ajaykumar. Enabling Interposer-based Disintegration of Multi-Core Processors.

Degree: 2015, University of Toronto

Silicon interposers enable high-performance processors to integrate a significant amount of in-package memory, thereby providing huge bandwidth gains while reducing the costs of accessing memory.… (more)

Subjects/Keywords: Computer Architecture; Network on Chip; 0464

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kannan, A. (2015). Enabling Interposer-based Disintegration of Multi-Core Processors. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/70378

Chicago Manual of Style (16th Edition):

Kannan, Ajaykumar. “Enabling Interposer-based Disintegration of Multi-Core Processors.” 2015. Masters Thesis, University of Toronto. Accessed January 24, 2020. http://hdl.handle.net/1807/70378.

MLA Handbook (7th Edition):

Kannan, Ajaykumar. “Enabling Interposer-based Disintegration of Multi-Core Processors.” 2015. Web. 24 Jan 2020.

Vancouver:

Kannan A. Enabling Interposer-based Disintegration of Multi-Core Processors. [Internet] [Masters thesis]. University of Toronto; 2015. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1807/70378.

Council of Science Editors:

Kannan A. Enabling Interposer-based Disintegration of Multi-Core Processors. [Masters Thesis]. University of Toronto; 2015. Available from: http://hdl.handle.net/1807/70378

[1] [2] [3] [4] [5] … [1625]

.